WO2021195942A1

WO2021195942A1 - Photoelectric co-packaging integrated device

Info

Publication number: WO2021195942A1
Application number: PCT/CN2020/082366
Authority: WO
Inventors: 张胜利; 湛红波; 杨明
Original assignee: 华为技术有限公司
Priority date: 2020-03-31
Filing date: 2020-03-31
Publication date: 2021-10-07
Also published as: CN114930525A

Abstract

A photoelectric co-packaging integrated device. A PIC (7) and an EIC (5) are face-up mounted on a package substrate (2); an ASIC (3) is flip-chip mounted on the package substrate (2); the PIC is coupled to the EIC by means of wire bonding, and the EIC is coupled to the package substrate by means of wire bonding, and is coupled to the ASIC by means of the package substrate, thereby implementing high-frequency connection between the PIC, the EIC, and the ASIC. The PIC is not flip-chip mounted, without needing to develop a TSV process, and is coupled to the EIC by means of wire bonding, thereby solving the technical problem of low yield of current photoelectric co-packaging integrated devices containing a PIC.

Description

Photoelectric sealing integrated device

Technical field

The embodiments of the present application relate to the technical field of circuit packaging, and in particular, to an optoelectronic sealing integrated device.

Background technique

Current optical transmission products generally use photonic integrated circuit (PIC), electronic integrated circuit (EIC) and application specific integrated circuit (ASIC) flip chip (FC) in the same A package structure on a substrate.

As shown in Figure 1, PIC101, drivers, trans-impedance amplifiers (drivers&TIAs; trans-impedance amplifier, TIA) 102 and ASIC103 are all flip-chip mounted on the interposer 104, where the PIC101 is coupled to the interposer 104 through the TSV process . The optical signal is input into PIC101 and then converted into electrical signal, and the electrical signal is converted on the upper layer of PIC101. Therefore, it is necessary to develop through silicon via (TSV) technology to transfer the electrical signal from the upper layer of PIC101 through silicon via. Transfer to the lower layer of PIC101. After the electrical signal is transmitted to the lower layer of the PIC101, it can be connected to the transfer substrate 104 through solder balls. Therefore, the electrical signal is transmitted to the driver and the transimpedance amplifier 102 for amplification, and finally the electrical signal is transmitted to the ASIC 103 to realize the corresponding function.

However, when developing through silicon vias in a chip, it is necessary to consider the thermal stress of the chip itself and the thermal stress of the through hole. If the thermal stress is mismatched, when the chip heats up, the chip and the through silicon via are likely to be different. Deformation, causing chip damage. At present, it is difficult to develop through silicon vias with better thermal stress adaptation. Therefore, due to the problem of thermal stress mismatch, the yield of PIC101 is low, resulting in a low yield of optoelectronic integrated devices containing PIC101.

Summary of the invention

The embodiment of the present application provides a photoelectric sealing integrated device, which is used to solve the technical problem of low yield of the current photoelectric sealing integrated device containing PIC.

The embodiment of the application provides an optoelectronic sealing integrated device, including a package substrate, a photonic integrated circuit PIC, an electronic integrated circuit EIC, and an application specific integrated circuit ASIC; the PIC is mounted on the package substrate in the forward direction, and the EIC is The ASIC is mounted on the package substrate, and the ASIC is flip-chip mounted on the package substrate; the input and output I/O terminals of the PIC are coupled with the first I/O terminal of the EIC by wire bonding The second I/O terminal of the EIC is coupled with the first I/O terminal of the package substrate by wire bonding; the first I/O terminal of the package substrate passes through the wire on the package substrate It is coupled with the second I/O terminal of the package substrate; the second I/O terminal of the package substrate is coupled with the I/O terminal of the ASIC.

In a possible implementation manner, the second I/O terminal of the EIC is coupled to the first I/O terminal of the package substrate by wire bonding, specifically: the second I/O of the EIC The terminal is coupled with the first I/O terminal of the transfer substrate by wire bonding; the first I/O terminal of the transfer substrate is coupled with the second I/O terminal of the transfer substrate; The second I/O terminal of the transfer substrate is coupled with the first I/O terminal of the packaging substrate.

In a possible implementation manner, a via hole is provided inside the interposer substrate; the first I/O end of the interposer substrate passes through the via hole and the second I/O end of the interposer substrate coupling.

In a possible implementation, the surface of the packaging substrate is two planes, a first plane and a second plane respectively; the first plane is used for mounting the ASIC; the second plane is used for mounting The EIC and the PIC; the first plane is parallel to the second I/O end of the EIC.

In a possible implementation manner, the photoelectric packaging integrated device further includes a first heat dissipation plate; the first heat dissipation plate is disposed between the packaging substrate and the EIC.

In a possible implementation manner, the photoelectric packaging integrated device further includes a second heat dissipation plate; the second heat dissipation plate is arranged between the packaging substrate and the PIC.

In a possible implementation manner, the photoelectric sealing integrated device further includes a printed circuit board PCB; the packaging substrate is coupled with the PCB.

In a possible implementation manner, the photoelectric sealing integrated device further includes an optical fiber interface; the PIC is coupled with the optical fiber interface for obtaining optical signals.

In a possible implementation manner, the first heat dissipation plate and the second heat dissipation plate are integrally formed.

In a possible implementation, the photoelectric packaging integrated device further includes a heat sink, and the heat sink is connected to the first heat dissipation plate or the second heat dissipation plate, or the heat dissipation plate is connected to the first heat dissipation plate and the first heat dissipation plate. The second heat dissipation plate.

In a possible implementation manner, the PIC is used to convert the acquired optical signal into an electrical signal and transmit it to the EIC; the EIC is used to amplify the electrical signal received from the PIC; The ASIC is used to implement the function designed by the ASIC according to the electrical signal received from the EIC.

In a possible implementation manner, the ASIC is used to output electrical signals according to the functions designed by the ASIC; the EIC is used to amplify or reduce the electrical signals received from the ASIC; and the PIC is used to The electrical signal received from the EIC is converted into an optical signal.

It can be seen from the above technical solutions that the embodiments of the present application have the following advantages: In the photoelectric packaging integrated device provided by the embodiments of the present application, the PIC and EIC are mounted on the package substrate in the forward direction, the ASIC is flip-chip mounted on the package substrate, and the PIC Through wire bonding and EIC coupling, EIC is coupled with the package substrate through wire bonding, and coupled with the ASIC through the package substrate, thereby realizing the high-frequency connection between the PIC, EIC and ASIC. In the embodiments of the present application, the PIC does not use flip chip, and does not need to develop the TSV process, and is coupled with the EIC through wire bonding, which solves the technical problem of low yield of photoelectric packaging integrated devices containing PIC.

Description of the drawings

Figure 1 is an example diagram of a photoelectric sealing integrated device using flip-chip technology;

Figure 2 is an example figure 2 of an optoelectronic sealing integrated device using flip-chip technology;

FIG. 3 is an example diagram 1 of an optoelectronic sealing integrated device provided by an embodiment of the application; FIG.

4 is an example diagram 2 of the photoelectric sealing integrated device provided by the embodiment of the application;

Figure 5 is an example Figure 3 of the photoelectric sealing integrated device provided by the embodiment of the application;

Fig. 6 is an example Fig. 4 of the photoelectric sealing integrated device provided by the embodiment of the application;

FIG. 7 is a perspective view of the photoelectric sealing integrated device provided by an embodiment of the application.

Detailed ways

The terms "first", "second", "third", "fourth", etc. (if any) in the description and claims of this application and the above-mentioned drawings are used to distinguish similar objects, without having to use To describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in a sequence other than those illustrated or described herein. In addition, the terms "including" and "corresponding to" and any variations of them are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to a clearly listed Instead, it may include other steps or units that are not clearly listed or are inherent to these processes, methods, products, or equipment.

In the embodiments of the present application, words such as "exemplary" or "for example" are used as examples, illustrations, or illustrations. Any embodiment or design solution described as "exemplary" or "for example" in the embodiments of the present application should not be construed as being more preferable or advantageous than other embodiments or design solutions. To be precise, words such as "exemplary" or "for example" are used to present related concepts in a specific manner. Fig. 1 is an example figure 1 of an optoelectronic sealing integrated device using flip-chip technology. In the embodiments of the present application, the packaging technology of the chip generally includes the chip front-mounting technology and the chip flip-chip technology. Among them, the chip front mounting technology means that the chip is placed on the substrate and the front side faces the opposite direction of the substrate (the front side of the chip generally refers to the side where the chip is provided with the circuit). The electrodes of the chip are exposed and can be connected to other chips or circuits through wires. The flip chip technology means that the chip is set on the substrate and the front side faces the substrate, and the electrodes of the chip can be connected to the circuit of the substrate (connected by solder balls). Therefore, the chip packaging technology shown in FIG. 1 is a flip chip technology.

As shown in Figure 1, PIC101, drivers, trans-impedance amplifiers (drivers&TIAs; trans-impedance amplifier, TIA) 102 and ASIC103 are all flip-chip mounted on the interposer 104, where the PIC101 is coupled to the interposer 104 through the TSV process . The transfer substrate 104 and the package substrate 105 are connected by solder balls. The PIC and the driver and the transimpedance amplifier 102 are electrically connected through the transfer substrate 104 or the packaging substrate 105. Similarly, the driver, the transimpedance amplifier 102 and the ASIC 103 are also electrically connected through the transfer substrate 104 or the packaging substrate 105.

Therefore, in the example of FIG. 1, the optical waveguide of the PIC101 faces upward, and a TSV process needs to be developed to transmit the signal to the transfer substrate 104. At present, the development of TSV technology on PIC requires high technical requirements, and the development is difficult. For example, when developing through silicon vias in a chip, it is necessary to consider the thermal stress of the chip itself and the thermal stress of the through hole. If the thermal stress is mismatched, when the chip heats up, the chip and the through hole are prone to different deformations. , Resulting in chip damage. It is currently difficult to develop a technical solution with better thermal stress adaptation. Therefore, due to the problem of thermal stress mismatch, the yield of PIC101 is low, resulting in a low yield of optoelectronic integrated devices containing PIC101.

Figure 2 is an example Figure 2 of an optoelectronic sealing integrated device using flip-chip technology. The optical waveguide of PIC101 in Figure 2 faces downwards. Although the PIC101 in Fig. 2 does not require the development of a TSV process, the PIC101 needs to develop a downward-facing ball planting process for the optical waveguide, which is a big technical challenge. In addition, the PIC101 is partially thinned or etched on the back surface, and the optical waveguide is coupled in the vertical direction between the back surface and the optical fiber. Therefore, there is a risk of stress caused by the mismatch of coefficient of thermal expansion (CTE) at the coupling position where the back of the PIC101 is locally thinned.

In order to solve the above-mentioned difficult technical problem of PIC development, an embodiment of the present application provides an optoelectronic sealing integrated device, as shown in FIG. 3, including ASIC3, EIC5 and PIC7. Among them, the ASIC3 is flip-chip mounted on the package substrate 2, the EIC5 and PIC7 are mounted on the heat sink 6 in the forward direction, and the heat sink 6 is mounted on the package base 2. The EIC5 and PIC7 are coupled by wire bonding. The lead from the EIC5 is coupled to the ASIC3 through the package substrate 2.

In the embodiments of this application, wire bonding refers to the use of wires (wires, thin metal wires, gold wires, etc.) to be tightly welded to ports on the chip, so that the chips are electrically interconnected, and the chips are electrically connected. Signal intercommunication. Under ideally controlled conditions, electron sharing or atomic interdiffusion occurs between the leads and the ports on the chip, so that atomic bonding between the two metals can be achieved.

In the embodiments of the present application, PIC7 is generally used to convert optical signals into electrical signals. The PIC7 can be coupled with the optical fiber interface 8 and obtain optical signals through the optical fiber interface 8. The optical fiber interface 8 is connected to an optical fiber for receiving optical signals from the optical fiber. PIC7 can also be coupled with other circuits to transmit the converted electrical signal. As shown in Figure 3, the PIC7 is mounted on the heat sink 6 in the forward direction, with the optical waveguide facing upwards, and there is no need to thin or etch the back. In addition, the PIC7 transmits the signal to EIC5 through wire bonding, so there is no need to develop TSV technology. The mature wire bonding technology is directly adopted, which reduces the difficulty of development, and at the same time increases the yield of PIC7, thereby improving optoelectronics. Yield rate of packaged integrated devices.

It is understandable that the coupling mode of PIC7 and EIC5 can be that the output terminal of PIC7 is coupled with the input terminal of EIC5, and is used to transmit the converted electric signal to EIC5. In some possible cases, the coupling mode of PIC7 and EIC5 can be that the input terminal of PIC7 and the output terminal of EIC5 are coupled to output the electrical signal of EIC5 to PIC7, and PIC7 can convert the electrical signal received from EIC5 into The optical signal is transmitted through the optical fiber interface 8. In some other embodiments, PIC7 and EIC5 are specifically coupled to the I/O terminal of PIC7 and the I/O terminal of EIC5, and are used to realize the above two functions, that is, they can be used to transmit the converted electrical signal to EIC5 and transfer the The electrical signal of EIC5 is output to PIC7.

In a possible embodiment, the surface where the I/O terminal of the PIC7 is located is adjacent to the surface where the I/O terminal of the EIC5 is located, which can reduce the length of the lead wire and save costs. In another possible embodiment, the surface where the I/O end of the PIC7 is located and the surface where the I/O end of the EIC5 is located are both facing away from the heat sink 6, so the wire bonding can be performed directly on the front side. Reduce the process requirements.

In the embodiment of the present application, the EIC5 obtains the electrical signal of the PIC7 through the lead. EIC5 can include, but is not limited to, drivers and transimpedance amplifiers. Among them, the transimpedance amplifier is used to amplify the electrical signal, and the driver is used to generate the output signal. The output signal generated by EIC5 through the driver reaches ASIC3 through the lead. In practical applications, EIC5 can also be other integrated circuit designs, which are not limited in the embodiments of the present application. The connection between EIC5 and PIC7 can be wire bonding. The lead may be a gold wire, which is not limited in the embodiment of the present application.

PIC7 and EIC5 are set up by forward mounting, which can reduce the complexity of the PIC7 ball planting process and avoid the risk of stress caused by flip-chip mounting.

In the embodiment of the present application, the ASIC 3 is flip-chip mounted on the packaging substrate 2 and connected to the packaging substrate 2 through solder balls (also referred to as solder balls or solder bumps). The ASIC3 can be designed into different circuits according to actual needs, and the specific design of the ASIC3 in the embodiment of the present application is not limited.

In the embodiment of the present application, the PIC7 and the EIC5 are connected by wire bonding to achieve high frequency connection, the EIC5 is bonded to the package substrate 2 by wire bonding, and then the package substrate 2 is connected to the ASIC 3 for high frequency connection. The photoelectric sealing integrated device does not need to develop complicated TSV technology or thinning and etching to realize high-frequency connection. Moreover, in the embodiment of the present application, a heat dissipation plate 6 is provided under the PIC7 and the EIC5 to dissipate the heat generated by the circuit. Compared with the full flip-chip structure, the embodiment of the present application can provide a heat dissipation plate 6 between the circuit element and the packaging substrate 2, which can dissipate heat more effectively.

In some embodiments, the output terminal of the EIC5 is coupled with the input terminal of the ASIC3 through the package substrate 2 for transmitting the signal from the EIC5 to the ASIC3 for further processing. In other embodiments, the input end of the EIC5 is coupled with the output end of the ASIC3 through the packaging substrate 2, and the signal output by the ASIC3 is transmitted to the EIC5, and finally can be transmitted to the PIC7 and transmitted out through the optical fiber interface 8. In other embodiments, the I/O terminal of EIC5 is coupled with the I/O terminal of ASIC3 through the package substrate 2 and can be used to transmit signals from EIC5 to ASIC3, and can also be used to transmit signals output by ASIC3 to EIC5.

It can be understood that in EIC5, the I/O terminal coupled with PIC7 and the I/O terminal coupled with ASIC3 are generally different I/O terminals. Therefore, the I/O terminal coupled with PIC7 can be used in EIC5. The first I/O terminal called EIC5, and the I/O terminal coupled with ASIC3 is called the second I/O terminal. In other cases, these two types of I/O terminals may also be referred to as other ports, which are not limited in the embodiment of the present application.

In some embodiments, the EIC5 is actually first coupled to the first I/O terminal of the package substrate 2 by wire bonding, and the first I/O terminal of the package substrate 2 passes through the internal wires or surface wires of the package substrate 2. Or it is coupled to the second I/O terminal of the package substrate 2 by means of vias, etc., and then the second I/O terminal of the package substrate 2 is coupled to the I/O terminal of the ASIC 3 by means of solder balls or the like. The embodiment of the present application can couple the front-mounted EIC5 and the flip-chip ASIC3 through this substrate coupling method, thereby realizing the coupling of the front-mounted chip and the flip-chip.

In a possible embodiment, the I/O terminal on the EIC5 that is coupled to the package substrate 2 is arranged on the side of the EIC5, so the leads can be directly connected to the package substrate 2 from the side of the EIC5, thereby reducing the number of leads. The length saves costs.

In a possible embodiment, the package substrate 2 is connected to a printed circuit board (PCB) 1 through solder balls, so that each circuit device on the package substrate 2 can be electrically connected to other circuit elements on the PCB1. connect.

In a possible embodiment, the heat dissipation plate 6 is connected to a heat sink for transferring heat to the heat sink, and the heat sink is used for dissipating heat. The radiator may be a passive radiator, an air-cooled radiator, a water-cooled radiator, etc., which is not limited in the embodiment of the present application. The heat sink can be arranged on the top or side of the chip, which is not limited in the embodiment of the present application. The heat dissipation plate 6 has good thermal contact with the radiator, and is mainly used to transfer the heat of the EIC5 through the radiator to ensure that the EIC5 works in a normal temperature range.

The photoelectric encapsulation integrated device provided by the embodiment of the present application encapsulates ASIC3, EIC5, and PIC7 together, which reduces the high-frequency interconnection loss between discretely packaged PIC, EIC and ASIC and impedance mismatch reflection at the connection. In addition, the PIC7 in the embodiment of the present application does not require the development of TSV technology, and directly adopts mature wire bonding technology, which reduces the difficulty of development and at the same time increases the yield of PIC7, thereby increasing the yield of optoelectronic integrated devices.

Fig. 4 is an example Fig. 2 of the photoelectric sealing integrated device provided by the embodiment of the application. In the example of FIG. 4, the heat dissipation plate 6 can be divided into a first heat dissipation plate 61 and a second heat dissipation plate 62 to realize the separate heat dissipation of the EIC5 and the PIC7, which makes the device design more flexible.

In a possible embodiment, the photoelectric sealing integrated device provided in the embodiment of the present application may be provided with only the first heat dissipation plate 61 and not the second heat dissipation plate 62, so as to specifically dissipate the EIC5, thereby saving component costs and improving heat dissipation. efficient.

In a possible embodiment, the photoelectric sealing integrated device provided in the embodiment of the present application may only be provided with the second heat dissipation plate 62 without the first heat dissipation plate 61, so as to specifically dissipate the PIC7, thereby saving component costs and improving heat dissipation. efficient.

In a possible embodiment, the first heat dissipation plate 61 and the second heat dissipation plate 62 may be integrally formed to form a heat dissipation plate, such as the heat dissipation plate 6 shown in FIG. 3. The embodiment of the application does not limit this.

Fig. 5 is an example Fig. 3 of the photoelectric sealing integrated device provided by the embodiment of the application. In the embodiment of the present application, the photoelectric packaging integrated device at least includes a package substrate 2, ASIC3, EIC5, PIC7, wherein the package substrate 2, ASIC3, EIC5, PIC7 are the same as the package substrate 2, ASIC3, EIC5, PIC7 in the foregoing embodiment Similar, not repeat them here.

In the embodiment of the present application, the shape of the packaging substrate 2 may be designed to be integrally formed with two rectangular parallelepipeds, wherein the height of one rectangular parallelepiped is higher than the height of the other rectangular parallelepiped, forming two planes, namely a first plane and a second plane, wherein, The first plane is higher than the second plane. The first plane can be used to carry and install ASIC3, and the second plane can be used to carry EIC5 and PIC7. In another description, the packaging substrate 2 can also be regarded as a rectangular parallelepiped, a part of which is cut out to form a groove. Then the groove can be used to carry EIC5 and PIC7.

This design can raise ASIC3, or lower EIC5 and PIC7, so that ASIC3 and EIC5 and PIC7 are not on the same plane. And the first plane can be aligned parallel to EIC5 and PIC7, specifically it can be aligned parallel to the second I/O terminal of EIC5, with a small height difference, which makes the wire bonding between the package substrate 2 and EIC5 easier and reduces the design difficulty. Improve wire bonding efficiency and improve product yield.

In some embodiments, a heat dissipation plate 6 is also provided between the EIC5, PIC7 and the package substrate. The heat dissipating plate 6 is similar to the heat dissipating plate 6 in the foregoing embodiments corresponding to FIG. 3, and will not be repeated here.

In some embodiments, the photoelectric sealing integrated device further includes an optical fiber interface 8. The optical fiber interface 8 is similar to the optical fiber interface 8 in each embodiment corresponding to FIG. 3 or FIG. 4, and will not be repeated here.

In some embodiments, the photoelectric sealing integrated device further includes PCB1. The PCB1 is similar to the PCB1 in the respective embodiments corresponding to FIG. 3 or FIG. 4, and will not be repeated here.

Fig. 6 is an example Fig. 4 of the photoelectric sealing integrated device provided by the embodiment of the application. The photoelectric packaging integrated device includes packaging substrates 2, ASIC3, EIC5, and PIC7. The packaging substrates 2, ASIC3, EIC5, and PIC7 are similar to the packaging substrates 2, ASIC3, EIC5, and PIC7 in the foregoing embodiments, and will not be repeated here.

The photoelectric sealing integrated device further includes a transfer substrate 4. The transfer substrate 4 is coupled with the package substrate 2 through solder balls. The EIC5 is specifically connected to the transfer substrate 4 by wire bonding. Therefore, electrical signals can be transmitted from the EIC 5 to the interposer substrate 4 and from the interposer substrate 4 to the ASIC 3 through the package substrate 2.

In the embodiment of the present application, the transfer substrate 4 is provided with a transmission medium that transmits the signal on the wire bond to the solder ball. For example, a via hole may be provided on the transfer substrate 4, and the signal on the wire bonding may be transmitted to the solder ball through the via hole. In practical applications, the signal on the top of the transfer substrate 4 can also be transmitted to the solder balls on the bottom of the transfer substrate 4 on the transfer substrate 4 in other ways, which is not limited in the embodiment of the present application. Since the transfer substrate 4 is not a complicated chip, the cost of designing the transmission medium on the transfer substrate 4 is low, the development difficulty is small, the process is simple, and the yield rate is high.

FIG. 7 is a perspective view of the photoelectric sealing integrated device provided by an embodiment of the application. The photoelectric sealing integrated device corresponds to FIG. 6, wherein the packaging substrate 2, ASIC 3, the transfer substrate 4, the EIC 5, the heat dissipation plate 6, the PIC 7, and the optical interface 8 can refer to the descriptions in the respective embodiments corresponding to the foregoing FIG. 6.

As shown in Fig. 7, EIC5 is coupled with PIC7 through wire bonding, wherein the wires may include multiple wires. Moreover, in the embodiment of the present application, the number of EIC5 may be two. In practical applications, the number of RIC5 can also be adjusted according to actual needs, which is not limited in the embodiment of the present application.

In the embodiment of the present application, the EIC5 is coupled with the transfer substrate 4 through wire bonding, where the wires may include multiple wires. The number of transfer substrates 4 can be adjusted according to actual conditions, which is not limited in the embodiment of the present application.

In the embodiment of the present application, the heat dissipation plate 6 extends all the way to the housing. The heat dissipation plate 6 is connected to the housing, and heat can be dissipated through the housing. In a possible situation, the heat dissipation plate 6 may also be connected to a heat sink (not shown in FIG. 7) on the housing, and heat dissipation is performed through the heat sink.

The photoelectric encapsulation integrated device provided by the embodiment of the present application encapsulates ASIC3, EIC5, and PIC7 together, which reduces the high-frequency interconnection loss between discretely packaged PIC, EIC and ASIC and impedance mismatch reflection at the connection. In addition, the PIC7 in the embodiment of the present application does not require the development of TSV technology, which solves the process difficulty and stress risk caused by PIC flip-chip.

Those skilled in the art can clearly understand that, for the convenience and conciseness of the description, the specific working process of the above-described system, device, and unit can refer to the corresponding process in the foregoing method embodiment, which will not be repeated here.

Claims

An optoelectronic sealing integrated device, which is characterized by comprising a package substrate, a photonic integrated circuit PIC, an electronic integrated circuit EIC, and an application-specific integrated circuit ASIC;

The PIC is forward mounted on the packaging substrate, the EIC is forward mounted on the packaging substrate, and the ASIC is flip-mounted on the packaging substrate;

The input/output I/O terminal of the PIC is coupled with the first I/O terminal of the EIC by wire bonding;

The second I/O terminal of the EIC is coupled with the first I/O terminal of the package substrate by wire bonding;

The first I/O terminal of the packaging substrate is coupled with the second I/O terminal of the packaging substrate through a wire on the packaging substrate;

The second I/O terminal of the packaging substrate is coupled with the I/O terminal of the ASIC.
The photoelectric sealing integrated device according to claim 1, characterized in that it further comprises a transfer substrate;

The second I/O terminal of the EIC is coupled to the first I/O terminal of the package substrate by wire bonding. Specifically, the second I/O terminal of the EIC is connected to the first I/O terminal by wire bonding. The first I/O terminal of the transfer substrate is coupled;

The first I/O terminal of the transfer substrate is coupled with the second I/O terminal of the transfer substrate;

The second I/O terminal of the transfer substrate is coupled with the first I/O terminal of the packaging substrate.
An optoelectronic sealing integrated device according to any one of claims 1 to 2, wherein a via hole is provided inside the transfer substrate;

The first I/O terminal of the transfer substrate is coupled with the second I/O terminal of the transfer substrate through the via hole.
The photoelectric sealing integrated device according to claim 1, wherein the surface of the packaging substrate is two planes, a first plane and a second plane respectively;

The first plane is used to install the ASIC;

The second plane is used to install the EIC and the PIC;

The first plane is parallel to the second I/O terminal of the EIC.
An optoelectronic sealing integrated device according to any one of claims 1 to 4, further comprising a first heat dissipation plate;

The first heat dissipation plate is arranged between the packaging substrate and the EIC.
An optoelectronic sealing integrated device according to any one of claims 1 to 5, further comprising a second heat dissipation plate;

The second heat dissipation plate is arranged between the packaging substrate and the PIC.
An optoelectronic sealing integrated device according to any one of claims 1 to 6, characterized in that it further comprises a printed circuit board (PCB);

The packaging substrate is coupled with the PCB.
An optoelectronic sealing integrated device according to any one of claims 1 to 7, characterized in that it further comprises an optical fiber interface;

The PIC is coupled with the optical fiber interface for obtaining optical signals.
The optoelectronic sealing integrated device according to any one of claims 1 to 7, wherein the first heat dissipation plate and the second heat dissipation plate are integrally formed.
The photoelectric sealing integrated device according to any one of claims 1 to 7, further comprising a heat sink, the heat sink is connected to the first heat dissipation plate or the second heat dissipation plate, or the heat dissipation The board connects the first heat dissipation plate and the second heat dissipation plate.
The photoelectric sealing integrated device according to any one of claims 1 to 7, wherein the PIC is used to convert the acquired optical signal into an electrical signal and transmit it to the EIC;

The EIC is used to amplify the electrical signal received from the PIC;

The ASIC is used to implement the function designed by the ASIC according to the electrical signal received from the EIC.
The photoelectric sealing integrated device according to any one of claims 1 to 7, wherein the ASIC is used to output electrical signals according to the function designed by the ASIC;

The EIC is used to amplify or reduce the electrical signal received from the ASIC;

The PIC is used to convert the electrical signal received from the EIC into an optical signal.