WO2021165639A1

WO2021165639A1 - Control method for a distributed processing system including a quantum information processor

Info

Publication number: WO2021165639A1
Application number: PCT/GB2021/050233
Authority: WO
Inventors: Andrew David Patterson
Original assignee: Oxford Quantum Circuits Limited
Priority date: 2020-02-21
Filing date: 2021-02-03
Publication date: 2021-08-26
Also published as: GB202002491D0; TW202134959A

Abstract

A method of transpiling a classical-quantum hybrid program to be executed by a distributed processing system is disclosed, the distributed processing system comprising one or more classical processors and a quantum information processor interrogable via classical analogue interaction means. The classical-quantum hybrid program includes a function to be executed by the quantum information processor. The method comprises parsing the classical-quantum hybrid program to generate an intermediate representation of the classical-quantum hybrid program, the intermediate representation comprising a series of basic blocks, each basic block comprising a sequence of instructions. The method comprises identifying basic blocks for which the sequence of instructions comprises one or more stream operation instructions, the one or more stream operation instructions configured to control interactions with the quantum information processor. The method comprises analysing the identified basic blocks to identify one or more subprograms for implementation on the one or more classical processor and quantum information processor. The method comprises, based on a target hardware configuration description for the analogue interaction means, replacing the one or more stream operation instructions of the subprograms with target hardware-specific code for controlling the analogue interaction means to interact with the quantum information processor, to generate a hardware-specific intermediate representation of the classical-quantum hybrid program. The method comprises translating the hardware-specific intermediate representation of the classical-quantum hybrid program into a transpiled classical-quantum hybrid program. A computer-readable medium, a distributed system controller, and a distributed processing system are also disclosed.

Description

Control method for a distributed processing system including a quantum information processor

Technical Field

[0001] The present disclosure relates to distributed computing systems. More particularly, the present disclosure relates to a distributed computing system comprising at least one quantum information processor.

Background

[0002] Current quantum computers are often unable to interpret instructions/program code themselves. Instead, one typically interacts with a quantum information processor via some analogue interaction means, both to execute quantum operations and to retrieve/read-out information. This has led to the development of the classical-quantum hybrid programming paradigm - quantum computers work as co-processors with powerful classical computers, shouldering elements of a problem that are inefficient using classical methods.

[0003] Such classical-quantum hybrid programs are typically hardware specific, which may mean they are inflexible and feature-limiting.

Summary

[0004] According to an aspect of the present invention, a method of transpiling a classical- quantum hybrid program to be executed by a distributed processing system is provided. The distributed processing system comprising one or more classical processors and a quantum information processor interrogable via classical analogue interaction means. The classical- quantum hybrid program includes a function to be executed by the quantum information processor. The method comprises parsing the classical-quantum hybrid program to generate an intermediate representation of the classical-quantum hybrid program, the intermediate representation comprising a series of basic blocks, each basic block comprising a sequence of instructions. The method comprises identifying basic blocks for which the sequence of instructions comprises one or more stream operation instructions, the one or more stream operation instructions configured to control interactions with the quantum information processor. The method comprises analysing the identified process blocks to identify one or more subprograms for implementation on the one or more classical processors and quantum information processor. The method comprises, based on a target hardware configuration description for the analogue interaction means, replacing the one or more stream operation instructions of the subprograms with target hardware-specific code for controlling the analogue interaction means to interact with the quantum information processor, to generate a hardware-specific intermediate representation of the classical-quantum hybrid program. The method comprises translating the hardware-specific intermediate representation of the classical-quantum hybrid program into a transpiled classical-quantum hybrid program.

[0005] The method may further comprise, subsequent to identifying basic blocks for which the sequence of instructions comprises one or more stream operation instructions, marking procedure calls for inlining. A procedure may comprise one or more basic blocks. The method may further comprise inlining the basic blocks containing the procedure calls marked for inlining. Marking procedure calls for inlining may comprise marking procedures containing one or more basic blocks for which the sequence of instructions comprises one or more stream operation instructions as belonging to a first set. Marking procedure calls for inlining may further comprise marking procedures from which any marked procedure of the first set are reachable as belonging to a second set. Marking procedure calls for inlining may further comprise combining the first set and the second set to form a third set. Marking procedure calls for inlining may further comprise, for each procedure in the third set, identifying all calling procedures which call that procedure, and if a calling procedure is already in the third set, or if a calling procedure is in the second set and calls another procedure in the second set, marking the call for inlining. Furthermore, if the calling procedure is in the second set and calls another procedure of the second set, then the calling procedure is added to the third set.

[0006] Analysing the identified basic blocks to identify one or more subprograms may comprise converting the identified basic blocks into a static single assignment form and additionally ensuring each stream operation instruction is dependent on at most one dominating stream operation instruction. Analysing the identified basic blocks to identify one or more subprograms may further comprise analysing the static single assignment form of the identified basic blocks to identify one or more subprograms for implementation on the one or more classical processors and quantum information processor.

[0007] Analysing the static single assignment form may include marking loops within the identified basic blocks for unrolling; and unrolling the loops marked for unrolling. Marking loops within the identified basic blocks for unrolling may comprise locating non-constant stream identifiers within the identified basic blocks; and may further comprise, if a non-constant stream identifier is dependent on a loop-induction variable, then marking the loop for unrolling.

[0008] A stream operation instruction may comprise one of an OPEN instruction for activating a stream, a READ instruction for reading from an open stream, a WRITE instruction for writing to an open stream, a CLOSE instruction for deactivating an open stream. [0009] Ensuring each stream operation instruction is dependent on at most one dominating stream operation instruction may comprise inserting a placeholder stream function wherever diverging paths of stream operations merge.

[0010] Converting the identified basic blocks into a static single assignment form may comprise analysing one or more of control flow, dominance hierarchy, and control dependence of the classical-quantum hybrid program.

[0011] Analysing the static single assignment form may comprise performing one or more of data flow analysis or constant propagation.

[0012] Replacing the one or more stream operation instructions of the subprograms with target hardware-specific code for controlling the analogue interaction means may comprise identifying subroutines of the subprograms, passing the subroutines to hardware / hardware backends according to the stream operation instructions of the subprograms and the target hardware configuration description to enable the hardware backends to generate hardware configuration data and instructions and to define hardware data flow, inserting commands into the static single assignment form of the classical-quantum hybrid program to push/pull data to/from the hardware backends based on the configuration data, instructions and hardware data flow.

[0013] Analysing the static single assignment form of the identified basic blocks to identify one or more subprograms for implementation on the one or more classical processors and quantum information processor may comprise analysing stream-dependence of the static single assignment form to build a stream dependence graph, and modifying connected subgraphs of the stream dependence graph to be strongly connected subgraphs. Analysing the static single assignment form may further comprise building a dependence graph based on the modified stream dependence graph, control-dependence, and data dependence of the static single assignment form of the classical-quantum hybrid program; and identifying strongly-connected components of the dependence graph as subprograms.

[0014] The method may further comprise receiving source code for the classical-quantum hybrid program.

[0015] The one or more classical processors may comprise a field programmable gate array. [0016] The method may further comprise distributing at least a part of the transpiled classical- quantum hybrid program to the one or more classical processors.

[0017] According to an aspect of the present invention, a computer-readable storage medium is provided, the computer-readable medium having instructions stored thereon which, when executed by one or more processors, cause the one or more processors to perform a method of transpiling a classical-quantum hybrid program as described herein. [0018] According to an aspect of the present invention, a computer-readable storage medium is provided, the computer-readable medium having stored thereon a transpiled classical-quantum hybrid program, the classical-quantum hybrid program transpiled according to a method of transpiling a classical-quantum hybrid program as described herein.

[0019] According to an aspect of the present invention, a distributed system controller is disclosed. The distributed system controller is configured to transpile a classical-quantum hybrid program to be executed by a distributed processing system, the distributed processing system comprising the distributed system controller, one or more classical processors and a quantum information processor interrogable via classical analogue interaction means, the classical-quantum hybrid program including a function to be executed by the quantum information processor. The distributed system controller comprises one or more memories. The distributed system controller further comprises one or more processors. The one or more processors are configured to parse the classical-quantum hybrid program to generate an intermediate representation of the classical- quantum hybrid program, the intermediate representation comprising a series of basic blocks, each basic block comprising a sequence of instructions. The one or more processors are configured to identify basic blocks for which the sequence of instructions comprises one or more stream operation instructions, the one or more stream operation instructions configured to control interactions with the quantum information processor. The one or more processors are configured to analyse the identified basic blocks to identify one or more subprograms for implementation on the one or more classical processors and quantum information processor. The one or more processors are configured to, based on a target hardware configuration description for the analogue interaction means, replace the one or more stream operation instructions of the subprograms with target hardware-specific code for controlling the analogue interaction means to interact with the quantum information processor, to a hardware-specific intermediate representation of the classical- quantum hybrid program. The one or more processors are configured to translate the hardware- specific intermediate representation of the classical-quantum hybrid program into a transpiled classical-quantum hybrid program.

[0020] According to an aspect of the invention, a distributed processing system is provided. The distributed system comprises a quantum information processor. The distributed system further comprises one or more classical processors. The distributed system further comprises a distributed system controller as described herein.

[0021] A computer program and/or the code/instructions for performing such methods as described herein may be provided to an apparatus, such as a computer, on a computer readable medium or computer program product. The computer readable medium could be, for example, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, or a propagation medium for data transmission, for example for downloading the code over the Internet. Alternatively, the computer readable medium could take the form of a physical computer readable medium such as semiconductor or solid-state memory, magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disc, and an optical disk, such as a CD-ROM, CD-R/W or DVD.

[0022] Many modifications and other embodiments of the inventions set out herein will come to mind to a person skilled in the art to which these inventions pertain in light of the teachings presented herein. Therefore, it will be understood that the disclosure herein is not to be limited to the specific embodiments disclosed herein. Moreover, although the description provided herein provides example embodiments in the context of certain combinations of elements, steps and/or functions may be provided by alternative embodiments without departing from the scope of the invention.

Brief Description of the Drawings

[0023] Embodiments of the invention will now be described by way of example only, with reference to the accompanying figures, in which:

Figure 1 shows a distributed processing system including a quantum information processor;

Figure 2 shows a block diagram of a computing device for use as a distributed system controller;

Figure 3 shows a block diagram of a hybrid computing apparatus;

Figure 4 shows a flowchart of a method of transpiling a classical -quantum hybrid program; Figure 5 shows a flowchart of a method for transpiling a classical-quantum hybrid program in more detail;

Figure 6 shows a flowchart of a method for marking basic blocks for inlining;

Figure 7 shows a flowchart of a method for marking loops for unrolling; and Figure 8 shows a flowchart of a method of identifying subprograms;

Figure 9 shows a flowchart of a method of configuring subprograms for use with target hardware;

Figure 10 shows a flowchart of a method for isolating subprograms; and Figure 11 shows a block diagram of a machine-readable storage medium.

[0024] Throughout the description and the drawings, like reference numerals refer to like parts. Description

[0025] Whilst various embodiments are described below, the invention is not limited to these embodiments, and variations of these embodiments may well fall within the scope of the invention, which is to be limited only by the appended claims.

[0026] Quantum information processing focuses on information processing and computing based on quantum mechanics. While current digital computers encode data in binary digits (bits), quantum computers are not limited to two states. They encode information as quantum bits, or qubits, which can exist in superposition. A qubit is a unit of quantum information. Qubits may be implemented with atoms, ions, photons or electrons (for example) and suitable control devices that work together to act as computer memory and a processor. In what follows, the terms quantum information processor and quantum computer have been used interchangeably. It is to be understood that a quantum information processor comprises a plurality of qubits and the apparatus required to maintain the qubits in a superposition state.

[0027] Quantum computers promise to provide ground breaking advances in the ability to solve several types of problem exponentially faster than the best classical computers. However, delivering on these promises may require overcoming considerable technological challenges. [0028] To at least partially alleviate the burden of such challenges, several classical-quantum hybrid algorithms have been proposed. A classical-quantum hybrid program is a program comprising one or more such classical-quantum hybrid algorithms. In a classical-quantum hybrid algorithm, both classical and quantum resources are used to perform a computational task. That computational task may be simple or may be more complicated. One non-trivial example is the Variational Quantum Eigensolver (VQE) algorithm, which uses quantum and classical resources to find variational solutions to eigenvalue and optimization problems that are not accessible to traditional classical computers. More specifically, the VQE algorithm is used to find eigenvalues of a (usually large) matrix H which may represent the Hamiltonian of a physical system. A quantum subroutine is run inside of a classical optimization loop. The quantum subroutine comprises preparing an ansatz quantum state |ψ(θ)> parametrised by a parameter θ and measuring the expectation value <ψ(θ)|H|ψ(θ)>. The variational principle ensures that this expectation value is always greater than the smallest eigenvalue of the matrix H. In the classical optimization loop, the parameter θ can be iteratively adjusted until a convergence condition is met. [0029] In order to best exploit the capabilities of classical-quantum hybrid programs, hybrid computing systems are required in which one or more classical processors carry out the bulk of a program's instructions and outsource to a quantum information processor only for very specific tasks. Such hybrid computing systems reduce the number of operations that the quantum information processor needs to perform, which means that errors can also be more efficiently corrected for. Computational tasks are distributed between classical and quantum information processors.

[0030] Current quantum computers are usually unable to interpret quantum computer programs themselves. Instead, one typically interacts with a quantum information processor using some classically controlled interaction means (for example microwave generators) to perform a quantum operation on the quantum information processor and to read out information from the quantum information processor. Software is required to configure the analogue interaction means, prepare and process data, perform calibration of the quantum information processor, execute programs provided by a user, and perform classical parts of classical -quantum hybrid algorithms. Standard solutions generally involve building classical programs that generate quantum programs. These quantum programs are individually processed to create e.g. microwave level instructions for performance by the interaction means. These microwave level instructions are usually interpreted by software in the lab to configure a specific hardware setup. This hardware setup then performs the experiment. Such a method is inflexible and feature-limiting due to the many fixed interfaces between the user and the final system.

[0031] The inventors have designed a compilation method for taking a single input program comprising both classical and quantum instructions and, based on target hardware specifications, outputting a transpiled program for coordinating the distribution of processing tasks across the appropriate hardware. The transpiled program may accordingly be distributed across the relevant classical processors, low-latency programmable hardware, and interaction means. Such an approach has several clear advantages. Firstly, variable levels of control in the hybrid program enable quantum engineers, software engineers and application end-users to utilise the same system. This reduces the maintenance burden that comes from multiple packages, and ensures a consistent experience across users and developers. Secondly, different hardware targets can be easily selected and updated. Updates can be made to hardware where they are needed to support programs or enable them to be more efficiently compiled. Without any required changes, programs may be compiled to make use of newly available features in hardware where available. Thirdly, by inputting a program describing exactly what one wants to do but not explicitly stating how or where it is done, the compiler has the best chance to find a way using the hardware target to enable this program to run. This allows for fully customisable, extremely low latency control of the quantum hardware. [0032] In its most general form, a compiler is a program that accepts as input a program text in a first language and produces as output a program text in another language, while preserving the meaning of that text. Most compilers translate a high-level programming language, such as C, into machine instructions, for performing functions on machine hardware.

[0033] Typically a compiler comprises a front-end software module, which performs an analysis of the input program text and produces a semantic representation of the input program text. A compiler further typically comprises a back-end software module, which generates the appropriate machine instructions from the semantic representation of the input program. If the compiler has a clean design, then the front-end may be entirely unaware of the target language, and the back-end may be totally unaware of the source language. However, there are many technical reasons why such a strict separation may be inefficient, and in practice most compilers have some form of compromise. For this reason, terms such as “front-end” and “back-end” are intended to be interpreted broadly.

[0034] A transcompiler, also known as a source-to-source compiler or a transpiler, is a type of compiler that takes the source code of a program written in a programming language as its input and produces a substantially equivalent program in the same or a different programming language. A transpiler thus translates between programming languages at approximately similar levels of abstraction.

[0035] In the transpilation methods described herein, a classical-quantum hybrid program is provided in a first programming language or equivalent data representation, and that hybrid program may be hardware-agnostic, or may provide only a target hardware specification. The classical -quantum hybrid program is deconstructed into a semantic representation and then some hardware-specific code is provided for executing certain commands across a distributed processing system. A transpiled classical-quantum hybrid program is produced in a second programming language or equivalent data representation (which may be the same as the first programming language or may not). Accordingly, the methods described herein translate a high-level, hardware- agnostic program into a high-level program that is, at least in part, hardware-specific. In particular, the transpiled hybrid program is suitable for execution across one or more classical processors and a quantum information processor.

[0036] Figure 1 illustrates a distributed processing system 100 according to an embodiment of the present invention. The distributed processing system 100 comprises a network 110, a distributed system controller 120, classical computing devices 130 and 135, and hybrid computing apparatus 140. The distributed processing system 100 may comprise more or fewer devices and components. The distributed system controller 120 and hybrid computing apparatus 140 are described in further detail below.

[0037] The network 110 may be any known type of computer network, enabling wired or wireless communication between computer devices 130/135 and the distributed system controller 120, and between the distributed system controller and the hybrid computing apparatus 140. The network may comprise, for example, a Local Area Network (LAN), a Wide Area Network (WAN), or the Internet. The distributed processing system may comprise multiple networks - for example the computing devices 130 and 135 may communicate with the distributed system controller 120 wirelessly while the distributed system controller 120 may communicate with the hybrid computing apparatus 140 via a wired connection.

[0038] The hybrid computing apparatus 140 comprises one or more classical processors 150, an interaction module 160, and a quantum information processor 170. The hybrid computing apparatus 140 of this example is configured to perform quantum operations on the quantum information processor 170 via the interaction module 160, while performing complementary classical operations on low-latency, dedicated classical processors 150, for example, field programmable gate arrays. These will be discussed in more detail further below.

[0039] The distributed system controller 120 may receive a classical-quantum hybrid program from a user. For example, a user may send a computer-executable file containing a classical- quantum hybrid program to the distributed system controller from a third party computer (such as classical computing device 130). Alternatively, the distributed system controller 120 itself may support program-writing functionality such that a user can design a classical-quantum hybrid program directly on the distributed system controller 120. In other embodiments, the hybrid computing apparatus 140 may itself be configured to act as a distributed system controller.

[0040] The distributed system controller 120 is configured to transpile a classical-quantum hybrid program according to a method as described herein to produce a transpiled classical-quantum hybrid program. The transpiled classical-quantum hybrid program includes hardware-specific code for controlling analogue interaction means of the interaction module 160 to interact with the quantum information processor 170 and code for performance on one or more classical processors such as classical processors 150 or computing device 135.

[0041] The distributed system controller 120 may be further configured to coordinate the execution of the program. This may be performed in any of several possible ways.

[0042] For example, the distributed system controller 120 may produce a transpiled classical- quantum hybrid program that may be executed on the controller 120 itself to directly control operations performed on the quantum information processor 170, the classical processors 150, and optionally on classical computing devices such as devices 130 and 135. In another example, the transpiled classical -quantum hybrid program may comprise several code portions which are each distributed to the classical processors and interaction module 160 for execution therefrom.

[0043] In another example, the hybrid computing apparatus 140 may be configured to act as a distributed system controller. The hybrid computing apparatus may therefore directly execute the instructions of the transpiled classical-quantum hybrid program itself. In other examples, the distributed system controller 120 may be responsible only for creating the transpiled classical- quantum hybrid program. A host device may be responsible for coordinating the execution of the transpiled program. The host device may comprise, for example, computing device 130 or computing device 135.

[0044] FIG. 2 depicts a block diagram of a distributed system controller 200, which may perform the role of distributed system controller 120 of FIG. 1. The distributed system controller 200 is an example of a computer, in which computer usable program code or instructions implementing the processes may be located and acted upon. The skilled person would appreciate that other architectures are envisaged. The distributed system controller 200 is configured to perform a method such as that described in relation to FIGs. 4-10 below.

[0045] The distributed system controller 200 includes a number of user interfaces including visualising means such as a visual display 280 and a virtual or dedicated user input/output unit 240. Input/output unit 240 allows for input and output of data with other devices / users that may be connected to device 200. For example, input/output unit 240 may provide a connection for user input through a keyboard, a mouse, and/or some other suitable input device. Further, input/output unit 240 may send output to a printer.

[0046] The distributed system controller 200 further includes one or more (classical) processors 210, a memory 220, a persistent memory 230, and a power system 260.

[0047] The distributed system controller 200 comprises a communications module 250 for sending and receiving communications between processor 210 and remote systems. For example, communications module 250 may be used to send and receive communications via a network 110 such as the Internet. Communications module 250 may provide communications through the use of either or both physical and wireless communications links.

[0048] The distributed system controller 200 further comprises a port 270 for receiving, for example, a non-transitory machine-readable/computer-readable medium containing instructions to be processed by the processor 210.

[0049] Memory 220 and persistent storage 230 are examples of storage devices. A storage device is any piece of hardware that is capable of storing information, such as, for example, without limitation, data, program code in functional form, and/or other suitable information either on a temporary basis and/or a permanent basis. Memory 220, in these examples, may be, for example, a random access memory or any other suitable volatile or non-volatile storage device. Persistent storage 230 may take various forms depending on the particular implementation. For example, persistent storage 230 may contain one or more components or devices. For example, persistent storage 230 may be a hard drive, a flash memory, a rewritable optical disk, a rewritable magnetic tape, or some combination of the above. The media used by persistent storage 230 also may be removable. For example, a removable hard drive may be used for persistent storage 230.

[0050] Instructions for the processor 210 may be stored. For example, the instructions may be in a functional form on persistent storage 230. These instructions may be loaded into memory 220 for execution by processor 210.

[0051] Processor 210 serves to execute instructions for software that may be loaded into memory 220. Processor unit 210 may be a set of one or more processors or may be a multiprocessor core, depending on the particular implementation. Further, processor unit 210 may be implemented using one or more heterogeneous processor systems in which a main processor is present with secondary processors on a single chip. As another illustrative example, processor unit 210 may be a symmetric multi-processor system containing multiple processors of the same type.

[0052] The processor 210 is configured to receive data, access the memory 220 and persistent storage 230, and to act upon instructions received either from said memory 220 or persistent storage 230, from communications module 250 or from user input device 240.

[0053] The skilled person would appreciate that the distributed system controller 200 of FIG. 2 is an example only. A distributed system controller may comprise more or fewer components and modules. For example, the distributed system controller may have no visual display capabilities. [0054] FIG. 3 depicts a block diagram of hybrid computing apparatus 300, which may perform the role of hybrid computing apparatus 140 of FIG. 1.

[0055] The hybrid computing apparatus 300 comprises an input/output unit 240’, a communications module 250’, a memory 220’, persistent memory 230’ and power 260’, and these components are configured to perform similar tasks to those performed by the similar components of the distributed system controller 200.

[0056] The hybrid computing apparatus 300 further comprises a quantum information processor 170 and an interaction module 160 for interacting with the quantum information processor 170. [0057] The quantum information processor 170 can be any device which is able to generate a quantum state for processing. The quantum information processor 170 may be of any suitable type, and may process qubits using any known method, including, but not limited to the following methods: nuclear magnetic resonance, ion traps, superconductors, quantum dots, electrons on liquid helium, solid-state spin spectroscopy, cavity QED.

[0058] In one example, the quantum information processor 170 may comprise superconducting circuits. In a superconducting circuit implementation of a quantum computer, the base unit of quantum computing, a qubit, can be implemented physically in a number of different ways. One or more Josephson junctions may be combined with capacitors and/or inductors, to form a high quality anharmonic circuit, the lowest quantised energy levels of which are used to define the qubit. For example, a commonly implemented and successful design, known as a charge qubit or transmon, consists in its simplest form of a single Josephson junction in parallel with a capacitor. The two electrodes of the qubit can be arranged in a number of ways; examples include arranging the electrodes collinearly in a geometry reminiscent of a dipole antenna, or using interdigitated capacitors, or with one electrode in a cross shape, and the other realised as a common ground plane.

[0059] The interaction module 160 is configured to receive instructions for interacting with the quantum information processor 170, and to execute those instructions. The interaction module 160 may comprise a dedicated memory and/or persistent memory for translating some incoming instructions to machine instructions for controlling the quantum information processor 170 - for example, the interaction module 160 may comprise a “back-end” software module for configuring an intermediate representation of the classical-quantum hybrid program for operation with the analogue interaction means. The interaction module 160 may additionally or alternatively be configured to interact with the memory 220’ and persistent memory 230’ of the hybrid computing apparatus, which may be shared with the classical processors 150.

[0060] The interaction module 160 comprises analogue interaction means for controlling interactions with the quantum information processor 170 to manipulate the qubits in order to perform quantum operations and to take measurements. In superconducting qubit quantum computers, control and measurement circuitry is typically implemented using planar circuitry integrated on-chip with the qubits, and/or using the 3D electromagnetic waveguides and cavities in which the qubit chips are embedded. Accordingly, while the interaction module 160 and quantum information processor 170 of FIG. 3 are shown as separate components, they may to some extent be integrated. The interaction module 160 may comprise circuitry to apply a voltage across a particular point in the superconducting circuit or apparatus for coordinating microwave pulses applied to the quantum information processor 170.

[0061] An arbitrary single qubit gate may be achieved by rotation in the Bloch sphere. The rotations between the different energy levels of a single qubit are induced by microwave pulses sent to an antenna or transmission line coupled to the qubit, with a frequency resonant with the energy separation between the levels. In such cases, the interaction module 160 may include interaction means in the form of a microwave generator. Coupling two qubits may be achieved by connecting them to an intermediate electrical coupling circuit. The coupling circuit might be a fixed element, such as a capacitor, or controllable, such as a DC-SQUID. In the first case, decoupling the qubits (during the time the gate is off) may be achieved by tuning the qubits out of resonance one from another, i.e. making the energy gaps between their computational states different.

[0062] The interaction module 160 accordingly comprises analogue interaction means for interrogating/controlling the quantum information processor 170.

[0063] The hybrid computing apparatus 300 further comprises one or more classical processors 150. The classical processors 150 are low-latency hardware for performing classical operations. The classical processors 150 may comprise, for example, field-programmable gate arrays (FPGAs). FPGAs typically contain an array of programmable logic blocks, and a hierarchy of reconfigurable interconnects that allow the programmable logic blocks to be connected in any of several different configurations. Logic blocks can be configured to perform complex combinational functions, or merely simple logic gates like AND and XOR gates. In most FPGAs, logic blocks also include memory elements, which may be simple flip-flops or more complete blocks of memory. Many FPGAs can be reprogrammed to implement different logic functions, allowing flexible reconfigurable computing as performed in computer software.

[0064] The hybrid computing apparatus 300 is shown in FIG. 3 as though it is within a single device in which all of the components are closely connected. However, the skilled person would appreciate that other architectures are envisaged. For example, the hybrid computing apparatus may itself be distributed across multiple spatially separated devices and components.

[0065] The skilled person would appreciate that the distributed processing system, distributed system controller and hybrid computing apparatus described above are examples only and that other architectures are envisaged.

[0066] For example, more or fewer devices may be comprised within the distributed processing system 100. The distributed processing system may comprise, for example, a single classical processor, an interaction module, and a quantum information processor. In such circumstances the classical processor may be configured to transpile a classical-quantum hybrid program for use with the available classical processor, interaction means, and quantum information processor available. Accordingly, a dedicated distributed system controller 120 may not be required. The classical processor may be further configured to execute the transpiled program, possibly after further compilation. Similarly, the dedicated low-latency processing hardware 150 of FIGs. 1 and 3 may or may not be required.

[0067] In use the distributed system controller 120 may be configured to receive a classical- quantum hybrid program. The program may include a target hardware specification, or the distributed system controller 120 may be configured to receive a target hardware specification for the program in some other way, for example via a separate communication from an external device, or by consulting its memory. The target hardware specification comprise information concerning the distributed processing system such as which hardware is available and what each piece of hardware is connected to (and also which simulated hardware may be available and which simulated connections are available). The target hardware specification may comprise the minimum requirements for implementing the program including detailed information such as, for example, a number of qubits required to perform a quantum operation.

[0068] The distributed system controller 120 is further configured to, based on the target hardware specification, transpile the classical-quantum hybrid program according to a method substantially as described herein. The resultant transpiled classical-quantum hybrid program accordingly comprises hardware specific instructions for implementing one or more quantum operations on the quantum information processor 170 using the interaction module 160. The transpiled classical- quantum program may further comprise hardware specific instructions for implementing one or more classical operations on dedicated classical processors 150. The transpiled classical-quantum program may further comprise high-level (i.e. substantially hardware-agnostic) instructions for performance on other classical processors such as on classical computing devices 130, 135, or on an internal processor of the distributed system controller 120 itself.

[0069] After transpilation/compilation, the resultant program may be executable by any suitable classical apparatus in combination with the hybrid computing apparatus 140. For example, the transpiled program may be executable by the distributed system controller 120. The distributed system controller 120 may accordingly, if required, compile any remaining hardware-agnostic parts of the program for performance on its processor or on a processor of an external device. When executing the transpiled program, the processor of the distributed system controller 120 may directly control the interaction module 160 and the dedicated processor 150 of the hybrid computing apparatus 140. Alternatively, the distributed system controller 120 may be configured to submit configurations to a scheduling module (which may be a software module provided in memory/persistent memory of the distributed system controller or in the memory/persistent memory of the hybrid computing apparatus) for scheduled processing. Alternatively, the transpiled classical-quantum program may be further translated to a plurality of executable files which may then be transmitted to the relevant processors/interaction module for execution. The distributed system controller 120 may be operable to act in some combination of these ways.

[0070] Roughly speaking, the transpiled program is a sequence of instructions that some host system can execute that will have the "net effect" of executing the original program. The instructions of the transpiled program themselves may contain instructions to configure other subsystems, send data to them, trigger them to execute code, and retrieve data from them. The final transpiled program may be very explicit in nature; all instructions that remain in the program may be directly executed on the host, but will include configuring other machines to execute parts of the program.

[0071] The transpiled classical-quantum hybrid program may instead be executable by a separate host device, such as classical computing device 130. The classical computing device 130 may accordingly, if required, compile any remaining hardware-agnostic parts of the program for performance on its processor or on a processor of an external device. When executing the transpiled program, the processor of the classical computing device 130 may directly control the interaction module 160 and the dedicated processor 150 of the hybrid computing apparatus 140. Alternatively, the classical computing device 130 may be configured to submit configurations to a scheduling module (which may be a software module provided in memory/persistent memory of the distributed system controller 120 or the classical computing device 130 or in the memory/persistent memory of the hybrid computing apparatus) for scheduled processing. Alternatively, the transpiled classical-quantum program may be further translated to a plurality of executable files which may then be transmitted to the relevant processors/interaction module for execution.

[0072] A method of transpiling a classical-quantum hybrid program will now be described with reference to Figure 4. In the following description, the quantum information processor is described in places as a superconducting qubit quantum information processor, and the interaction module is described as comprising analogue interaction means in the form of a microwave signal generator. However, the skilled person would appreciate that this is for descriptive purposes only and is not intended to be limiting. In particular, the quantum information processor may comprise any suitable quantum information processor and the analogue interaction means may be any analogue interaction means suitable for interacting with the quantum information processor. The method of FIG. 4 may be performed by, for example, the distributed system controller 120 described above in relation to FIG. 1.

[0073] Figure 4 illustrates a flow chart of a method of transpiling a classical-quantum hybrid program to be executed by a distributed processing system. The distributed processing system comprises one or more classical processors 150 and a quantum information processor 170 interrogable via classical analogue interaction means (in this example comprised within the interaction module 160). The classical-quantum hybrid program includes at least one function to be executed on the quantum information processor 170.

[0074] The classical-quantum hybrid program may be expressed in any high-level programming language that is not hardware specific. For example, the classical-quantum hybrid program may be written in Python, C, C++, Fortran, Pascal or any other such language. The classical-quantum hybrid program may include procedures for calibrating the quantum information processor, and may include procedures for implementing quantum logic operations on a quantum information processor. Procedures for implementation by a quantum information processor typically include one or more stream operation instructions, which after the transpilation method correspond to instructions for the analogue interaction means. The stream operation instructions may accordingly be thought of as an interface between the processing operations to be performed on a quantum information processor and the processing operations performed by the rest of the distributed processing system - the stream operation instructions describe interactions with the quantum information processor. For example, the stream operation instructions may comprise instructions for the microwave signal generator to generate microwave signals for interacting with the quantum information processor.

[0075] At 410, the classical-quantum hybrid program is parsed to generate an intermediate representation. The intermediate representation comprises a series of basic blocks, each basic block comprising a sequence of instructions. As such, the intermediate representation is assembly- like in nature. As a result of this intermediate representation, each instruction is in essence “single- effect”. Instructions are organised into a list, one single-effect instruction after another (although the skilled person would appreciate that the intermediate representation may contain several multiple-effect instructions). Jumps and/or conditional jumps enable non-linear flow through the instruction list. A basic block may be a continuous block of code, beginning with a label instruction enabling the block to be identified, and concluding with a final jump instruction. A basic block comprises a sequence of instructions with one entry point and one exit point - from nowhere in the program can one jump into the middle of the basic block, nor can one exit the basic block from the middle.

[0076] An example of a basic block is as follows:

LABEL(“A”) // each block starts with a label “instruction” that identifies the block MOV(“X”, 3) // the move instruction sets the variable “x” to the value of 3 JMP “B” II each block ends in a jump (or conditional -jump) instruction, specifying (or allowing calculation of) the next block to execute.

[0077] Basic instructions within a basic block may take the form of one of the following:

LABEL(unique_label_name) // designates a unique id for the basic block EVAL(expr) // evaluate the expression in expr

MOV(unique_var_name, expr) // move value in expr into designated variable JUMP(label_name) // jump to label

CJUMP(expr, label_name, label_name) // conditional jump to one of two labels depending on value of expr and expressions may be stored as tree structures that can include basic structures such as constant values, references to variables, and arithmetic operations:

CONST(const value) // specification of a constant value TEMP(unique_var_name), // reference to the value of a variable ADD(expr, expr) // expression with value that is the sum of two expressions [0078] Expressions may also include more complex structures such as function calls which in a traditional compiler would eventually be translated to a more basic instruction such as those described above, but which in the present methods are translated more selectively. The form of the call expression may be, for example:

CALL(function_name, expr_list)

[0079] “Special” function calls are the method by which stream operations (e.g. OPEN, READ, WRITE, CLOSE) may be provided in the input program. These may have the respective function name values strm open, strm read, strm write, strm close.

[0080] The compiler may support, for example, four low-level instructions that perform operations on streams:

OPEN: A list of one or more streams are opened at once, marking their use as synchronous. In analogy with data analysis, this can be thought of as an assignment to these opened streams;

READ: A particular (opened) stream is read from, with either the data array or the length of data to return also being specified; WRITE: A particular (opened) stream is written to, with either the data array or the length of data to return also being specified;

CLOSE: A list of one or more streams are closed. This command must logically follow an OPEN command for these same streams. In analogy with data analysis, this can be thought of as an assignment to these streams.

[0081] At 420, basic blocks having one or more stream operation instructions are identified. The stream operation instructions relate to instructions that would be performed by the analogue interaction means, in this example a microwave signal generator. As the stream operation instructions relate in general to commands for the microwave signal generator which interacts with the superconducting qubits of the quantum information processor, identifying basic blocks which contain stream operation instructions is useful for identifying operations which may be outsourced to the microwave signal generator as opposed to a classical processor.

[0082] At 430, the identified basic blocks are analysed to identify one or more subprograms for implementation on the one or more classical processors and quantum information processor. This may comprise converting the identified basic blocks to single stream assignment (SSA) form and further ensuring that the basic blocks are converted into a form in which each stream operation instruction is dependent on at most one dominant stream instruction. In compiler design, SSA form is a property of an intermediate representation which requires that each variable is assigned exactly once, and every variable is defined before it is used. Converting the identified basic blocks to SSA form may comprise, for example, replacing the target of each assignment with a new variable, and replacing each use of a variable with the version of the variable reaching that point.

[0083] Data flow analysis is made easier by converting code into SSA form. Consider as an example:

MOV(TEMP(‘x’), CONST(3)) // x=3

MOV(TEMP‘y’), ADD(TEMP(‘x’), CONST(2)) // y=x+2

The second statement has data dependence on the first instruction, so data flow analysis would pick up that there was a ‘use’ of temp ‘x’ in the second instruction that was linked to the ‘definition‘/’def’ of ‘x’ in the first instruction. Data flow analysis is the process of building up use- def chains. Consider the next example:

MOV(TEMP(‘x’), CONST(3)) // x=3

MOV(TEMP‘y’), ADD(TEMP(‘x’), CONST(2)) // y=x+2 MOV(TEMP(‘z’), ADD(TEMP(‘x’), CONST(2)) // z=x+2

Instruction 2 uses the definition of x in instruction 1. Instruction 3 uses the definition of x in instruction 1. As there is no dependence of instruction 3 on instruction 2, the order in which instructions 3 and 2 are executed does not matter, and so switching them or executing them in parallel is possible. Consider the next example:

MOV(TEMP(‘x’), CONST(3)) // x=3

MOV(TEMP‘y’), ADD(TEMP(‘x’), CONST(2)) // y=x+2

MOV(TEMP(‘z’), ADD(TEMP(‘y’), CONST(2)) // z=y+2

Instruction 2 uses the definition of x in instruction 1. Instruction 3 uses the definition of y in instruction 2. As there is dependence of 3 on 2 and of 2 on 1, the order in which the instructions may be executed is fixed. Consider the next example:

MOV(TEMP(‘x’), CONST(3)) // x=3 MOV(TEMP(‘x’), ADD(TEMP(‘x’), CONST(2)) // x=x+2 MOV(TEMP(‘x’), ADD(TEMP(‘x’), CONST(2)) // x=y+2

Instruction 2 uses the definition of x in instruction 1. Instruction 3 uses the definition of x in instruction 2.

[0084] Sometimes, flow of control makes it impossible to determine the most recent version of a variable. In these cases, the compiler inserts an artificial definition for that variable called a Phi (F) function or Phi node. This new definition merges all the incoming versions of the variable to create a new name for it. Since it is not possible to determine which of several branches will be followed at runtime (for example, whether a condition inside an IF statement is met), conversion to SSA form may involve inserting such a Phi function which is the result of “merging” the different options. A Phi function may be implemented by, for example, using the same location in memory as the destination for any operation that produces an input to the Phi function. A Phi function is a placeholder function, assisting during compilation and optimisation steps, but not requiring actual execution.

[0085] Consider as an example, the following high-level pseudocode: if(y) then: x = 3; else: x = 2; y = x + 2;

This pseudocode may be represented in the intermediate representation as a series of basic blocks of the form:

LABEL(“ START”)

MOV(TEMP(‘y’), ?) // y is set to “something” beforehand

CJUMP( TEMP(y), LABEL(“A”), LABEL(“B”) ) // if y is true execute A, if y is false execute B

LABEL(“A”)

MOV(TEMP(‘x’), CONST(3)) // x=3 JUMP(“C”)

LABEL(“B”)

MOV(TEMP(‘x’), CONST(2)) // x=2 JUMP(“C”)

LABEL(“C”)

MOV(TEMP(‘y’), ADD(TEMP(‘x’), CONST(2))) // y = x + 2 JUMP(“END”)

LABEL(“END”)

JUMP(“END”)

In this pseudocode, the y=x+2 statement is clearly a ‘use’ of temp x. Depending on program flow, the definition of x it is using will either be the definition in the “x=3” or the “x=2” instruction. Use-def chains constructed in this way are therefore many-to-many, in that any definition may have multiple uses and any use may have multiple definitions. SSA form simplifies data analysis by ensuring that use-def chains are many-to-one - for any given use of a variable, there is only one definition. This is achieved by converting the pseudocode as follows:

LABEL(“ START”)

MOV(TEMP(‘y’), ?) // y is set to “something” beforehand CJUMP( TEMP(y), LABEL(“A”), LABEL(“B”) ) // if y is true execute A, if y is false execute B

LABEL(“A”)

MOV(TEMP(‘xl’), CONST(3)) 11 xl=3 JUMP(“C”)

LABEL(“B”)

MOV(TEMP(‘x2’), CONST(2)) // x2=2 JUMP(“C”)

LABEL(“C”)

MOV(TEMP(‘x’), PHI(TEMP(‘xl’), TEMP(‘x2’)) // x = xl or x = x2, as dictated by previous program flow

MOV(TEMP‘y’), ADD(TEMP(‘x’), CONST(2))) // y = x + 2 JUMP(“END”)

LABEL(“END”)

JUMP(“END”)

[0086] Methods for inserting Phi functions to ensure SSA form are well known and presented in standard compiler literature. They include analysis of potential paths of “flow” through the program ( control flow analysis ), and can be performed efficiently by further analysis of the control flow to produce what is called a dominance hierarchy, from which can be computed a dominance frontier of every block. A block “A” dominates another “B” if all paths in control flow from “A” to the end of the program pass through “B”. A block “C” is on the dominance frontier of “A” if it is the first block reached on any control flow path from “A” that is not dominated by “A”.

[0087] The SSA form is well known. However, the current method extends the principle of SSA form to the concept of stream operations.

[0088] Logically, stream operations both affect the state of particular streams (“defining” a new stream state) and depend on the state of particular streams (“use” of current stream state). An exception to this is the strm open instruction which is dependent on (“uses”) no streams; it rather sets the streams to be open and a blank slate - similar to “defining” them to a specific initial state. [0089] The strm open instruction may be defined to have the form:

EVAL(CALL( ‘ strm open ’ , exprli st(C ON ST( ’ uni que_strm_name_1’), CONST(^,unique_strm_name_2’), ...) ))

[0090] The strm close instruction may be defined to have the form:

EVAL(CALL(‘strm_close’, exprlist(CONST(^,unique_strm_name_r), CONST(^,unique_strm_name_2’), ...) ))

[0091] The strm read instruction may be defined to have the form:

EVAL(CALL(‘strm_read^,, exprlist(CONST(^,unique_strm_name’), EXPR, ...) )) where EXPR is an expression evaluating to the number of samples to be read from the stream.

[0092] The strm write instruction may be defined to have the form:

EVAL(CALL(‘strm_write’, exprlist(CONST(^,unique_strm_name’), EXPR, ...) )) where EXPR is an expression evaluating to the sample, or array of samples, to be written to the stream.

[0093] In the above, the stream names provided have been given as constant expressions. This allows use-def chains of the stream operations to be built. Handling cases where these expressions are non-constant is required but discussed later.

[0094] Analogous to the Phi functions/Phi nodes that help to denote variables when it is not possible to determine which branch of a program will be followed at runtime, in this extended SSA form, an analogous placeholder stream operation, herein referred to as a StreamPhi operation (or ‘strm phi’), is inserted wherever diverging paths of stream operations merge. By using such StreamPhi operations, each stream operation is made dependent on at most one prior (dominating) stream operation instruction.

[0095] One may introduce a strm phi operation, with the form:

EVAL(CALL(‘ strm _phi ’ , exprlist(CONST( ’unique_ strm_name, ’ ))))

A strm_phi is also considered as both a use and a definition of the stream.

[0096] As in standard SSA form, one may insert strm phi operations by analysis of control-flow, the resulting dominance information, and the current use-def chains. This results in a set of use- def chains where every strm_open, strm_write, strm_read, strm close command has a dependence on only one prior stream_operation.

[0097] Strm _phi operations remain dependent on multiple prior stream operations, as can be seen in this example in which streams have not been renamed to ensure only one definition of each (we are working implicitly rather than explicitly in SSA form): data1 = ? data2 = ? y = ? strm_open(‘strm 1’,) if(y) then: strm_write(‘strm 1’, data1) x = 3; else: strm_write(‘strm 1,’ data2) x = 2; y = x + 2; strm _phi(‘strm 1’,) // this strm _phi command has been inserted as two different control flow paths have converged with strml in differing states. strm_write(‘strm 1’, datal) strm_close(‘ strm 1 ’ )

[0098] A stream dependence chain can now be built, in which individual stream operation instructions are marked where appropriate as being dependent on a prior operation, and StreamPhi operations are marked to be dependent on multiple prior operations. A stream dependence graph / stream dependence chain is a directed graph in which each node represents a stream operation instruction, and each directed edge representing a dependency of one stream operation instruction on another.

[0099] This extension of the SSA form to also cover stream operation instructions is sometimes referred to herein as single stream state form.

[0100] The skilled person would appreciate that the entire intermediate representation of the classical-quantum hybrid program may be converted to SSA form. In other examples, only the basic blocks identified at 420 may be converted to SSA form.

[0101] By converting the identified basic blocks to this SSA form, the program can be somewhat optimised in order to perform control flow analysis and data-flow analysis and to perform appropriate transformations and optimizations to the program.

[0102] Control flow analysis (CFA) is a static-code-analysis technique for determining the control flow of a program. The control flow may be expressed as a control-flow graph (CFG). A CFG is a representation, using graph notation, of all paths that might be traversed through a program during its execution. In a CFG each node in the graph represents a basic block (at least some of which will be in SSA form), and directed edges between adjacent nodes can be used to represent jumps in the control flow. The CFG includes at least one entry block through which control enters into the CFG and at least one exit block, through which control leaves the CFG. An operation or basic block is said to dominate a second operation or second basic block is every path from the entry that reaches the second operation or second basic block passes through the first operation or basic block. While control-flow graphs and graph operations on control flow graphs may be described further below, the skilled person would appreciate that such graphs and graph operations are described for illustrative purposes only. CFA is typically performed by known computational procedures.

[0103] Data-flow analysis is a technique for gathering information about the possible set of values calculated at various points in a computer program. A program's control flow graph (CFG) may be used to determine those parts of a program to which a particular value assigned to a variable might propagate. Data-flow analysis may be performed by any known computational procedures. [0104] Analysing the identified basic blocks to identify one or more subprograms for implementation on the one or more classical processors and quantum information processor may further comprise analysing the single stream state form of the classical-quantum hybrid program in order to identify any subprograms for implementation on the quantum information processor 170. Subprograms comprise a collection of individual instructions. Any blocks that contain one such instruction are considered blocks of the subprogram, but not all instructions within these blocks are necessarily instructions within the subprogram. The primary purpose of subprogram identification is to identify instructions that have critical timing requirements to others, or perform stream operations. These are not suitable for execution on the host controller and must be (directly or indirectly) executed in (one or more) specific hardware components with both the physical capability to cause any stream operations to occur, enabling actual interrogation of the quantum device, and the capability to execute any other instructions within specific, short, time windows, with respect to other instructions and stream operations.

[0105] Stream flow dependencies may be considered to be time-critical, and so all such dependent instructions may be added to a self-contained subprogram. Any other instruction (or set of instructions) that has both an instruction already in the subprogram which is dependent on it, and a dependence on an instruction already in the subprogram, may be added to the subprogram, and any instructions now satisfying this constraint may also be added to the subprogram.

[0106] An example method of discovering all such instructions efficiently is as follows. Firstly, generate a directed graph of all dependencies where nodes represent instructions and edges point in the direction of dependence (from one instruction to the instruction it is dependent on). Secondly, insert additional pseudo-dependencies such that any stream instruction is reachable on the graph from any other (which may be as simple as inserting a dependence from strm open to strm close in typical cases). This ensures all stream instructions form a strongly connected component of the graph (by definition). Thirdly, detect strongly connected components using Kosaraju's algorithm or similar. The strongly connected components of this graph will now contain all required instructions for the subprogram, as any instruction(s) on a dependence path that both leaves the subprogram and then again enters it would clearly form part of the strongly connected component itself.

[0107] A more detailed method or identifying such subprograms is described further below. [0108] The single stream state form of the classical-quantum hybrid program may be analysed to identify any subprograms for implementation on the classical processors 150 or the classical computing devices 130, 135.

[0109] At 440, based on a target hardware configuration description for the microwave signal generator, the one or more low-level stream operation instructions of the identified subprograms are replaced with target hardware-specific code for controlling the analogue interaction means 160 to interact with the quantum information processor 170, to generate a hardware-specific intermediate representation of the classical-quantum hybrid program. As will be described in detail further below, the target-hardware specific code for controlling the analogue interaction means is provided by passing the relevant instructions to the relevant target hardware back-end module, which may be stored in memory in the interaction module 160 or in memory in the distributed system controller 120. The target-hardware specific code provides the hardware configuration instructions etc that are required to, for example, generate microwave signals for interacting with the quantum information processor 170.

[0110] Similarly, subprograms for controlling low-latency classical processors 150 are identified and, with the aid of a relevant target hardware back-end module, target-hardware specific code for controlling the low-latency classical processors 150 is inserted.

[0111] The target-hardware specific code for the classical processors 150 and quantum information processor enable fast and effective processing of classical-quantum hybrid operations. For example, such instructions may help to enable the classical processors 150 to, for example, iterate through an induction variable on which the microwave signal generator operations depend. [0112] At 450, the hardware-specific intermediate representation of the classical-quantum hybrid program is translated into a transpiled classical-quantum hybrid program. In particular, the transpiled classical-quantum hybrid program comprises mainly high-level code. However, now any operations that are required to be run on the classical processor 150 or the quantum information processor 170 are represented by hardware-specific code for implementing those operations on the relevant processor. [0113] FIG. 5 illustrates a flowchart of a method for transpiling a classical -quantum hybrid program as in FIG. 4, and provides further detail. The method starts at 502.

[0114] At 504, the classical-quantum hybrid program is parsed into an intermediate representation (as at step 410).

[0115] At 506, several basic blocks are marked for inlining, in particular those basic blocks containing one or more stream operation instructions. Marking basic blocks for inlining may comprise marking basic blocks for which the sequence of instructions comprises one or more stream operation instructions as belonging to a first set, marking basic blocks from which any marked basic block of the first set are reachable as belonging to a second set, and combining the first set and the second set to form a third set, and then subsequently, for each basic block in the third set, identifying all callers of the basic block and if the basic block is in the first set, or if the basic block is in the second set and calls a basic block in the second set, marking the basic block for inlining. Inlining, also known as inline expansion is a form of compiler optimisation that replaces a function call site with the body of the called function.

[0116] At 508, the basic blocks marked for inlining are inlined.

[0117] FIG. 6 shows a flowchart of a method for marking basic blocks for inlining. At 602, the method begins. At 604, a directed graph is built. A directed graph is a graph made up of a set of vertices/nodes connected by edges, where the edges have a direction associated with them. In particular, the procedure s/basic blocks are assigned to nodes. Edges of the graph relate to relationships between basic blocks. In particular, the directed edges are formed between any calling procedure and called procedures. The skilled person would appreciate that the graph need not be generated in any physical sense, merely an analysis is performed that is similar to such graph building.

[0118] A directed graph is said to be strongly connected if there is a path between all pairs of vertices. A strongly connected component of a directed graph is a maximal strongly connected subgraph. At 606, any strongly connected components of the directed graph built at 604 are identified and marked as recursive.

[0119] At 608, any basic blocks containing stream operation instructions are marked as belonging to a first set, here denoted as S. At 610, any basic blocks from which a basic block in the first set S is reachable is denoted as belonging to a second set ES.

[0120] At 612, the first set and the second set are combined to form a third set, T.

[0121] At 614, a working list W is built from the procedures of the third set T. [0122] At 616, a determination is made as to whether W is empty. If W is empty then the method ends at 618. If instead W is not empty, then the method proceeds to 620, at which a first procedure A is removed from W.

[0123] At 622, all callers of A are found. At 624, a determination is made for each caller as to whether either the caller is in the third set T or the caller is in ES and calls another procedure in ES. If the determination is negative, then the method proceeds to 616. Alternatively, if the determination is positive then the call is marked for inlining. If the caller is not in T then the caller is added to T and W.

[0124] In this way, relevant basic blocks are marked for inlining.

[0125] With reference again to FIG. 5, at 510, analysis of the control flow, dominance hierarchy and control dependence of the program is performed. The control flow, dominance hierarchy and control dependence may be recalculated at several stages throughout performance of the transpilation method.

[0126] At 512, the intermediate representation of basic blocks containing one or more stream operations is converted to single static analysis form. At this stage, each variable is assigned exactly once, and every variable is defined before it is used, but stream operation instructions themselves may not be arranged into SSA form.

[0127] At 514, a data-flow analysis is performed. Uses of a variable are mapped to prior assignment of that variable, such that for any given instruction the prior instructions which that given instruction has a “data-dependency” on are clear, and vice versa. As the generated code is in SSA form, if the assignment is not within the same basic block one can simply ascend the dominance tree until an assignment is found.

[0128] At 516 constant propagation is performed. From the data-flow analysis, expressions may be inspected to find if they are constant, or are simple expressions (or even intemal/extemal procedure calls) with constant arguments, and in such cases these expressions may be replaced by constant values. This reduces the data dependencies within the program, and makes argument analysis of key instructions, such as stream operation instructions, easier to perform/possible to perform.

[0129] At 520, basic blocks containing loops, in which the loops contain one or more stream operation instructions, are identified and the associated loops marked for unrolling. Loop unrolling, also known as loop unwinding, is a loop transformation technique that attempts to optimize a program's execution speed at the expense of its binary size. At 522 the marked loops are unrolled, and at 524 constant propagation is performed again. [0130] In any loop within the program in which a stream being accessed is marked as a variable in the loop, it is beneficial to unroll - copy and repeat the code to remove the looping - such that the stream being accessed is a constant. Once basic blocks containing stream operation instructions inside of loops are identified, loops may be marked for unrolling by locating non-constant stream identifiers within the identified basic blocks and, if a non-constant stream identifier is dependent on a loop-induction variable, marking the loop for unrolling. FIG. 7 illustrates a flowchart of a method 700 for marking loops for unrolling, unrolling the marked loops, and performing constant propagation. At 702 the method begins.

[0131] At 704, any natural loops in the program are identified. This may be performed using any known method. In one example, if one considers a control flow dependency graph, then any edge in the control flow from a dominating block is considered as a back edge forming a loop, with the loop header being the dominator and the loop body containing any basic blocks reachable from the header along a path that passes through the back edge. The skilled person would appreciate that any method may be used to detect loops in the program.

[0132] At 706, any combinable natural loops are combined - that is, any natural loops within the same loop header form a single natural loop.

[0133] At 708, induction variables are detected. Induction variables are in particular any variable that is assigned only to itself plus or minus some constant value within the loop body.

[0134] At 710, the stream operation instructions are searched for any non-constant stream identifiers. If any identifiers are dependent on loop-induction variables (i.e. if the stream identifier is non-constant within the loop) then the loop is marked for unrolling (712).

[0135] For any marked loops, the value of any escape expression is found at each iteration from loop-constants and induction variables, in order to calculate the iteration count (714).

[0136] At 716, any marked loop blocks are replaced with a repeatedly cloned body - the loop is unrolled - and it is ensured that jump instructions have their corresponding targets changed accordingly.

[0137] At 718, constant propagation is performed in order to make the stream identifiers constant. [0138] The method ends at 720. By unrolling loops in this way, it is easier to put the program into single stream state form.

[0139] With reference again to FIG. 5, at 526, the program is put into single stream state form. As described above in relation to FIG. 4, this single stream state form is an extension of the SSA form in which the basic block is converted into a form in which each stream operation instruction is dependent on at most one dominant stream instruction. [0140] From the single stream state form of the program, a stream dependence chain can be built at 528, in which each operation is marked as being dependent on a prior operation, and StreamPhi operations are marked as dependent on multiple prior operations. OPEN and CLOSE operations enable the same streams to be accessed without total dependence, effectively enabling the program to state clearly where unbroken control over the quantum information processor is required, and where it is not.

[0141] At 530, this single stream state form of the program is analysed to identify any subprograms for implementation on the one or more classical processors and to identify one or more subprograms for implementation on the quantum information processor. A method for detecting the subprograms is defined further below in relation to FIG. 8. FIG. 8 shows a flowchart of a method for analysing the (extended) static single assignment form (otherwise known as the single stream state form) to identify one or more subprograms for implementation on the one or more classical processors and the quantum information processor. In particular, from analysis of the single stream state form of the program, each stream operation instruction can be associated with a node of a stream dependence graph, with directed edges of the stream dependence graph indicating that one stream operation instruction is dependent on another. At 802, the method begins.

[0142] The stream dependence graph can be partitioned into connected subgraphs (804) (ignoring the directionality of the edges). A graph or subgraph is said to be connected when it has at least one vertex and there is a path between every pair of vertices.

[0143] Each connected subgraph of the stream dependence graph is modified to ensure strong connectivity (806). A graph is said to be strongly connected if every vertex of the graph is reachable from every other vertex. A directed graph or subgraph is strongly connected if there is a path in each direction between each pair of vertices of the graph. Accordingly, modifying each stream dependence subgraph may comprise ignoring the directionality of the edges and/or introducing additional edges.

[0144] At 808, a dependency graph is built by combining edges of control-dependence graphs, data-dependence graphs and stream-dependence graphs. A dependency graph is a directed graph representing dependencies of several objects towards each other. The dependency graph accordingly captures the dependencies between the various variables and streams of the program. [0145] At 810, strongly connected components of the dependency graph are found using Kosaraju's algorithm. Kosaraju's algorithm (also known as the Kosaraju-Sharir algorithm) is a linear time algorithm to find the strongly connected components of a directed graph. The skilled person would appreciate that other suitable algorithms may be used to determine the strongly connected components of the directed graph. Each of the strongly connected components of the directed graph represents a subprogram (812). The subprogram entry point is designated as the lowest common ancestor of all subprogram elements in the control dominance tree (814). The dominance frontier of the entry point marks points of assured exit - and subprogram points that flow into these nodes are marked as exits (816).

[0146] At 818, the method ends.

[0147] With reference again to FIG. 5, based on a target hardware configuration description, any stream operations in the identified subprograms are replaced with target hardware-specific code for controlling the analogue interaction means to interact with the quantum information processor. A method for transforming the program in this way is described further below in relation to FIG. 9. At 902, the method begins.

[0148] At 904, the subprogram is broken into basic blocks of stream operations, otherwise referred to as subroutines. In particular, a subprogram spans multiple basic blocks. For processing it is useful to group stream operation instructions by block (as when one executes, they all execute). A stream subroutine refers to a group of stream operation instructions within the same subroutine. [0149] At 906 the subroutines are passed to relevant hardware backends according to the streams used and any available target hardware configuration information. The backends may define an execution type for each subroutine, and statements are inserted into the main program based on the execution type where needed to trigger execution.

[0150] The backends may query data sources/target, including any actual data for constants (912). The backends may define which data is sent (914). Furthermore, statements are inserted into the main program to push/pull data to/from the relevant hardware where needed (916). At 918, the method of FIG. 9 ends.

[0151] Subprograms are not necessarily formed of contiguous instructions within the full program. They may be interleaved with other program elements, or even each other. They will also have dependencies (for example a data dependency on a variable that is used or set) with the external program. The subprograms are those portions of the program that are intended for distributed execution across available the various components of the distributed processing system. With reference again to FIG. 5, at 534, those subprograms are accordingly separated from those that occur both before and after the subprogram from the subprogram itself. This includes the configuration and data retrieval instructions produced at 532. A method for isolating the subprograms is provided further below in relation to FIG. 10.

[0152] With reference to FIG. 10, the method starts at 1002. At 1004, basic blocks reachable from subprogram entry without passing through an exit are marked as subprogram blocks. An “execution” block is inserted between an exit block and a non-subprogram block (1006). The exit block(s) of the subprogram is(are) defined as the blocks within the subprogram that may executed immediately prior to a non-subprogram block being executed.

[0153] At 1008, the block structure is cloned and inserted between the execution block and the non-subprogram block. The original block is referred to here as a “pre-process block” and the new block is referred to as a “post-process” block. Subprogram instructions are those that are within the subprogram (1010).

[0154] At 1012, 1014, and 1016, various blocks are marked. In particular, an instruction is marked as an “Input” instructions where the subprogram or another Input instruction has a dependency on it; an instruction is marked as an “Output” instruction if it is dependent on the program; and an instruction may be marked as “Parallel” if it is dependent on an instruction that is not in he subprogram and is not itself in the subprogram.

[0155] At 1018, output instructions are moved to a corresponding position in the Post-Processing block. Where a variable is assigned in a pre-processing block, instructions are inserted to push the value of the variable to a pipe (1020). A pipe comprises a first-in-first-out stack of variable values. This value can be retrieved in post-processing (1022). Conditional jump instructions in postprocessing are also modified to retrieve values from a pre-processing block via a pipe (1024). The method of FIG. 10 ends at 1026.

[0156] With reference again to FIG. 5, at 536, the program is translated into a standard high-level representation. That is, at 536, the code is translated into a transpiled classical-quantum hybrid program. The transpiled classical-quantum hybrid program differs from the initial classical- quantum hybrid program in several ways, most notably in that it contains some hardware-specific code in place of code pertaining to stream operations. The transpiled classical-quantum hybrid program is accordingly produced for execution by the distributed system controller.

[0157] The skilled person would appreciate that while in FIG. 5 the transpiled classical -quantum hybrid program is for execution on the distributed system controller which in turn controls the classical processors 150 and quantum information processor, the transpiled program may be designed for execution by another device. For example, the transpiled program may be executed on a PC located within the laboratory or otherwise having a low-latency communication with the hardware in the laboratory. The program may be configured to directly and seamlessly configure hardware to perform subprograms as needed during execution, or may be configured to instead submit configurations to a scheduling system.

[0158] At 538, the method ends.

[0159] Figure 11 illustrates a computer readable medium 1100 according to some examples. [0160] The computer readable medium 1100 stores units, with each unit including instructions 1110 that, when executed, cause a processor or other processing device to perform particular operations. The computer readable medium 1100 includes instructions 1110 that, when executed, cause a processing device to implement a method as described herein.

[0161] A computer-readable medium such as computer-readable medium 1000 may be able to interact with a device such as distributed system controller 200 via a port e.g. port 270 of the device 200

[0162] Variations of the described embodiments are envisaged, for example, the features of all the disclosed embodiments may be combined in any way.

[0163] For example, in one application, the methods used herein can be used as part of a calibration/tuning procedure for the distributed processing system.

[0164] It will be appreciated that embodiments of the present invention can be realised in the form of hardware, software or a combination of hardware and software. Any such software may be stored in the form of volatile or non-volatile storage such as, for example, a storage device like a ROM, whether erasable or rewritable or not, or in the form of memory such as, for example, RAM, memory chips, device or integrated circuits or on an optically or magnetically readable medium such as, for example, a CD, DVD, magnetic disk or magnetic tape. It will be appreciated that the storage devices and storage media are embodiments of machine-readable storage that are suitable for storing a program or programs that, when executed, implement embodiments of the present invention. Accordingly, embodiments provide a program comprising code for implementing a system or method as claimed in any preceding claim and a machine-readable storage storing such a program. Still further, embodiments of the present invention may be conveyed electronically via any medium such as a communication signal carried over a wired or wireless connection and embodiments suitably encompass the same

[0165] All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and/or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and/or steps are mutually exclusive.

[0166] Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features. The invention is not restricted to the details of any foregoing embodiments. The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one, or any novel combination, of the steps of any method or process so disclosed. The claims should not be construed to cover merely the foregoing embodiments, but also any embodiments which fall within the scope of the claims.

Claims

1. A method of transpiling a classical-quantum hybrid program to be executed by a distributed processing system, the distributed processing system comprising one or more classical processors and a quantum information processor interrogable via classical analogue interaction means, the classical-quantum hybrid program including a function to be executed by the quantum information processor, the method comprising: parsing the classical-quantum hybrid program to generate an intermediate representation of the classical-quantum hybrid program, the intermediate representation comprising a series of basic blocks, each basic block comprising a sequence of instructions; identifying basic blocks for which the sequence of instructions comprises one or more stream operation instructions, the one or more stream operation instructions configured to control interactions with the quantum information processor; analysing the identified basic blocks to identify one or more subprograms for implementation on the one or more classical processor and quantum information processor; based on a target hardware configuration description for the analogue interaction means, replacing the one or more stream operation instructions of the subprograms with target hardware-specific code for controlling the analogue interaction means to interact with the quantum information processor, to generate a hardware-specific intermediate representation of the classical-quantum hybrid program; and translating the hardware-specific intermediate representation of the classical- quantum hybrid program into a transpiled classical-quantum hybrid program.

2. A method according to claim 1, further comprising, subsequent to identifying basic blocks for which the sequence of instructions comprises one or more stream operation instructions: marking procedure calls for inlining, wherein a procedure comprises one or more basic blocks; and inlining the basic blocks containing the procedure calls marked for inlining.

3. A method according to claim 2, wherein marking procedure calls for inlining comprises: marking procedures containing one or more basic blocks for which the sequence of instructions comprises one or more stream operation instructions as belonging to a first set; marking procedures from which any marked procedure of the first set are reachable as belonging to a second set; combining the first set and the second set to form a third set; for each procedure in the third set; identifying all calling procedures which call that procedure; and if a calling procedure is in the third set, then the call is marked for inlining; if a calling procedure is in the second set and calls another procedure of the second set, then the call is marked for inlining and the calling procedure is added to the third set.

4. A method according to any preceding claim, wherein analysing the identified basic blocks to identify one or more subprograms comprises: converting the identified basic blocks into a static single assignment form and additionally ensuring each stream operation instruction is dependent on at most one dominating stream operation instruction; analysing the static single assignment form of the identified basic blocks to identify one or more subprograms for implementation on the one or more classical processor and quantum information processor.

5. A method according to any preceding claim, wherein analysing the identified basic blocks includes: marking loops within the identified basic blocks for unrolling; and unrolling the loops marked for unrolling.

6. A method according to claim 5 wherein marking loops within the identified basic blocks for unrolling comprises: locating non-constant stream identifiers within the identified basic blocks; and if a non-constant stream identifier is dependent on a loop-induction variable, then marking the loop for unrolling.

7. A method according to any preceding claim, wherein a stream operation instruction comprises one of: an OPEN instruction for activating a stream; a READ instruction for reading from an open stream; a WRITE instruction for writing to an open stream; a CLOSE instruction for deactivating an open stream.

8. A method according to any preceding claim, wherein ensuring each stream operation instruction is dependent on at most one dominating stream operation instruction comprises inserting a placeholder stream function wherever diverging paths of stream operations merge.

9. A method according to claim 4, wherein converting the identified basic blocks into a static single assignment form comprises analysing control flow, dominance hierarchy, and control dependence of the classical-quantum hybrid program.

10. A method according to claim 4 or claim 9, wherein analysing the basic blocks in static single assignment form comprises performing one or more of data flow analysis or constant propagation.

11. A method according to any preceding claim, wherein replacing the one or more stream operation instructions of the subprograms with target hardware-specific code for controlling the analogue interaction means comprises: identifying subroutines of the subprograms; passing the subroutines to hardware backends according to the stream operation instructions of the subprograms and the target hardware configuration description to enable the hardware backends to generate hardware configuration data and instructions and to define hardware data flow; inserting commands into the static single assignment form of the classical- quantum hybrid program to push/pull data to/from the hardware based on the configuration data, instructions and hardware data flow

12. A method according to claim 4 or claim 9 or claim 10, wherein analysing the static single assignment form of the identified basic blocks to identify one or more subprograms for implementation on the one or more classical processors and quantum information processor comprises: analysing stream-dependence of the static single assignment form to build a stream dependence graph; modifying connected subgraphs of the stream dependence graph to be strongly connected subgraphs; building a dependence graph based on the modified stream dependence graph, and control-dependence and data dependence of the static single assignment form of the classical -quantum hybrid program; and identifying strongly-connected subgraphs of the dependence graph as subprograms.

13. A method according to any preceding claim, further comprising receiving source code for the classical-quantum hybrid program.

14. A method according to any preceding claim, wherein the one or more classical processors comprise a field programmable gate array.

15. A method according to any preceding claim, further comprising distributing at least a part of the transpiled classical-quantum hybrid program to the one or more classical processors.

16. A computer-readable storage medium having instructions stored thereon which, when executed by one or more processors, cause the one or more processors to perform a method according to any preceding claim.

17. A computer-readable storage medium having stored thereon a transpiled classical- quantum hybrid program, the classical-quantum hybrid program transpiled according to a method according to any of claims 1 to 15.

18. A distributed system controller configured to transpile a classical-quantum hybrid program to be executed by a distributed processing system, the distributed processing system comprising the distributed system controller, one or more classical processors and a quantum information processor interrogable via classical analogue interaction means, the classical-quantum hybrid program including a function to be executed by the quantum information processor, the distributed system controller comprising: one or more memories; and one or more processors configured to: parse the classical-quantum hybrid program to generate an intermediate representation of the classical-quantum hybrid program, the intermediate representation comprising a series of basic blocks, each basic block comprising a sequence of instructions; identify basic blocks for which the sequence of instructions comprises one or more stream operation instructions, the one or more stream operation instructions configured to control interactions with the quantum information processor; analyse the identified basic blocks to identify one or more subprograms for implementation on the one or more classical processor and quantum information processor; based on a target hardware configuration description for the analogue interaction means, replace the one or more stream operation instructions of the subprograms with target hardware-specific code for controlling the analogue interaction means to interact with the quantum information processor, to a hardware-specific intermediate representation of the classical-quantum hybrid program; and translate the hardware-specific intermediate representation of the classical- quantum hybrid program into a transpiled classical-quantum hybrid program.

19. A distributed processing system comprising: a quantum information processor; one or more classical processors; and a distributed system controller configured to: parse the classical-quantum hybrid program to generate an intermediate representation of the classical-quantum hybrid program, the intermediate representation comprising a series of basic blocks, each basic block comprising a sequence of instructions; identify basic blocks for which the sequence of instructions comprises one or more stream operation instructions, the one or more stream operation instructions configured to control interactions with the quantum information processor; analyse the identified basic blocks to identify one or more subprograms for implementation on the one or more classical processor and quantum information processor; based on a target hardware configuration description for the analogue interaction means, replace the one or more stream operation instructions of the subprograms with target hardware-specific code for controlling the analogue interaction means to interact with the quantum information processor, to a hardware-specific intermediate representation of the classical-quantum hybrid program; and translate the hardware-specific intermediate representation of the classical- quantum hybrid program into a transpiled classical-quantum hybrid program.