WO2021161448A1

WO2021161448A1 - Semiconductor device

Info

Publication number: WO2021161448A1
Application number: PCT/JP2020/005553
Authority: WO
Inventors: 櫛田　知義; 喜隆長里; 直高岩田; 裕之榊
Original assignee: 株式会社デンソー; 学校法人トヨタ学園
Priority date: 2020-02-13
Filing date: 2020-02-13
Publication date: 2021-08-19
Also published as: JP7274156B2; JPWO2021161448A1

Abstract

This semiconductor device includes a semiconductor substrate, a source electrode, a drain electrode, and a gate electrode. The semiconductor substrate includes an upper layer, a middle layer, and a lower layer that are formed from a first semiconductor material, a first channel forming layer that is located between the upper layer and the middle layer, and a second channel forming layer that is located between the middle layer and the lower layer. The first and second channel forming layers each have one or a plurality of dissimilar material layers formed from a second semiconductor material having a bandgap which differs from that of the first semiconductor material. In the first channel forming layer, a two-dimensional carrier gas of a first conductivity type is generated at the pair of heterointerfaces formed on opposing sides of each dissimilar material layer. In the second channel forming layer, a two-dimensional carrier gas of a second conductivity type is generated at the pair of heterointerfaces formed on opposing sides of each dissimilar material layer. The source electrode and the drain electrode are in contact with one channel forming layer, and the gate electrode is in contact with or adjacent to the other channel forming layer.

Description

Semiconductor device

The technology disclosed herein relates to a semiconductor device having a plurality of heterointerfaces.

Patent Document 1 discloses a semiconductor device having a plurality of heterointerfaces. In this semiconductor device, a plurality of heterointerfaces are formed by alternately laminating two types of semiconductor materials, and two-dimensional electron gas and two-dimensional hole gas are alternately laminated at these heterointerfaces. Generated. According to such a configuration, it is possible to exhibit excellent withstand voltage when not energized while reducing resistance when energized. In the present specification, the two-dimensional electron gas and the two-dimensional hole gas may be collectively referred to as a two-dimensional carrier gas.

Japanese Unexamined Patent Publication No. 2019-57589

In the above-mentioned semiconductor device, the resistance at the time of energization can be further reduced by increasing the number of heterointerfaces, that is, the number of two-dimensional electron gas and two-dimensional hole gas. However, there is a problem that the thickness of the semiconductor substrate is increased due to the need for further multi-layering of the semiconductor substrate. In particular, it is necessary to provide a certain distance between the two-dimensional hole gas and the two-dimensional electron gas having different polarities. Therefore, in a structure in which two-dimensional hole gas and two-dimensional electron gas are alternately generated, it is necessary to form each layer relatively thick, and the thickness of the semiconductor substrate is relatively large due to the multi-layering. It will increase.

In view of the above, the present specification provides a technique capable of reducing resistance during energization while suppressing an increase in the thickness of a semiconductor substrate in a semiconductor device having a plurality of heterointerfaces.

The technology disclosed in this specification is embodied in the following semiconductor devices. This semiconductor device includes a semiconductor substrate and a source electrode, a drain electrode, and a gate electrode provided on the semiconductor substrate. The semiconductor substrate includes an upper layer, a middle layer and a lower layer made of a first semiconductor material, a first channel forming layer located between the upper layer and the middle layer, and a second channel forming layer located between the middle layer and the lower layer. And. Each of the first channel cambium and the second channel cambium has one or more dissimilar material layers composed of a second semiconductor material having a bandgap different from that of the first semiconductor material, and one or more of them. The thickness of each of the dissimilar material layers is smaller than the thickness of the middle layer. In the first channel forming layer, the first polar two-dimensional carrier gas (that is, the two-dimensional hole gas and the two-dimensional electron gas) are formed at a pair of heterointerfaces formed on both sides of one or more dissimilar material layers. On the other hand) is generated. In the second channel forming layer, a pair of heterointerfaces formed on both sides of one or more dissimilar material layers are of a second polar two-dimensional carrier gas (that is, a two-dimensional hole gas and a two-dimensional electron gas). The other) is generated. The source electrode and the drain electrode are in contact with one of the first channel cambium and the second channel cambium. The gate electrode is in contact with or adjacent to the other of the first channel cambium and the second channel cambium.

In the above-mentioned semiconductor device, by adjusting the voltage applied to the gate electrode, the first channel forming layer and the second channel forming layer are depleted, or two-dimensional carrier gas (that is, two-dimensional hole gas or two-dimensional hole gas or two-dimensional hole gas) or two-dimensional carrier gas (that is, two-dimensional hole gas) or two-dimensional carrier gas (that is, two-dimensional hole gas) or two-dimensional carrier gas (that is, two-dimensional hole gas or two). Dimensional electron gas) can be generated. When two-dimensional carrier gas is generated in the first channel cambium and the second channel cambium, the source electrode and the drain electrode are electrically connected via the first channel cambium or the second channel cambium. Will be done. In particular, each of the first channel cambium and the second channel cambium has at least a pair (that is, two or more even numbers) of heterointerfaces, and a two-dimensional carrier gas is generated along each heterointerface. Will be done. As a result, the source electrode and the drain electrode are electrically connected with a relatively low resistance.

Here, since only two-dimensional carrier gases having the same polarity are generated in each of the first channel cambium and the second channel cambium, it is not necessary to provide an interval between adjacent two-dimensional carrier gases. Therefore, it is possible to reduce the resistance at the time of energization by generating a large amount of two-dimensional carrier gas while suppressing an increase in the thickness of the semiconductor substrate. On the other hand, since a relatively thick middle layer exists between the first channel cambium and the second channel cambium, a sufficient distance should be provided between the two-dimensional carrier gases having different polarities. Can be done. As a result, it is possible to realize a semiconductor device in which resistance during energization is reduced while suppressing an increase in the thickness of the semiconductor substrate.

The technology disclosed in this specification is also embodied in the following semiconductor devices. This semiconductor device includes a semiconductor substrate and a first electrode and a second electrode provided on the semiconductor substrate. The semiconductor substrate includes an upper layer, a middle layer and a lower layer made of a first semiconductor material, a first channel forming layer located between the upper layer and the middle layer, and a second channel forming layer located between the middle layer and the lower layer. And. Each of the first channel cambium and the second channel cambium has one or more dissimilar material layers composed of a second semiconductor material having a bandgap different from that of the first semiconductor material, and one or more of them. The thickness of each of the dissimilar material layers is smaller than the thickness of the middle layer. In the first channel forming layer, the first polar two-dimensional carrier gas (that is, the two-dimensional hole gas and the two-dimensional electron gas) are formed at a pair of heterointerfaces formed on both sides of one or more dissimilar material layers. On the other hand) is generated. In the second channel forming layer, a pair of heterointerfaces formed on both sides of one or more dissimilar material layers are of a second polar two-dimensional carrier gas (that is, a two-dimensional hole gas and a two-dimensional electron gas). The other) is generated. The first electrode is in contact with one of the first channel cambium and the second channel cambium. The second electrode is in contact with the other of the first channel cambium and the second channel cambium.

In the above-mentioned semiconductor device, one of the first electrode and the second electrode serves as an anode, and the other of the first electrode and the second electrode serves as a cathode, which can function as a diode. For example, in a configuration in which a two-dimensional hole gas is generated in the first channel cambium and a two-dimensional electron gas is generated in the second channel cambium, the first electrode functions as an anode and the second electrode is a cathode. Functions as. On the other hand, if the configuration is such that two-dimensional electron gas is generated in the first channel cambium and two-dimensional hole gas is generated in the second channel cambium, the first electrode functions as a cathode and the second electrode is an anode. Functions as.

Also in this semiconductor device, since only two-dimensional carrier gases having the same polarity are generated in each of the first channel cambium and the second channel cambium, the distance between adjacent two-dimensional carrier gases is relatively small. can do. Therefore, the thickness of the first channel cambium and the second channel cambium can be made relatively small with respect to the number of two-dimensional carrier gases produced. On the other hand, since a relatively thick middle layer exists between the first channel cambium and the second channel cambium, a sufficient distance should be provided between the two-dimensional carrier gases having different polarities. Can be done. As a result, it is possible to realize a semiconductor device in which resistance during energization is reduced while suppressing an increase in the thickness of the semiconductor substrate.

The plan view which shows typically the semiconductor device 10A of Example 1. FIG. FIG. 2 is a cross-sectional view taken along the line II-II in FIG. 1, schematically showing a cross-sectional structure of the semiconductor device 10A of the first embodiment. The plan view which shows typically the semiconductor device 10B of Example 2. FIG. FIG. 2 is a cross-sectional view taken along the line II-II in FIG. 3, schematically showing a cross-sectional structure of the semiconductor device 10B of the second embodiment. The plan view which shows typically the semiconductor device 10C of Example 3. FIG. FIG. 5 is a cross-sectional view taken along the line VI-VI in FIG. 5, which is a plan view schematically showing a cross-sectional structure of the semiconductor device 10C of the third embodiment. FIG. 5 is a cross-sectional view taken along the line VII-VII in FIG. 5, schematically showing a cross-sectional structure of the semiconductor device 10C of the third embodiment. The plan view which shows typically the semiconductor device 10D of Example 4. FIG. FIG. 8 is a cross-sectional view taken along the line IX-IX in FIG. 8 and schematically shows a cross-sectional structure of the semiconductor device 10D of the fourth embodiment. The plan view which shows typically the semiconductor device 10E of Example 5. FIG. 10 is a cross-sectional view taken along the line XI-XI in FIG. 10, and schematically shows a cross-sectional structure of the semiconductor device 10E of the fifth embodiment. FIG. 10 is a cross-sectional view taken along the line XII-XII in FIG. 10, schematically showing a cross-sectional structure of the semiconductor device 10E of the fifth embodiment. The plan view which shows typically the semiconductor device 10F of Example 6. It is a cross-sectional view of XIV-XIV in FIG. 13, and shows schematically the cross-sectional structure of the semiconductor device 10F of Example 6. The plan view which shows typically the semiconductor device 10G of Example 7. FIG. 15 is a cross-sectional view taken along the line XVI-XVI in FIG. 15, schematically showing a cross-sectional structure of the semiconductor device 10G of the seventh embodiment. The plan view which shows typically the semiconductor device 10H of Example 8. FIG. 17 is a cross-sectional view taken along the line XVIII-XVIII in FIG. 17, which is a plan view schematically showing a cross-sectional structure of the semiconductor device 10H of the eighth embodiment. FIG. 5 is a plan view schematically showing the semiconductor device 10I of the ninth embodiment. FIG. 19 is a cross-sectional view taken along the line XX-XX in FIG. 19, which schematically shows a cross-sectional structure of the semiconductor device 10I of the ninth embodiment. The plan view which shows typically the semiconductor device 10J of Example 10. FIG. 21 is a cross-sectional view taken along the line XXII-XXII in FIG. 21, schematically showing a cross-sectional structure of the semiconductor device 10J of the tenth embodiment. FIG. 5 is a plan view schematically showing the semiconductor device 10K of the eleventh embodiment. FIG. 2 is a cross-sectional view taken along the line XXIV-XXIV in FIG. 23, schematically showing a cross-sectional structure of the semiconductor device 10K of the eleventh embodiment. The plan view which shows typically the semiconductor device 10L of Example 12. FIG. 5 is a cross-sectional view taken along the line XXVI-XXVI in FIG. 25, schematically showing a cross-sectional structure of the semiconductor device 10L of the twelfth embodiment. FIG. 5 is a cross-sectional view taken along the line XXVII-XXVII in FIG. 25, schematically showing a cross-sectional structure of the semiconductor device 10L of Example 12. The plan view which shows typically the semiconductor device 10M of Example 13. FIG. 28 is a cross-sectional view taken along the line XXIX-XXIX in FIG. 28, schematically showing a cross-sectional structure of the semiconductor device 10M of the thirteenth embodiment. The band diagram which shows the energy band in the thickness direction of the semiconductor substrate 12 in Example 13. The line Ec shows the lowest energy in the conduction band, the line Ev shows the maximum energy in the valence band, and the line Ef shows the energy at the Fermi level. The plan view which shows typically the semiconductor device 10N of Example 14. FIG. 3 is a cross-sectional view taken along the line XXXII-XXXII in FIG. 31, schematically showing a cross-sectional structure of the semiconductor device 10N of Example 14. The plan view which shows typically the semiconductor device 10P of Example 15. FIG. 3 is a cross-sectional view taken along the line XXXIV-XXXIV in FIG. 33, schematically showing a cross-sectional structure of the semiconductor device 10P of Example 15. The plan view which shows typically the semiconductor device 10Q of Example 16. FIG. 3 is a cross-sectional view taken along the line XXXVI-XXXVI in FIG. 35, schematically showing a cross-sectional structure of the semiconductor device 10Q of Example 16. FIG. 3 is a cross-sectional view taken along the line XXXVII-XXXVII in FIG. 35, schematically showing a cross-sectional structure of the semiconductor device 10Q of Example 16. The plan view which shows typically the semiconductor device 10R of Example 17. It is a cross-sectional view of XXXX-XXXIX in FIG. 38, and schematically shows the cross-sectional structure of the semiconductor device 10R of Example 17. The plan view which shows typically the semiconductor device 10S of Example 18. It is a cross-sectional view of XLI-XLI in FIG. 40, and schematically shows the cross-sectional structure of the semiconductor device 10S of Example 18. The plan view which shows typically the semiconductor device 10T of Example 19. FIG. 42 is a cross-sectional view taken along the line XLIII-XLIII in FIG. 42, schematically showing a cross-sectional structure of the semiconductor device 10T of Example 19. The plan view which shows typically the semiconductor device 10U of Example 20. FIG. 4 is a cross-sectional view taken along the line XLV-XLV in FIG. 44, schematically showing a cross-sectional structure of the semiconductor device 10U of the 20th embodiment.

In one embodiment of the present technology, the first conductive type (that is, either p-type or n-type) impurities may be introduced into the first channel cambium along the hetero interface. In addition, in the second channel cambium, impurities of the second conductive type (that is, the other of the p-type or the n-type) may be introduced along the hetero interface. As a result, carriers (holes or electrons) for generating a two-dimensional carrier gas can be supplied to the first channel cambium and / the second channel cambium.

In one embodiment of the present technology, the bandgap of the first semiconductor material may be narrower than the bandgap of the second semiconductor material. In this case, since the first polar two-dimensional carrier gas is generated outside the dissimilar material layer in the first channel cambium, the first conductive type impurities are introduced into the dissimilar material layer, although not particularly limited. It is good. Similarly, in the second channel cambium, the second polar two-dimensional carrier gas is formed outside the dissimilar material layer, so it is preferable that the second conductive type impurities are introduced into the dissimilar material layer. With such a configuration, it is possible to prevent the movement of carriers in the two-dimensional carrier gas from being hindered by impurities.

In the above-described embodiment, the first semiconductor material may be gallium arsenide (GaAs), and the second semiconductor material may be aluminum gallium arsenide (AlGaAs). Since the crystal growth of gallium arsenide is relatively easy, gallium arsenide can be preferably used as the first semiconductor material constituting the upper layer, the middle layer and the lower layer. However, as another embodiment, the first semiconductor material may be gallium nitride (GaN) and the second semiconductor material may be aluminum gallium nitride (AlGaN).

In one embodiment of the present technology, the bandgap of the first semiconductor material may be wider than the bandgap of the second semiconductor material. In this case, since the first polar two-dimensional carrier gas is generated in the dissimilar material layer in the first channel cambium, the first conductive type impurities are introduced outside the dissimilar material layer, although not particularly limited. It is good. Similarly, in the second channel cambium, since the second polar two-dimensional carrier gas is formed in the dissimilar material layer, the second conductive type impurities are introduced outside the dissimilar material layer, although not particularly limited. It is good. With such a configuration, it is possible to prevent the movement of carriers in the two-dimensional carrier gas from being hindered by impurities.

In the above-described embodiment, the first semiconductor material may be gallium arsenide (GaAs), and the second semiconductor material may be indium gallium arsenide (InGaAs). Alternatively, the first semiconductor material may be aluminum arsenide gallium (AlGaAs) and the second semiconductor material may be indium gallium arsenide (InGaAs). Alternatively, the first semiconductor material is _{indium aluminum gallium arsenate represented by the composition formula of In x} Al _y Ga _1-xy As (0 <x <0.3, 0 <y <0.5). The second semiconductor material may be indium aluminum gallium arsenium represented by the composition formula of _{In a} Al _b Ga _{1-ab As (a> x, y> b).}

In one embodiment of the present technology, a plurality of different material layers may be provided in each of the first channel cambium and the second channel cambium. In this case, a layer made of the first semiconductor material may be interposed between the plurality of dissimilar material layers. As the number of dissimilar material layers increases, more two-dimensional carrier gases are generated, which further reduces the resistance when energized.

In one embodiment of the present technology, in each of the first channel cambium and the second channel cambium, the distance between two heterointerfaces adjacent to each other may be 3 nm or more and 20 nm or less. According to such a structure, adjacent two-dimensional carrier gases can be superposed at least partially to increase the carrier concentration in the two-dimensional carrier gas. As a result, the thickness of the first channel cambium and the second channel cambium can be reduced while maintaining the total number of carriers.

In one embodiment of the present technology, a plurality of first-polarity two-dimensional carrier gases may be generated in the first channel cambium. In this case, in the plurality of two-dimensional carrier gases, the two-dimensional carrier gas having a shorter distance to the second channel cambium may have a larger carrier concentration. Similarly, in the second channel cambium, a plurality of second polar two-dimensional carrier gases may be generated. In this case, in the plurality of two-dimensional carrier gases, the two-dimensional carrier gas having a shorter distance to the first channel cambium may have a larger carrier concentration. According to such a configuration, it is possible to suppress or eliminate the time difference when the plurality of two-dimensional carrier gases are depleted in each of the first channel forming layer and the second channel forming layer. Therefore, the switching speed (time required for switching) of the semiconductor device can be improved.

In one embodiment of the present technology, the source electrode and the drain electrode may be in contact with the second channel cambium. In this case, the gate electrode may be in contact with the first channel cambium. Alternatively, the gate electrode may be provided in the upper layer and isolated from the first channel cambium via a part of the upper layer. According to the latter configuration, the gate electrode can be made relatively small and can be easily formed.

In one embodiment of the present technology, when the source electrode and the drain electrode are in contact with the second channel cambium, the gate electrode may extend from the upper layer through the first channel cambium to the middle layer. Then, the distance from the gate electrode to the second channel cambium may be shorter than the distance from the first channel cambium to the second channel cambium. According to such a configuration, the carrier concentration in the two-dimensional carrier gas can be reduced at a position close to the gate electrode, for example, in a recess gate structure in a high electron mobility transistor (HEMT). As a result, the threshold voltage (gate voltage required to cut off the current) can be increased, and a normally-off type or a semiconductor device close to the normal off type can be realized.

In the above-described embodiment, a plurality of second-polarity two-dimensional carrier gases may be generated in the second channel cambium. In this case, in the plurality of two-dimensional carrier gases, the two-dimensional carrier gas having a shorter distance to the gate electrode may have a larger carrier concentration. According to such a configuration, the carrier concentration of each of the plurality of two-dimensional carrier gases can be evenly reduced at a position close to the gate electrode, and the threshold voltage can be further increased.

In the above embodiment, the one or more two-dimensional carrier gases generated in the second channel cambium may be one or more two-dimensional electron gases. In this case, although not particularly limited, the gate electrode may be made of a semiconductor material into which a first conductive type impurity is introduced. According to such a configuration, a built-in electric field is formed between the p-type gate electrode and the n-type second channel cambium, and the threshold voltage can be further increased by the built-in electric field.

In some of the above-described embodiments, in particular, in the embodiment in which the source electrode and the drain electrode contact the second channel cambium, two recesses are provided on the upper surface of the semiconductor substrate to pass through the upper layer and reach the middle layer. May be good. In this case, the source electrode may extend from the bottom surface of one of the two recesses to the second channel cambium. The drain electrode may also extend from the other bottom surface of the two recesses to the second channel cambium. According to such a configuration, each of the source electrode and the drain electrode can be electrically connected to the second channel cambium while being electrically insulated from the first channel cambium by a relatively simple structure. can.

In one embodiment of the present technology, the source electrode and the drain electrode may be in contact with the first channel cambium. In this case, the gate electrode may extend from the upper layer through the first channel forming layer and the middle layer to the second channel forming layer, and may face the first channel forming layer in the upper layer. According to such a configuration, the first channel cambium connecting between the source electrode and the drain electrode passes between the gate electrode having the recess gate structure and the second channel cambium connected to the gate electrode. do. As a result, the carrier concentration of the first channel cambium is significantly reduced at the position where the first channel cambium passes, so that by increasing the threshold voltage, a normally-off type operation or an operation close to the normal off type can be realized.

In the above-described embodiment, a plurality of first-polarity two-dimensional carrier gases may be generated in the first channel cambium. In this case, in the plurality of two-dimensional carrier gases, each two-dimensional carrier gas located on both the upper and lower sides may have a larger carrier concentration than at least one two-dimensional carrier gas located between them. .. According to such a configuration, the carrier concentration of each of the plurality of two-dimensional carrier gases can be reduced evenly, and the threshold voltage can be made higher.

In some of the above-described embodiments, in particular, in the embodiment in which the source electrode and the drain electrode come into contact with the first channel cambium, a recess that passes through the upper layer and reaches the middle layer may be provided on the upper surface of the semiconductor substrate. .. In this case, the gate electrode may extend from the bottom surface of the recess toward the second channel cambium. According to such a configuration, the gate electrode can be brought into contact with or close to the second channel cambium while being electrically insulated from the first channel cambium by a relatively simple structure.

In one embodiment of the present technology, the semiconductor substrate is located above the upper layer and has an insulating property, and is located between the upper buffer layer and the upper layer, and is 1 × 10 ¹² / cm ² or more. An upper potential fixation layer having an interface state concentration may be further provided. When the semiconductor substrate has the upper potential fixed layer, the potential (electric field strength) in the upper layer can be fixed regardless of the structure above the upper potential fixed layer, and the channel concentration of the first channel forming layer ( Or the potential) is stable. Therefore, an additional structure such as a protective film can be freely provided above the upper potential fixing layer, and it is necessary to consider the influence on the first channel cambium 30 and the second channel cambium at that time. There is no.

In the above-described embodiment, the upper potential fixed layer may be composed of a group III-V compound semiconductor into which carbon (C), oxygen (O) or iron (Fe) has been introduced. In this case, although not particularly limited, the upper potential fixing layer may have a thickness of 1 nm to 10 μm. However, as another embodiment, the thickness of the upper potential fixed layer may be, for example, a thickness of several atomic layers or less, and an arbitrary crystal defect may be provided therein.

In addition to or in place of the above-mentioned upper potential fixing layer, the semiconductor substrate is located below the lower layer and has an insulating property, and is located between the lower buffer layer and the lower layer, and 1 × 10. Further, a lower potential fixing layer having an interface state concentration of ¹² / cm ^{2 or more may be further provided.} According to such a configuration, the potential (electric field strength) in the upper layer can be fixed regardless of the structure below the lower potential fixing layer, and the channel concentration (or potential) of the second channel cambium is stabilized. Can be done. Therefore, an additional structure such as a support substrate can be freely provided below the lower potential fixed layer, and it is necessary to consider the influence on the first channel cambium and the second channel cambium at that time. No.

The lower potential fixed layer may also be composed of a group III-V compound semiconductor into which carbon (C), oxygen (O) or iron (Fe) has been introduced. In this case, the lower potential fixing layer may have a thickness of 1 nm to 10 μm, although not particularly limited. However, as another embodiment, the thickness of the upper potential fixed layer may be, for example, a thickness of one atomic layer or less, or an arbitrary crystal defect may be provided therein.

(Example 1) The semiconductor device 10A of the first embodiment will be described with reference to FIGS. 1 and 2. The semiconductor device 10A of this embodiment includes a semiconductor substrate 12, a source electrode 14, a drain electrode 16, and a gate electrode 18 provided on the semiconductor substrate 12. The source electrode 14, the drain electrode 16, and the gate electrode 18 are not particularly limited, but are provided in a trench formed on the upper surface 12a of the semiconductor substrate 12. The source electrode 14, the drain electrode 16, and the gate electrode 18 are made of a conductive material. As an example, the source electrode 14 and the drain electrode 16 may be made of an n-type semiconductor (for example, n-GaAs), and the gate electrode 18 may be made of a p-type semiconductor (for example, p-GaAs). ..

The semiconductor substrate 12 is formed between the upper layer 20, the middle layer 22 and the lower layer 24, which are i-type semiconductor layers, the first channel cambium 30 located between the upper layer 20 and the middle layer 22, and the middle layer 22 and the lower layer 24. It includes a second channel cambium 40 located. The upper layer 20, the middle layer 22, and the lower layer 24 are made of the first semiconductor material. The thicknesses of the upper layer 20, the middle layer 22, and the lower layer 24 are not particularly limited, but may be several tens of nm to 1 μm. The first semiconductor material may be a group III-V compound semiconductor or other semiconductor material. A protective film 2 covering the upper surface 12a of the semiconductor substrate 12 is provided above the upper layer 20, and a support substrate 4 composed of a semi-insulating substrate is provided below the lower layer 24.

The first channel cambium 30 has one dissimilar material layer 32. The dissimilar material layer 32 is composed of a second semiconductor material having a bandgap different from that of the first semiconductor material. The thickness of the dissimilar material layer 32 is, for example, 3 nm to 50 nm, which is sufficiently smaller than the thickness of each of the upper layer 20, the middle layer 22, and the lower layer 24. The dissimilar material layer 32 is in contact with each of the upper layer 20 and the middle layer 22, and a pair of hetero interfaces 34 are formed on both sides of the dissimilar material layer 32. Then, two-dimensional hole gas 2DHG is generated along each hetero interface 34. Here, p-type impurities are introduced into the dissimilar material layer 32 of the first channel cambium 30, and holes are supplied from the dissimilar material layer 32 to the two-dimensional hole gas 2DHG. The second semiconductor material is not particularly limited, but may be a group III-V compound semiconductor or other semiconductor material.

The second channel cambium 40 has one dissimilar material layer 42. The dissimilar material layer 42 is made of a second semiconductor material, like the first channel cambium 30 described above. The thickness of the dissimilar material layer 42 is, for example, 3 nm to 50 nm, which is smaller than the thickness of each of the upper layer 20, the middle layer 22, and the lower layer 24. The dissimilar material layer 42 is in contact with each of the middle layer 22 and the lower layer 24, and a pair of hetero interfaces 44 are formed on both sides of the dissimilar material layer 42. Then, a two-dimensional electron gas 2DEG is generated along each hetero interface 44. Here, an n-type impurity is introduced into the dissimilar material layer 42 of the second channel forming layer 40, and electrons are supplied from the dissimilar material layer 42 to the two-dimensional electron gas 2DEG.

As an example, in the semiconductor device 10A of this embodiment, gallium arsenide (GaAs) is adopted as the first semiconductor material constituting the upper layer 20, the middle layer 22, and the lower layer 24, and the dissimilar material layers 32 and 42. Aluminum gallium arsenide (AlGaAs) is used as the second semiconductor material constituting the above. Therefore, in the semiconductor device 10A of the present embodiment, the band gap of the first semiconductor material (GaAs) is narrower than the band gap of the second semiconductor material (AlGaAs). The first semiconductor material and the second semiconductor material are not limited to these semiconductor materials. For example, the first semiconductor material may be gallium nitride (GaN) and the second semiconductor material may be aluminum gallium nitride (AlGaN). Even in this case, the band gap of the first semiconductor material is narrower than the band gap of the second semiconductor material.

Due to the magnitude relationship of the band gap described above, the two-dimensional hole gas 2DHG is formed on the outside of the dissimilar material layer 32 in the first channel cambium 30. Therefore, in the first channel cambium 30, p-type impurities are introduced inside the dissimilar material layer 32 so that the movement of holes is not hindered by the presence of impurities. Similarly, in the second channel cambium 40, the two-dimensional electron gas 2DEG is generated outside the dissimilar material layer 42. Therefore, in the second channel cambium 40, n-type impurities are introduced inside the dissimilar material layer 42 so that the movement of electrons is not hindered by the presence of impurities. However, in the first channel cambium 30, it is sufficient that p-type impurities are introduced along each hetero interface 34, and p-type impurities may be introduced outside the dissimilar material layer 32. In the second channel cambium 40 as well, n-type impurities may be introduced along each hetero interface 44, and n-type impurities may be introduced outside the dissimilar material layer 42.

Each of the source electrode 14 and the drain electrode 16 extends from the upper surface 12a of the semiconductor substrate 12 to the second channel cambium 40 and is in contact with the second channel cambium 40. As a result, the source electrode 14 and the drain electrode 16 are electrically connected to each other via the two-dimensional electron gas 2DEG of the second channel forming layer 40. On the other hand, the gate electrode 18 extends from the upper surface 12a of the semiconductor substrate 12 to the first channel cambium 30 and is in contact with the first channel cambium 30. As a result, the gate electrode 18 is electrically connected to the two-dimensional hole gas 2DHG of the first channel cambium 30.

Here, two recesses 12b are provided on the upper surface 12a of the semiconductor substrate 12. Each recess 12b passes through the upper layer 20 and reaches the middle layer 22. The source electrode 14 extends from the bottom surface of one of the two recesses 12b to the second channel cambium 40. The drain electrode 16 extends from the other bottom surface of the two recesses 12b to the second channel cambium 40. According to such a configuration, the source electrode 14 and the drain electrode 16 are electrically insulated from the first channel cambium 30 and electrically to the second channel cambium 40 by a relatively simple structure. Can be connected.

With the above configuration, in the semiconductor device 10A of the present embodiment, by adjusting the voltage applied to the gate electrode 18, the first channel forming layer 30 and the second channel forming layer 40 are depleted, or they are two-dimensionally positive. It is possible to generate a hole gas 2DHG and a two-dimensional electron gas 2DEG. When the two-dimensional electron gas 2DEG is generated in the second channel cambium 40, the source electrode 14 and the drain electrode 16 are electrically connected via the second channel cambium 40. In particular, the second channel cambium 40 has a pair (ie, two) heterointerfaces 44, and two-dimensional electron gas 2DEG is generated along each heterointerface 44. As a result, the source electrode 14 and the drain electrode 16 are electrically connected with a relatively low resistance.

On the other hand, when the first channel cambium 30 and the second channel cambium 40 are depleted, the source electrode 14 and the drain electrode 16 are electrically insulated from each other. Here, the direction in which the first channel forming layer 30 and the second channel forming layer 40 face each other (vertical direction in FIG. 2) is relative to the direction connecting the source electrode 14 and the drain electrode 16 (horizontal direction in FIG. 2). Are orthogonal to each other. Therefore, when the first channel cambium 30 and the second channel cambium 40 are depleted, the electric field caused by the depletion is also generated in the direction orthogonal to the direction in which the source electrode 14 and the drain electrode 16 are aligned. In this case, similarly to the so-called super junction structure, since the electric field strength becomes uniform between the source electrode 14 and the drain electrode 16, the semiconductor device 10A can realize a high off withstand voltage.

Here, in each of the first channel cambium 30 and the second channel cambium 40, only a two-dimensional carrier gas having the same polarity (that is, a two-dimensional hole gas 2DHG or a two-dimensional electron gas 2DEG) is generated. Therefore, in each of the first channel cambium 30 and the second channel cambium 40, it is not necessary to provide a space between adjacent two-dimensional carrier gases. Therefore, the thicknesses of the dissimilar material layers 32 and 42 can be sufficiently reduced. Thereby, the resistance at the time of energization can be reduced by generating a large amount of two-dimensional carrier gas (2DHG or 2DEG) while suppressing the thickness of the semiconductor substrate 12.

In the semiconductor device 10A of this embodiment, the upper layer 20, the middle layer 22, and the lower layer 24 are made of gallium arsenide (GaAs), and the dissimilar material layers 32 and 42 are made of aluminum gallium arsenide (GaAlAs). Here, aluminum gallium arsenide has a problem that the impurity concentration at the time of crystal growth is relatively high as compared with gallium arsenide. However, since the dissimilar material layers 32 and 42 made of aluminum gallium arsenide are sufficiently thinner than the upper layer 20, the middle layer 22 and the lower layer 24 made of gallium arsenide, the influence of such impurities can be suppressed. Can be done. As a result, for example, fluctuations in carrier concentration in the first channel cambium 30 and the second channel cambium 40 are suppressed.

In the semiconductor device 10A of this embodiment, as described above, the dissimilar material layers 32 and 42 made of aluminum gallium arsenide are sufficiently thinner than the upper layer 20, the middle layer 22 and the lower layer 24 made of gallium arsenide. .. According to such a configuration, even when two types of semiconductor materials are alternately crystal-grown, the accumulation of strain due to the difference in lattice constant is suppressed, so that the semiconductor substrate 12 having a multilayer structure is relatively easy. Can be manufactured in.

(Example 2) The semiconductor device 10B of the second embodiment will be described with reference to FIGS. 3 and 4. In the semiconductor device 10B of this embodiment, the configurations of the first channel forming layer 30 and the second channel forming layer 40 are changed as compared with the semiconductor device 10A of the first embodiment. In the following, the differences from the first embodiment will be mainly described, and the configurations common to the first embodiment will be designated by the same reference numerals, and duplicate description will be omitted.

The first channel cambium 30 has two dissimilar material layers 32. Each dissimilar material layer 32 is made of aluminum gallium arsenide and has p-type impurities introduced, as in the semiconductor device 10A of Example 1. A layer made of a first semiconductor material (that is, gallium arsenide) is interposed between the two dissimilar material layers 32. That is, the first channel cambium 30 has a structure in which the first semiconductor material and the second semiconductor material are alternately laminated. The distance between the two dissimilar material layers 32 may be about the same as the thickness of the dissimilar material layer 32, for example, 3 nm to 50 nm. In each dissimilar material layer 32, a pair of heterointerfaces 34 are formed on both sides thereof. Therefore, the first channel cambium 30 has four heterointerfaces 34. Then, two-dimensional hole gas 2DHG is generated along each hetero interface 34. Here, between the two dissimilar material layers 32 (that is, between the two adjacent hetero interfaces 34), the two two-dimensional hole gas 2DHGs are at least partially superposed, thereby apparently one two. Dimensional hole gas 2DHG may be generated.

Similarly, the second channel cambium 40 has two dissimilar material layers 42. Each dissimilar material layer 42 is made of aluminum gallium arsenide and has n-type impurities introduced, as in the semiconductor device 10A of Example 1. A layer made of a first semiconductor material (that is, gallium arsenide) is interposed between the two dissimilar material layers 42. That is, also for the second channel cambium 40, the distance between the two dissimilar material layers 32 having a structure in which the first semiconductor material and the second semiconductor material are alternately laminated is the same as the thickness of the dissimilar material layer 42. It may be about, for example, 3 nm to 50 nm. In each dissimilar material layer 42, a pair of hetero interfaces 44 are formed on both sides thereof. Therefore, the second channel cambium 40 also has four heterointerfaces 44. Then, a two-dimensional electron gas 2DEG is generated along each hetero interface 44. Here, between the two dissimilar material layers 42 (that is, the two adjacent heterointerfaces 44), the two two-dimensional electron gases 2DEG are at least partially superposed, so that they are apparently one two-dimensional. An electron gas 2DEG may be generated.

As described above, in the semiconductor device 10B of the present embodiment, each of the first channel forming layer 30 and the second channel forming layer 40 has two dissimilar material layers 32 and 42, whereby many

different material layers

32 and 42 are provided. Two-dimensional hole gas 2DHG or two-dimensional electron gas 2DEG is generated. According to such a configuration, since the source electrode 14 and the drain electrode 16 are connected via a large number of two-dimensional electron gas 2DEGs, the resistance at the time of energization is further reduced. The first channel cambium 30 and the second channel cambium 40 may each have three or more dissimilar material layers 32 and 42.

(Example 3) The semiconductor device 10C of the third embodiment will be described with reference to FIGS. 5 to 7. The semiconductor device 10C of this embodiment is different from the semiconductor device 10A of the first embodiment in the positions where the two-dimensional hole gas 2DHG and the two-dimensional electron gas 2DEG are generated. In the following, the differences from the first embodiment will be mainly described, and the configurations common to the first embodiment will be designated by the same reference numerals, and duplicate description will be omitted.

In the first channel cambium 30, n-type impurities are introduced into the dissimilar material layer 32, which is different from Example 1. Therefore, in the first channel cambium 30, two-dimensional electron gas 2DEG is generated along each hetero interface 34. On the other hand, in the second channel cambium 40, p-type impurities are introduced into the dissimilar material layer 42. Therefore, in the second channel cambium 40, two-dimensional hole gas 2DHG is generated along each hetero interface 44.

Each of the source electrode 14 and the drain electrode 16 extends from the upper surface 12a of the semiconductor substrate 12 to the first channel cambium 30 and is in contact with the first channel cambium 30. As a result, the source electrode 14 and the drain electrode 16 are electrically connected to each other via the two-dimensional electron gas 2DEG of the first channel forming layer 30. On the other hand, the gate electrode 18 extends from the upper surface 12a of the semiconductor substrate 12 through the first channel forming layer 30 to the second channel forming layer 40, and is in contact with the second channel forming layer 40. As a result, the gate electrode 18 is electrically connected to the two-dimensional hole gas 2DHG of the second channel cambium 40. The gate electrode 18 is electrically insulated from the first channel cambium 30 by, for example, an insulating region 19.

Although not particularly limited, as shown in FIGS. 6 and 7, the gate electrode 18 in this embodiment has a recess gate portion 18A and a pillar portion 18B. The recess gate portion 18A is provided in the upper layer 20 and extends parallel to the first channel cambium 30. The pillar portion 18B extends from the recess gate portion 18A to the second channel cambium 40 and is in contact with the second channel cambium 40. That is, the gate electrode 18 extends from the upper layer 20 through the first channel forming layer 30 and the middle layer 22 to the second channel forming layer 40, and faces the first channel forming layer 30 in the upper layer 20. There is. According to such a configuration, the first channel forming layer 30 connecting between the source electrode 14 and the drain electrode 16 is connected to the recess gate portion 18A of the gate electrode 18 and the second channel forming layer 40 connected to the gate electrode 18. Pass between and. Since the carrier concentration of the first channel cambium 30 drops significantly at the position where it passes, the threshold voltage of the semiconductor device 10C becomes high. As a result, the semiconductor device 10C can realize a normally-off type operation or an operation close to the normal off type.

(Example 4) The semiconductor device 10D of the fourth embodiment will be described with reference to FIGS. 8 and 9. In the semiconductor device 10D of the present embodiment, the second semiconductor material constituting the dissimilar material layers 32 and 42 is changed as compared with the semiconductor device 10A of the first embodiment. In the following, the differences from the first embodiment will be mainly described, and the configurations common to the first embodiment will be designated by the same reference numerals, and duplicate description will be omitted.

In the semiconductor device 10D of this embodiment, i-type indium gallium arsenide (i-InGaAs) is adopted as the second semiconductor material constituting the dissimilar material layers 32 and 42. On the other hand, as for the first semiconductor material constituting the upper layer 20, the middle layer 22, and the lower layer 24, i-type gallium arsenide (i-GaAs) is adopted as in the first embodiment. Therefore, in the semiconductor device 10D of the present embodiment, the band gap of the first semiconductor material (GaAs) is wider than the band gap of the second semiconductor material (InGaAs).

According to the magnitude relationship of the band gap described above, in the first channel cambium 30, a two-dimensional hole gas 2DHG is formed inside the dissimilar material layer 32. Therefore, in the first channel cambium 30, p-type impurities are introduced to the outside of the dissimilar material layer 32 so that the movement of holes is not hindered by the presence of impurities. Therefore, hole supply layers 36 made of p-type gallium arsenide (p-GaAs) are formed on both sides of the dissimilar material layer 32. Similarly, in the second channel cambium 40, the two-dimensional electron gas 2DEG is generated inside the dissimilar material layer 42. Therefore, in the second channel cambium 40, n-type impurities are introduced to the outside of the dissimilar material layer 42 so that the movement of electrons is not hindered by the presence of impurities. Therefore, electron supply layers 46 made of n-type gallium arsenide (n-GaAs) are formed on both sides of the dissimilar material layer 42.

The first semiconductor material and the second semiconductor material are not limited to the above combinations. For example, the first semiconductor material may be aluminum arsenide gallium (AlGaAs), and the second semiconductor material may be indium gallium arsenide (InGaAs). Alternatively, the first semiconductor material is _{indium aluminum gallium arsenate represented by the composition formula of In x} Al _y Ga _1-xy As (0 <x <0.3, 0 <y <0.5). The second semiconductor material may be indium aluminum gallium arsenium represented by the composition formula of _{In a} Al _b Ga _{1-ab As (a> x, y> b).} Even with these combinations, the bandgap of the first semiconductor material is wider than the bandgap of the second semiconductor material.

Also in the semiconductor device 10D of the present embodiment, in each of the first channel forming layer 30 and the second channel forming layer 40, two or more

different material layers

32 and 42 are laminated via the first semiconductor material. May be good. Further, as in the semiconductor device 10C of the third embodiment, the two-dimensional electron gas 2DEG is generated in the first channel forming layer 30, and the two-dimensional hole gas 2DHG is generated in the second channel forming layer 40. You may. Further, in addition to or in place of the hole supply layer 36 and the electron supply layer 46 described above, p-type impurities or n-type impurities may be introduced into the dissimilar material layers 32 and 42.

(Example 5) The semiconductor device 10E of the fifth embodiment will be described with reference to FIGS. 10-12. The semiconductor device 10E of the present embodiment has a structure in which the structure of the semiconductor device 10A of the first embodiment, particularly the laminated structure from the upper layer 20 to the lower layer 24, is repeated along the thickness direction of the semiconductor substrate 12. As described above, the semiconductor device 10E may include a plurality of combinations of the first channel cambium 30 and the second channel cambium 40. In this case, each of the source electrode 14 and the drain electrode 16 is in contact with the respective second channel cambium 40 and is electrically insulated from the respective first channel cambium 30 by, for example, the insulating

regions

15 and 17. It is good. Further, the gate electrode 18 may be in contact with each first channel cambium 30 and may be electrically insulated from each second channel cambium 40 by, for example, an insulating region 19.

In the semiconductor device 10E of this embodiment, the specific structures of the first channel forming layer 30 and the second channel forming layer 40 are not particularly limited. Various structures disclosed in the present specification can be appropriately adopted for the first channel cambium 30 and the second channel cambium 40.

(Example 6) The semiconductor device 10F of the sixth embodiment will be described with reference to FIGS. 13 and 14. In the semiconductor device 10F of this embodiment, the configurations of the first channel forming layer 30 and the second channel forming layer 40 are changed as compared with the semiconductor device 10A of the first embodiment. In the following, the differences from the first embodiment will be mainly described, and the configurations common to the first embodiment will be designated by the same reference numerals, and duplicate description will be omitted.

The first channel cambium 30 has one dissimilar material layer 32. As in the first embodiment, aluminum gallium arsenide is used as the second semiconductor material constituting the dissimilar material layer 32. However, in this embodiment, the p-type impurities are not introduced inside the dissimilar material layer 32, and the p-type impurities are introduced outside the dissimilar material layer 32. Therefore, the dissimilar material layer 32 is made of i-type aluminum gallium arsenide (i-AlGaAs), and both sides of the dissimilar material layer 32 are made of p-type gallium arsenide (p-GaAs). The hole supply layer 36 is formed. That is, in the first channel cambium 30 of this embodiment, the p-type impurity is introduced to the outside of the dissimilar material layer 32, and the two-dimensional hole gas 2DHG is generated to the outside of the dissimilar material layer 32. The first channel cambium 30 may have two or more dissimilar material layers 32.

Similarly, the second channel cambium 40 has one dissimilar material layer 42. The dissimilar material layer 42 is composed of i-type aluminum gallium arsenide (i-AlGaAs), and electrons composed of n-type gallium arsenide (n-GaAs) on both sides of the dissimilar material layer 42. The supply layer 46 is formed. That is, also in the second channel cambium 40, the n-type impurities are introduced to the outside of the dissimilar material layer 42, and the two-dimensional electron gas 2DEG is generated to the outside of the dissimilar material layer 32. The second channel cambium 40 may also have two or more dissimilar material layers 42.

(Example 7) The semiconductor device 10G of the seventh embodiment will be described with reference to FIGS. 15 and 16. In the semiconductor device 10G of this embodiment, the configurations of the first channel forming layer 30 and the second channel forming layer 40 are changed as compared with the semiconductor device 10A of the first embodiment. In the following, the differences from the first embodiment will be mainly described, and the configurations common to the first embodiment will be designated by the same reference numerals, and duplicate description will be omitted.

The first channel cambium 30 has two dissimilar material layers 32. Each dissimilar material layer 32 is made of aluminum gallium arsenide and has p-type impurities introduced, as in the semiconductor device 10A of Example 1. A layer made of a first semiconductor material (that is, gallium arsenide) is interposed between two adjacent dissimilar material layers 32. A pair of heterointerfaces 34 are formed on both sides of each dissimilar material layer 32, and four heterointerfaces 34 are present in the first channel cambium 30. Then, two-dimensional hole gas 2DHG is generated along each hetero interface 34.

The distance between two adjacent hetero interfaces 34 is 3 nm to 20 nm, which is relatively small. According to such a configuration, the carrier concentration (that is, the hole density) is obtained by at least partially superimposing the two two-dimensional hole gas 2DHG between the two dissimilar material layers 32 (X in the figure). Two-dimensional hole gas 2DHG with high density is generated. As a result, the thickness of the first channel cambium 30 can be reduced while maintaining the excellent conductivity (that is, low resistance) of the first channel cambium 30. In addition, between the two dissimilar material layers 32 (X), the distribution of the carrier concentration in the thickness direction is made uniform, so that the maximum electric field strength that can occur in the first channel cambium 30 is reduced. The first channel cambium 30 may have three or more dissimilar material layers 32.

Similarly, the second channel cambium 40 has two dissimilar material layers 42. Each dissimilar material layer 42 is made of aluminum gallium arsenide and has n-type impurities introduced, as in the semiconductor device 10A of Example 1. A layer made of a first semiconductor material (that is, gallium arsenide) is interposed between two adjacent dissimilar material layers 42. A pair of heterointerfaces 44 are formed on both sides of each dissimilar material layer 42, and four heterointerfaces 44 are present in the second channel cambium 40. Then, a two-dimensional electron gas 2DEG is generated along each hetero interface 44.

The distance between two adjacent hetero interfaces 44 is 3 nm to 20 nm, which is relatively small. According to such a configuration, the carrier concentration (that is, the electron density) is high by at least partially superimposing the two two-dimensional electron gases 2DEG between the two dissimilar material layers 42 (Y in the figure). Two-dimensional electron gas 2DEG is generated. As a result, the thickness of the second channel cambium 40 can be reduced while maintaining the excellent conductivity (that is, low resistance) of the second channel cambium 40. Further, since the distribution of the carrier concentration in the thickness direction is uniform between the two dissimilar material layers 42 (Y), the maximum electric field strength that can occur in the second channel cambium 40 is reduced. The second channel cambium 40 may also have three or more dissimilar material layers 32.

(Example 8) The semiconductor device 10H of the eighth embodiment will be described with reference to FIGS. 17 and 18. In the semiconductor device 10H of this embodiment, the configurations of the first channel forming layer 30 and the second channel forming layer 40 are changed as compared with the semiconductor device 10A of the first embodiment. In the following, the differences from the first embodiment will be mainly described, and the configurations common to the first embodiment will be designated by the same reference numerals, and duplicate description will be omitted.

The first channel cambium 30 has two dissimilar material layers 32. Each dissimilar material layer 32 is composed of i-type indium gallium arsenide (i-InGaAs). A layer made of a first semiconductor material (that is, gallium arsenide) is interposed between two adjacent dissimilar material layers 32. A pair of heterointerfaces 34 are formed on both sides of each dissimilar material layer 32, and four heterointerfaces 34 are present in the first channel cambium 30. Then, two-dimensional hole gas 2DHG is generated along each hetero interface 34. Here, the bandgap of indium gallium arsenide constituting the dissimilar material layer 32 is narrower than the bandgap of the first semiconductor material (that is, gallium arsenide) constituting the upper layer 20, the middle layer 22, the lower layer 24, and the like. Therefore, the two-dimensional hole gas 2DHG is generated inside the dissimilar material layer 32. A hole supply layer 36 made of p-type gallium arsenide (p-GaAs) is formed on both sides of each of the dissimilar material layers 32. The first channel cambium 30 may have three or more dissimilar material layers 32.

The thickness of each dissimilar material layer 32, that is, the distance between two adjacent hetero interfaces 34 is 3 nm to 20 nm, which is relatively small. According to such a configuration, two two-dimensional hole gas 2DHGs have a high carrier concentration (that is, hole density) by at least partially superimposing inside the dissimilar material layer 32. Is generated. As a result, the thickness of the first channel cambium 30 can be reduced while maintaining the excellent conductivity (that is, low resistance) of the first channel cambium 30. Further, since the carrier concentration is uniformly increased in all the two-dimensional hole gas 2DHG, the maximum electric field strength that can be generated in the first channel cambium 30 can be further reduced. As a result, the withstand voltage of the semiconductor device 10H is improved.

Similarly, the second channel cambium 40 has two dissimilar material layers 42. Each dissimilar material layer 42 is composed of i-type indium gallium arsenide (i-InGaAs). A layer made of a first semiconductor material (that is, gallium arsenide) is interposed between two adjacent dissimilar material layers 42. A pair of heterointerfaces 44 are formed on both sides of each dissimilar material layer 42, and four heterointerfaces 44 are present in the second channel cambium 40. Then, a two-dimensional electron gas 2DEG is generated along each hetero interface 44. These two-dimensional electron gas 2DEGs are generated inside the dissimilar material layer 42. An electron supply layer 46 made of n-type gallium arsenide (n-GaAs) is formed on both sides of each dissimilar material layer 42.

Also in the second channel cambium 40, the thickness of each dissimilar material layer 32, that is, the distance between two adjacent hetero interfaces 44 is 3 nm to 20 nm, which is relatively small. According to such a configuration, two two-dimensional electron gas 2DEGs are at least partially overlapped inside the dissimilar material layer 42 to generate a two-dimensional electron gas 2DEG having a high carrier concentration (that is, electron density). NS. As a result, the thickness of the second channel cambium 40 can be reduced while maintaining the excellent conductivity (that is, low resistance) of the second channel cambium 40. Further, since the carrier concentration is uniformly increased in all the two-dimensional electron gas 2DEG, the maximum electric field strength that can occur in the second channel cambium 40 can be further reduced. As a result, the withstand voltage of the semiconductor device 10H is improved.

In the semiconductor device 10H of this embodiment, the first semiconductor material and the second semiconductor material are not limited to the above combinations. For example, the first semiconductor material is _{aluminum gallium arsenide (AlGaAs) represented by the composition formula of Al x} Ga _1-x As (0 <x <1), and the second semiconductor material is In _y Ga. It may be indium gallium arsenide represented by the composition formula of _{1-y As (0 <y <0.5).} Alternatively, the first semiconductor material is _{indium aluminum gallium arsenate represented by the composition formula of In x} Al _y Ga _1-xy As (0 <x <0.3, 0 <y <0.5). The second semiconductor material may be indium aluminum gallium arsenium represented by the composition formula of _{In a} Al _b Ga _{1-ab As (a> x, y> b).} Even with these combinations, the bandgap of the first semiconductor material is wider than the bandgap of the second semiconductor material.

(Example 9) The semiconductor device 10I of the ninth embodiment will be described with reference to FIGS. 19 and 20. In the semiconductor device 10I of this embodiment, the configuration of the gate electrode 18 is changed as compared with the semiconductor device 10H of the eighth embodiment. In the following, the differences from the eighth embodiment will be mainly described, and the configurations common to the eighth embodiment will be designated by the same reference numerals and duplicated description will be omitted.

As shown in FIG. 20, in the semiconductor device 10I of this embodiment, the gate electrode 18 is provided in the upper layer 20 and is isolated from the first channel cambium 30 via a part of the upper layer 20. As described above, the gate electrode 18 does not necessarily have to be in contact with the first channel cambium 30 (or the second channel cambium 40). Even if the gate electrode 18 is separated from the first channel cambium 30, the gate electrode 18 and the first channel cambium 30 are electrically coupled by applying a voltage to the gate electrode 18, and the first channel cambium 30 is formed. 30 and the second channel cambium 40 can be depleted. Such a configuration of the gate electrode 18 can be adopted in all the examples described herein.

(Example 10) The semiconductor device 10J of the tenth embodiment will be described with reference to FIGS. 21 and 22. In the semiconductor device 10J of this embodiment, the configurations of the first channel forming layer 30 and the second channel forming layer 40 are changed as compared with the semiconductor device 10A of the first embodiment. In the following, the differences from the first embodiment will be mainly described, and the configurations common to the first embodiment will be designated by the same reference numerals, and duplicate description will be omitted.

The first channel cambium 30 has four dissimilar material layers 32. Each dissimilar material layer 32 is composed of i-type indium gallium arsenide (i-InGaAs). A layer made of a first semiconductor material (that is, gallium arsenide) is interposed between two adjacent dissimilar material layers 32. A pair of heterointerfaces 34 are formed on both sides of each dissimilar material layer 32, and eight heterointerfaces 34 are present in the first channel cambium 30. Then, two-dimensional hole gas 2DHG is generated along each hetero interface 34. Here, the bandgap of indium gallium arsenide constituting the dissimilar material layer 32 is narrower than the bandgap of the first semiconductor material (that is, gallium arsenide) constituting the upper layer 20, the middle layer 22, the lower layer 24, and the like. Therefore, the two-dimensional hole gas 2DHG is generated inside the dissimilar material layer 32. A hole supply layer 36 made of p-type gallium arsenide (p-GaAs) is formed on both sides of each of the dissimilar material layers 32.

Four two-dimensional hole gas 2DHGs are generated in the first channel cambium 30. Among the four two-dimensional hole gas 2DHGs, the two-dimensional hole gas 2DHG having a shorter distance to the second channel cambium 40 has a larger carrier concentration. That is, in the four two-dimensional hole gas 2DHGs shown in FIG. 22, the two-dimensional hole gas 2DHG located below has a larger carrier concentration. In order to form such a carrier concentration distribution, it is advisable to give a difference in impurity concentration to the plurality of hole supply layers 36. Since the carrier concentration of the two-dimensional hole gas 2DHG depends on the impurity concentration of the hole supply layer 36 adjacent thereto, the hole supply layer 36 having a shorter distance to the second channel cambium 40 has a higher impurity concentration. It is good to do.

Similarly, the second channel cambium 40 has four dissimilar material layers 42. Each dissimilar material layer 42 is composed of i-type indium gallium arsenide (i-InGaAs). A layer made of a first semiconductor material (that is, gallium arsenide) is interposed between two adjacent dissimilar material layers 42. A pair of heterointerfaces 44 are formed on both sides of each dissimilar material layer 42, and eight heterointerfaces 44 are present in the second channel cambium 40. Then, a two-dimensional electron gas 2DEG is generated along each hetero interface 44. These two-dimensional electron gas 2DEGs are generated inside the dissimilar material layer 42. An electron supply layer 46 made of n-type gallium arsenide (n-GaAs) is formed on both sides of each dissimilar material layer 42.

Four two-dimensional electron gas 2DEG is also generated in the second channel cambium 40. Among the four two-dimensional electron gas 2DEGs, the shorter the distance to the first channel cambium 30 is, the larger the carrier concentration is. That is, in the four two-dimensional electron gas 2DEG shown in FIG. 22, the two-dimensional electron gas 2DEG located above has a larger carrier concentration. In order to form such a carrier concentration distribution, it is advisable to give a difference in impurity concentration to the plurality of electron supply layers 46. Since the carrier concentration of the two-dimensional electron gas 2DEG depends on the impurity concentration of the electron supply layer 46 adjacent thereto, it is preferable that the electron supply layer 46 having a shorter distance to the first channel cambium 30 has a higher impurity concentration. ..

As described above, in the semiconductor device 10J of the present embodiment, a difference in carrier concentration is provided between the plurality of two-dimensional hole gas 2DHG and the plurality of two-dimensional electron gas 2DEG. According to such a configuration, it is possible to suppress or eliminate the time difference when the plurality of two-dimensional carrier gases are depleted in each of the first channel forming layer 30 and the second channel forming layer 40. Therefore, the switching speed (time required for switching) of the semiconductor device 10J can be improved.

(Example 11) The semiconductor device 10K of the eleventh embodiment will be described with reference to FIGS. 23 and 24. The semiconductor device 10K of this embodiment is modified in some respects as compared with the semiconductor device 10A of Example 1. In the following, the differences from the first embodiment will be mainly described, and the configurations common to the first embodiment will be designated by the same reference numerals, and duplicate description will be omitted.

In the semiconductor device 10K of this embodiment, i-type aluminum gallium arsenide (i-AlGaAs) is used as the first semiconductor material, and i-type gallium arsenide (i-) is used as the second semiconductor material. GaAs) is adopted. That is, the upper layer 20, the middle layer 22, and the lower layer 24 are composed of i-type gallium arsenide, and the dissimilar material layers 32 and 42 of the first channel forming layer 30 and the second channel forming layer 40 are i-type arsenide. It is composed of aluminum gallium arsenide (i-GaAs). In the first channel cambium 30, a pair of hole supply layers 36 are formed along both sides of the dissimilar material layer 32. Each hole supply layer 36 is composed of a first semiconductor material (that is, p-AlGaAs) into which p-type impurities have been introduced.

In the second channel cambium 40, a pair of electron supply layers 46 are formed along both sides of the dissimilar material layer 42. Each electron supply layer 46 is composed of a first semiconductor material (that is, n-AlGaAs) into which an n-type impurity has been introduced. Here, in the pair of electron supply layers 46, the concentrations of n-type impurities are different from each other. Specifically, the electron supply layer 46 closer to the gate electrode 18 (that is, the upper side in FIG. 24) is n than the electron supply layer 46 farther from the gate electrode 18 (that is, the lower side in FIG. 24). Type impurities are high.

In this embodiment, since the first semiconductor material is aluminum gallium arsenide and the second semiconductor material is gallium arsenide, the band gap of the first semiconductor material is larger than the band gap of the second semiconductor material. Is also widening. Therefore, in the first channel cambium 30, the two-dimensional hole gas 2DHG is formed inside the dissimilar material layer 32 along the hetero interface 34 formed on both sides of the dissimilar material layer 32. Similarly, in the second channel cambium 40, the two-dimensional electron gas 2DEG is formed inside the dissimilar material layer 42 along the hetero interface 44 formed on both sides of the dissimilar material layer 42. Each of the first channel forming layer 30 and the second channel forming layer 40 has two or more

different material layers

32 and 42, and is a hole supply layer 36 or an electron supply layer made of the first semiconductor material. It may have a structure in which 46 and dissimilar material layers 32 and 42 composed of a second semiconductor material are alternately laminated.

The gate electrode 18 passes from the upper layer 20 through the first channel cambium 30 and extends to the middle layer 22. As a result, the distance from the gate electrode 18 to the second channel cambium 40 is shorter than the distance from the first channel cambium 30 to the second channel cambium 40. According to such a configuration, at a position close to the gate electrode 18 (Z in FIG. 24), such as a recess gate structure in a high electron mobility transistor (HEMT), the two-dimensional electron gas 2DEG The carrier concentration can be reduced. As a result, the threshold voltage (gate voltage required to cut off the current) becomes high, so that the semiconductor device 10K can realize a normal-off type operation or an operation close to it.

In addition, in the second channel cambium 40 of this embodiment, as described above, the pair of electron supply layers 46 are provided with a difference in the concentration of n-type impurities, and the electron supply is close to the gate electrode 18. The layer 46 has a higher impurity concentration. According to such a configuration, in the second channel cambium 40, two two-dimensional electron gas 2DEGs are generated so that the shorter the distance to the gate electrode 18 is, the larger the carrier concentration is. As a result, at the position Z close to the gate electrode, the carrier concentration of each of the plurality of two-dimensional electron gases 2DEG can be uniformly reduced, and the threshold voltage can be further increased.

(Example 12) The semiconductor device 10L of the twelfth embodiment will be described with reference to FIGS. 25 to 27. The semiconductor device 10L of the present embodiment differs from the semiconductor device 10A of the first embodiment in some points. In the following, the differences from the first embodiment will be mainly described, and the configurations common to the first embodiment will be designated by the same reference numerals, and duplicate description will be omitted.

In the semiconductor device 10L of this embodiment, i-type indium gallium arsenide (i-InGaAs) is adopted as the second semiconductor material constituting the dissimilar material layers 32 and 42. On the other hand, as for the first semiconductor material constituting the upper layer 20, the middle layer 22, and the lower layer 24, i-type gallium arsenide (i-GaAs) is adopted as in the first embodiment. Therefore, in the semiconductor device 10D of the present embodiment, the band gap of the first semiconductor material (GaAs) is wider than the band gap of the second semiconductor material (InGaAs).

The first channel cambium 30 has a plurality of dissimilar material layers 32. A layer made of a first semiconductor material (that is, gallium arsenide) is interposed between two adjacent dissimilar material layers 32. On both sides of each of the dissimilar material layers 32, electron supply layers 36 into which n-type impurities have been introduced are formed. That is, the electron supply layer 36 is made of n-type gallium arsenide (n-GaAs) and is in contact with the dissimilar material layer 32 made of i-type indium arsenide aluminum gallium (i-InGaAs). .. Therefore, in each dissimilar material layer 32, a pair of heterointerfaces 34 are formed on both sides thereof, and a two-dimensional electron gas 2DEG is generated along each heterointerface 34. As described above, the bandgap of indium gallium arsenide is narrower than the bandgap of gallium arsenide, so that the two-dimensional electron gas 2DEG is generated inside the dissimilar material layer 32.

Similarly, the second channel cambium 40 has a plurality of dissimilar material layers 42. A layer made of a first semiconductor material (that is, gallium arsenide) is interposed between two adjacent dissimilar material layers 42. Hole supply layers 46 into which p-type impurities have been introduced are formed on both sides of each dissimilar material layer 42. That is, the hole supply layer 46 is made of p-type gallium arsenide (p-GaAs) and is in contact with the dissimilar material layer 42 made of i-type indium aluminum gallium arsenide (i-InGaAs). There is. Therefore, in each dissimilar material layer 42, a pair of heterointerfaces 44 are formed on both sides thereof, and two-dimensional hole gas 2DHG is generated along each heterointerface 44. This two-dimensional hole gas 2DHG is also generated inside the dissimilar material layer 42.

Each of the source electrode 14 and the drain electrode 16 extends from the upper surface 12a of the semiconductor substrate 12 to the first channel cambium 30 and is in contact with the first channel cambium 30. As a result, the source electrode 14 and the drain electrode 16 are electrically connected to each other via the two-dimensional electron gas 2DEG of the first channel forming layer 30. On the other hand, the gate electrode 18 extends from the upper surface 12a of the semiconductor substrate 12 to the second channel cambium 40 and is in contact with the second channel cambium 40. As a result, the gate electrode 18 is electrically connected to the two-dimensional hole gas 2DHG of the second channel cambium 40. The gate electrode 18 is electrically insulated from the first channel cambium 30 by, for example, an insulating region 19.

Here, the gate electrode 18 in this embodiment has a recess gate portion 18A and a pillar portion 18B. The recess gate portion 18A is provided in the upper layer 20 and extends parallel to the first channel cambium 30. The pillar portion 18B extends from the recess gate portion 18A to the second channel cambium 40 and is in contact with the second channel cambium 40. That is, the gate electrode 18 extends from the upper layer 20 through the first channel forming layer 30 and the middle layer 22 to the second channel forming layer 40, and faces the first channel forming layer 30 in the upper layer 20. There is. According to such a configuration, the first channel forming layer 30 connecting between the source electrode 14 and the drain electrode 16 is connected to the recess gate portion 18A of the gate electrode 18 and the second channel forming layer 40 connected to the gate electrode 18. Pass between and. Since the carrier concentration of the first channel cambium 30 drops significantly at the position where it passes, the threshold voltage of the semiconductor device 10L becomes high. As a result, the semiconductor device 10L can realize a normal-off type operation or an operation close to the normal-off type.

In addition, in the first channel cambium 30, a difference may be provided in the carrier concentration in the plurality of two-dimensional electron gases 2DEG. Specifically, each two-dimensional electron gas 2DEG located on both the upper and lower sides may have a larger carrier concentration than at least one two-dimensional electron gas 2DEG located between them. That is, a two-dimensional electron gas 2DEG having a shorter distance to the gate electrode 18 or the second channel cambium 40 may have a larger carrier concentration. According to such a configuration, the carrier concentration of each of the plurality of two-dimensional electron gas 2DEGs can be reduced evenly, and the threshold voltage can be made higher.

(Example 13) The semiconductor device 10M of the thirteenth embodiment will be described with reference to FIGS. 28 to 30. The semiconductor device 10M of this embodiment further includes an upper buffer layer 50, an upper potential fixing layer 52, a lower buffer layer 60, and a lower potential fixing layer 62 as compared with the semiconductor device 10A of the first embodiment. In the following, the differences from the first embodiment will be mainly described, and the configurations common to the first embodiment will be designated by the same reference numerals, and duplicate description will be omitted.

The upper buffer layer 50 is located above the upper layer 20 in the semiconductor substrate 12, and is interposed between the upper layer 20 and the protective film 2. The upper buffer layer 50 is made of an insulating or semi-insulating material. The material constituting the upper buffer layer 50 is not particularly limited, but may be, for example, type i gallium arsenide (that is, the first semiconductor material). The upper potential fixing layer 52 is located between the upper buffer layer 50 and the upper layer 20, and has an interface state concentration of ^{1 × 10 12} / cm ^{2 or more.} The thickness of the upper potential fixing layer 52 may be, for example, about 1 nm to 10 um, or may be a thickness of several atomic layers or less.

When the semiconductor substrate 12 has the upper potential fixing layer 52, the potential (electric field strength) in the upper layer 20 can be fixed regardless of the structure above the upper potential fixing layer 52. Thereby, the channel concentration in the first channel cambium 30 can be stabilized at a desired value. Therefore, an additional structure such as a protective film 2 can be freely provided above the upper potential fixing layer 52, and at that time, the influence on the first channel forming layer 30 and the second channel forming layer 40 can be exerted. No need to consider.

The lower buffer layer 60 is located below the lower layer 24 in the semiconductor substrate 12, and is interposed between the lower layer 24 and the support substrate 4. The lower buffer layer 60 is made of an insulating or semi-insulating material. The material constituting the lower buffer layer 60 is not particularly limited, but may be, for example, type i gallium arsenide (that is, the first semiconductor material). The lower potential fixing layer 62 is located between the lower buffer layer 60 and the lower layer 24, and has an interface state concentration of ^{1 × 10 12} / cm ^{2 or more.} The thickness of the lower potential fixing layer 62 may be, for example, about 1 nm to 10 um, or may be a thickness of several atomic layers or less.

Similar to the upper potential fixing layer 52 described above, when the semiconductor substrate 12 has the lower potential fixing layer 62, the potential (electric field strength) in the lower layer 24 is increased regardless of the structure below the lower potential fixing layer 62. It can be fixed (see FIG. 30). Thereby, the channel concentration in the second channel cambium 40 can be stabilized at a desired value. Further, by combining with the upper potential fixing layer 52, the channel concentration can be balanced between the first channel cambium 30 and the second channel cambium 40. Therefore, an additional structure such as a support substrate 4 can be freely provided below the lower potential fixing layer 62, and at that time, the influence on the first channel forming layer 30 and the second channel forming layer 40 can be exerted. No need to consider.

The specific configuration of the upper potential fixing layer 52 and the lower potential fixing layer 62 is not particularly limited. For example, even if each of the upper potential fixing layer 52 and the lower potential fixing layer 62 is composed of a group III-V compound semiconductor into which impurities such as carbon (C), oxygen (O) or iron (Fe) have been introduced. good. In this case, the group III-V compound semiconductor may be gallium nitride (GaN), aluminum gallium nitride (AlGaN), or a superlattice layer of gallium nitride and aluminum gallium nitride. In this case, the thickness of the upper potential fixing layer 52 and the lower potential fixing layer 62 can be about 1 nm to 10 um.

As another example, each of the upper potential fixing layer 52 and the lower potential fixing layer 62 may be delta-doped with impurities such as carbon, oxygen or iron. Alternatively, it may be a disorder of the crystal lattice of several atomic layers or less, such as unevenness of the interface. As long as the above numerical requirements for the interface state concentration are satisfied, the configurations of the upper potential fixing layer 52 and the lower potential fixing layer 62 are not particularly limited, and for example, the protective film 2 made of _{silicon oxide (SiO 2) and the like.} It may be the interface of. The interface state concentration of the upper potential fixing layer 52 and the lower potential fixing layer 62 can also be adjusted from the outside after the production of the semiconductor substrate 12 is completed. For example, in order to increase the interface state concentration, the semiconductor substrate 12 may be irradiated with ultraviolet rays or plasma. Alternatively, in order to reduce the interface state concentration, heat treatment such as lamp annealing or laser annealing may be performed.

(Example 14) The semiconductor device 10N of the 14th embodiment will be described with reference to FIGS. 31 and 32. In the semiconductor device 10N of this embodiment, the configurations of the first channel forming layer 30 and the second channel forming layer 40 are changed as compared with the semiconductor device 10M of the thirteenth embodiment. In the following, the differences from the thirteenth embodiment will be mainly described, and the same reference numerals will be given to the configurations common to the thirteenth embodiment to omit duplicated description.

In the semiconductor device 10N of this embodiment, in the semiconductor device 10N of this embodiment, indium gallium arsenide (InGaAs) is adopted as the second semiconductor material constituting the dissimilar material layers 32 and 42. On the other hand, as for the first semiconductor material constituting the upper layer 20, the middle layer 22, and the lower layer 24, i-type gallium arsenide (i-GaAs) is adopted as in Example 13. Therefore, in the semiconductor device 10N of this embodiment, the band gap of the first semiconductor material (GaAs) is wider than the band gap of the second semiconductor material (InGaAs). A p-type impurity is introduced into the dissimilar material layer 32 of the first channel cambium 30, and the p-type indium gallium arsenide (p-InGaAs) serves as a hole supply layer for supplying holes. Also works. Further, n-type impurities are introduced into the dissimilar material layer 42 of the second channel cambium 40, and the n-type indium gallium arsenide (n-InGaAs) also functions as an electron supply layer for supplying electrons. do.

According to the above configuration, in the first channel cambium 30, two-dimensional hole gas 2DHG is generated inside the dissimilar material layer 32 along the pair of heterointerfaces 34. At this time, when the thickness of the dissimilar material layer 32 is about 3 to 20 nm, the two two-dimensional hole gas 2DHG generated along the two hetero interfaces 34 are apparently superimposed at least partially. , Form one two-dimensional hole gas 2DHG. Similarly, in the second channel cambium 40, two-dimensional electron gas 2DEG is generated inside the dissimilar material layer 42 along the pair of heterointerfaces 44. When the thickness of the dissimilar material layer 42 is about 3 to 20 nm, the two two-dimensional electron gas 2DEG formed along the two hetero interfaces 44 are apparently one by superimposing at least partially. Generates two two-dimensional electron gas 2DEG.

(Example 15) The semiconductor device 10P of the 15th embodiment will be described with reference to FIGS. 33 and 34. The semiconductor device 10P of this embodiment differs from the semiconductor device 10M of the thirteenth embodiment in some respects. In the following, the differences from the thirteenth embodiment will be mainly described, and the same reference numerals will be given to the configurations common to the thirteenth embodiment to omit duplicated description.

The first channel cambium 30 has one dissimilar material layer 32. As in the first embodiment, aluminum gallium arsenide is used as the second semiconductor material constituting the dissimilar material layer 32. However, in the first channel cambium 30 of this embodiment, an n-type impurity is introduced into the dissimilar material layer 32, and a two-dimensional electron gas 2DEG is generated along each hetero interface 34. ing. The gate electrode 18 is in contact with the first channel cambium 30 and is electrically connected to the two-dimensional electron gas 2DEG. Therefore, the gate electrode 18 is not particularly limited, but is composed of an n-type semiconductor such as n-type gallium arsenide (n-GaAs). Further, the gate electrode 18 is electrically insulated from the first channel cambium 30 by, for example, an insulating region 19. The first channel cambium 30 may have two or more dissimilar material layers 32.

Similarly, the second channel cambium 40 has one dissimilar material layer 42. Aluminum gallium arsenide is also used as the second semiconductor material constituting the dissimilar material layer 42. However, in the second channel cambium 40 of this embodiment, p-type impurities are introduced into the dissimilar material layer 42, and a two-dimensional hole gas 2DHG is generated along each hetero interface 44. Has been done. The source electrode 14 and the drain electrode 16 are in contact with the first channel cambium 30 and are connected to each other via the two-dimensional hole gas 2DHG. Therefore, the source electrode 14 and the drain electrode 16 are not particularly limited, but are made of a p-type semiconductor such as p-type gallium arsenide (p-GaAs). The second channel cambium 40 may also have two or more dissimilar material layers 42.

In the semiconductor device 10P of this embodiment, the source electrode 14 and the drain electrode 16 are electrically connected to each other via the two-dimensional electron gas 2DEG of the first channel forming layer 30. On the other hand, the gate electrode 18 is electrically connected to the two-dimensional hole gas 2DHG of the second channel cambium 40. Even with such a configuration, by adjusting the voltage applied to the gate electrode 18, the first channel forming layer 30 and the second channel forming layer 40 can be depleted, or the two-dimensional electron gas 2DEG and the two-dimensional can be made into them. Hole gas 2DHG can be generated. As a result, the source electrode 14 and the drain electrode 16 can be electrically connected or cut off. The configuration in which the source electrode 14 and the drain electrode 16 are connected to each other via one or a plurality of two-dimensional hole gas 2DHGs is similarly adopted in the other embodiments disclosed in the present specification. can do.

(Example 16) The semiconductor device 10Q of the 16th embodiment will be described with reference to FIGS. 35-37. The semiconductor device 10Q of this embodiment further includes an upper buffer layer 50, an upper potential fixing layer 52, a lower buffer layer 60, and a lower potential fixing layer 62 as compared with the semiconductor device 10L of the twelfth embodiment. As described above, the upper potential fixing layer 52 and the lower potential fixing layer 62 can be added in any of the examples disclosed in the present specification. In the semiconductor device 10Q of this embodiment, each of the first channel forming layer 30 and the second channel forming layer 40 has a plurality of

different material layers

32 and 42. However, each of the first channel cambium 30 and the second channel cambium 40 may have at least one

dissimilar material layer

32, 42.

(Example 17) The semiconductor device 10R of the 17th embodiment will be described with reference to FIGS. 38 and 39. In the semiconductor device 10R of this embodiment, the positions of the source electrode 14, the drain electrode 16 and the gate electrode 18 are changed as compared with the semiconductor device 10M of the thirteenth embodiment. Further, the first channel cambium 30 is configured to generate a two-dimensional electron gas 2DEG, and the second channel cambium 40 is configured to generate a two-dimensional hole gas 2DHG. Also in this respect, Example 13 It is different from the semiconductor device 10M of. In the following, the differences from the thirteenth embodiment will be mainly described, and the same reference numerals will be given to the configurations common to the thirteenth embodiment to omit duplicated description.

In the first channel cambium 30, n-type impurities are introduced into the dissimilar material layer 32, which is different from Example 13. Therefore, in the first channel cambium 30, two-dimensional electron gas 2DEG is generated along each hetero interface 34. On the other hand, in the second channel cambium 40, p-type impurities are introduced into the dissimilar material layer 42. Therefore, in the second channel cambium 40, two-dimensional hole gas 2DHG is generated along each hetero interface 34. As described in Example 1, the first semiconductor material constituting the upper layer 20, the middle layer 22, and the lower layer 24 is gallium arsenide (GaAs), and the second semiconductor material constituting the dissimilar material layers 32 and 42. The semiconductor material is aluminum gallium arsenide (AlGaAs).

Each of the source electrode 14 and the drain electrode 16 extends from the upper surface 12a of the semiconductor substrate 12 to the first channel cambium 30 and is in contact with the first channel cambium 30. As a result, the source electrode 14 and the drain electrode 16 are electrically connected to each other via the two-dimensional electron gas 2DEG of the first channel forming layer 30. On the other hand, the gate electrode 18 is located on the recess 12b provided on the upper surface 12a of the semiconductor substrate 12, and extends from the bottom surface of the recess 12b to the second channel cambium 40. As a result, the gate electrode 18 is electrically connected to the two-dimensional hole gas 2DHG of the second channel cambium 40. The recess 12b extends from the upper layer 20 to the middle layer 22 and exposes the middle layer 22. By providing the gate electrode 18 in the recess 12b, the gate electrode 18 can be easily insulated from the first channel cambium 30.

The structure in which the gate electrode 18 is provided on the recess 12b can be similarly adopted in some other examples disclosed in the present specification. Further, the number of recesses 12b and gate electrodes 18 is not limited to one, and a plurality of them may be provided. Further, in the semiconductor device 10R of this embodiment, the upper buffer layer 50, the upper potential fixing layer 52, the lower buffer layer 60, and the lower potential fixing layer 62 are not always required.

(Example 18) The semiconductor device 10S of the 18th embodiment will be described with reference to FIGS. 40 and 41. In the semiconductor device 10S of this embodiment, the second semiconductor material constituting the dissimilar material layers 32 and 42 is changed as compared with the semiconductor device 10M of the thirteenth embodiment. In the following, the differences from the thirteenth embodiment will be mainly described, and the same reference numerals will be given to the configurations common to the thirteenth embodiment to omit duplicated description.

In the semiconductor device 10S of this embodiment, i-type indium gallium arsenide (i-InGaAs) is adopted as the second semiconductor material constituting the dissimilar material layers 32 and 42. On the other hand, as for the first semiconductor material constituting the upper layer 20, the middle layer 22, and the lower layer 24, i-type gallium arsenide (i-GaAs) is adopted as in Example 13. Therefore, in the semiconductor device 10S of the present embodiment, the band gap of the first semiconductor material (GaAs) is wider than the band gap of the second semiconductor material (InGaAs).

Here, the semiconductor device 10S of the present embodiment is also a semiconductor device 10D of the fourth embodiment to which the upper buffer layer 50, the upper potential fixing layer 52, the lower buffer layer 60, and the lower potential fixing layer 62 are added. .. As described in the fourth embodiment, also in the semiconductor device 10S of the present embodiment, the first semiconductor material and the second semiconductor material are not limited to the above-mentioned combination.

(Example 19) The semiconductor device 10T of the 19th embodiment will be described with reference to FIGS. 42 and 43. Compared with the semiconductor device 10M of the thirteenth embodiment, the semiconductor device 10T of this embodiment includes a first semiconductor material constituting the upper layer 20, the middle layer 22, and the lower layer 24, and a

second material layer

32, 42. The semiconductor materials of are changed respectively. In the following, the differences from the thirteenth embodiment will be mainly described, and the same reference numerals will be given to the configurations common to the thirteenth embodiment to omit duplicated description.

In the semiconductor device 10T of this embodiment, each of the upper layer 20, the middle layer 22, and the lower layer 24 is composed of i-type gallium nitride (i-GaN). On the other hand, aluminum gallium nitride (AlGaN) is used as the second semiconductor material constituting the dissimilar material layers 32 and 42. The bandgap of gallium nitride is narrower than the bandgap of aluminum gallium nitride. Therefore, in the first channel cambium 30, two-dimensional hole gas 2DHG is generated outside the dissimilar material layer 32, so that p-type impurities are introduced inside the dissimilar material layer 32. Similarly, in the second channel cambium 40, since the two-dimensional electron gas 2DEG is generated outside the dissimilar material layer 42, n-type impurities are introduced inside the dissimilar material layer 42. Further, the support substrate 4 is not particularly limited, but a silicon carbide (SiC) substrate having insulating properties is adopted. However, the support substrate 4 is not limited to a silicon carbide (SiC) substrate, and may be a silicon (Si) or gallium nitride (GaN) substrate.

(Example 20) The semiconductor device 10T of the 19th embodiment will be described with reference to FIGS. 44 and 45. The semiconductor device 10T of this embodiment functions as a tie, and is different from the semiconductor device 10A-10S of the above-described embodiment in this respect.

As shown in FIGS. 42 and 43, the semiconductor device 10T includes a semiconductor substrate 12 and an anode electrode 14'and a cathode electrode 16'provided on the semiconductor substrate 12. The anode electrode 14'and the cathode electrode 16'are not particularly limited, but are provided in a trench formed on the upper surface 12a of the semiconductor substrate 12. The anode electrode 14'and the cathode electrode 16'are made of a conductive material. As an example, the anode electrode 14'may be composed of a p-type semiconductor (for example, p-GaAs), and the cathode electrode 16'may be composed of an n-type semiconductor (for example, n-GaAs).

The semiconductor substrate 12 includes an upper layer 20, a middle layer 22, and a lower layer 24 made of a first semiconductor material, a first channel cambium 30 located between the upper layer 20 and the middle layer 22, and a middle layer 22 and a lower layer 24. It includes a second channel cambium 40 located between them. The upper layer 20, the middle layer 22, and the lower layer 24 are made of i-type gallium nitride (i-GaN). As the first semiconductor material constituting the upper layer 20, the middle layer 22, and the lower layer 24, various semiconductor materials can be adopted as understood from the various examples described above.

Each of the first channel cambium 30 and the second channel cambium 40 may have one or more dissimilar material layers 32 and 42. The dissimilar material layers 32 and 42 are made of, for example, aluminum gallium nitride (AlGaN). As for the second semiconductor material constituting the dissimilar material layers 32 and 42, various semiconductor materials can be adopted as understood from the various examples described above. The thickness of each of the one or more dissimilar material layers 32, 42 is sufficiently smaller than the thickness of the upper layer 20, the middle layer 22, and the lower layer 24. In the first channel cambium 30, a pair of heterointerfaces 34 are formed on both sides of each of the one or more dissimilar material layers 32, and two-dimensional hole gas 2DHG is generated along each heterointerface 34. NS. In the second channel cambium 40, a pair of hetero interfaces 44 are formed on both sides of each of the one or more dissimilar material layers 42, and a two-dimensional electron gas 2DEG is generated along each hetero interface 44. ..

The anode electrode 14'is in contact with the first channel cambium 30 and is electrically connected to the two-dimensional hole gas 2DHG in the first channel cambium 30. The cathode electrode 16'is in contact with the second channel cambium 40 and is electrically connected to the two-dimensional electron gas 2DEG in the second channel cambium 40. Here, the cathode electrode 16'is located in the recess 12b formed on the upper surface 12a of the semiconductor substrate 12, and extends from the bottom surface of the recess 12b to the second channel cambium 40.

With the above configuration, in the semiconductor device 10T of this embodiment, a structure similar to a PIN diode (p-intrinsic-n diode) is formed between the anode electrode 14'and the cathode electrode 16'. Therefore, when a positive voltage is applied to the anode electrode 14'with respect to the cathode electrode 16', the anode electrode 14'and the cathode electrode 16' are electrically connected. At this time, holes move at high speed in the two-dimensional hole gas 2DHG in the first channel cambium 30, and electrons move at high speed in the two-dimensional electron gas 2DEG in the second channel forming layer 40. Is significantly suppressed.

On the other hand, when a negative voltage is applied to the anode electrode 14'with respect to the cathode electrode 16', the first channel forming layer 30 and the second channel forming layer 40 are depleted, so that the cathode electrode 16'and the anode electrode are depleted. It is electrically insulated from 14'. Here, the direction in which the first channel forming layer 30 and the second channel forming layer 40 face each other (vertical direction in FIG. 45) is the direction connecting the anode electrode 14'and the cathode electrode 16' (horizontal direction in FIG. 45). Is approximately orthogonal to. Therefore, when the first channel cambium 30 and the second channel cambium 40 are depleted, the electric field caused by the depletion is also in a direction substantially orthogonal to the direction in which the anode electrode 14'and the cathode electrode 16'are aligned. appear. In this case, similarly to the so-called super junction structure, since the electric field strength becomes uniform between the anode electrode 14'and the cathode electrode 16', the semiconductor device 10U can realize a high withstand voltage.

The configuration of the semiconductor device 10U can be changed in various ways. For example, the anode electrode 14'may be configured to be in contact with the second channel cambium 40, and the cathode electrode 16'may be configured to be in contact with the first channel cambium 30. In this case, the first channel cambium 30 may be configured to generate two-dimensional electron gas 2DEG, and the second channel cambium 40 may be configured to generate two-dimensional hole gas 2DHG. Further, the first channel cambium 30 and the second channel cambium 40 may have two or more dissimilar material layers 32 and 42. For the semiconductor substrate 12 in this embodiment, the configuration of the semiconductor substrate 12 in the above-mentioned Examples 1-19 can be adopted alone or in various combinations.

The specific examples of the technology disclosed in the present specification have been described in detail above, but these are merely examples and do not limit the scope of claims. The techniques described in the claims include various modifications and modifications of the specific examples illustrated above. The technical elements described in the present specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. The techniques illustrated in the present specification or drawings can achieve a plurality of objectives at the same time, and achieving one of the objectives itself has technical usefulness.

2: Protective film 4: Support substrate 10A-10U: Semiconductor device 12: Semiconductor substrate 14: Source electrode 14': Electrode electrode 16: Drain electrode 16': Cathode electrode 18: Gate electrode 20: Upper layer 22: Middle layer 24: Lower layer 30 : 1st channel forming layer 32: Dissimilar material layer of 1st channel forming layer 34: Hetero interface 36 of 1st channel forming layer: Hole supply layer or electron supply layer of 1st channel forming layer 40: 2nd channel forming layer 42: Dissimilar material layer of the second channel forming layer 44: Hetero interface of the second channel forming layer 46: Hole supply layer or electron supply layer of the second channel forming layer 50: Upper buffer layer 52: Upper potential fixing layer 60: Lower buffer layer 62: Lower potential fixed layer

Claims

With a semiconductor substrate
A source electrode, a drain electrode, and a gate electrode provided on the semiconductor substrate are provided.
The semiconductor substrate is
The upper layer, middle layer and lower layer composed of the first semiconductor material,
A first channel cambium located between the upper layer and the middle layer,
A second channel cambium located between the middle layer and the lower layer is provided.
Each of the first channel cambium and the second channel cambium has one or more dissimilar material layers composed of a second semiconductor material having a bandgap different from that of the first semiconductor material.
The thickness of each of the one or more dissimilar material layers is smaller than the thickness of the middle layer.
In the first channel cambium, a first polar two-dimensional carrier gas is generated at a pair of heterointerfaces formed on both sides of each of the one or more dissimilar material layers.
In the second channel cambium, a second polar two-dimensional carrier gas is generated at a pair of heterointerfaces formed on both sides of each of the one or more dissimilar material layers.
The source electrode and the drain electrode are in contact with one of the first channel cambium and the second channel cambium.
The gate electrode is in contact with or adjacent to the other of the first channel cambium and the second channel cambium.
Semiconductor device.
In the first channel cambium, first conductive type impurities are introduced along the hetero interface.
The semiconductor device according to claim 1, wherein a second conductive type impurity is introduced into the second channel cambium along the hetero interface.
The bandgap of the first semiconductor material is narrower than the bandgap of the second semiconductor material.
In the first channel cambium, the first conductive type impurities are introduced into the dissimilar material layer, and the first polar two-dimensional carrier gas is generated outside the dissimilar material layer.
Claimed in the second channel cambium, the second conductive type impurity is introduced into the dissimilar material layer, and the second polar two-dimensional carrier gas is generated outside the dissimilar material layer. 2. The semiconductor device according to 2.
The first semiconductor material is gallium arsenide (GaAs), and the second semiconductor material is aluminum gallium arsenide (AlGaAs), or
The semiconductor device according to claim 3, wherein the first semiconductor material is gallium nitride (GaN), and the second semiconductor material is gallium nitride (AlGaN).
The bandgap of the first semiconductor material is wider than the bandgap of the second semiconductor material.
In the first channel cambium, the first conductive type impurities are introduced outside the dissimilar material layer, and the first polar two-dimensional carrier gas is generated in the dissimilar material layer.
Claimed that in the second channel cambium, the second conductive type impurities are introduced outside the dissimilar material layer, and the second polar two-dimensional carrier gas is generated in the dissimilar material layer. 2. The semiconductor device according to 2.
The first semiconductor material is gallium arsenide (GaAs), and the second semiconductor material is indium gallium arsenide (InGaAs), or
The first semiconductor material is aluminum gallium arsenide (AlGaAs), and the second semiconductor material is indium gallium arsenide (InGaAs), or
The first semiconductor material is indium aluminum gallium arsenium represented by the composition formula of In x Al y Ga 1-xy As (0 <x <0.3, 0 <y <0.5). The second semiconductor material is indium aluminum gallium arsenium represented by the composition formula of In a Al b Ga 1-ab As (a> x, y> b), according to claim 5. Semiconductor device.
The semiconductor device according to any one of claims 1 to 6, wherein each of the first channel cambium and the second channel cambium is provided with the plurality of different material layers.
The semiconductor device according to any one of claims 1 to 7, wherein in each of the first channel cambium and the second channel cambium, the distance between two heterointerfaces adjacent to each other is 3 nm or more and 20 nm or less.
In the first channel cambium, a plurality of the first polar two-dimensional carrier gases are generated, and in the plurality of two-dimensional carrier gases, the shorter the distance to the second channel cambium, the larger the two-dimensional carrier gas. Has a carrier concentration and
In the second channel cambium, a plurality of the second polar two-dimensional carrier gases are generated, and in the plurality of two-dimensional carrier gases, the shorter the distance to the first channel cambium is, the higher the carrier concentration is. The semiconductor device according to any one of claims 1 to 8.
The source electrode and the drain electrode are in contact with the second channel cambium.
The semiconductor device according to any one of claims 1 to 9, wherein the gate electrode is in contact with the first channel cambium.
The source electrode and the drain electrode are in contact with the second channel cambium.
The semiconductor device according to any one of claims 1 to 9, wherein the gate electrode is provided in the upper layer and is isolated from the first channel cambium via a part of the upper layer.
The source electrode and the drain electrode are in contact with the second channel cambium.
The gate electrode extends from the upper layer through the first channel cambium to the middle layer.
The semiconductor device according to any one of claims 1 to 9, wherein the distance from the gate electrode to the second channel cambium is shorter than the distance from the first channel cambium to the second channel cambium. ..
In the second channel cambium, a plurality of the two-dimensional carrier gases of the second polarity are generated, and in the plurality of two-dimensional carrier gases, the shorter the distance to the gate electrode, the higher the carrier concentration. The semiconductor device according to claim 12.
The one or more two-dimensional carrier gases generated in the second channel cambium are one or more two-dimensional electron gases.
The semiconductor device according to claim 13, wherein the gate electrode is made of a semiconductor material into which first conductive type impurities are introduced.
Two recesses that pass through the upper layer and reach the middle layer are provided on the upper surface of the semiconductor substrate.
The source electrode extends from the bottom surface of one of the two recesses to the second channel cambium.
The semiconductor device according to any one of claims 10 to 14, wherein the drain electrode extends from the other bottom surface of the two recesses to the second channel cambium.
The source electrode and the drain electrode are in contact with the first channel cambium.
The gate electrode extends from the upper layer through the first channel forming layer and the middle layer to the second channel forming layer, and faces the first channel forming layer in the upper layer. Item 2. The semiconductor device according to any one of Items 1 to 8.
In the first channel forming layer, a plurality of the first polar two-dimensional carrier gases are generated, and in the plurality of two-dimensional carrier gases, the two-dimensional carrier gases located on both the upper and lower sides are placed between them. The semiconductor device according to claim 16, which has a larger carrier concentration than at least one two-dimensional carrier gas located.
The source electrode and the drain electrode are in contact with the first channel cambium.
A recess is provided on the upper surface of the semiconductor substrate to pass through the upper layer and reach the middle layer.
The semiconductor device according to any one of claims 1 to 9, wherein the gate electrode extends from the bottom surface of the recess toward the second channel cambium.
The semiconductor substrate is
An upper buffer layer located above the upper layer and having an insulating property,
The invention according to any one of claims 1 to 18, further comprising an upper potential fixing layer located between the upper buffer layer and the upper layer and having an interface state concentration of 1 × 10 12 / cm 2 or more. Semiconductor device.
The semiconductor device according to claim 19, wherein the upper potential fixed layer is composed of a group III-V compound semiconductor into which carbon (C), oxygen (O) or iron (Fe) is introduced.
The semiconductor substrate is
A lower buffer layer that is located below the lower layer and has insulating properties,
The invention according to any one of claims 1 to 20, further comprising a lower potential fixing layer located between the lower buffer layer and the lower layer and having an interface state concentration of 1 × 10 12 / cm 2 or more. Semiconductor device.
With a semiconductor substrate
A first electrode and a second electrode provided on the semiconductor substrate are provided.
The semiconductor substrate is
The upper layer, middle layer and lower layer composed of the first semiconductor,
A first channel cambium located between the upper layer and the middle layer,
A second channel cambium located between the middle layer and the lower layer is provided.
Each of the first channel cambium and the second channel cambium has one or more dissimilar material layers composed of a second semiconductor material having a bandgap different from that of the first semiconductor material.
The thickness of each of the one or more dissimilar material layers is smaller than the thickness of the middle layer.
In the first channel cambium, a first polar two-dimensional carrier gas is generated at a pair of heterointerfaces formed on both sides of each of the one or more dissimilar material layers.
In the second channel cambium, a second polar two-dimensional carrier gas is generated at a pair of heterointerfaces formed on both sides of each of the one or more dissimilar material layers.
The first electrode is in contact with the first channel cambium and is in contact with the first channel cambium.
The second electrode is in contact with the second channel cambium.
Semiconductor device.