WO2021152020A1

WO2021152020A1 - Processing a wafer of a semiconductor material

Info

Publication number: WO2021152020A1
Application number: PCT/EP2021/052003
Authority: WO
Inventors: Ludovicus Marie AUGUSTIN; Jeroen Antonius Maria DUIS
Original assignee: SMART Photonics Holding B.V.
Priority date: 2020-01-31
Filing date: 2021-01-28
Publication date: 2021-08-05
Also published as: GB202001403D0; TW202133318A; GB2592905A

Abstract

A method of processing a wafer of a semiconductor material for at least one of: an optoelectronic device, an electronic device or a photonic device. The method comprises: determining a first region of the wafer between a second region of the wafer for a structure for a photonic integrated circuit and a sacrificial third region of the wafer; and modifying the wafer in the first region to restrict transfer of energy from the sacrificial third region to the second region.

Description

PROCESSING A WAFER OF A SEMICONDUCTOR MATERIAL

Background

Wafers comprising semiconductor materials are often brittle allowing for the propagation of edge defects through much of the wafer material. Propagation of the edge defect to another edge of the wafer will cause the wafer material to break. Edge defects are for example caused by handling of the wafer during fabrication processes.

Wafer breakages lead to sections of the wafer material that are unusable for the fabrication of devices. Defects can lead to failure of the epitaxial growth or to device failures in devices fabricated on the surface of the wafer of semiconductor material, which limits the device yield of the wafer. Wafers comprising semiconductor materials often require a high purity and high-quality single crystalline structure for the fabrication of sensitive micro structure or nanostructure devices resulting in large acquisition costs. The edges of the wafer can be used by various detector types for the determination of the position and accurate alignment of the wafer prior to fabrication processes. A common method of reducing the chances of the formation of edge defects is to mechanically or chemically grind the edges of the wafer to increase the curvature of the edges of the wafer material. This has the disadvantage of increasing the error in a detector determining the edge of the wafer and therefore the alignment of the wafer. Accurate determination of the position of the wafer is required during fabrication processes to ensure a high-quality device structure.

Wafers can be commercially utilised to form electronic, photonic and/or optoelectronic devices. A commonly commercially utilised wafer comprising semiconductor material for optoelectronic devices is indium phosphide (InP), which allows for integration of optically active and passive functions on into so-called photonic integrated circuits (PICs).

It is desirable to reduce the chances of wafer damage during a fabrication process, whilst maintaining the ability to accurately align the wafer during such a fabrication process. Brief Description of the Drawings

Figure l is a flow diagram illustrating a method of modifying a first region of a wafer of a semiconductor material to restrict transfer of energy from a sacrificial third region to a second region of the wafer, according to examples; Figure 2 is a schematic diagram of a modified wafer of a semiconductor material, according to examples;

Figure 3 is a schematic diagram of a wafer of a semiconductor material where the wafer has been modified by reducing a thickness of the wafer in the first region, according to examples; Figure 4 is a schematic diagram of a wafer of a semiconductor material where the wafer has been modified by removing a portion of the wafer in the first region, according to examples;

Figure 5 is a schematic diagram of a modified wafer of a semiconductor material where the wafer has been modified by modifying a physical property of the semiconductor material in the first region, according to examples; and

Figure 6 is a schematic diagram of a modified wafer of a semiconductor material for an electronic, photonic or optoelectronic device, according to examples.

Detailed Description Examples described herein relate to methods of processing a wafer of semiconductor material. In particular, but not exclusively, they relate to processing a wafer of a semiconductor material for an electronic, photonic and/or optoelectronic device.

As will be elaborated below, at least in the example of a wafer of a semiconductor material comprising InP, examples described herein provide a wafer which is less prone to damage or breakage, as a result, for example, of an impact to the edge of the wafer. Accordingly, an edge defect may be prevented from, or is less likely to, propagate through the semiconductor material. This can prevent the formation of undesirable defects in the wafer material which will lead to unusable sections and may even cause wafer breakage, decreasing the yield of fabricated devices per wafer. In examples, the processing is performed in a manner to maintain a straight edge of the wafer (e.g. the straight edge taken along a thickness of the wafer) for detection processes used to determine the crystal orientation with respect to the position of the wafer.

Figure 1 is a flow diagram illustrating, in a general manner, a method 100 of processing a wafer of a semiconductor material. A corresponding example of the processed wafer is described below with reference to Figure 2.

The wafer is typically a thin slice of solid material with one or two planar surfaces facing in opposite directions to each other. In examples, the wafer is a disc. The wafer of semiconductor material may be used as a substrate for the deposition of other layers. The controlled deposition of layers in contact with the substrate through various fabrication processes such as molecular beam epitaxy (MBE), chemical vapour deposition (CVD) and metalorganic vapour-phase epitaxy (MOVPE) may be used to form devices or structures on the surface of the wafer such as PICs. In some examples, each of the layers is deposited substantially across the whole surface of the substrate, except for areas of the substrate that are deliberately masked or clamped by a wafer clamp of a reactor in which the device is being manufactured. By saying that each of the layers is deposited substantially across the whole surface of the substrate, it is envisaged that the layers are deposited to cover the whole surface of the wafer within acceptable tolerances.

As illustrated by Figure 2 in the schematic diagram of a modified wafer of a semiconductor material, the wafer 200a in these examples is circular in shape. In examples, the wafer has a diameter from 50-450 millimetres with a thickness of 50- 1500 micrometres (microns). It will be appreciated that although the examples discussed in the present disclosure illustrate circular wafers, in further examples the wafer has a different shape and dimensions without diverging from the scope of the appended claims.

The wafer may comprise defect-free single crystalline semiconductor material formed using a method such as Czochralski growth into a boule which is then sliced with a wafer saw. It will be appreciated that in practice defect-free single crystalline semiconductor material may still contain undesirable defects, but the undesirable defects are limited in comparison to lower quality crystal semiconductor material. It will also be appreciated that the methods discussed in this disclosure may also be implemented for an amorphous semiconductor material. The upper and or/bottom surface of the wafer may be polished. It will be appreciated the method of examples disclosed herein can be implemented either before or after the polishing process.

In examples, the semiconductor material is a ternary semiconductor alloy or a quaternary semiconductor alloy. The semiconductor material for example, comprises a III-V semiconductor compound, containing elements from group III and group V in the periodic table. Group III materials include boron (B), aluminium (Al), gallium (Ga) and indium (In). Group V materials include nitrogen (N), phosphor (P), arsenic (As) and antimony (Sb). The semiconductor material is for example a nitride, phosphide, arsenide or antimonide. The semiconductor material in some examples comprises mainly of silicon (Si). By saying the semiconductor material comprises mainly of a particular element, for example Si, it is envisaged that the semiconductor material comprises more than 50% of that element, e.g. Si, in chemical composition.

The semiconductor material in examples is an InP material, comprising mainly of InP. By saying that the semiconductor material comprises mainly of InP, the semiconductor material comprises more than 50% InP in chemical composition. As the skilled person will appreciate the semiconductor material may comprise different materials in addition. In examples, the semiconductor material is purely InP (within acceptable purity tolerances) with the material comprising at least 99% InP in chemical composition. In examples the semiconductor material comprises other materials such as dopants or impurities. In some examples, the wafer comprises semiconductor material which is doped with a dopant material so that the semiconductor material is considered n-doped. In other examples the semiconductor material is doped with a dopant material so that the semiconductor material is considered p-doped. In further examples the semiconductor material is doped with a dopant material such as iron (Fe) so that the semiconductor material is considered semi-insulating. Semi-insulating materials typically have conductivity close to that of insulators but can still carry electrical current.

At block 101, a first region of the wafer for modification is determined. At block 102 a second region of the wafer for a PIC structure is determined. At block 103 a third sacrificial region of the wafer is determined. The first region, second region and third region all penetrate the depth of the wafer respectively. The term region is therefore, used to indicate a portion of the volume of the wafer. In examples, the first region of the wafer is determined by inserting the wafer into a processing clamp and aligning modification apparatus relative to the wafer. The second region and third region are determined by the inner boundary and outer boundary of the first region respectively. In further examples, the third region of the wafer is determined by considering the volume of the wafer which is deemed to be sacrificial at the edge of the wafer. The inner boundary of the third region defines the outer boundary of the first region. Aligning the modification apparatus relative to the wafer then defines the inner boundary of the first region and outer boundary of the second region.

Figure 200a illustrates the upper surface of a wafer of semiconducting material with the depth of the wafer into page. The upper surface of the wafer is the surface of the wafer which will undergo fabrication processes. For example, the upper surface of the wafer may be the surface to be in contact with deposited layers which comprise the electronic, photonic or optoelectronic device. Electronic devices comprise components for controlling the flow of electrical current. Photonic devices comprise components for creating, manipulating or detecting light. Optoelectronic devices comprise electronic and photonic components. A PIC is typically considered an optoelectronic device where all components may be formed on a single wafer. The surface of the wafer is substantially planar. By saying that the wafer is substantially planar, it is envisaged that the upper surface of the wafer is flat (within acceptable tolerances) and in some cases is parallel with the bottom surface of the wafer. The centre point of the wafer surface 200a is in examples the innermost part of the wafer where the edge of the wafer surface 200a is the outermost part of the wafer.

The second region 202a is used for the fabrication of devices to maximise the yield of the wafer. The yield of the wafer is for example, the number of devices that can be produced per wafer. The second region 202a in these examples is circular. The outer boundary of the second region 202a is coincident with the inner boundary of the first region 201a.

The outer boundary of the third region 203a is the edge of the wafer, with the third region 203a encompassing a volume inside the edge of the wafer. The inner boundary of the third region 203a is circular and is coincident with the outer boundary of the first region 201a. The third region 203 a is sacrificial as it intentionally may be sacrificed, through damage, when an edge defect propagates through the material of the third region 203a to the outer boundary of the first region 201a without restriction. Along a radial axis, the width of the third region may be 1 millimetre. In another example, the width of the third region is limited to no larger than 1 millimetre as this offers a satisfactory sacrificial function without overly limiting the yield of the wafer. A larger width third region 203a will lead to a lower wafer yield.

The first region 201a abuts the second region 202a and third region 203 a of the wafer. The outer boundary of the second region 202a and inner boundary of the third region 203a delineate the surface of the first region 201a. Along a radial axis, the width of the first region 201a is a result of the modification to be made to the first region 201a. In examples, the modification is achieved using modification apparatus where aligning the modification apparatus relative to the wafer then defines the width of the first region. The width of the first region is limited to reduce the effect on the yield of the wafer. A larger area first region 201a will lead to a lower wafer yield. In examples, the width of the first region is between 1 to 2 millimetres. The outer boundary of the second region 201a, outer boundary of the first region 201a and outer boundary of the third region 203a in examples are concentric circles. In examples the distance between the outer boundary of the third region 203a and inner boundary of the first region 201a is less than 5 millimetres.

Figure 200b illustrates a cross section of the wafer, where the view of the wafer at a right angle to the surface axis at the centre of the wafer. The first region 201b, second region 202b and third region 203b are shown.

At block 104, the first region 201a of the wafer is modified to restrict the transfer of energy from the sacrificial third region 203 a to the second region 202a. The restriction of the transfer of energy is relative to the energy transfer properties of the first region, for transfer of energy from the third region 203 a to the second region 202a, before the modification. That is to say, the amount of energy transferrable per unit of time, from the third region 203a to the second region 202a, is reduced by modifying the first region 201a. The restriction may be a total restriction or blocking of the transfer of energy however, it is understood that in other examples some transfer of energy may still occur and that the modification reduces the transfer of energy. The energy is for example impact energy which has been caused by the wafer being held inappropriately or knocked resulting in the formation of edge defects. The impact energy may be transferred through the crystal structure of the wafer from the third region toward the second region of the wafer generating defects in the crystal structure of the wafer material as the impact energy is transferred.

Modifying the wafer in the first region comprises at least one of: reducing a thickness of the wafer in the first region, removing a portion of the wafer in the first region or modifying a physical property of the semiconductor material in the first region. Further details of each of these modifications is now explained below, with figures. Note that some features in one figure are common or similar to features in another figure. Such features are labelled with the same reference numeral, but prefixed with a different value corresponding to the Figure number. So, feature 202a in Figure 2 is similar to feature 302a in Figure 3. For such features, for conciseness, an earlier description of the feature should be taken to apply for the feature in figures described later.

Figure 3 is a schematic diagram of a wafer of a semiconductor material where the wafer has been modified by reducing a thickness of the wafer in the first region. The diagram shows the cross section of the wafer 300b and the upper surface of the wafer 300a after the modification with the first region 301a, second region 302a and third region 303a demonstrated. The thickness of the first region is the depth of the wafer from the upper surface 300a to the bottom surface of the wafer. As demonstrated by the cross section of the wafer 300b, the magnitude of the thickness of the wafer in the first region 301b is less than the magnitude of the thickness of at least the third region 303b and second region 302b abutting the first region. The magnitude of the thickness of the wafer in the first region is less, than the original magnitude of the thickness of the wafer in the first region before modification. The thickness is reduced in the first region by removing material from either the bottom surface of the wafer in the first region or the upper surface of the wafer in the first region. In the present example, the latter scenario will be discussed in greater detail but it will be appreciated that in other examples the method of reducing the thickness of the first region is implemented for the bottom surface of the wafer in the first region. In further examples, the method of reducing the thickness of the first region is implemented partially on the bottom surface of the wafer and partially on the upper surface of the wafer in the first region.

In examples the thickness of the first region is reduced in a manner such that the upper surface of the first region is substantially planar. By saying that the upper surface of the first region is substantially planar in the first region, it is envisaged that the upper surface of the wafer is parallel with the bottom surface of the wafer in the first region. In other examples, the upper surface of the wafer in the first region after modification has a degree of curvature as a result of the modification method. In examples, the thickness reduction is carried out equally across the entire surface of the first region 301a, forming a reduced thickness region of the wafer in the first region 301a around the second region 302a.

In examples the thickness reduction of the first region 301a, as viewed from the upper surface of the wafer 300a, forms a circular groove. The groove is circular as the boundaries of the groove define the inner and outer boundaries of the first region 301a. In examples the groove is a channel or recess in the wafer formed by the reduction in thickness of the first region.

In examples, the circular groove has a depth of between 10 and 20 microns. It is envisioned that the depth of the groove is the difference between the thickness of the second region (taken at the boundary with the first region) and the reduced thickness of the first region after modification. Alternatively, the depth of the groove is the difference between the thickness of the third region (taken at the boundary with the first region) and the reduced thickness of the first region after modification. In examples, the average thickness across the surface of the second region and the average thickness across the surface of the third region is the same. By saying the average thickness across the surface of each region is the same, it is envisaged that the surface of the wafer in both regions is flat (within acceptable tolerances) and has the same magnitude of thickness (within acceptable tolerances). The depth of the circular groove is the depth of material removed from the first region when the first region has had its thickness reduced. In the present examples, the thickness of the material removed from the first region is between 10 and few hundred microns across the entire surface of the first region and the surface is planar. In other examples, the thickness of the material removed from the first region is no more than 50% of the thickness of the wafer with in some examples the thickness of material removed from the first region greater than 10 microns or greater than 20 microns.

The modification in some examples is implemented by etching the wafer in the first region. Etching may remove the upper surface material of the first region to reduce the thickness of the first region. Etching the upper surface material of the first region across the entire surface 301a, under the same conditions will ensure the thickness reduction is carried out equally across the entire surface of the first region, resulting in a planar surface. As the skilled person will appreciate, various techniques may be used to etch the wafer in accordance with examples described herein. Such techniques may include wet chemical, electromechanical, pure plasma, reactive ion and high temperature vapor etching.

By reducing the thickness of the wafer in the first region the transfer of energy from the sacrificial third region to the second region is restricted. There is less wafer material in the first region of the wafer for a propagating defect to travel through. It may be that the defect reaches the outer boundary of the first region and finds there is no wafer material to propagate through, restricting the transfer of energy to the second region. The reduction in thickness of the wafer in the first region may make the wafer in this region more susceptible to breaking. The energy transferred from the third region to the first region may cause a breakage of the wafer in the first region which will consume the transferred energy, restricting the transfer of energy to the second region. The energy which would have been transferred to the second region has been redirected into a breakage of the wafer in the first region.

Figure 4 is a schematic diagram of a wafer of a semiconductor material where the wafer has been modified by removing a portion of the wafer in the first region. The diagram shows the cross section of the wafer 400b and the upper surface of the wafer 400a after the modification with the first region 401a, second region 402a and third region 403a demonstrated. A portion of the wafer in the first region is a part of the volume of the wafer in the first region. In the present example, the portion is a volume of the wafer of the first region in which the volume comprises the entire thickness of the wafer in the first region which is demonstrated in the wafer cross section 400b. The cross section is taken in the centre point of the wafer and in the centre of the removed portion of the wafer in the first region 401b. The second region 402b and third region 403b are also demonstrated. The portions are removed in the first region of the wafer 401b symmetrically so appear on either side of the centre in the cross section of the wafer 400b.

In examples, removing a portion of the wafer in the first region comprises forming one or more holes in the wafer in the first region. The holes 404a are circular as demonstrated by the view of the upper surface of the wafer 400a. The diameter of the holes is equal to the width of the first region or the distance between the inner and outer boundary of the first region. In examples, removing a portion of the wafer in the first region comprises creating a plurality of holes in the wafer in the first region, each of the plurality of holes separated from another of the plurality of holes by a respective portion of the wafer in the first region. In examples, the portion of the wafer in the first region separating each hole is equal in volume. In other examples, the plurality of holes may be created in such a way as to minimise the portion of the wafer in the first region separating each hole whilst ensuring the structural integrity of the first region such that the first region of the wafer does not break apart.

Removing a portion of the wafer in the first region may comprise etching the wafer in the first region using the same etching techniques discussed previously. Removing a portion of the wafer in the first region may also comprise using laser ablation or photoablation for removing the portion of the wafer in the first region. Laser ablation or photoablation is where the wafer in the first region of the material is removed by irradiating the material with a laser beam. A form of protection may be utilised to ensure that the second region and third region of the wafer are protected from the removal method.

By removing a portion of the wafer in the first region the transfer of energy from the sacrificial third region to the second region is restricted. A defect that reaches the outer boundary of the first region is likely to find there is no wafer material to propagate through, restricting the transfer of energy to the second region. The reduction in the volume of the wafer in the first region may make the wafer in the first region more susceptible to breaking. The energy transferred from the third region to the first region may cause a breakage of the wafer in the first region which will consume the transferred energy, restricting the transfer of energy to the second region. Figure 5 is a schematic diagram of a modified wafer of a semiconductor material where the wafer has been modified by modifying a physical property of the semiconductor material in the first region. The diagram shows the cross section of the wafer 500b and the upper surface of the wafer 500a after the modification with the first region 501a, second region 502a and third region 503a demonstrated. In examples, the physical property of the semiconductor material in the first region relates to the crystallinity of the semiconductor material. The crystallinity of the semiconductor in the first region relates to the degree of structural order in the crystal structure. In examples, the crystal structure of the semiconductor in the first region is modified to be amorphous, more amorphous than the second and/or third regions, less crystalline than the second and/or third regions, or non-crystalline, where the structural order of the crystal structure lacks long range order.

In examples, a substantial portion of the first region is amorphous as shown by the upper surface of the first region 501a and cross section of the first region 501b where shading and the letter ‘A’ have been used to indicate the difference in crystal structure of the first region to both the second region 502b and third region 503b. A substantial portion is used to indicate that at least 50% of the volume of the crystal structure of the first region has been modified. In other examples, the crystal structure of the first region is amorphous in its entirety, although it will be appreciated there may be some slight deviation due to error.

In one example the modification of the physical property of the semiconductor material in the first region comprises using laser ablation to reduce the crystallinity of a crystal structure of the semiconductor material in the first region. This may be achieved using low energy laser ablation.

By modifying a physical property of the semiconductor material in the first region the transfer of energy from the sacrificial third region to the second region is restricted. A high degree of order in the crystal structure can create pathways which defects can easily propagate through. By modifying the crystal structure in the first region to be amorphous the degree of order in the crystal structure is decreased. For the defect to propagate from the third region, through the first region to reach the second region, a greater amount of energy will need to be expended to navigate the irregular crystal structure. The irregular crystal structure may also lead to the propagation of the defect causing a break in the first region. This can prevent the defect from propagating any further restricting the transfer of energy from the sacrificial third region to the second region.

It should be noted that any of the modifications to the first region of the wafer discussed in previous examples may be achieved by treating the wafer from the upper surface of the wafer or from the bottom surface of the wafer or by partially treating the wafer from both the upper surface and bottom surface of the wafer, where the upper surface of the wafer is the surface on which fabrication processes is carried out to form at least part of the structure of a device..

Figure 6 is a schematic diagram of a modified wafer of a semiconductor material for an electronic, photonic or optoelectronic device, according to examples. In examples, after modifying the wafer in the first region to restrict the transfer of energy from the sacrificial third region to the second region, the second region is processed to form at least part of the structure for a device. The processing may comprise depositing a series of epitaxial layers in contact with the upper surface of the wafer in the second region 602. The epitaxial layers may form part of the structure for components for a PIC such as waveguides, multimode interferometers (MMIs) and P-N junctions. Waveguides are used for the confinement of light to guide it to various components of the PIC. MMIs can be used to split light into its constituent eigenmodes. P-N junctions comprise p-type and n-type semiconductor material and are used to construct many PIC components such as photodetectors.

In examples, the second region of the wafer 602 is processed to form a plurality of parts of structures for a plurality of PIC. The processing of the second region of the wafer may involve the wafer being moved between various fabrication reactors for each of the epitaxial layers. The wafer may also have to be positioned accurately for the fabrication of each single PIC. The modified first region of the wafer 601 will restrict the transfer of energy from the third region 603 to the second region 602 when the wafer is moved in fabrication, protecting the second region from propagating defects or breakages of the wafer that may originate from a knock or impact energy.

When the fabrication process is completed and the plurality of parts of structures for the plurality of PIC are fabricated the wafer is diced to produce a plurality of PIC as demonstrated by the upper surface of the wafer 600. Dicing the wafer may comprise scribing and breaking, mechanical sawing or laser cutting. The modified first region of the wafer 601 will also protect the second region of the wafer during this process. It should be noted that the modification to the first region of the wafer may be implemented after the plurality of parts of structures for the plurality of PIC are formed but before the wafer is diced.

The above examples are to be understood as illustrative examples. It is to be understood that any feature described in relation to any one example may be used alone, or in combination with other features described, and may also be used in combination with one or more features of any other of the examples, or any combination of any other of the examples. Furthermore, equivalents and modifications not described above may also be employed without departing from the scope of the accompanying claims.

Claims

1. A method of processing a wafer of a semiconductor material for at least one of: an optoelectronic device, an electronic device or a photonic device, comprising: determining a first region of the wafer between a second region of the wafer for a structure for a photonic integrated circuit and a sacrificial third region of the wafer; and modifying the wafer in the first region to restrict transfer of energy from the sacrificial third region to the second region.

2. The method of claim 1, wherein the wafer of the semiconductor material is for a photonic integrated circuit.

3. The method of claim 2, wherein modifying the wafer in the first region comprises at least one of:

(i) reducing a thickness of the wafer in the first region;

(ii) removing a portion of the wafer in the first region; or

(iii) modifying a physical property of the semiconductor material in the first region.

4. The method of claim 3, wherein at least one of (i) or (ii) comprises etching the wafer in the first region.

5. The method of claim 3 or 4, wherein (i) comprises forming a circular groove in the wafer in the first region.

6. The method of claim 5, wherein the groove has a depth of more than 10 microns.

7. The method of claim 3 or 4, wherein (i) comprises forming a reduced thickness region of the wafer in the first region around the second region.

8. The method of claim 3 or 4, wherein (ii) comprises forming a hole in the wafer in the first region.

9. The method of claim 3 or 4, wherein (ii) comprises creating a plurality of holes in the wafer in the first region, each of the plurality of holes separated from another of the plurality of holes by a respective portion of the wafer in the first region.

10. The method of claim 3, wherein (ii) comprises using laser ablation for removing the portion of the wafer in the first region.

11. The method of claim 3, wherein (iii) comprises using laser ablation to reduce the crystallinity of a crystal structure of the semiconductor material in the first region.

12. The method of claim 3, wherein (iii) comprises modifying the crystallinity of the semiconductor material in the first region.

13. The method of any preceding claim comprising, after modifying the wafer in the first region, processing the second region to form at least part of the structure for the at least one of the: optoelectronic device, electronic device or photonic device.

14. The method of any preceding claim, comprising polishing a first side of the wafer before modifying the wafer in the first region.

15. The method of any preceding claim, wherein modifying the first region comprises applying a wafer modification treatment to part of a first side of the wafer, the first side comprising an area of the second region for processing to form at least part of the structure for the at least one of the: optoelectronic device, electronic device or photonic device.

16. The method of any of claims 1 to 14, wherein modifying the wafer in the first region comprises applying a wafer modification treatment to a second side of the wafer, the second side opposite to a first side of the wafer comprising an area of the second region for processing to form at least part of the structure for the at least one of the optoelectronic device, electronic device or photonic device.

17. The method of any preceding claim, wherein modifying the wafer in the first region to restrict transfer of energy from the sacrificial third region to the second region reduces a tendency of the wafer in the second region to be damaged in response to the third region receiving an impact.

18. The method of any preceding claim, wherein modifying the wafer in the first region to restrict transfer of energy from the sacrificial third region to the second region increases a tendency of the wafer in the first region to break in response to the third region receiving an impact.

19. The method of any preceding claim, wherein modifying the wafer in the first region to restrict transfer of energy from the sacrificial third region to the second region increases a capability of the wafer in the first region to redirect energy, from an impact received to the third region, away from the second region.

20. The method of any preceding claim, wherein an inner boundary of the first region is at most 5 millimetres from an outer edge of the wafer.

21. The method of any preceding claim, wherein the semiconductor material comprises a III-V compound.

22. The method of any preceding claim, wherein the semiconductor material comprises InP.

23. The method of any preceding claim, wherein the energy is impact energy received by the outer edge of the wafer.

24. A wafer of semiconductor material to be processed to form a structure for at least one of an optoelectronic device, electronic device or photonic device, the wafer comprising: a first region between a second region for processing to form the structure for the at least one of the: optoelectronic device, electronic device or photonic device and a sacrificial third region, wherein the first region is configured to restrict transfer of energy from the sacrificial third region to the second region.

25. The wafer of claim 24, wherein the wafer of semiconductor material is to be processed to form a structure for a photonic integrated circuit.

26. The wafer of claim 24, wherein the first region comprises at least one of:

(i) a reduced thickness region of the wafer relative to a thickness of at least one of the second region or the sacrificial third region;

(ii) a hole in the wafer; or

(iii) a different value of a physical property of the semiconductor material in the first region relative to a value of the physical property in at least one of the second region or the sacrificial third region.

27. The wafer of claim 24, in accordance with (i), wherein the reduced thickness region surrounds the second region.

28. The wafer of claim 24 or 25, in accordance with (i), the first region comprising a circular groove.

29. An optoelectronic device, an electronic device or a photonic device formed from a wafer of semiconductor processed according to the method of any of claims 1 to 22.