WO2021151491A1

WO2021151491A1 - An analog-to-digital converter

Info

Publication number: WO2021151491A1
Application number: PCT/EP2020/052281
Authority: WO
Inventors: Bingxin Li; Ola Pettersson; Anders Jakobsson
Original assignee: Huawei Technologies Co., Ltd.
Priority date: 2020-01-30
Filing date: 2020-01-30
Publication date: 2021-08-05
Also published as: CN115004555A; EP4085531A1

Abstract

The invention relates to an analog-to-digital converter (100) for converting an input voltage to a binary code. The analog-to-digital converter (100) comprises a comparator (104) which has an adjustable biasing current. The comparator (104) determines bits of a binary code (C1) based on a set of comparisons between an input voltage (Vin) and a set of reference voltages (Vref1, Vref2, …, Vrefn) and in dependence on the biasing current of the comparator (104). The value of the biasing current is dependent on a redundancy of the binary code (C1) such that the value of the biasing current is decreased with increased redundancy and increased with decreased redundancy. Thereby, an improved trade-off between power and resolution can be achieved for the analog-to-digital converter (100).

Description

AN ANALOG-TO-DIGITAL CONVERTER

Technical Field

The invention relates to an analog-to-digital converter comprising a comparator which has an adjustable biasing current. The invention further relates to a communication device comprising such an analog-to-digital converter.

Background

A successive-approximation-register analog-to-digital converter (SAR ADC) uses a comparator to convert an input voltage to a binary code based on a number of successive approximations of the input voltage. At each successive step, the SAR ADC compares the input voltage to the output of an internal digital-to-analog converter corresponding to a midpoint of a selected voltage range. In a SAR ADC, the noise from the comparator often limits the resolution of the converter.

Summary

An objective of embodiments of the invention is to provide a solution which mitigates or solves the drawbacks and problems of conventional solutions.

The above and further objectives are solved by the subject matter of the independent claims. Further advantageous embodiments of the invention can be found in the dependent claims.

According to a first aspect of the invention, the above mentioned and other objectives are achieved with an analog-to-digital converter for converting an input voltage to a binary code, the analog-to-digital converter comprising an input configured to receive an input voltage; a comparator configured to determine bits of a binary code based on a set of comparisons between the input voltage and a set of reference voltages and in dependence on a biasing current, wherein a value of the biasing current is dependent on a redundancy of the binary code; and an output configured to output the binary code.

The biasing current can be the current flow through the comparator which defines the operating point of the comparator.

An advantage of the analog-to-digital converter according to the first aspect is that the biasing current of the comparator in the analog-to-digital converter can be adjusted based on the redundancy of the binary code. For example, the biasing current can be reduced when the binary code is protected by redundancy. A reduced biasing current leads to power savings but also causes larger thermal noise in the comparator which may lead to wrong decisions in the comparisons. But when the binary code is protected by redundancy, a wrong decision can be corrected by later comparisons. Thus, by adjusting the biasing current of the comparator based on the redundancy of the binary code, power consumption can be reduced without compromising the accuracy of the conversion. The more redundancy a binary code has, the more current saving can be achieved. Thereby, an improved trade-off between power consumption and resolution can be achieved for the analog-to-digital converter.

In an implementation form of an analog-to-digital converter according to the first aspect, the comparator is configured to determine a bit of the binary code for each comparison in the set of comparisons.

An advantage with this implementation form is that it provides a good match to conventional comparator functionality.

In an implementation form of an analog-to-digital converter according to the first aspect, the value of the biasing current is dependent on a redundancy of a bit of the binary code.

An advantage with this implementation form is that the biasing current can be adjusted to be suitable for determining each bit of the binary code.

In an implementation form of an analog-to-digital converter according to the first aspect, the redundancy of the bit of the binary code is dependent on the position of the bit in the binary code. In an implementation form of an analog-to-digital converter according to the first aspect, the redundancy of the bit of the binary code further is dependent on at least one of a number of redundant bits in the binary code, a weight of a redundant bit in the binary code, and a position of a redundant bit in the binary code.

An advantage with this implementation form is that it provides a good match to conventional redundancy functionality.

In an implementation form of an analog-to-digital converter according to the first aspect, the value of the biasing current is decreased with increased redundancy, and increased with decreased redundancy. An advantage with this implementation form is that the power consumption can be reduced without compromising the accuracy of the conversion. Thereby, an improved trade-off between power consumption and resolution can be achieved for the analog-to-digital converter.

In an implementation form of an analog-to-digital converter according to the first aspect, the value of the biasing current is controlled by changing a number of active biasing transistors of the comparator. The comparator may comprise a set of biasing transistors and the value of the biasing current may be controlled by selecting a number of active biasing transistors from the set of biasing transistors of the comparator. The number of active biasing transistors can be selected using one or more switches associated with the set of biasing transistors of the comparator.

An advantage with this implementation form is that it provides a simple and robust way of changing the biasing current in a dynamic comparator.

In an implementation form of an analog-to-digital converter according to the first aspect, the value of the biasing current is controlled by changing a current mirror ratio of the comparator. The current mirror ratio can be the transistor size ratio in a current mirror of the comparator, where the transistors have the same gate-to-source voltage.

An advantage with this implementation form is that it provides a simple and robust way of changing the biasing current in a static comparator.

In an implementation form of an analog-to-digital converter according to the first aspect, the analog-to-digital converter comprises a circuit configured to control the value of the biasing current. The circuit can be a logic circuit.

An advantage with this implementation form is that it provides a simple and robust way of controlling the value of the biasing current.

In an implementation form of an analog-to-digital converter according to the first aspect, the analog-to-digital converter is a successive approximation register analog-to-digital converter.

An advantage with this implementation form is that an improved trade-off between power consumption and resolution can be achieved for the successive approximation register analog- to-digital converter. According to a second aspect of the invention, the above mentioned and other objectives are achieved with a communication device for a communication system comprising an analog-to- digital converter according to any one of the implementation forms of the analog-to-digital converter according to the first aspect.

An advantage of the communication device according to the second aspect are the same as those for the corresponding implementation forms of the analog-to-digital converter according to the first aspect.

According to a third aspect of the invention, the above mentioned and other objectives are achieved with a method for converting an input voltage to a binary code, the method comprises receiving an input voltage; determining bits of a binary code based on a set of comparisons between the input voltage and a set of reference voltages and in dependence on a biasing current, wherein a value of the biasing current is dependent on a redundancy of the binary code; and outputting the binary code.

The method according to the third aspect can be extended into implementation forms corresponding to the implementation forms of the analog-to-digital converter according to the first aspect. Hence, an implementation form of the method comprises the feature(s) of the corresponding implementation form of the analog-to-digital converter.

The advantages of the methods according to the third aspect are the same as those for the corresponding implementation forms of the analog-to-digital converter according to the first aspect.

Further applications and advantages of the embodiments of the invention will be apparent from the following detailed description.

Brief Description of the Drawings

The appended drawings are intended to clarify and explain different embodiments of the invention, in which:

- Fig. 1 schematically illustrates an analog-to-digital converter according to an embodiment of the invention;

- Fig. 2 schematically illustrates a comparator according to an embodiment of the invention; - Fig. 3 schematically illustrates an analog-to-digital converter according to an embodiment of the invention;

- Fig. 4 schematically illustrates a static comparator according to an embodiment of the invention;

- Fig. 5 schematically illustrates a dynamic comparator according to an embodiment of the invention;

- Fig. 6 schematically illustrates a communication device according to an embodiment of the invention.

Detailed Description

One factor limiting the resolution of a SAR ADC is noise from the comparator. The noise from the comparator can be reduced by increasing the biasing current of the comparator. However, by increasing the biasing current of the comparator, the power consumption of the SAR ADC is increased. Therefore, causing a trade-off between power consumption and resolution in the SAR ADC.

Redundancy techniques have been used in SAR-ADCs for a long time. Redundancy provides the possibility to recover a wrong comparison decision, as long as the error is within a recover range. The redundancy may be based on the use of redundant bits in the binary code to be determined. A redundant bit protects bits which are more significant than the redundant bit in the binary code, as a wrong decision for a protected bit due to noise or settling error can be corrected by later comparisons.

An objective of the invention is to address the above mentioned drawbacks and provide an analog-to-digital converter with an improved trade-off between power consumption and resolution. This is achieved with an analog-to-digital converter according to the invention which comprises a comparator, where a biasing current of the comparator is adjustable based on a redundancy of a binary code to be determined by the comparator. By adjusting the biasing current of the comparator based on the redundancy of the binary code, the power consumption of the analog-to-digital converter can be reduced without limiting the resolution of the analog- to-digital converter.

Fig. 1 schematically illustrates an analog-to-digital converter 100 according to an embodiment of the invention. The analog-to-digital converter 100 may be used for converting an input voltage to a binary code, i.e. for converting an analog input voltage to a binary code representing the magnitude of the input voltage. The analog-to-digital converter 100 may be used for a wide variety of applications such as data/signal acquisition, sensor applications, sound/voice applications, and video applications and further in a number of different devices.

The analog-to-digital converter 100 comprises an input 102 configured to receive an input voltage Vin. The input voltage Vin may be a sample of an analog voltage received by the input 102. The analog-to-digital converter 100 further comprises a comparator 104 configured to determine bits of a binary code C1 based on a set of comparisons between the input voltage Vin and a set of reference voltages Vrefl, Vref2, ... , Vrefn. The set of comparisons are performed by the comparator 104 in dependence on a biasing current, where a value of the biasing current is dependent on a redundancy of the binary code C1. The analog-to-digital converter 100 further comprises an output 106 configured to output the binary code C1.

With reference to Fig. 1 , the analog-to-digital converter 100 may further comprise a circuit 108 configured to control the value of the biasing current. The circuit 108 may e.g. be a logic circuit implemented in hardware and/or software. The circuit 108 may control the value of the biasing current e.g. by providing control signals to the comparator 104.

The comparator 104 performs the set of comparisons in dependence on the biasing current which is adjustable based on the redundancy of the binary code C1. The biasing current can be understood to be the current flow through the comparator 104 which defines the operating point of the comparator 104. Fig. 2 schematically illustrates the comparator 104 according to an embodiment of the invention. The comparator 104 compares a first input voltage inp and a second input voltage inn, e.g. compares the input voltage Vin with a reference voltage in the set of reference voltages Vrefl , Vref2, ... , Vrefn. The comparison is dependent on the biasing current lb of the comparator 104 which is adjustable, as indicated in Fig. 2. The value of the biasing current lb is based on the redundancy of the binary code C1 which is to be determined by the comparator 104. Based on the comparison the comparator 104 outputs a first output voltage outp and a second output voltage outn. The difference between the first output voltage outp and the second output voltage outn indicates either a logic high or a logic low.

In embodiments, the value of the biasing current is decreased with increased redundancy, and increased with decreased redundancy of the binary code C1. For example, the biasing current may have a first value at a first redundancy and a second value at a second redundancy, where the first value is lower than second value when the first redundancy is higher than the second redundancy. When the value of the biasing current is decreased the thermal noise in the comparator 104 is increased, leading to a higher risk of a wrong decision for a comparison. By decreasing the value of the biasing current when redundancy is increased, the redundancy can compensate for the higher risk of a wrong decision as the redundancy allows a wrong decision to be corrected by later comparisons as long as the error is within redundancy range. Thus, with a higher redundancy a lower value of the biasing current can be used without compromising the accuracy of the conversion.

In embodiments, the comparator 104 is configured to determine a bit of the binary code C1 for each comparison in the set of comparisons. The set of comparisons may be seen as a binary search pattern where each comparison determines one bit of the binary code C1 by comparing the input voltage Vin to one of the reference voltages in the set of reference voltages Vrefl, Vref2, ... , Vrefn. For example, the comparator 104 performs a first comparison to determine a first bit of the binary code C1. The first bit in the binary code C1 may be the most significant bit (MSB) in the binary code C1. In the first comparison, the input voltage Vin is compared to a first reference voltage Vrefl . The first reference voltage Vrefl may be set to a predefined value. Depending on the outcome of the first comparison, the first bit in the binary code C1 is set to a binary 1 or 0. The comparator 104 then performs a second comparison to determine a second bit of the binary code C1. The second bit in the binary code C1 may be the second most significant bit in the binary code C1. In the second comparison, the input voltage Vin is compared to a second reference voltage Vref2, where the second reference voltage Vref2 is determined based on the outcome of the first comparison. Depending on the outcome of the second comparison the second bit in the binary code C1 is set to a binary 1 or 0. The comparator 104 continues in the same way until a comparison has been performed for every bit in the binary code C1. In this way, each bit of the binary code C1 is determined in a step wise manner by the set of comparisons.

The redundancy of the binary code C1 may be bit specific such that each bit of the binary code C1 is associated with a redundancy. In this case, the value of the biasing current may be dependent on a redundancy of a bit of the binary code C1. The redundancy of a bit of the binary code C1 may be based on the number of redundant bits in the binary code C1. Each redundant bit protects any bit of the binary code C1 which is more significant than the redundant bit. The redundancy of the bit of the binary code C1 may hence be dependent on the position of the bit in the binary code C1, i.e. where in the binary code C1 the bit is located and hence the significance of the bit. The redundancy of the bit of the binary code C1 may further be dependent on at least one of a number of redundant bits in the binary code C1 , a weight of a redundant bit in the binary code C1 , and a position of a redundant bit in the binary code C1. In other words, the redundancy of the bit of the binary code C1 may be dependent on the position of the bit relative to the position of the one or more redundant bits in the binary code C1 , as well as the weight of the one or more redundant bit. The weight of a redundant bit is related to the size of the redundant bit which in turn is dependent on the position of the redundant bit in the binary code C1.

Fig. 3 schematically illustrates an analog-to-digital converter 100 according to an embodiment of the invention where the analog-to-digital converter 100 is an N-bit converter with two redundant bits. That the analog-to-digital converter 100 is an N-bit converter can be understood to mean that the analog-to-digital converter 100 converts the input voltage Vin to a binary code C1 comprising a number N bits.

In the embodiment shown in Fig. 3, the analog-to-digital converter 100 is a successive approximation register (SAR) analog-to-digital converter comprising a SAR 110, a digital-to- analog converter (DAC) 112, and the comparator 104. The SAR 110 comprises a SAR logic and a N-bit register which outputs a test binary code to the DAC 112 which in turn generates the set of reference voltages Vrefl, Vref2, ... , Vrefn.

With reference to Fig. 3, the DAC 112 is a capacitor array comprising a number of capacitors C1 , C2, Cr1, C3, C4, Cr2, C5, C6, ... , CN-1. The number of capacitors is determined by the number N and the number of redundant bits used. In the embodiment shown in Fig. 3, which is a top-plate-sampling structure, the capacitor array comprises the number N minus 1 capacitors associated with the number N bits of the binary code C1 plus two capacitors associated with the two redundant bits. The two redundant bits are a first redundant bit and a second redundant bit associated with a first redundant capacitor Cr1 and a second redundant capacitor Cr2, respectively. In embodiments where the analog-to-digital converter 100 is a bottom-plate-sampling structure, the capacitor array may instead comprise the number N capacitors associated with the number N bits of the binary code C1 plus a capacitor per redundant bit used.

Each comparison in the comparator 104 determines a bit in the binary code C1. For each comparison, the SAR 110 feeds a test binary code to the DAC 112, where the test binary code is an approximation of the binary code C1 determined based on previous comparisons. The DAC 112 provides a reference voltage Vref to the comparator 104 based on the test binary code and internal reference voltages Vref+ and Vref-. The comparator 104 compares the reference voltage Vref to a comparator voltage Vcm which corresponds to a sample of the input voltage Vin. The comparator 104 outputs a logic low or high depending on whether the comparator voltage Vcm is lower or higher than the reference voltage Vref. Based on the logic low or high from the comparator 104, the SAR 110 determines whether the bit to be determined by the comparison is set to a binary 1 or 0. When the full set of comparisons have been performed all the number N bits in the binary code C1 have been determined and are output by the SAR 110.

In the embodiment shown in Fig. 3, the position of the first and second redundant bits are such that the first N-1 comparisons are protected by redundancy. Of these comparisons, the first N- 4 comparisons are protected by both the first and second redundant bits, while the next three comparisons are protected by the first redundant bit only. As previously described, the redundancy of each bit depends on the position of the bit in the binary code C1 , the number and position of redundant bits, and the weight of the redundant bits. Table 1 shows the weight and redundancy per bit in the binary code C1 including the two redundant bits according to the embodiment shown in Fig. 3. The redundancy of a n^th bit is dependent on the weight of the other bits and can be calculated according to the following equation: redundancy bit_n = sum (weight of bih to weight of bit_n-i) - weight of bit_n + 1

As shown in table 1 , the three least significant bits are not protected by redundancy, the next three bits are protected by a first redundancy based on the first redundant bit, and the remaining bits except the most significant bit are protected with a second redundancy based on the first and second redundant bits. The most significant bit is protected by a third redundancy which is higher than the second redundancy due to that the weight of the most significant bit is decreased to allow the addition of the two redundant bits.

Table 1

The biasing current of the comparator 104 in Fig. 3 may be adjusted according to the redundancy of the bit to be determined. When the comparator 104 performs the set of comparisons to determine the bits in the binary code C1 , the biasing current may e.g. be set to a first value for the first N-4 comparisons, to a second value for the next three comparisons, and to a third value for the last three comparisons. As previously described, the biasing current may be increased with decreased redundancy of the bit to be determined. The first value of biasing current may hence be lower than the second value of the biasing current, and the second value of the biasing current may be lower than the third value of the biasing current. In this way, as the redundancy decreases the value of the biasing current is increases such that the noise of the comparator is reduced.

The comparator 104 in the analog-to-digital converter 100 according to any of the described embodiments may be a dynamic comparator or a static comparator. In embodiments where the comparator 104 is a dynamic comparator, the value of the biasing current may be controlled by changing a number of active biasing transistors of the comparator 104. In embodiments where the comparator 104 is a static comparator, the value of the biasing current may be controlled by changing a current mirror ratio of the comparator 104. Further details related to the controlling of the biasing current in the two types of comparators will now be described with reference to Figs. 4 and 5.

Fig. 4 shows a comparator 104 according to an embodiment of the invention where the comparator 104 is a static comparator such as e.g. an operational amplifier (op-amp) based comparator. The comparator 104 comprises a number of transistors M1 , M2, M3, M4, M5 and specifically a set of current mirror transistors M5_1, M5_2, ... , M5_N which are connected in parallel. The set of current mirror transistors M5_1, M5_2, ... , M5_N form a current mirror with the fourth transistor M4. Depending on the number of active current mirror transistors, i.e. the number of connected current mirror transistors, in the set of current mirror transistors M5_1, M5_2, ... , M5_N, the current mirror ratio of the comparator 104 can be changed. The biasing current lb of the comparator 104 depends on the current mirror ratio of the comparator 104 and hence by changing the current mirror ratio the value of the biasing current lb of the comparator 104 can be controlled.

Each current mirror transistor M5_1 ; M5_2; ... ; M5_N is connected to a respective switch S1 ; S2; ... ; SN which controls whether the current mirror transistor M5_1; M5_2; ... ; M5_N is active or not. With the use of the switches S1 , S2, ... , SN, i.e. by opening and/or closing the switches S1 , S2, ... , SN, the number of active current mirror transistors in the set of current mirror transistors M5_1, M5_2, ... , M5_N can be changed such that the current mirror rate and hence the value of the biasing current can be changed. For example, by activating/connecting more current mirror transistors the value of the biasing current lb can be increased, and vice versa. In embodiments, the switches S1 , S2, , SN are controlled by the previously described circuit

108 in the analog-to-digital converter 100. The switches S1 , S2, ... , SN-1, SN may in such embodiments be opened or closed based on control signals from the circuit 108.

Fig. 5 shows a comparator 104 according to an embodiment of the invention where the comparator 104 is a dynamic comparator. The operation of the comparator 104 is controlled by a clock signal elk. The comparator 104 comprises a set of biasing transistors M_1, M_2, ... , M_N which are connected in parallel. The biasing current lb of the comparator 104 depends on a number of active biasing transistors, i.e. the number of connected biasing transistors, in the set of biasing transistors M_1, M_2, ... , M_N. Thus, by changing the number of active biasing transistors of the comparator 104, the value of the biasing current lb of the comparator 104 can be controlled.

Each biasing transistor M_1; M_2; ... ; M_N is connected to a respective switch S1; S2; ... ; SN which controls whether the biasing transistor M_1 ; M_2; ... ; M_N is active or not. The number of active biasing transistors of the comparator 104 may hence be changed using the switches S1 , S2, ... , SN to activate and/or deactivate one or more of the biasing transistors in the set of biasing transistors M_1, M_2, ... , M_N. For example, by activating/connecting more biasing transistors the value of the biasing current lb can be increased, and vice versa. As for the static comparator, the switches S1, S2, ... , SN may be controlled by the circuit 108 in the analog-to- digital converter 100. The switches S1, S2, ... , SN may e.g. be opened or closed based on control signals from the circuit 108.

As previously described, the analog-to-digital converter 100 may be a successive approximation register analog-to-digital converter. However, the analog-to-digital converter 100 according to the invention is not limited thereto and may be any type of analog-to-digital converter which is based on comparisons performed by a comparator.

According to embodiments of the invention a communication device 200 is further provided. The communication device 200 comprises an analog-to-digital converter 100 according to any of the described embodiments of the invention. The analog-to-digital converter 100 may be used for converting input voltages to binary codes for one or more applications in the communication device 200. The communication device 200 may be configured for wireless communicate in a wireless communication system and/or wired communicate in wired communication system. Fig. 6 shows the communication device 200 according to an embodiment of the invention where the communication device 200 is a wireless communication device. The communication device 200 is configured to operate in a wireless communication system 500 comprising at least one network access node 400, as shown in Fig. 6. In embodiments, the communication device 200 may e.g. be a client device also denoted a user equipment configured to operate according to the 3GPP standard. The communication device 200 comprises the analog-to- digital converter 100 according to any one of the described embodiments of the invention. The analog-to-digital converter 100 may convert input voltages to binary codes to support e.g. voice and/or data applications in the communication device 200.

Finally, it should be understood that the invention is not limited to the embodiments described above, but also relates to and incorporates all embodiments within the scope of the appended independent claims.

Claims

1. An analog-to-digital converter (100) for converting an input voltage to a binary code, the analog-to-digital converter (100) comprising an input (102) configured to receive an input voltage (Vin); a comparator (104) configured to determine bits of a binary code (C1) based on a set of comparisons between the input voltage (Vin) and a set of reference voltages (Vrefl , Vref2, , Vrefn) and in dependence on a biasing current, wherein a value of the biasing current is dependent on a redundancy of the binary code (C1); and an output (106) configured to output the binary code (C1).

2. An analog-to-digital converter (100) according to claim 1, wherein the comparator (104) is configured to determine a bit of the binary code (C1) for each comparison in the set of comparisons.

3. An analog-to-digital converter (100) according to claim 1 or 2, wherein the value of the biasing current is dependent on a redundancy of a bit of the binary code (C1).

4. An analog-to-digital converter (100) according to claim 3, wherein the redundancy of the bit of the binary code (C1) is dependent on the position of the bit in the binary code (C1).

5. An analog-to-digital converter (100) according to claim 4, wherein the redundancy of the bit of the binary code (C1) further is dependent on at least one of a number of redundant bits in the binary code (C1), a weight of a redundant bit in the binary code (C1), and a position of a redundant bit in the binary code (C1).

6. An analog-to-digital converter (100) according to any one of the preceding claims, wherein the value of the biasing current is decreased with increased redundancy, and increased with decreased redundancy.

7. An analog-to-digital converter (100) according to any one of the preceding claims, wherein the value of the biasing current is controlled by changing a number of active biasing transistors of the comparator (104).

8. An analog-to-digital converter (100) according to any one of claims 1 to 6, wherein the value of the biasing current is controlled by changing a current mirror ratio of the comparator (104).

9. An analog-to-digital converter (100) according to any one of the preceding claims, wherein the analog-to-digital converter (100) comprises a circuit (108) configured to control the value of the biasing current.

10. An analog-to-digital converter (100) according to any one of the preceding claims, wherein the analog-to-digital converter (100) is a successive approximation register analog-to-digital converter.

11. A communication device (200) for a communication system, comprising an analog-to- digital converter (100) according to any one of the preceding claims.

12. A method for converting an input voltage to a binary code, the method comprising receiving an input voltage (Vin); determining bits of a binary code (C1) based on a set of comparisons between the input voltage (Vin) and a set of reference voltages (Vrefl, Vref2, ... , Vrefn) and in dependence on a biasing current, wherein a value of the biasing current is dependent on a redundancy of the binary code (C1); and outputting the binary code (C1).