WO2021148128A1

WO2021148128A1 - Processing unit for safe execution of machine code

Info

Publication number: WO2021148128A1
Application number: PCT/EP2020/051703
Authority: WO
Inventors: Rémi Robert Michel DENIS-COURMONT
Original assignee: Huawei Technologies Co., Ltd.
Priority date: 2020-01-24
Filing date: 2020-01-24
Publication date: 2021-07-29

Abstract

The present invention relates to the field of computer security and safe execution of machine code. More specifically, the present invention relates to providing a remedy for return-oriented programming (ROP) attacks, e.g. enabled by a software bug. The present invention therefore provides a processing unit (100) for safe execution of machine code (101), wherein the processing unit (100) is configured to when a return instruction (102) in the machine code (101) is encountered during the execution of the machine code (101), determine a return address (103) of the return instruction (102); determine, whether a return address indicator, RAI, (104) is associated with the return address (103); and execute the return instruction (102), only if it is determined that a RAI (104) is associated with the return address (103).

Description

PROCESSING UNIT FOR SAFE EXECUTION OF MACHINE CODE

TECHNICAL FIELD The present disclosure relates to the field of computer security and safe execution of machine code. More specifically, the present disclosure relates to providing a remedy for return-oriented programming (ROP) attacks, e.g. enabled by a software bug. In particular, the present disclosure provides a processing unit for safe execution of machine code and a corresponding compiler for creating safe executable machine code.

BACKGROUND

In conventional imperative or object-oriented programming languages, a given computer program is structured in such a way that it starts with a “main” function or procedure. This function can then call other functions, which can call other functions, and so on. When a called function ends, it returns to the caller function, at the point after the function call. That point is identified by the return address. The list of nested function calls is called the stack or the call stack. To keep track of which caller function to return to, and at which point exactly within the caller function to return to, a called function typically saves the return address on the stack. The stack also can contain other intermediate computation values that the called function needs to retain in memory transiently. If e.g. function “main()” calls function “ftinc aO”, which then calls function “func bO”, the stack looks like it is illustrated in FIG. 5 (in this illustration, the stack grows downward). It is to be noted that the return addresses and temporary values are interleaved in FIG. 5.

In memory unsafe programming languages, such as C, C++, Objective C and “assembler”, memory accesses to read and write the temporary values from the stack are not boundary-checked. As a consequence, a programming mistake (e.g. a bug) may allow that the return address is read or written instead of, or in addition to, the intended temporary value. This is an out-of-bound memory access, usually called a stack-based buffer overflow (though it is not necessarily an overflow properly speaking). In the occurrence of such bug, an attacker may be able to pick a carefully selected return address, or set of return addresses to overwrite the stack memory with. This allows the attacker to steer the control flow of the program in unintended illegitimate and typically harmful manner.

Several strategies exist which try to protect or constrain the return address, such as stack canaries, pointer authentication, shadow stack, or address space layout randomization. However, these conventional strategies rely on secrecy or concealment and only provide statistical protection. In some cases, an attacker can perform a brute force attack or even guess a useful return address to overcome the protection. Moreover, the above approaches require extra processing instructions in the code and additional logic evaluation from the microprocessor.

SUMMARY

In view of the above-mentioned problem, embodiments of the present invention aim to improve the conventional solutions to protect against ROP attacks.

Thereby, it is an object to provide deterministic protection against ROP attacks in which invalid return addresses cannot be returned to in any circumstance.

The object is achieved by embodiments of the invention as described in the enclosed independent claims. Advantageous implementations of embodiments of the invention are further defined in the dependent claims.

In particular, embodiments of the present invention ensure that a return instruction in machine code is only executed when a return address indicator (RAI) is associated with the return address of the return instruction.

A first aspect of the present invention provides a processing unit for safe execution of machine code, wherein the processing unit is configured to, when a return instruction in the machine code is encountered during the execution of the machine code, determine a return address of the return instruction; determine, whether a return address indicator, RAI, is associated with the return address; and execute the return instruction, only if it is determined that a RAI is associated with the return address.

This is beneficial, as the RAI that is associated with the return address protects against an attack, such as a code reuse attack. In the code reuse attack, an address and/or place within the machine code can be selected maliciously. That is, during the code reuse attack, by evaluating the instructions in the machine code in a different order than it is intended, malicious behavior can be effected. This can be prevent by the RAI.

In particular, the processing unit may be a physical processing unit or a virtual processing unit, e.g. an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a central processing unit (CPU), or a virtualized CPU.

In particular, a return instruction (which can also be called return statement) may be an instruction to leave a current subroutine and resume at a point in the machine code immediately after an instruction which called the subroutine.

In particular, the return address may be the point in the machine code immediately after the instruction which called the subroutine.

In an implementation form of the first aspect, the RAI indicates that the return address is a valid return address.

This allows to protect against code reuse attacks, as a return instruction is only executed if it points to a valid return address.

In particular, a valid return address is an address which is not malicious. In particular, a valid return address is an address determined while the machine code was compiled from a higher programming language, and which was not altered afterwards. In particular, the RAI which indicates the valid return address, protects against code reuse attacks.

In a further implementation form of the first aspect, the machine code comprises the RAI. This ensures that an RAI or a valid return address can be indicated in the machine code, which makes the machine code more resistant against attacks.

In a further implementation form of the first aspect, the processing unit is further configured to determine that the RAI is associated with the return address, if the return address is located immediately adjacent to the RAI in the machine code.

This provides an effective and precise manner of determining an RAI in machine code.

In particular, the processing unit is further configured to determine that the RAI is associated with the return address, if the return address is located immediately after the RAI in the machine code.

In a further implementation form of the first aspect, the RAI comprises a function call or a branch-and-link instruction.

This provides another effective and precise manner of determining an RAI in machine code.

In a further implementation form of the first aspect, the processing unit is further configured to determine that the RAI is associated with the return address, if the return address is located immediately after the function call or the branch-and-link instruction in the machine code.

In a further implementation form of the first aspect, the processing unit is further configured to determine that the RAI is associated with the return address, if the RAI is located at the return address in the machine code.

This provides another effective and precise manner of determining an RAI in machine code. In particular, if the RAI is located at the return address, the processing of machine code will continue at the next instruction immediately after the RAI, if the return instruction to the RAI was executed.

In particular, the RAI only indicates a legitimate return address at the place of the RAI. Thus, the RAI can also be called "hint" or "no-op" instruction. If the legitimate return address is at the place of the RAI, code flow (that is, execution of machine code) will continue to the next instruction, i.e. the one in order immediately after the RAI instruction.

In a further implementation form of the first aspect, the processing unit is further configured to interrupt the execution of the machine code and/or raise an exception, if it is determined that no RAI is associated with the return address.

This ensures that execution of machine code is interrupted and an attack is prevented, if no RAI is associated with the return address.

In a further implementation form of the first aspect, the processing unit is further configured to perform the safe execution of the machine code, if a flag is set.

This is beneficial as it allows to look for the RAI only in code that is known to embed the RAI, which is more efficient.

In particular, the flag may be a run-time processor flag, or a bit in a system register.

A second aspect of the present invention provides a method for safe execution of machine code, wherein the method comprises the steps of, when a return instruction in the machine code is encountered during the execution of the machine code, determining, by a processing unit, a return address of the return instruction; determining, by the processing unit, whether a return address indicator, RAI, is associated with the return address; and executing, by the processing unit, the return instruction, only if it is determined that a RAI is associated with the return address. In a further implementation form of the second aspect, the RAI indicates that the return address is a valid return address.

In a further implementation form of the second aspect, the machine code comprises the RAI.

In a further implementation form of the second aspect, the method further includes determining, by the processing unit, that the RAI is associated with the return address, if the return address is located immediately adjacent to the RAI in the machine code.

In a further implementation form of the second aspect, the RAI comprises a function call or a branch-and-link instruction.

In a further implementation form of the second aspect, the method further includes determining, by the processing unit, that the RAI is associated with the return address, if the return address is located immediately after the function call or the branch-and-link instruction in the machine code.

In a further implementation form of the second aspect, the method further includes determining, by the processing unit, that the RAI is associated with the return address, if the RAI is located at the return address in the machine code.

In a further implementation form of the second aspect, the method further includes interrupting, by the processing unit, the execution of the machine code and/or raising an exception, if it is determined that no RAI is associated with the return address.

In a further implementation form of the second aspect, the method further includes performing, by the processing unit, the safe execution of the machine code, if a flag is set.

The second aspect and its implementation forms include the same advantages as the first aspect and its respective implementation forms. A third aspect of the present invention provides a computer program product comprising instructions which, when the program is executed by a computer, cause the computer to carry out the steps of the method of the second aspect or any of its implementation forms.

The third aspect and its implementation forms include the same advantages as the first aspect and its respective implementation forms.

A fourth aspect of the present invention provides a non-transitory computer-readable storage medium comprising instructions which, when executed by a computer, cause the computer to carry out the steps of the method of the second aspect or any of its implementation forms.

The fourth aspect and its implementation forms include the same advantages as the first aspect and its respective implementation forms.

A fifth aspect of the present invention provides a compiler for creating safe machine code, wherein the compiler is configured to determine a valid return address based on source code of a higher programming language; and insert a return address identifier, RAI, that is associated with the valid return address in machine code obtained based on the source code of the higher programming language.

In an implementation form of the fifth aspect, the valid return address is an address immediately after a function call instruction.

In particular, the valid return address is an address immediately after a function call instruction in the machine code.

In particular, the function call instruction is a branch-and-link instruction. A sixth aspect of the present invention provides a method for compiling safe machine code, wherein the method comprises the steps of determining, by a compiler, a valid return address based on source code of a higher programming language; and inserting, by the compiler, a return address identifier, RAI, that is associated with the valid return address in machine code obtained based on the source code of the higher programming language.

In an implementation form of the sixth aspect, the valid return address is an address immediately after a function call instruction.

The sixth aspect and its implementation forms include the same advantages as the fifth aspect and its respective implementation forms.

A seventh aspect of the present invention provides a computer program product comprising instructions which, when the program is executed by a computer, cause the computer to carry out the steps of the method of sixth aspect or any of its implementation forms.

The seventh aspect and its implementation forms include the same advantages as the fifth aspect and its respective implementation forms.

An eight aspect of the present invention provides a non-transitory computer-readable storage medium comprising instructions which, when executed by a computer, cause the computer to carry out the steps of the method of sixth aspect or any of its implementation forms.

The eight aspect and its implementation forms include the same advantages as the fifth aspect and its respective implementation forms.

It has to be noted that all devices, elements, units and means described in the present application could be implemented in the software or hardware elements or any kind of combination thereof. All steps which are performed by the various entities described in the present application as well as the functionalities described to be performed by the various entities are intended to mean that the respective entity is adapted to or configured to perform the respective steps and functionalities. Even if, in the following description of specific embodiments, a specific functionality or step to be performed by external entities is not reflected in the description of a specific detailed element of that entity which performs that specific step or functionality, it should be clear for a skilled person that these methods and functionalities can be implemented in respective software or hardware elements, or any kind of combination thereof.

BRIEF DESCRIPTION OF DRAWINGS The above-described aspects and implementation forms of the present invention will be explained in the following description of specific embodiments in relation to the enclosed drawings, in which

FIG. 1 shows a schematic view of a processing unit according to an embodiment of the present invention.

FIG. 2 shows a schematic view of a method according to an embodiment of the present invention. FIG. 3 shows a schematic view of a compiler according to an embodiment of the present invention.

FIG. 4 shows a schematic view of a method according to an embodiment of the present invention.

FIG. 5 shows a schematic view of a stack.

DETAILED DESCRIPTION OF EMBODIMENTS

FIG. 1 shows a schematic view of a processing unit 100 according to an embodiment of the present invention. The processing unit 100 is for safe execution of machine code 101. To this end, the processing unit 100 is configured to, when a return instruction 102 in the machine code 101 is encountered during the execution of the machine code 101, determine a return address 103 of the return instruction 102. The processing unit 100 is further configured to determine, whether a return address indicator, RAI, 104 is associated with the return address 103, and to execute the return instruction 102, only if it is determined that a RAI 104 is associated with the return address 103.

In particular, an explicit mark (that is, the RAI 104) for a valid return address 103 can be defined. The valid return address 103 may e.g. be determined while a given computer program is compiled, and may thus be static while the computer program (that is, the machine code 101) is being executed. Any candidate return address 103 that does not carry that mark (the RAI 104) may be treated as invalid.

All features of the processing unit 100 which are described in the following are optional features of the processing unit 100.

Each memory address 103 within the executable code (that is, the machine code 101) that constitutes a legitimate return address 103 is marked. This reduces the number of return address 103 that the processing unit 100 will permit, thus reducing the number of availability of code “gadgets” for attacks relying on ROP or “retum-into-libc” type attacks. In other words, the RAI 104 can indicate that the return address 103 is a valid return address 103.

In particular, the set of legitimate return addresses 103 may be known at the time of compilation, when source code is converted into executable machine code 101. That is, the machine code 101 can comprises the RAI 104.

Optionally, it may be determined by the processing unit 100 that the RAI 104 is associated with the return address 103, if the return address 103 is located immediately adjacent to the RAI 104 in the machine code 101.

In particular, legitimate return addresses 103 can be addresses immediately after a function call instruction (which can also be called branch-and-link instruction). In other words, the RAI 104 can comprise a function call or a branch-and-link instruction.

Optionally, the processing device 100 may provide changes to a programming language compiler, such that the compiler can mark every legitimate return address 103 with an RAI 104. However, existing programming language paradigms can be sufficient for the compiler to infer the valid return address 103. In particular, embodiments of the invention may involve a recompilation of an existing computer program by a software vendor, but do not require any change to the source code by a programmer.

At run-time, the processing unit 100 can check, while executing a return instruction 102, if a return address 103 of the return instruction 102 points to an RAI 104. If the return address 103 does not point to an RAI 104, an attack can be assumed and detected by the processing unit 100, and an exception can be raised by the processing unit 100 to interrupt the corrupted program. This can inhibit the attack. This can e.g. be implemented by a small change to the processor logic of a processor of the processing unit 100, by a small change to the “microcode” of the processor, or a mix of both.

According to embodiments of the invention, several implementation manners of an RAI 104 are possible. In a first optional variant, a RAI 104 may comprise any existing “branch-and-link” instruction within the instruction set of the processing unit 101. In this case, a branch-and-link instruction can specify that the address 103 immediately after the instruction 102 is a valid return address. In other words, the RAI 104 comprises a function call or a branch-and-link instruction. That is, it can be determined that the RAI 104 is associated with the return address 103, if the return address 103 is located immediately after the function call or the branch-and-link instruction in the machine code 101.

In a second optional variant, a RAI 104 may comprise a predefined branch-and-link instruction added to the instruction set of the processing unit 101. As with the first variant, the address 103 immediately after the instruction may be the one that is then deemed a valid return address 103.

In a third optional variant, a fully dedicated instruction can be added to the instruction set of the processing unit 101. This instruction has no side effects when executed, in other words it evaluates as a “no-op”. In this case, the exact address where the instruction is presents the valid return address 103. In other words, it can be determined that the RAI 104 is associated with the return address 103, if the RAI 104 is located at the return address 103 in the machine code 101.

Regardless of the variant used, a compiler may be responsible for ensuring that an RAI 104 is present at the necessary addresses 103 within the executable code 101, i.e. the addresses 103 that are intended to be valid return addresses 103. Conversely, the compiler may avoid inserting any RAI 104 where not strictly necessary, so as to maximize effectiveness.

Also regardless of the RAI 104 variant used, the processing unit 100 can check for a valid RAI 104 while evaluating a return instruction 102. If an RAI 104 is present that marks the return address 103 as valid, then the return instruction is 102 permitted as normal. Otherwise, if an RAI 104 is not present, then the processing unit can generate a synchronous software exception, for instance an instruction fetch exception, or software signal, for instance an illegal instruction signal, instead of executing the return operation as it would normally occur. In other words, execution of the machine code 101 is interrupted and/or an exception is raised, if it is determined that no RAI 104 is associated with the return address 103. The instruction set architecture (ISA) of the processing unit 100 may already define exceptions, while signals can be defined by C language specifications.

For backward compatibility with pre-existing software, several different variants, as mentioned above, can be defined. For example, if machine code 101 that does not define a RAI 104 properly is run while the processing unit 100 expects a RAI 104, then that machine code 101 may not be able to run correctly, since unintended exceptions may occur.

Optionally, the processing unit 100 may be controlled by a flag (e.g. a run-time flag), such as a bit in a system register: if the bit is set, the processing unit 100 may function according to an embodiment of the invention. Else, it may be inactive (or vice versa), or may function conventionally. In other words, the processing unit 100 can be configured to perform the safe execution of the machine code 101 only if the flag is set. Optionally, the processing unit 100 according to an embodiment of the invention may be enabled through a memory management unit (MMU) on a system-specific granularity. In particular, in an “application” processor with virtual memory capability, the MMU may use address translation tables, and/or translation look-aside buffers (TLBs). In such a case, a one-bit flag may be defined for translation table entries, and/or TLB entries: the flag determines whether addresses of executable code mapped by a given entry are expected to contain RAIs. The processing unit 100 may only be enabled to function according to an embodiment of the invention, when the return address 103 points to a virtual memory mapping whose underlying entry has said flag set. This variant may allow hybrid functionality of the processing unit 100, partly functioning according to an embodiment of the invention and partly not.

FIG. 2 shows a schematic view of a method 200 according to an embodiment of the present invention. The method 200 is for safe execution of machine code 101. The method comprises a step of, when a return instruction 102 in the machine code 101 is encountered during the execution of the machine code 101, determining 201, by a processing unit 100, a return address 103 of the return instruction 102. The method comprises a further step of determining 202, by the processing unit 100, whether a return address indicator, RAI, 104 is associated with the return address 103. The method comprises a further step of executing 203, by the processing unit 100, the return instruction 102, only if it is determined that a RAI 104 is associated with the return address 103.

FIG. 3 shows a schematic view of a compiler 300 according to an embodiment of the present invention. The compiler 300 is for creating safe machine code 301, and is configured to determine a valid return address 302 based on source code 303 of a higher programming language; and insert a return address identifier, RAI, 304 that is associated with the valid return address 302 in machine code 301 obtained based on the source code 303 of the higher programming language.

The machine code 301 of FIG. 3 corresponds to the machine code 101 of FIG. 1. The valid return address 302 of FIG. 3 corresponds to the valid return address 103 of FIG. 1. The RAI 304 of FIG. 3 corresponds to the RAI 104 of FIG. 1. A higher programming language comprises at least one of: BASIC, Pascal, C, C++, Objective C, D, Go, Rust. Machine code 301 comprises a sequence of bytes that represent both commands and data. Machine code 301 comprises may comprise assembler code.

The valid return address 302 determined by the compiler 300 may be an address immediately after a function call instruction.

FIG. 4 shows a schematic view of a method 400 according to an embodiment of the present invention. The method 400 is for compiling safe machine code 301. The method 400 comprises a step of determining 401, by a compiler 300, a valid return address 302 based on source code 303 of a higher programming language. The method 400 comprises a step of inserting 402, by the compiler 300, a return address identifier, RAI, 304 that is associated with the valid return address 302 in machine code 301 obtained based on the source code 303 of the higher programming language.

The present invention has been described in conjunction with various embodiments as examples as well as implementations. However, other variations can be understood and effected by those persons skilled in the art and practicing the claimed invention, from the studies of the drawings, this disclosure and the independent claims. In the claims as well as in the description the word “comprising” does not exclude other elements or steps and the indefinite article “a” or “an” does not exclude a plurality. A single element or other unit may fulfill the functions of several entities or items recited in the claims. The mere fact that certain measures are recited in the mutual different dependent claims does not indicate that a combination of these measures cannot be used in an advantageous implementation.

Claims

1. A processing unit (100) for safe execution of machine code (101), wherein the processing unit (100) is configured to:

- when a return instruction (102) in the machine code (101) is encountered during the execution of the machine code (101), determine a return address (103) of the return instruction (102);

- determine, whether a return address indicator, RAI, (104) is associated with the return address (103); and

- execute the return instruction (102), only if it is determined that a RAI (104) is associated with the return address (103).

2. The processing unit (100) according to claim 1, wherein the RAI (104) indicates that the return address (103) is a valid return address (103).

3. The processing unit (100) according to claim 1 or 2, wherein the machine code (101) comprises the RAI (104).

4. The processing unit (100) according to any one of the preceding claims, further configured to determine that the RAI (104) is associated with the return address (103), if the return address (103) is located immediately adjacent to the RAI (104) in the machine code (101).

5. The processing unit (100) according to any one of the preceding claims, wherein the

RAI (104) comprises a function call or a branch-and-link instruction.

6. The processing unit (100) according to claim 5, further configured to determine that the RAI (104) is associated with the return address (103), if the return address (103) is located immediately after the function call or the branch-and-link instruction in the machine code (101).

7. The processing unit (100) according to any one of claims 1 to 3, further configured to determine that the RAI (104) is associated with the return address (103), if the RAI (104) is located at the return address (103) in the machine code (101).

8. The processing unit (100) according to any one of the preceding claims, further configured to interrupt the execution of the machine code (101) and/or raise an exception, if it is determined that no RAI (104) is associated with the return address (103).

9. The processing unit (100) according to any one of the preceding claims, further configured to perform the safe execution of the machine code (101), if a flag is set.

10. A method (200) for safe execution of machine code (101), wherein the method (200) comprises the steps of:

- when a return instruction (102) in the machine code (101) is encountered during the execution of the machine code (101), determining (201), by a processing unit (100), a return address (103) of the return instruction (102);

- determining (202), by the processing unit (100), whether a return address indicator, RAI, (104) is associated with the return address (103); and

- executing (203), by the processing unit (100), the return instruction (102), only if it is determined that a RAI (104) is associated with the return address (103).

11. A computer program product comprising instructions which, when the program is executed by a computer, cause the computer to carry out the steps of the method (200) of claim 10.

12. A compiler (300) for creating safe machine code (301), wherein the compiler (300) is configured to:

- determine a valid return address (302) based on source code (303) of a higher programming language; and

- insert a return address identifier, RAI, (304) that is associated with the valid return address (302) in machine code (301) obtained based on the source code (303) of the higher programming language.

13. The compiler (300) according to claim 12, wherein the valid return address (302) is an address immediately after a function call instruction.

14. A method (400) for compiling safe machine code (301), wherein the method (400) comprises the steps of:

- determining (401), by a compiler (300), a valid return address (302) based on source code (303) of a higher programming language; and

- inserting (402), by the compiler (300), a return address identifier, RAI, (304) that is associated with the valid return address (302) in machine code (301) obtained based on the source code (303) of the higher programming language.

15. A computer program product comprising instructions which, when the program is executed by a computer, cause the computer to carry out the steps of the method (400) of claim 14.