WO2021147721A1

WO2021147721A1 - Network-on-chip interconnection structure of many-core system, data transmission method, board card, electronic device, and computer-readable storage medium

Info

Publication number: WO2021147721A1
Application number: PCT/CN2021/071449
Authority: WO
Inventors: 陈贺; 王封
Original assignee: 北京灵汐科技有限公司
Priority date: 2020-01-20
Filing date: 2021-01-13
Publication date: 2021-07-29
Also published as: CN113138955A; CN113138955B

Abstract

A network-on-chip interconnection structure of a many-core system. The applicable many-core system comprises at least one chip. Multiple cores are integrated in each chip. The network-on-chip interconnection structure comprises: at least two blocks located on a chip, wherein each block comprises at least one core; an interchip routing module arranged corresponding to each block, wherein each interchip routing module is configured to interact with at least one of the other interchip routing modules; and a network-on-chip configured to interact with various interchip routing modules and exchange data between various cores.

Description

Many-core system on-chip network interconnection structure, data transmission method, board, electronic equipment, computer readable storage medium

Technical field

The embodiments of the present disclosure relate to the field of artificial intelligence technology, and in particular to a many-core system on-chip network interconnection structure, data transmission method, board card, electronic device, and computer-readable storage medium.

Background technique

A many-core system includes one or more chips (processors), and a chip usually integrates multiple complete cores (computing engines, cores), and the cores within a chip or among multiple chips can work together.

Therefore, the interaction between the board-level (on a board) chip and the chip, as well as the signals and data between the cores inside the chip, is very important to the many-core system, so the realization of the above interaction structure is important for the entire many-core system. The performance also plays a vital role.

In related technologies, the cores in the many-core system basically use a fixed data route to transmit data, and the cores receive and process the data, and then the transceiver module transmits the data. This transmission mode is fixed, and the data routing for communication between the cores is single. At some moments, the data path will be congested at a certain node, and the data will be waiting and cannot be received and sent in time. For many-core systems, this method cannot maximize the use of the core's computing power, and it takes a long time to transmit data, which will result in reduced data throughput and performance degradation.

Summary of the invention

In order to solve the above problems, the purpose of the embodiments of the present disclosure is to provide an on-chip network interconnection structure, data transmission method, board card, electronic device, and computer-readable storage medium of a many-core system.

In the first aspect, the embodiments of the present disclosure provide a many-core system on-chip network interconnection structure. The many-core system includes at least one chip, and each chip integrates multiple cores. The on-chip network interconnection structure includes:

At least two blocks located on the chip, each block includes at least one core;

An inter-chip routing module corresponding to each block, and each inter-chip routing module is configured to interact with at least one other inter-chip routing module; and,

It is configured as an on-chip network that interacts with each inter-chip routing module and exchanges data between each core.

In some embodiments, at least part of the inter-chip routing modules corresponding to adjacent blocks are configured to interact.

In some embodiments, at least part of the block is connected to a data interface for transferring external data;

The on-chip network interconnection structure is configured to realize the receiving and processing of external data and the transmission of the processed data between the cores of a single chip.

In some embodiments, the inter-chip routing module corresponding to the block connected to the data interface is used to receive and process the external data transmitted by the data interface, and transmit the processed data to the on-chip in the block where the target core is located. Network node

The on-chip network node in the block where the target core is located is used to receive the processed data and transfer the processed data to the target core;

Wherein, the block connected with the data interface is the block where the target core is located.

In some embodiments, the inter-chip routing module corresponding to the block connected to the data interface is used to receive and process the external data transmitted by the data interface, and transmit the processed data to other inter-chip routing modules until the destination Inter-chip routing modules corresponding to adjacent blocks of the block where the core is located;

The inter-chip routing module corresponding to the adjacent block of the block where the target core is located is used to receive the processed data and transfer the processed data to the adjacent block where the target core is located. On-chip network node;

The on-chip network node in a block adjacent to the target core is used to receive the processed data and transfer the processed data to the on-chip network node in the block where the target core is located;

In some embodiments, the inter-chip routing module corresponding to the block connected to the data interface is used to receive and process the external data transmitted by the data interface, and transmit the processed data to the block connected to the data interface. On-chip network node;

The on-chip network node in the block connected to the data interface is used to receive the processed data and transfer the processed data to the on-chip network node in the block where the target core is located;

Wherein, the block connected with the data interface is not the block where the target core is located.

In some embodiments, the inter-chip routing module corresponding to the block connected to the data interface is used to receive and process the external data transmitted by the data interface, and transmit the processed data to other inter-chip routing modules until the destination Inter-chip routing module corresponding to the block where the core is located;

The inter-chip routing module corresponding to the block where the target core is located is used to receive the processed data and transfer the processed data to the on-chip network node in the block where the target core is located;

In some embodiments, the target core includes:

The routing receiving module is used to receive data;

The calculation module is used to perform calculations based on the received data.

In some embodiments, the on-chip network interconnection structure is configured to implement data transmission between cores of multiple chips.

In some embodiments, the inter-chip routing module corresponding to a block of the first chip is connected to the inter-chip routing module corresponding to a block of the second chip, so that the block of the first chip is connected to the second chip. Of the block connection;

The source core of the first chip is used to transfer data to the on-chip network node in the block where the source core of the first chip is located;

An on-chip network node in a block where the source core of the first chip is located, configured to receive the data and transfer the data to an inter-chip routing module corresponding to the block where the source core of the first chip is located;

The inter-chip routing module corresponding to the block where the source core of the first chip is located is used to receive the data and transfer the data to other inter-chip routing modules of the first chip until the first chip connected to the second chip Inter-chip routing module corresponding to the block of a chip;

The inter-chip routing module corresponding to the block of the first chip connected to the second chip is used to receive the data and transfer the data to the inter-chip routing corresponding to the block where the target core of the second chip is located Module

An inter-chip routing module corresponding to the block where the target core of the second chip is located, configured to receive the data and transfer the data to the on-chip network node in the block where the target core of the second chip is located;

The on-chip network node in the block where the target core of the second chip is located is used to receive the data and transfer the data to the target core of the second chip.

The on-chip network node in the block where the source core of the first chip is located, configured to receive the data and transfer the data to the on-chip network node in other blocks of the first chip;

The on-chip network nodes in other blocks of the first chip are used to receive the data and transmit the data to the inter-chip routing module corresponding to the block of the first chip connected to the second chip;

In a second aspect, the embodiments of the present disclosure provide a data transmission method applied to a many-core system, wherein the many-core system includes at least one chip, each chip integrates multiple cores, and each chip is provided with at least two blocks. Each block includes at least one core, and each block corresponds to an inter-chip routing module. The data transmission method includes:

Data transmission between blocks is realized through the inter-chip routing module, data transmission with the inter-chip routing module and data transmission between the cores are realized through the on-chip network.

In some embodiments, the realization of data transmission between blocks through the inter-chip routing module includes:

The data transmission between adjacent blocks is realized by the inter-chip routing module.

In some embodiments, at least part of the blocks are connected to the data interface used to transfer external data; the inter-chip routing module is used to realize data transmission between blocks, and the data transmission and data transmission with the inter-chip routing module is realized through the on-chip network. Transmission between cores, including:

The external data is received and processed through the inter-chip routing module corresponding to the block connected to the data interface, and the processed data is transmitted to the target core through the on-chip network and/or other inter-chip routing modules to realize the reception and processing of external data The data is transmitted between the cores of a single chip.

In some embodiments, the external data is received and processed through the inter-chip routing module corresponding to the block connected to the data interface, and the processed data is transmitted to the target core through the on-chip network and/or other inter-chip routing modules, including:

Receiving and processing the external data through an inter-chip routing module corresponding to the block connected to the data interface;

Transfer the processed data to the on-chip network node in the block where the target core is located through the inter-chip routing module corresponding to the block connected to the data interface;

Transfer the processed data to the target core through the on-chip network node in the block where the target core is located;

Transfer the processed data to other inter-chip routing modules through the inter-chip routing module corresponding to the block connected to the data interface until the inter-chip routing module corresponding to the adjacent block of the block where the target core is located;

Transmitting the processed data to the on-chip network node in the adjacent block of the target core through the inter-chip routing module corresponding to the adjacent block of the target core;

Transferring the processed data to the on-chip network node in the block where the target core is located through the on-chip network node in the adjacent block of the block where the target core is located;

Transfer the processed data to the on-chip network node in the block connected to the data interface through the inter-chip routing module corresponding to the block connected to the data interface;

Transferring the processed data to the on-chip network node in the block where the target core is located through the on-chip network node in the block connected to the data interface;

Transfer the processed data to other inter-chip routing modules through the inter-chip routing module corresponding to the block connected to the data interface until the inter-chip routing module corresponding to the block where the target core is located;

Transmitting the processed data to the on-chip network node in the block where the target core is located through the inter-chip routing module corresponding to the block where the target core is located;

In some embodiments, the data transmission method further includes: a routing receiving module in the destination core receives data, and a calculation module in the destination core performs calculations based on the received data.

In some embodiments, data transmission between blocks is realized through the inter-chip routing module, data transmission with the inter-chip routing module and data transmission between cores are realized through the on-chip network, including:

The data is transmitted from the source core of one chip to the destination core of another chip through the inter-chip routing modules and the on-chip network, so as to realize the transmission of data among the cores of multiple chips.

In some embodiments, the inter-chip routing module corresponding to a block of the first chip is connected to the inter-chip routing module corresponding to a block of the second chip, so that the block of the first chip is connected to the second chip. The block is connected; the data is transmitted from the source core of one chip to the destination core of another chip through the inter-chip routing modules and the on-chip network, including:

Transmitting data to the on-chip network node in the block where the source core of the first chip is located through the source core of the first chip;

Transmitting the data to an inter-chip routing module corresponding to the block where the source core of the first chip is located through an on-chip network node in the block where the source core of the first chip is located;

Transferring the data to other inter-chip routing modules of the first chip through an inter-chip routing module corresponding to the block where the source core of the first chip is located;

Transmitting the data to the inter-chip routing module corresponding to the block of the first chip connected to the second chip through other inter-chip routing modules of the first chip;

Transmitting the data to the inter-chip routing module corresponding to the block where the target core of the second chip is located through the inter-chip routing module provided corresponding to the block of the first chip connected to the second chip;

Transmitting the data to an on-chip network node in the block where the target core of the second chip is located through an inter-chip routing module corresponding to the block where the target core of the second chip is located;

The data is transferred to the target core of the second chip through an on-chip network node in the block where the target core of the second chip is located.

Transmitting the data to network nodes on a chip in other blocks of the first chip through a network node on a chip in the block where the source core of the first chip is located;

Transmitting the data to the inter-chip routing module corresponding to the block of the first chip connected to the second chip through on-chip network nodes in other blocks of the first chip;

In some embodiments, each chip includes a plurality of inter-chip routing modules arranged along its circumference; the realization of data transmission between blocks through the inter-chip routing module includes:

During data transmission, in multiple inter-chip routing modules on the same chip, data is transmitted in a predetermined clockwise direction.

In a third aspect, an embodiment of the present disclosure provides a board, and any one of the on-chip network interconnection structures of the embodiments of the present disclosure is integrated on the board.

In a fourth aspect, an embodiment of the present disclosure provides an electronic device including a memory and a processor, wherein the memory is used to store one or more computer instructions, and the one or more computer instructions can be executed by the processor to achieve Any data transmission method in the embodiments of the present disclosure.

In a fifth aspect, embodiments of the present disclosure provide a computer-readable storage medium on which computer program instructions are stored, and when executed by a processor, the computer program instructions implement any of the embodiments of the present disclosure Data transmission method.

In the embodiments of the present disclosure, the different cores of the many-core system can only exchange data "directly" through the network-on-chip, or exchange data "indirectly" through the inter-chip routing module and the network-on-chip, that is, there are at least two of them. Different types of data routing; thus, when data transmission, data routing can be selected according to needs. For example, when the data path of a data routing is congested at a certain node, another data routing can be used to avoid data waiting. Ensure that data can be received and sent in time, reduce the time consumed for data transmission, make full use of the computing power of the core, increase data throughput and processing speed, and improve the performance of the many-core system.

Description of the drawings

In order to more clearly describe the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some of the embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative labor. .

FIG. 1 is a schematic diagram of data routing for data transmission between cores of a single chip according to an embodiment of the present disclosure, wherein the block connected with the PCIE interface is the block where the target core is located;

2 is a schematic diagram of data routing for data transmission between cores of a single chip according to an embodiment of the present disclosure, wherein the block connected to the PCIE interface is not the block where the target core is located;

3 is a schematic diagram of data routing for data transmission between cores of multiple chips according to an embodiment of the disclosure.

Detailed ways

The technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of the present disclosure.

It should be noted that if there are directional indications (such as up, down, left, right, front, back...) involved in the embodiments of the present disclosure, the directional indication is only used to explain that it is in a specific posture (as shown in the drawings). If the specific posture changes, the relative positional relationship, movement, etc. of the components below will also change the directional indication accordingly.

In addition, in the description of the embodiments of the present disclosure, the terms used are only for illustrative purposes, and are not intended to limit the scope of the present disclosure. The terms "including" and/or "including" are used to specify the existence of the described elements, steps, operations and/or components, but do not exclude the presence or addition of one or more other elements, steps, operations and/or components . The terms "first", "second", etc. may be used to describe various elements, do not represent the order, and do not limit these elements. In addition, in the description of the present disclosure, unless otherwise specified, "plurality" means two or more. These terms are only used to distinguish one element from another. These and/or other aspects become obvious in conjunction with the following drawings, and it is easier for those of ordinary skill in the art to understand the description of the embodiments of the present disclosure. The drawings are used for illustration purposes only to depict the embodiments of the present disclosure. Those skilled in the art will easily recognize from the following description that, without departing from the principles described in the present disclosure, alternative embodiments of the structure and method shown in the embodiments of the present disclosure may be adopted.

In the first aspect, the embodiments of the present disclosure provide an on-chip network interconnection structure of a many-core system. The many-core system includes at least one chip (processor), and each chip integrates multiple cores (computing engine, core). The on-chip network interconnection structure includes: At least two blocks located on the chip, each block includes at least one core; an inter-chip routing module corresponding to each block, and each inter-chip routing module is configured to interact with at least one other inter-chip routing module ( Including one-way data interaction, or two-way data interaction); and, a network on chip configured to interact with each inter-chip routing module and exchange data between each core.

The on-chip network interconnection structure of the embodiments of the present disclosure is used in a many-core system, or the on-chip network interconnection structure is a part of the many-core system. That is, the many-core system includes multiple chips, and each chip includes multiple cores, and the on-chip network interconnection structure can realize data interaction between different cores (including different cores in one chip and cores in different chips), so that more The individual cores and the on-chip network interconnect structure together constitute a many-core system that can work together.

Therefore, the embodiments of the present disclosure actually provide a many-core system, which includes the above-mentioned on-chip network interconnection structure.

Among them, each chip is divided into multiple blocks in terms of area, and each block has at least one core, and each block corresponds to an inter-chip routing module; and the on-chip network interconnection structure also includes on-chip network, on-chip The network can realize data interaction between different cores (including data interaction between different cores in a block, and data interaction between cores in different blocks), and can also realize data interaction with inter-chip routing modules, so the on-chip network can be realized The data interaction between each core in a block and the corresponding inter-chip routing module of the block; at the same time, at least part of the inter-chip routing modules can also realize data interaction, so as to realize the corresponding block (that is, the core in the corresponding block). ) Data exchange between.

Specifically, the network on chip may include multiple network on chip nodes (NoC, Network on chip). Each on-chip network node is distributed in each block of each chip, and is connected to each other to form a network topology (can also be divided into different levels, such as three levels), and at least part of the on-chip network nodes are also connected to core and/or inter-chip routing modules Connection, so that data interaction between different cores and between cores and inter-chip routing modules can be realized through the network topology of the on-chip network nodes. Among them, the on-chip network node can use some related technologies to complete the design, which will not be described in detail here.

Referring to Figures 1 to 3, since the blocks are obtained by dividing the "area" of the chip, some blocks are "adjacent" in position, and every two adjacent blocks must correspond to "a pair ( Two)" inter-chip routing modules, and among multiple "pairs" inter-chip routing modules, at least part of the "pairs" of the two inter-chip routing modules can realize data exchange.

For example, referring to Figures 1 and 2, for block bank0, block bank1 and block bank3 are adjacent blocks, where the inter-chip routing module CR0 corresponding to block bank0 and the chip corresponding to bank1 Data exchange can be realized between the inter-chip routing modules CR1, and the inter-chip routing module CR0 corresponding to the block bank0 and the inter-chip routing module CR3 corresponding to the block bank3 may not be able to exchange data.

In some embodiments, at least part of the block is connected to a data interface for transferring external data; the on-chip network interconnection structure is configured to realize the reception and processing of external data and the transmission of processed data between cores of a single chip.

The many-core system may also include a data interface connected to the block (for example, the inter-chip routing module corresponding to the block). The data interface is used to receive data from the outside (external data), so that the on-chip network interconnection structure can also receive external Data and process it, and send the processed data to the corresponding core (destination core).

It should be understood that the target core corresponds to specific external data, that is, the target core may be different in different data transmission processes.

In different specific situations, the optimal data routing in the many-core system can be obtained through AI model training to achieve optimal data transmission and minimize the time consumed for data transmission, and different AI models may be trained Different optimal data routing.

For example, referring to Figure 1 and Figure 2, for a Chip (chip), it can be divided into four banks (blocks), each bank corresponds to a CR (inter-chip routing module), and some banks are connected to the PCIE interface (data interface) , PCIE interface is connected to the server (Server), and the network on chip is specifically implemented by NoC (Network Node on Chip).

Exemplarily, the data routing when transmitting data in the above chip may include:

The first data routing:

CR->NoC (in the bank)->Core, the data routing is to use CR to send data to the NoC in the bank, and pass it to the target core through different levels of NoC for calculation.

In some embodiments, referring to FIG. 1, when the block connected to the data interface is the block where the target core is located, the inter-chip routing module corresponding to the block connected to the data interface is used to receive and process the external data transmitted by the data interface , And deliver the processed data to the on-chip network node in the block where the target core is located; the on-chip network node in the block where the target core is located is used to receive the processed data and transfer the processed data to the target core.

The specific data routing can be as follows: the data first passes through the inter-chip routing module set corresponding to the block where the target core is located, then is transferred to the on-chip network node in the block where the target core is located, and finally transferred to the target core for calculation.

In some embodiments, referring to Figure 2, when the block connected to the data interface is not the block where the target core is located, the inter-chip routing module corresponding to the block connected to the data interface is used to receive and process the external data transmitted by the data interface , And transfer the processed data to the on-chip network node in the block connected to the data interface; the on-chip network node in the block connected to the data interface is used to receive the processed data and pass the processed data to the destination The on-chip network node in the block where the core is located; the on-chip network node in the block where the target core is located, used to receive processed data and transfer the processed data to the target core.

The specific data routing can be as follows: the data first passes through the inter-chip routing module corresponding to the block connected to the data interface, and then passes the on-chip network node in the block to the on-chip network node in the block where the target core is located, and finally passes to the destination In the core, perform calculations.

The second data routing:

CR->CRx->NoC (in the bank)->Core, the data routing is transmitted in the form of loop CR (that is, the data sequentially passes through the inter-chip routing module), and the data is transmitted to the bank where the destination Core is located through loop CR. Then transfer by the NoC in the bank. Among them, CRx represents one or more inter-chip routing modules.

In some embodiments, referring to FIG. 1, when the block connected to the data interface is the block where the target core is located, the inter-chip routing module corresponding to the block connected to the data interface is used to receive and process the external data transmitted by the data interface , And transfer the processed data to other inter-chip routing modules until the inter-chip routing module corresponding to the adjacent block of the target core block; the inter-chip routing module corresponding to the adjacent block of the target core block, Used to receive processed data, and transfer the processed data to the on-chip network node in the adjacent block of the target core block; the on-chip network node in the adjacent block of the target core block is used for receiving and processing And transfer the processed data to the on-chip network node in the block where the target core is located; the on-chip network node in the block where the target core is located is used to receive the processed data and transfer the processed data to Purpose nuclear.

The specific data routing can be as follows: the data first passes through the inter-chip routing module corresponding to the block where the target core is located, and then passes through other inter-chip routing modules in turn, until the inter-chip routing module corresponding to the adjacent block of the target core block. Then it is passed to the on-chip network node in the block where the target core is located through the on-chip network node in the adjacent block of the block where the target core is located, and finally transferred to the target core for calculation.

In some embodiments, referring to Figure 2, when the block connected to the data interface is not the block where the target core is located, the inter-chip routing module corresponding to the block connected to the data interface is used to receive and process the external data transmitted by the data interface , And pass the processed data to other inter-chip routing modules until the inter-chip routing module corresponding to the block where the target core is located; the inter-chip routing module corresponding to the block where the target core is located is used to receive the processed data, And transfer the processed data to the on-chip network node in the block where the target core is located; the on-chip network node in the block where the target core is located is used to receive the processed data and transfer the processed data to the target core.

The specific data routing can be as follows: the data first passes through the inter-chip routing module corresponding to the block connected to the data interface, then passes through other inter-chip routing modules in turn, until the inter-chip routing module corresponding to the block where the target core is located, and finally passes through the target core The on-chip network nodes in the block are passed to the target core for calculation.

Both of the above two data routing schemes can send data to the destination core, which can solve the problem of performance degradation caused by data congestion and reduce the time of data transmission.

In some embodiments, the target core includes: a routing receiving module, which is used to receive data; and a calculation module, which is used to perform calculations based on the received data.

Therefore, after the data is transmitted to the target core, the routing receiving module in the target core receives the data, and the calculation module in the target core performs calculations.

For many-core systems, communication between cores in different chips can also be realized, such as sending data from the source core of one chip to the destination core of another chip.

It should be understood that the source core and the target core correspond to the starting point and the end point of specific data, that is, the source core, the target core, and the chips on which they are located in different data transmission processes may be different.

For example, referring to Figure 3, a many-core system can include multiple Chips. For each Chip, it can be divided into four banks (blocks). Each bank corresponds to a CR (Inter-Chip Routing Module). The data routing is completed by NoC topologically, and the data routing between banks is completed by CR.

In some embodiments, the inter-chip routing module corresponding to a block of the first chip is connected to the inter-chip routing module corresponding to a block of the second chip, so that the block of the first chip is connected to the second chip. Of the block connection.

Among them, a block of the first chip and a block of the second chip are connected through respective inter-chip routing modules. For example, referring to Figure 3, CR2 of Chip0 is connected to CR3 of Chip1, so that bank2 of Chip0 is connected to Chip1. The bank3 is connected to achieve cross-chip data transmission.

Exemplarily, the data routing during data transmission in the above many-core system may include:

The first data routing:

Core(Chip0 src)->NoC(Chip0 bank)->CRx(Chip0)->…CRx(Chip0)->CRx(Chip1)->NoC(Chip1 bank)->Core(Chip1 dst). Among them, CRx represents one or more inter-chip routing modules, chip0 is the first chip, Chip1 is the second chip, Core (src) indicates the source core, and Core (dst) indicates the destination core.

In some embodiments, the source core of the first chip is used to transfer data to the on-chip network node in the block where the source core of the first chip is located; the on-chip network node in the block where the source core of the first chip is located is used To receive data and transfer the data to the inter-chip routing module corresponding to the block where the source core of the first chip is located; the inter-chip routing module corresponding to the block where the source core of the first chip is located is used to receive data and transfer the data The other inter-chip routing modules to the first chip, to the inter-chip routing module corresponding to the block of the first chip connected to the second chip; the inter-chip routing module corresponding to the block of the first chip connected to the second chip The module is used to receive data and transfer the data to the inter-chip routing module corresponding to the block where the target core of the second chip is located; the inter-chip routing module corresponding to the block where the target core of the second chip is located is used to receive data and The data is transferred to the on-chip network node in the block where the target core of the second chip is located; the on-chip network node in the block where the target core of the second chip is located is used to receive the data and transfer the data to the target core of the second chip.

The specific data routing can be as follows: the data is first transmitted through the source core of the first chip (Chip0) to the on-chip network node in the block where the source core is located, and then through the inter-chip routing module corresponding to the block where the source core is located, and then sequentially pass through The other inter-chip routing modules of the first chip (Chip0) until the inter-chip routing module corresponding to the block on the first chip (Chip0) connected to the block where the target core of the second chip (Chip1) is located, and then pass through the second chip (Chip1) The inter-chip routing module corresponding to the block where the target core is located is finally passed to the target core through the on-chip network node in the block where the target core is located for calculation.

The second data routing:

Core(Chip0 src)->NoC(Chip0 bank)->…->NoC(Chip0 bank)->CRx(Chip0)->CRx(Chip1)->NoC(Chip1 bank)->Core(Chip1( dst). Among them, CRx represents one or more inter-chip routing modules, chip0 is the first chip, Chip1 is the second chip, Core (src) is the source core, and Core (dst) is the destination core.

In some embodiments, the source core of the first chip is used to transfer data to the on-chip network node in the block where the source core of the first chip is located; the on-chip network node in the block where the source core of the first chip is located is used It is used to receive data and transfer the data to the on-chip network nodes in other blocks of the first chip; the on-chip network nodes in other blocks of the first chip are used to receive data and transfer the data to the second chip connected to the second chip. The inter-chip routing module corresponding to the block of one chip; the inter-chip routing module corresponding to the block of the first chip connected to the second chip, which is used to receive data and transfer the data to the area where the target core of the second chip is located The inter-chip routing module corresponding to the block; the inter-chip routing module corresponding to the block where the target core of the second chip is located, and is used to receive data and transfer the data to the on-chip network node in the block where the target core of the second chip is located; The on-chip network node in the block where the target core of the second chip is located is used to receive data and transfer the data to the target core of the second chip.

The specific data routing can be as follows: data is first transferred to the on-chip network node in the block where the source core is located through the source core of the first chip (Chip0), and then transferred to the on-chip network nodes in the other blocks of the first chip (Chip0) The inter-chip routing module corresponding to the block on the first chip (Chip0) connected to the block where the target core of the second chip (Chip1) is located, and then the inter-chip routing module corresponding to the block where the target core of the second chip (Chip1) is located After the routing module, it is finally transferred to the target core through the on-chip network node in the block where the target core is located for calculation.

When there is a block connection between different chips, the data can be first transferred to the inter-chip routing module (CR2 set corresponding to bank2 of Chip0) in the block connected to the second chip in the first chip, and then transferred to the second chip In the inter-chip routing module corresponding to the block connected to the first chip (CR3 corresponding to bank3 of Chip1), and finally transferred to the target core of the second chip.

The above two data routing schemes can send data from the source core to the destination core, which can solve the problem of performance degradation caused by data congestion and reduce the time of data transmission.

In the specific example shown in Figure 3, the block in the second chip where the target core is located, that is, the block in the second chip that is connected to the first chip (bank3 of Chip1), and the block in the second chip where the target core is located is correspondingly set The inter-chip routing module and the inter-chip routing module corresponding to the block connected to the first chip in the second chip are also the same inter-chip routing module (CR3 of Chip1). However, it should be understood that if the target core is in another block of the second chip, after the data is transferred to the inter-chip routing module corresponding to the block connected to the first chip in the second chip, the above data can be further followed The method of transmission within a single chip, transmission to the target core (including indirect transmission through the inter-chip routing module and the on-chip network, or direct transmission through the on-chip network), will not be described in detail here.

At the same time, it should be understood that if the first chip where the source core is located and the second chip where the destination core is located are not directly connected, but indirectly connected through other chips, it is also feasible; that is, during the data transmission process, other chips need to pass through. In each other chip, data can be transmitted through the inter-chip routing module or through the on-chip network.

In a second aspect, the embodiments of the present disclosure provide a data transmission method, which is applied to a many-core system. The many-core system includes at least one chip, each chip integrates multiple cores, and each chip is provided with at least two blocks, and each block includes At least one core, each block corresponds to an inter-chip routing module, and the data transmission method includes:

The data transmission between the blocks is realized through the inter-chip routing module, and the data transmission with the inter-chip routing module and the data transmission between the cores are realized through the on-chip network.

Corresponding to the aforementioned on-chip network interconnection structure, when data transmission is performed, the inter-chip routing module can be used to realize data transmission between blocks (or between cores of different blocks), and the data transmission with the inter-chip routing module can be realized through the on-chip network And data transmission between cores, so as to solve the problem of performance degradation caused by data congestion and reduce the time of data transmission.

In some embodiments, realizing data transmission between blocks through the inter-chip routing module includes: realizing data transmission between adjacent blocks through the inter-chip routing module.

In the embodiment of the present disclosure, every two adjacent blocks must correspond to a "pair (two)" inter-chip routing module, and among multiple "pairs" inter-chip routing modules, there are at least partially "pairs" of two slices. Data interaction can be realized between the routing modules.

In some embodiments, at least part of the blocks are connected to the data interface used to transfer external data; the data transmission between the blocks is realized through the inter-chip routing module, and the data transmission with the inter-chip routing module is realized through the on-chip network, and the data is transmitted in each core. Inter-transmission, including:

According to the above method, there are at least two data routes to choose from during the data transmission process. In order to determine which data route is selected for each actual data transmission process, a default data route (such as the one obtained through AI model training) can be set in advance. Optimal data route), when the data path of the data route is congested, another data route is switched as a backup.

Exemplarily, the data routing when transmitting data between the cores of the above single chip may include:

The first data routing:

CR->NoC (in the bank)->Core, the data routing is to use CR to send data to the NoC in the bank, and then pass it to the target core through different levels of NoC for calculation.

In some embodiments, as shown in FIG. 1, when the block connected to the data interface is the block where the target core is located, the external data is received and processed through the inter-chip routing module corresponding to the block connected to the data interface. And/or other inter-chip routing modules transmit the processed data to the target core, including:

External data is received and processed through the inter-chip routing module corresponding to the block connected to the data interface; the processed data is transmitted to the on-chip network in the block where the target core is located through the inter-chip routing module corresponding to the block connected to the data interface Node: The processed data is delivered to the target core through the on-chip network node in the block where the target core is located.

In some embodiments, as shown in FIG. 2, when the block connected to the data interface is not the block where the target core is located, the external data is received and processed through the inter-chip routing module corresponding to the block connected to the data interface. And/or other inter-chip routing modules transmit the processed data to the target core, including: receiving and processing external data through the inter-chip routing module corresponding to the block connected to the data interface; The inter-chip routing module transfers the processed data to the on-chip network node in the block connected to the data interface; passes the processed data to the on-chip in the block where the target core is located through the on-chip network node in the block connected to the data interface Network node: The processed data is delivered to the target core through the on-chip network node in the block where the target core is located.

The second data routing:

In some embodiments, as shown in FIG. 1, when the block connected to the data interface is the block where the target core is located, the external data is received and processed through the inter-chip routing module corresponding to the block connected to the data interface. And/or other inter-chip routing modules transmit the processed data to the target core to realize the reception and processing of external data and the transmission of processed data between the cores of a single chip, including:

Receive and process external data through the inter-chip routing module corresponding to the block connected to the data interface; pass the processed data to other inter-chip routing modules through the inter-chip routing module corresponding to the block connected to the data interface until the destination core The inter-chip routing module corresponding to the adjacent block of the block where the target core is located; the inter-chip routing module corresponding to the adjacent block where the target core is located transmits the processed data to the adjacent block of the target core block On-chip network node; through the on-chip network node in the adjacent block where the target core is located, the processed data is transferred to the on-chip network node in the block where the target core is located; processed by the on-chip network node in the block where the target core is located The later data is passed to the destination core.

In some embodiments, as shown in Figure 2, when the block connected to the data interface is not the block where the target core is located, the external data is received and processed through the inter-chip routing module corresponding to the block connected to the data interface, and the external data is processed through the network on chip. And/or other inter-chip routing modules transmit the processed data to the target core, including:

Receive and process external data through the inter-chip routing module corresponding to the block connected to the data interface; pass the processed data to other inter-chip routing modules through the inter-chip routing module corresponding to the block connected to the data interface until the destination core The inter-chip routing module corresponding to the block where the target core is located; the inter-chip routing module corresponding to the block where the target core is located transmits the processed data to the on-chip network node in the block where the target core is located; The on-chip network node delivers the processed data to the target core.

The specific data routing can be as follows: the data first passes through the inter-chip routing module corresponding to the block connected to the data interface, then passes through other inter-chip routing modules in turn, until the inter-chip routing module corresponding to the block where the target core is located, and finally passes through the target core. The on-chip network nodes in the block are passed to the target core for calculation.

In some embodiments, the data transmission method further includes: a routing receiving module in the target core receives data, and a calculation module in the target core performs calculations based on the received data.

In some embodiments, the data transmission between blocks is realized through the inter-chip routing module, and the data transmission with the inter-chip routing module and the data transmission between the cores are realized through the on-chip network, including:

The data transmission method of the embodiment of the present disclosure is aimed at a many-core system, so it can also realize the transmission of data between cores of different chips, that is, data is transmitted from the source core of one chip to another through the inter-chip routing modules and the on-chip network. The target core of the chip.

Similarly, according to the above method, there are at least two data routes to choose from during the data transmission process. To determine which data route to choose for each actual data transmission process, a default data route can be set in advance (for example, through AI model training). The optimal data route obtained), when the data path of the data route is congested, another data route is switched as a backup.

The first data routing:

In some embodiments, transmitting data from the source core of one chip to the destination core of another chip through the inter-chip routing modules and the on-chip network includes:

The data is transferred to the on-chip network node in the block where the source core of the first chip is located through the source core of the first chip; the data is transferred to the source of the first chip through the on-chip network node in the block where the source core of the first chip is located The inter-chip routing module corresponding to the block where the core is located; the inter-chip routing module corresponding to the block where the source core of the first chip is located transmits data to other inter-chip routing modules of the first chip; through other chips of the first chip The inter-chip routing module transmits data to the inter-chip routing module corresponding to the block of the first chip connected to the second chip; the data is transmitted through the inter-chip routing module corresponding to the block of the first chip connected to the second chip The inter-chip routing module corresponding to the block where the target core of the second chip is located; the inter-chip routing module corresponding to the block where the target core of the second chip is located is used to transfer data to the block where the target core of the second chip is located On-chip network node: The data is transferred to the target core of the second chip through the on-chip network node in the block where the target core of the second chip is located.

The specific data routing can be as follows: the data is first transmitted through the source core of the first chip (Chip0) to the on-chip network node in the block where the source core is located, and then through the inter-chip routing module corresponding to the block where the source core is located, and then sequentially pass through The other inter-chip routing modules of the first chip (Chip0) until the inter-chip routing module corresponding to the block on the first chip (Chip0) connected to the block where the target core of the second chip (Chip1) is located, and then pass through the second chip (Chip1) The inter-chip routing module corresponding to the block where the target core is located is finally delivered to the target core through the on-chip network node in the block where the target core is located.

The second data routing:

The data is transferred to the on-chip network node in the block where the source core of the first chip is located through the source core of the first chip; the data is transferred to the other on the first chip through the on-chip network node in the block where the source core of the first chip is located On-chip network nodes in a block; through on-chip network nodes in other blocks of the first chip to transmit data to the inter-chip routing module corresponding to the block of the first chip connected to the second chip; The inter-chip routing module corresponding to the block of the connected first chip transmits data to the inter-chip routing module corresponding to the block where the target core of the second chip is located; the chip corresponding to the block where the target core of the second chip is located The inter-routing module transfers the data to the on-chip network node in the block where the target core of the second chip is located; and transfers the data to the target core of the second chip through the on-chip network node in the block where the target core of the second chip is located.

The specific data routing can be as follows: data is first transferred to the on-chip network node in the block where the source core is located through the source core of the first chip (Chip0), and then transferred to the on-chip network node in other blocks of the first chip (Chip0) The inter-chip routing module corresponding to the block on the first chip (Chip0) connected to the block where the target core of the second chip (Chip1) is located, and then the inter-chip routing module corresponding to the block where the target core of the second chip (Chip1) is located After the routing module, it is finally transferred to the target core through the on-chip network node in the block where the target core is located for calculation.

At the same time, it should be understood that if the first chip where the source core is located and the second chip where the destination core is located are not directly connected, but indirectly connected through other chips, it is also feasible; that is, during the data transmission process, it is also necessary to pass through other chips. In each other chip, data can be transmitted through the inter-chip routing module or through the on-chip network.

In the process of data transmission, in multiple inter-chip routing modules, the data is transmitted in a predetermined clockwise direction.

In the embodiment of the present disclosure, each chip includes a plurality of (for example, 3 or more) inter-chip routing modules, and these inter-chip routing modules are divided into "a circle" along the circumferential direction of the chip, wherein any two in the circumferential direction A data connection in a certain direction is formed between two adjacent inter-chip routing modules, so that in these inter-chip routing modules, data is transmitted in a predetermined clockwise direction (clockwise or counterclockwise), or in other words, forms a "ring ( loop)".

Of course, it should be understood that the clockwise and counterclockwise directions are related to the direction of "seeing" the chip, but no matter which direction you "see" from, the actual data transmission direction between the inter-chip routing modules will not change.

For example, referring to Figures 1 and 2, each chip includes 4 inter-chip routing modules, and in these two figures, data can pass through multiple inter-chip routing modules in a clockwise direction, that is, transmitted from CR0 to CR1. Transfer from CR1 to CR2, from CR2 to CR3, and from CR3 to CR0 (not shown by arrows in the transfer diagram); it cannot be direct back propagation, for example, data cannot be directly transferred from CR0 to CR3.

Of course, the above limitation only indicates the transmission direction of data in the inter-chip routing modules of a chip, and referring to Figure 3, the inter-chip routing module on one chip can also be connected with the inter-chip routing modules of other chips to transmit data To other chips, the data transmission between the inter-chip routing modules of different chips does not necessarily conform to a specific clockwise direction.

According to the above method, only the transmission line between the inter-chip routing modules is arranged in a single direction, which can effectively save the chip area and break through the limitation of the manufacturing process.

In particular, data transmission between inter-chip routing modules usually has a large bandwidth and low delay, so even if it is only transmitted in a predetermined clockwise direction, it will not cause a significant increase in transmission time.

Of course, if the data transmission direction is not limited (for example, the data between the adjacent inter-chip routing modules can be transmitted in "two-way"), or the "network-like" connection between the inter-chip routing modules is also feasible, which can further improve the data transmission Speed and performance of many-core systems.

In a data transmission method of the embodiment of the present disclosure, the entire data transmission process can be divided into two parts: the AI model part and the board (many-core system) data processing part;

AI model part: The work of the AI model is completed on the server side (such as a server or a computer), and the AI model will be trained according to certain rules to obtain data routing information (that is, the optimal data routing). According to the results of the training, the server will combine the data to be transmitted to the board through the PCIE interface into the form of "data part (128bits) + data header (128bit)" according to the compilation rules of the tool chain, and send it to the board via the PCIE interface To the board. The "data part" includes the content of the actual data to be transmitted, and the "data header" contains the data routing information obtained by training, so that the many-core system can select the default data routing based on the data routing information.

Board data processing part: The PCIE interface of the board receives the data (external data) sent by the server and converts it into data that can be received and processed by the inter-chip routing module (CR). The inter-chip routing module receives the data and unpacks and packs the data. Then, the next step of data transmission is carried out, such as sending the data to the network node on chip (NoC) or inter-chip routing module, etc., and finally transmitted to the target core for processing. Among them, the actual data route used can refer to the foregoing, for example, the best data route in the data route information of the "data header" is used by default, and other data routes are selected when congested.

In the third aspect, the embodiments of the present disclosure provide a board (such as a printed circuit board) on which any one of the on-chip network interconnection structures of the embodiments of the present disclosure is integrated.

In a fourth aspect, an embodiment of the present disclosure provides an electronic device including a memory and a processor, where the memory is used to store one or more computer instructions, and one or more computer instructions can be executed by the processor to implement the embodiments of the present disclosure Any of the data transmission methods.

In some embodiments, the electronic device may be a server, a terminal, or the like.

In some embodiments, the electronic device includes: at least one processor; a memory communicatively connected with the at least one processor; and a communication component communicatively connected with other external storage media, the communication component receiving and sending data under the control of the processor Wherein, the memory stores instructions that can be executed by at least one processor, and the instructions are executed by at least one processor to implement the data transmission method of the many-core system in the foregoing embodiment.

In some embodiments, the memory, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules. The processor executes various functional applications and data processing of the electronic device by running non-volatile software programs, non-volatile computer executable programs and modules stored in the memory, that is, realizing the data transmission method of the above-mentioned many-core system .

In some embodiments, the memory may include a program storage area and a data storage area, where the program storage area may store an operating system and an application program required by at least one function; the storage data area may store a list of options and the like.

In some embodiments, the memory may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one magnetic disk storage device, a flash memory device, or other non-volatile solid-state storage devices.

In some embodiments, the memory may optionally include a memory remotely arranged with respect to the processor, and these remote memories may be connected to an external device through a network. Examples of the aforementioned networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

In some embodiments, one or more modules are stored in the memory, and when the one or more modules are executed by the processor, the data transmission method of the many-core system in any of the foregoing method embodiments is executed.

The above-mentioned electronic device can execute the data transmission method of the many-core system provided in the embodiment of the present disclosure, and has the corresponding functional modules and beneficial effects of the execution method. For details, refer to the data transmission method of the many-core system provided in the embodiment of the present disclosure.

In a fifth aspect, embodiments of the present disclosure provide a computer-readable storage medium on which computer program instructions are stored, and the computer program instructions implement any data transmission method in the embodiments of the present disclosure when executed by a processor.

In some embodiments, the computer-readable storage medium is used to store a computer-readable program, and the computer-readable program is used for a computer to execute some or all of the above-mentioned embodiments of the many-core system data transmission method.

In some embodiments, the computer-readable program to be executed can be written in any combination of one or more programming languages. The programming languages include: object-oriented programming languages such as C++, etc.; and conventional process programming languages such as " C" programming language or similar assembly language.

Those skilled in the art can understand that all or part of the steps in the data transmission method of the above embodiment can be implemented by instructing relevant hardware through a program. The program is stored in a storage medium and includes several instructions to enable a device (It may be a single-chip microcomputer, a chip, etc.) or a processor (processor) executes all or part of the steps of the data transmission method of the embodiment of the present disclosure. The aforementioned storage media include: on-chip memory or Flash and other media that can store program codes.

Hereinafter, the embodiments of the present disclosure will be further described through three specific embodiments in conjunction with the accompanying drawings.

In Embodiment 1, the on-chip network interconnection structure of the embodiment of the present disclosure is adopted to realize the communication between the cores of a single chip. As shown in FIG. 1, data can be transmitted and sent to the target core through two kinds of data routes.

The first type: PCIE->CR0->NoC(bank0)->target Core (target core). Specifically, the data packet (PCIE protocol data packet) of the server Server passes through the inter-chip routing module CR0 corresponding to the block bank0, and then passes the on-chip network node in the block bank0 to the target Core for calculation.

The second type: PCIE->CR0->CR1->CR2->CR3->NoC(bank3)->NoC(bank0)->target Core (destination core). Specifically, the data packet (PCIE protocol data packet) of the server server first passes through the inter-chip routing module CR0 corresponding to block bank0, and then sequentially passes through the inter-chip routing module CR1 corresponding to block bank1, block bank2, and block bank3. The inter-chip routing module CR2 and the inter-chip routing module CR3 are then passed to the on-chip network node in bank0 through the on-chip network node in block bank3, and finally to the target Core for calculation.

As mentioned above, the server will select one of the two data routes according to the results of the AI model training, and send the data to the board through the PCIE interface. For example, the AI model training results choose the first data route by default. In this type of data routing, for example, when a certain on-chip network node data needs to wait before being transmitted, the data will be transmitted to the destination core through the second type of data routing.

In the second embodiment, the on-chip network interconnection structure of the embodiment of the present disclosure is adopted to realize the communication between the cores of a single chip. As shown in FIG. 2, data can be transmitted and sent to the target core through two kinds of data routes.

The first type: PCIE->CR0->NoC(bank0)->NoC(bank3)->target Core (target core). Specifically, the data packet (PCIE protocol data packet) of the server Server passes through the inter-chip routing module CR0 corresponding to the block bank0, and then passes the on-chip network node in the block bank0 to the on-chip network node in the block bank3, and finally to the Perform calculations in the target Core.

The second type: PCIE->CR0->CR1->CR2->CR3->NoC(bank3)->target Core (target core). Specifically, the data packet (PCIE protocol data packet) of the server server first passes through the inter-chip routing module CR0 corresponding to block bank0, and then sequentially passes through the inter-chip routing module CR1 corresponding to block bank1, block bank2, and block bank3. , Inter-chip routing module CR2 and inter-chip routing module CR3, and finally passed to the target Core through the on-chip network node in block bank3 for calculation.

In Embodiment 3, the on-chip network interconnection structure of the embodiment of the present disclosure is adopted to realize the communication between cores of different chips. As shown in FIG. 3, data can be transmitted and sent to the target core through two kinds of data routes.

The first type: Core(Chip0src)->NoC(Chip0bank0)->CR0(Chip0bank0)->CR1(Chip0bank1)->CR2(Chip0bank2)->CR3(Chip1bank3)->NoC(Chip1bank3) ->Core(Chip1 dst). Specifically, the data sent by the source core Core (Chip0src) of the first chip Chip0 is first transmitted to the inter-chip routing module corresponding to the block bank0 of the first chip Chip0 through the on-chip network node in the block bank0 of the first chip Chip0 CR0, and then pass through the inter-chip routing module CR1 and the inter-chip routing module CR2 corresponding to the bank1 and bank2 of the first chip Chip0, and then pass the inter-chip routing corresponding to the bank3 of the second chip Chip1 The module CR3 is finally transferred to the target core Core (Chip1 dst) of the second chip Chip1 through the on-chip network node in the block bank3 of the second chip Chip1 for calculation.

The second type: Core(Chip0src)->NoC(Chip0 bank0)->NoC(Chip0 bank3)->NoC(Chip0 bank2)->CR2(Chip0 bank2)->CR3(Chip1 bank3)->NoC(Chip1 bank3) ->Core(Chip1 dst). Specifically, the data sent by the source core Core (Chip0src) of the first chip Chip0 is first transmitted to the on-chip network node in the block bank3 of the first chip Chip0 through the on-chip network node in the block bank0 of the first chip Chip0, and then transmitted To the on-chip network node in the bank2 of the first chip Chip0, and then to the inter-chip routing module CR2 corresponding to the bank2 of the first chip Chip0, and then to the corresponding setting of the bank3 of the second chip Chip1 The inter-chip routing module CR3 of the second chip is finally transferred to the target core Core (Chip1 dst) of the second chip Chip1 through the on-chip network node in the block bank3 of the second chip Chip1 for calculation.

In the instructions provided here, a lot of specific details are explained. However, it can be understood that the embodiments of the present disclosure may be practiced without these specific details. In some instances, well-known methods, structures, and technologies are not shown in detail, so as not to obscure the understanding of this specification.

In addition, those of ordinary skill in the art can understand that although some embodiments described herein include certain features included in other embodiments but not other features, the combination of features of different embodiments means that they are within the scope of the present disclosure. Within and form different embodiments. For example, in the claims, any one of the claimed embodiments can be used in any combination.

Those skilled in the art should understand that although the present disclosure has been described with reference to exemplary embodiments, various changes may be made and equivalents may be substituted for its elements without departing from the scope of the embodiments of the present disclosure. In addition, without departing from the essential scope of the embodiments of the present disclosure, many modifications may be made to adapt a particular situation or material to the teaching of the present disclosure. Therefore, the present disclosure is not limited to the specific embodiments disclosed, but the present disclosure will include all embodiments falling within the scope of the appended claims.

Claims

A many-core system on-chip network interconnection structure, wherein the many-core system includes at least one chip, each chip integrates multiple cores, and the on-chip network interconnection structure includes:

At least two blocks located on the chip, each block includes at least one core;

An inter-chip routing module corresponding to each block, and each inter-chip routing module is configured to interact with at least one other inter-chip routing module; and,

It is configured as an on-chip network that interacts with each inter-chip routing module and exchanges data between each core.
The on-chip network interconnection structure according to claim 1, wherein:

At least part of the inter-chip routing modules corresponding to adjacent blocks are configured to interact.
The on-chip network interconnection structure according to claim 2, wherein at least part of the blocks are connected to a data interface for transferring external data;

The on-chip network interconnection structure is configured to realize the receiving and processing of external data and the transmission of the processed data between the cores of a single chip.
The on-chip network interconnection structure according to claim 3, wherein the inter-chip routing module corresponding to the block connected to the data interface is used to receive and process the external data transmitted by the data interface, and transmit the processed data to The on-chip network node in the block where the target core is located;

The on-chip network node in the block where the target core is located is used to receive the processed data and transfer the processed data to the target core;

Wherein, the block connected with the data interface is the block where the target core is located.
The on-chip network interconnection structure according to claim 3, wherein the inter-chip routing module corresponding to the block connected to the data interface is used to receive and process the external data transmitted by the data interface, and transmit the processed data to Other inter-chip routing modules, up to the inter-chip routing module corresponding to the adjacent block of the block where the target core is located;

The inter-chip routing module corresponding to the adjacent block of the block where the target core is located is used to receive the processed data and transfer the processed data to the adjacent block where the target core is located. On-chip network node;

The on-chip network node in a block adjacent to the target core is used to receive the processed data and transfer the processed data to the on-chip network node in the block where the target core is located;

The on-chip network node in the block where the target core is located is used to receive the processed data and transfer the processed data to the target core;

Wherein, the block connected with the data interface is the block where the target core is located.
The on-chip network interconnection structure according to claim 3, wherein the inter-chip routing module corresponding to the block connected to the data interface is used to receive and process the external data transmitted by the data interface, and transmit the processed data to The on-chip network node in the block connected with the data interface;

The on-chip network node in the block connected to the data interface is used to receive the processed data and transfer the processed data to the on-chip network node in the block where the target core is located;

The on-chip network node in the block where the target core is located is used to receive the processed data and transfer the processed data to the target core;

Wherein, the block connected with the data interface is not the block where the target core is located.
The on-chip network interconnection structure according to claim 3, wherein the inter-chip routing module corresponding to the block connected to the data interface is used to receive and process the external data transmitted by the data interface, and transmit the processed data to Other inter-chip routing modules, up to the inter-chip routing module corresponding to the block where the target core is located;

The inter-chip routing module corresponding to the block where the target core is located is used to receive the processed data and transfer the processed data to the on-chip network node in the block where the target core is located;

The on-chip network node in the block where the target core is located is used to receive the processed data and transfer the processed data to the target core;

Wherein, the block connected with the data interface is not the block where the target core is located.
7. The on-chip network interconnection structure according to any one of claims 4-7, wherein the target core comprises:

The routing receiving module is used to receive data;

The calculation module is used to perform calculations based on the received data.
The on-chip network interconnection structure according to claim 1, wherein the on-chip network interconnection structure is configured to realize data transmission between cores of multiple chips.
The on-chip network interconnection structure according to claim 9, wherein the inter-chip routing module corresponding to a block of the first chip is connected to the inter-chip routing module corresponding to a block of the second chip, so that the first chip The block of is connected to the block of the second chip;

The source core of the first chip is used to transfer data to the on-chip network node in the block where the source core of the first chip is located;

An on-chip network node in a block where the source core of the first chip is located, configured to receive the data and transfer the data to an inter-chip routing module corresponding to the block where the source core of the first chip is located;

The inter-chip routing module corresponding to the block where the source core of the first chip is located is used to receive the data and transfer the data to other inter-chip routing modules of the first chip until the first chip connected to the second chip Inter-chip routing module corresponding to the block of a chip;

The inter-chip routing module corresponding to the block of the first chip connected to the second chip is configured to receive the data and transfer the data to the inter-chip routing corresponding to the block where the target core of the second chip is located Module

An inter-chip routing module corresponding to the block where the target core of the second chip is located, configured to receive the data and transfer the data to the on-chip network node in the block where the target core of the second chip is located;

The on-chip network node in the block where the target core of the second chip is located is used to receive the data and transfer the data to the target core of the second chip.
The on-chip network interconnection structure according to claim 9, wherein the inter-chip routing module corresponding to a block of the first chip is connected to the inter-chip routing module corresponding to a block of the second chip, so that the first chip The block of is connected to the block of the second chip;

The source core of the first chip is used to transfer data to the on-chip network node in the block where the source core of the first chip is located;

The on-chip network node in the block where the source core of the first chip is located, configured to receive the data and transfer the data to the on-chip network node in other blocks of the first chip;

The on-chip network nodes in other blocks of the first chip are used to receive the data and transmit the data to the inter-chip routing module corresponding to the block of the first chip connected to the second chip;

The inter-chip routing module corresponding to the block of the first chip connected to the second chip is used to receive the data and transfer the data to the inter-chip routing corresponding to the block where the target core of the second chip is located Module

An inter-chip routing module corresponding to the block where the target core of the second chip is located, configured to receive the data and transfer the data to the on-chip network node in the block where the target core of the second chip is located;

The on-chip network node in the block where the target core of the second chip is located is used to receive the data and transfer the data to the target core of the second chip.
A data transmission method applied to a many-core system, wherein the many-core system includes at least one chip, each chip integrates multiple cores, each chip is provided with at least two blocks, each block includes at least one core, and each chip integrates multiple cores. Inter-chip routing modules are set corresponding to each block, and the data transmission method includes:

Data transmission between blocks is realized through the inter-chip routing module, data transmission with the inter-chip routing module and data transmission between the cores are realized through the on-chip network.
The data transmission method according to claim 12, wherein the realization of data transmission between blocks through the inter-chip routing module comprises:

The data transmission between adjacent blocks is realized by the inter-chip routing module.
The data transmission method according to claim 13, wherein at least part of the blocks are connected to a data interface for transferring external data; the inter-chip routing module is used to realize the data transmission between the blocks, and the inter-chip routing is realized through the on-chip network The data transmission of the module and the transmission of data between the cores include:

The external data is received and processed through the inter-chip routing module corresponding to the block connected to the data interface, and the processed data is transmitted to the target core through the on-chip network and/or other inter-chip routing modules to realize the reception and processing of external data The data is transmitted between the cores of a single chip.
The data transmission method according to claim 14, wherein the external data is received and processed through the inter-chip routing module corresponding to the block connected to the data interface, and the processed data is transmitted through the on-chip network and/or other inter-chip routing modules To the target core, including:

Receiving and processing the external data through an inter-chip routing module corresponding to the block connected to the data interface;

Transfer the processed data to the on-chip network node in the block where the target core is located through the inter-chip routing module corresponding to the block connected to the data interface;

Transfer the processed data to the target core through the on-chip network node in the block where the target core is located;

Wherein, the block connected with the data interface is the block where the target core is located.
The data transmission method according to claim 14, wherein the external data is received and processed through the inter-chip routing module corresponding to the block connected to the data interface, and the processed data is transmitted through the on-chip network and/or other inter-chip routing modules To the target core, including:

Receiving and processing the external data through an inter-chip routing module corresponding to the block connected to the data interface;

Transfer the processed data to other inter-chip routing modules through the inter-chip routing module corresponding to the block connected to the data interface until the inter-chip routing module corresponding to the adjacent block of the block where the target core is located;

Transmitting the processed data to the on-chip network node in the adjacent block of the target core through the inter-chip routing module corresponding to the adjacent block of the target core;

Transferring the processed data to the on-chip network node in the block where the target core is located through the on-chip network node in the adjacent block of the block where the target core is located;

Transfer the processed data to the target core through the on-chip network node in the block where the target core is located;

Wherein, the block connected with the data interface is the block where the target core is located.
The data transmission method according to claim 14, wherein the external data is received and processed through the inter-chip routing module corresponding to the block connected to the data interface, and the processed data is transmitted through the on-chip network and/or other inter-chip routing modules To the target core, including:

Receiving and processing the external data through an inter-chip routing module corresponding to the block connected to the data interface;

Transfer the processed data to the on-chip network node in the block connected to the data interface through the inter-chip routing module corresponding to the block connected to the data interface;

Transferring the processed data to the on-chip network node in the block where the target core is located through the on-chip network node in the block connected to the data interface;

Transfer the processed data to the target core through the on-chip network node in the block where the target core is located;

Wherein, the block connected with the data interface is not the block where the target core is located.
The data transmission method according to claim 14, wherein the external data is received and processed through the inter-chip routing module corresponding to the block connected to the data interface, and the processed data is transmitted through the on-chip network and/or other inter-chip routing modules To the target core, including:

Receiving and processing the external data through an inter-chip routing module corresponding to the block connected to the data interface;

Transfer the processed data to other inter-chip routing modules through the inter-chip routing module corresponding to the block connected to the data interface until the inter-chip routing module corresponding to the block where the target core is located;

Transmitting the processed data to the on-chip network node in the block where the target core is located through the inter-chip routing module corresponding to the block where the target core is located;

Transfer the processed data to the target core through the on-chip network node in the block where the target core is located;

Wherein, the block connected with the data interface is not the block where the target core is located.
The data transmission method according to any one of claims 14-18, further comprising:

The routing receiving module in the destination core receives the data, and the calculation module in the destination core performs calculations based on the received data.
The data transmission method according to claim 12, wherein the data transmission between the blocks is realized by the inter-chip routing module, the data transmission with the inter-chip routing module and the data transmission between the cores are realized through the on-chip network, including :

The data is transmitted from the source core of one chip to the destination core of another chip through the inter-chip routing modules and the on-chip network, so as to realize the transmission of data among the cores of multiple chips.
The data transmission method according to claim 20, wherein the inter-chip routing module corresponding to a block of the first chip is connected to the inter-chip routing module corresponding to a block of the second chip, so that the The block is connected to the block of the second chip; transmitting data from the source core of one chip to the destination core of another chip through the inter-chip routing modules and the on-chip network, including:

Transmitting data to the on-chip network node in the block where the source core of the first chip is located through the source core of the first chip;

Transmitting the data to an inter-chip routing module corresponding to the block where the source core of the first chip is located through an on-chip network node in the block where the source core of the first chip is located;

Transferring the data to other inter-chip routing modules of the first chip through an inter-chip routing module corresponding to the block where the source core of the first chip is located;

Transmitting the data to the inter-chip routing module corresponding to the block of the first chip connected to the second chip through other inter-chip routing modules of the first chip;

Transmitting the data to the inter-chip routing module corresponding to the block where the target core of the second chip is located through the inter-chip routing module provided corresponding to the block of the first chip connected to the second chip;

Transmitting the data to an on-chip network node in the block where the target core of the second chip is located through an inter-chip routing module corresponding to the block where the target core of the second chip is located;

The data is transferred to the target core of the second chip through an on-chip network node in the block where the target core of the second chip is located.
The data transmission method according to claim 20, wherein the inter-chip routing module corresponding to a block of the first chip is connected to the inter-chip routing module corresponding to a block of the second chip, so that the The block is connected to the block of the second chip; transmitting data from the source core of one chip to the destination core of another chip through the inter-chip routing modules and the on-chip network, including:

Transmitting data to the on-chip network node in the block where the source core of the first chip is located through the source core of the first chip;

Transmitting the data to network nodes on a chip in other blocks of the first chip through a network node on a chip in the block where the source core of the first chip is located;

Transmitting the data to the inter-chip routing module corresponding to the block of the first chip connected to the second chip through on-chip network nodes in other blocks of the first chip;

Transmitting the data to the inter-chip routing module corresponding to the block where the target core of the second chip is located through the inter-chip routing module provided corresponding to the block of the first chip connected to the second chip;

Transmitting the data to an on-chip network node in the block where the target core of the second chip is located through an inter-chip routing module corresponding to the block where the target core of the second chip is located;

The data is transferred to the target core of the second chip through an on-chip network node in the block where the target core of the second chip is located.
The data transmission method according to claim 12, wherein each chip includes a plurality of inter-chip routing modules arranged along its circumference; the realization of inter-block data transmission through the inter-chip routing module includes:

During data transmission, in multiple inter-chip routing modules on the same chip, data is transmitted in a predetermined clockwise direction.
A board card, wherein the board card is integrated with the on-chip network interconnection structure according to any one of claims 1-11.
An electronic device, comprising a memory and a processor, wherein the memory is used to store one or more computer instructions, wherein the one or more computer instructions can be executed by the processor to implement as claimed in claims 12-23 Any of the data transmission methods.
A computer-readable storage medium, wherein computer program instructions are stored on the computer-readable storage medium, and the computer program instructions, when executed by a processor, realize the data transmission according to any one of claims 12-23 method.