WO2021146979A1

WO2021146979A1 - Data storage system and method

Info

Publication number: WO2021146979A1
Application number: PCT/CN2020/073701
Authority: WO
Inventors: 刘荣斌; 王正波; 伍青青
Original assignee: 华为技术有限公司
Priority date: 2020-01-22
Filing date: 2020-01-22
Publication date: 2021-07-29
Also published as: CN114730594A

Abstract

A data storage system and method. The data storage system comprises a memory (20), a controller (10), and a temperature measurement circuit (30). The controller (10) is used for setting a temperature measurement period of the memory (20); the temperature measurement circuit (30) is used for measuring the temperature of the memory (20) according to the temperature measurement period, and transmitting, to the controller (10), measurement information corresponding to the temperature; the controller (10) is further used for determining the refresh frequency of the memory (20) according to the measurement information; and the memory (20) is used for performing refreshing according to the refresh frequency, so as to hold data stored by the memory (20).

Description

Data storage system and method

Technical field

This application relates to the field of memory technology, and in particular to a data storage system and method.

Background technique

The memory generally stores data according to the level state; and in the dynamic random access memory (Dynamic Random Access Memory, DRAM), the charge stored in the capacitor will disappear after a relatively short period of time, resulting in data failure, so it is to maintain storage If the data is not lost, the DRAM must be refreshed periodically, that is, the device must be charged to the initial charge level after reading the data repeatedly. The maximum allowable time between refresh operations is determined by the charge storage capacity of the capacitors that make up the DRAM cell array.

Currently, the DRAM refresh frequency is adjusted according to the temperature of the DRAM. Generally, a temperature detection circuit is built into the DRAM. Adjust the desired refresh frequency according to the temperature detection result of the circuit module; generally, the higher the temperature, the higher the desired refresh frequency. Specifically, the controller reads the mode register inside the DRAM, obtains the current temperature detection result of the DRAM, and determines the corresponding expected refresh frequency. For example, in a high bandwidth memory (High Bandwidth Memory, HBM) application, the DRAM outputs a 3-bit result in real time to indicate the desired refresh frequency.

However, the controller needs to read the mode register inside the DRAM periodically or in real time; as the number of reads increases, the data bus occupies more times, which increases the overhead and affects the effective memory access bandwidth of the DRAM; and, the detection cycle of the temperature detection circuit Can't be adjusted flexibly. In existing HBM applications, DRAM not only outputs temperature detection results in real time, but the detection temperature range corresponding to the output 3bit results cannot be adjusted; when the temperature fluctuates at the critical point of different temperature ranges (such as 16°C-25°C and 25°C) The critical point of -40°C is 25°C), there are mis-sampling results that lead to multiple adjustments of the refresh frequency; and real-time output of temperature detection results will cause a certain amount of energy consumption.

Therefore, how to reasonably adjust the temperature refresh frequency of the memory according to the temperature situation is an urgent problem to be solved.

Summary of the invention

The embodiments of the present application provide a data storage system and method, which can configure the temperature detection period of the memory; and according to the obtained temperature detection results, adjust the refresh frequency of the memory effectively and reasonably.

In the first aspect, an embodiment of the present application provides a data storage system, including:

A memory, a controller, and a temperature detection circuit; the controller is connected with the temperature detection circuit; the memory is connected with the controller;

The controller is used to set the temperature detection period of the memory;

The temperature detection circuit is used for:

Detecting the temperature of the memory according to the temperature detection period;

Sending detection information corresponding to the temperature to the controller;

The controller is further configured to set the refresh frequency of the memory according to the detection information;

The memory is used for refreshing according to the refresh frequency.

The embodiment of the application mainly configures the temperature detection cycle of the memory by the controller, so that the controller can obtain the temperature of the memory according to a certain cycle (for example, the temperature range of the memory temperature at a certain moment); according to the temperature of the memory, pass The controller adjusts the refresh frequency in the memory. Specifically, the temperature detection cycle of the memory is set by the controller; when the count value reaches the temperature detection cycle (for example, the cycle is 50us, and the count value corresponding to 50us is reached after resetting the detection cycle), the temperature detection circuit detects the memory The current temperature, and the target detection information corresponding to the current temperature is sent to the controller; after the controller receives the target detection information, the corresponding refresh frequency is determined to instruct the memory to refresh to maintain the stored data. However, in the prior art, the temperature detection cycle cannot be changed by the controller, and is usually a fixed value or real-time temperature detection, which makes it difficult to obtain memory temperature information reasonably; and the acquisition of temperature information requires occupying a data bus, which causes an increase in overhead. By implementing the embodiments of the present application, not only can different temperature detection periods be configured according to system requirements, but also the energy consumption generated by real-time monitoring can be reduced. Further, the refresh frequency of the memory is adjusted in time according to the temperature information, and the data bus is not occupied to obtain the temperature detection result, which effectively improves the memory access efficiency.

In a possible implementation manner, the system further includes: a counter connected to the controller; the controller is further configured to send the temperature detection period to the counter; the counter is configured to : Cycle counting until the count value reaches the temperature detection period; when the count value reaches the temperature detection period, send a detection instruction to the temperature detection circuit; the temperature detection circuit is specifically used to: When the instruction is detected, the temperature of the memory is detected, and the detection information corresponding to the temperature is sent to the controller. In the embodiment of this application, the set temperature detection period is sent to the counter through the controller; after receiving the temperature detection period, the counter starts to count from the initial value (for example, 0) until the count value (corresponding time) reaches the detection period value. The counter triggers the temperature detection circuit to perform temperature detection. The accurate calculation of the relationship between the time and the set period through the counting of the counter helps the temperature detection circuit to accurately detect the temperature according to the period.

In a possible implementation manner, the controller is further configured to send a detection instruction to the temperature detection circuit according to the temperature detection cycle; the temperature detection circuit is specifically configured to detect when the detection instruction is received The temperature of the memory, and sending detection information corresponding to the temperature to the controller. In the embodiment of the present application, the controller sends a detection instruction to the temperature detection circuit according to the temperature detection cycle. Among them, the controller integrates the function of cycle counting, and sends a detection command at a certain moment to make the temperature detection circuit enter the enabled state.

In a possible implementation manner, the temperature detection circuit is specifically configured to: determine a target temperature range in which the temperature of the memory is located, and the target temperature range is among the multiple temperature ranges managed by the temperature detection circuit One of; sending detection information corresponding to the target temperature range to the controller. In the embodiment of the present application, after the temperature is detected by the temperature detection circuit, combined with multiple preset temperature ranges, it is determined that the temperature range of the temperature is a certain temperature range of the multiple temperature ranges (for example, the temperature range is -40 to -10). ℃); Send the target detection information corresponding to the temperature range to the controller (such as 000 in the 3bit temperature data). In the embodiment of this application, a variety of temperature ranges are sent as the basis for adjusting the refresh frequency. On the one hand, it conforms to the corresponding relationship between the temperature of the memory and the refresh frequency (that is, the corresponding refresh frequency within a certain temperature range of the memory is consistent, such as 20- The same refresh frequency is applicable within 30°C); on the other hand, due to the lack of sufficient input and output ports (ie I/O ports) in the memory to output specific temperature values, the use of the output temperature range can reduce the occupation of I/O and The temperature range (for example, the number of bits corresponding to the output) can be adjusted to increase or decrease the use of the I/O port to adapt to the specific memory configuration.

In a possible implementation manner, the system further includes: a register connected to the controller; the register is also connected to the temperature detection circuit; the register is used to store one or more detection information A plurality of first temperature ranges corresponding to each detection information in the plurality of first temperature ranges, the one or more detection information includes the target detection information; the controller is further configured to: determine from the plurality of first temperature ranges The second temperature range matched by each detection information; the register is further used to send the second temperature range matched by each detection information to the temperature detection circuit. In the embodiment of the present application, from the multiple first temperature ranges stored in the register, the controller selects the second temperature range that each detection information matches; for example, the detection information is 000 in 3bit data, and the register stores the corresponding value of 000. 4 temperature ranges (such as -40～-10℃, -40～-15℃, -40～-5℃ and -40～0℃); the default temperature range corresponding to 000 is -40～-10℃. The temperature range corresponding to 000 can be changed by the controller, that is, the temperature range corresponding to the configuration detection information can be configured, and the temperature range configuration can be performed on 8 kinds of detection information to meet the refreshing requirements of different memories or the adaptable temperature under different conditions of the same memory.

In a possible implementation manner, the detection information includes information used to indicate a target temperature range in which the temperature of the memory is located, and the controller is specifically configured to: determine the target according to the detection information Temperature range; according to the target temperature range, the refresh frequency of the memory is determined. In the embodiment of the present application, the target detection information is obtained from the temperature detection circuit by the controller; the temperature range corresponding to the detection information is determined according to the target detection information; the refresh frequency corresponding to the temperature range is determined by the controller. According to the detection information in different temperature ranges, different refresh frequencies can be determined to adapt to the temperature changes of the memory.

In a possible implementation manner, the temperature detection circuit is specifically configured to: send the target detection information to the controller through a pin. In the embodiment of the present application, the target detection information is directly sent to the controller through the pins of the temperature detection circuit, so as to avoid the situation that the controller reads the target temperature detection from the register and causes the bus occupation.

In a possible implementation manner, the controller is further configured to send a refresh instruction to the memory according to the refresh frequency; the memory is specifically configured to: receive the refresh instruction, and according to the refresh instruction Perform automatic refresh to maintain the data stored in the memory. In the embodiment of the present application, the controller sends a refresh instruction to the memory according to the determined refresh frequency to instruct the memory to refresh in time, so as to keep the stored data from being lost.

In a possible implementation manner, the temperature detection cycle is 64 clock cycles, 128 clock cycles, 256 clock cycles, 512 clock cycles, 1024 clock cycles, 2048 clock cycles, or 4096 clock cycles. The embodiments of the present application provide a variety of different cycle configurations to meet different energy consumption requirements. For example, if 4096 clock cycles (ie, temperature detection cycles) are configured to perform a temperature detection, and the temperature detection enable time is 8 clock cycles, then the energy consumption after the configuration cycle is reduced to 1/512 compared with the case of real-time detection.

In a possible implementation manner, the controller is further configured to shorten the temperature detection period when the degree of change of the detection information in the temperature detection period is greater than a preset change threshold. According to the embodiment of the present application, the temperature detection period is adjusted according to the temperature change of the memory or the requirements of the system to adapt to the current operating condition of the memory.

In a possible implementation manner, the controller is further configured to send one or more temperature configuration parameters to the register, and the one or more temperature configuration parameters are used to determine one or more temperature configuration parameters stored in the register. The first temperature range matched by each of the two detection information. In the embodiment of the application, the temperature configuration parameter sent by the controller to the register is used to accurately adjust and configure the temperature range corresponding to the detection information.

In a second aspect, an embodiment of the present application provides a data storage device applied to a dynamic random access memory, including: a memory, a controller connected to the memory, the memory including a temperature detection circuit; the controller, The temperature detection circuit is used to set a temperature detection period for the memory; the temperature detection circuit is used to: detect the temperature of the memory when the count value reaches the temperature detection period; and send the temperature to the controller Corresponding target detection information; the controller is further configured to: determine the refresh frequency of the memory according to the target detection information; the memory is configured to refresh according to the refresh frequency to maintain the memory storage The data.

In a possible implementation manner, the memory further includes a counter connected to the temperature detection circuit; the controller is further configured to send the temperature detection period to the counter; and the counter is configured to : Cycle counting until the count value reaches the temperature detection period; when the count value reaches the temperature detection period, send a detection instruction to the temperature detection circuit; the temperature detection circuit is specifically used to: In the detection instruction, the temperature of the memory is detected, and target detection information corresponding to the temperature is sent to the controller.

In a possible implementation manner, the temperature detection circuit is specifically configured to: determine the target temperature range in which the temperature is located from one or more first temperature ranges; and determine the target temperature range that matches the target temperature range. Target detection information; sending the target detection information to the controller.

In a possible implementation manner, the memory further includes a register connected to the temperature detection circuit for storing multiple first temperature ranges corresponding to each detection information in one or more detection information, and The one or more detection information includes the target detection information; the controller is further configured to: determine a second temperature range matched by each detection information from the plurality of first temperature ranges; the register It is also used to send the second temperature range matched by each detection information to the temperature detection circuit.

In a possible implementation manner, the controller is specifically configured to: determine the target temperature range according to the detection information; and determine the refresh frequency of the memory according to the target temperature range.

In a possible implementation manner, the temperature detection circuit is specifically configured to: send the detection information to the controller through a pin.

In a possible implementation manner, the controller is further configured to send a refresh instruction to the memory according to the refresh frequency; the memory is specifically configured to: receive the refresh instruction, and according to the refresh instruction Refresh is performed to maintain the data stored in the memory.

In a possible implementation manner, the temperature detection cycle is 64 clock cycles, 128 clock cycles, 256 clock cycles, 512 clock cycles, 1024 clock cycles, 2048 clock cycles, or 4096 clock cycles.

In a possible implementation manner, the controller is further configured to shorten the temperature detection period when the degree of change of the detection information in the temperature detection period is greater than a preset change threshold.

In a third aspect, an embodiment of the present application provides a data storage method, including: setting a temperature detection period of a memory, and the temperature detection period is a period in which a temperature detection circuit detects the temperature of the memory and sends detection information corresponding to the temperature. cycle;

Receiving the detection information from the temperature detection circuit according to the temperature detection period;

The refresh frequency of the memory is set according to the detection information.

In a possible implementation manner, the method further includes:

Sending the temperature detection period to the counter;

Counting cyclically through the counter until the count value reaches the temperature detection period;

When the count value reaches the temperature detection period, a detection instruction is sent to the temperature detection circuit through the counter, and the detection instruction is used to instruct the temperature detection circuit to detect the temperature of the memory and send the Detection information corresponding to temperature.

In a possible implementation manner, it is characterized in that the method further includes:

Send a detection instruction to the temperature detection circuit according to the temperature detection cycle; the detection instruction is used to instruct the temperature detection circuit to detect the temperature of the memory, and send detection information corresponding to the temperature.

In a possible implementation manner, the detection information includes information used to indicate a target temperature range in which the temperature of the memory is located, and the refresh frequency of the memory is set according to the detection information, include:

Determining the target temperature range according to the detection information;

According to the target temperature range, the refresh frequency of the memory is set.

According to the refresh frequency, a refresh instruction is sent to the memory; the refresh instruction is used to instruct the memory to refresh.

In a possible implementation manner, the method further includes:

When the degree of change of the detection information in the temperature detection period is greater than a preset change threshold, the temperature detection period is shortened.

In a possible implementation manner, the receiving the detection information from the temperature detection circuit includes:

The detection information is received from the temperature detection circuit through a pin.

In a fourth aspect, an embodiment of the present application provides a chip system, which can be implemented by executing the method described in any one of the third aspect.

In a fifth aspect, an embodiment of the present application provides an electronic device, which may include: the data storage device as described in the first or second aspect above, and a discrete device coupled to the outside of the data storage device.

In a sixth aspect, an embodiment of the present application provides a terminal, the terminal includes a processor, and the processor is configured to support the terminal to perform a corresponding function in the data storage method provided in the third aspect. The terminal may also include a memory, which is used for coupling with the processor and stores necessary program instructions and data for the terminal. The terminal may also include a communication interface for the terminal to communicate with other devices or communication networks.

Description of the drawings

In order to more clearly describe the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings that need to be used in the description of the embodiments.

FIG. 1 is a schematic diagram of a data storage system architecture provided by an embodiment of the present application;

2 is a schematic diagram of another data storage system architecture provided by an embodiment of the present application;

FIG. 3 is a schematic diagram of a data storage function corresponding to FIG. 2 provided by an embodiment of the present application;

4 is a schematic diagram of a part of the structure of a data storage device provided by an embodiment of the present application;

FIG. 5 is a schematic diagram of a part of the structure of another data storage device provided by an embodiment of the present application;

FIG. 6 is a schematic diagram of a periodic detection process of a temperature detection circuit provided by an embodiment of the present application;

FIG. 7 is a schematic partial structural diagram of yet another data storage device provided by an embodiment of the present application; FIG.

FIG. 8 is a schematic flowchart of a data storage method provided by an embodiment of the present application;

FIG. 9 is a schematic structural diagram of a device provided by an embodiment of the present application.

Detailed ways

The embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

The terms "first", "second", "third" and "fourth" in the specification and claims of this application and the drawings are used to distinguish different objects, not to describe a specific order ; And the objects described by the terms "first", "second", "third" and "fourth" may also be the same objects, or contain each other or have other relationships. In addition, the terms "including" and "having" and any variations of them are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes unlisted steps or units, or optionally also includes Other steps or units inherent to these processes, methods, products or equipment.

The reference to "embodiments" herein means that a specific feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art clearly and implicitly understand that the embodiments described herein can be combined with other embodiments.

The terms "component", "module", "system", etc. used in this specification are used to denote computer-related entities, hardware, firmware, a combination of hardware and software, software, or software in execution. For example, the component may be, but is not limited to, a process, a processor, an object, an executable file, an execution thread, a program, and/or a computer running on a processor. Through the illustration, both the application running on the computing device and the computing device can be components. One or more components may reside in processes and/or threads of execution, and components may be located on one computer and/or distributed among two or more computers. In addition, these components can be executed from various computer readable media having various data structures stored thereon. The component can be based on, for example, a signal having one or more data packets (e.g. data from two components interacting with another component in a local system, a distributed system, and/or a network, such as the Internet that interacts with other systems through a signal) Communicate through local and/or remote processes.

It should be noted that the module in the embodiment of the present application can be understood as a coupling of a circuit or a device; the embodiment of the present application does not limit this.

First of all, some terms in this application are explained to facilitate the understanding of those skilled in the art.

(1) Dynamic random access memory (Dynamic Random Access Memory, DRAM) is a type of semiconductor memory. Its main function is to use the amount of charge stored in a capacitor to represent whether a binary bit (bit) is 1 or 0. Due to the leakage current phenomenon of the transistor, the amount of charge stored on the capacitor is not enough to correctly distinguish the data, which leads to data corruption. Therefore, for DRAM, it needs to be charged periodically to store data normally.

(2) Enable, which can be an input pin of the chip or an input port of the circuit. Only when the pin is activated, for example, when it is set to a high level, the entire module can work normally. Enabling is not just about controlling, it is a kind of demand response that needs to meet certain conditions. For example, when the enable terminal is active at low level, the circuit realizes the NAND function; when the enable terminal is at high level, the circuit is in a high impedance state. The enabling application range is also very wide. For example, the flip-flops and counters of the power number will have an enable terminal to control their work or other components to work.

(3) The clock period, also known as the oscillation period, is defined as the reciprocal of the clock frequency. The clock cycle is the most basic and smallest unit of time in a computer. In one clock cycle, the CPU only completes one of the most basic actions. A clock period is a quantity of time. The clock cycle can represent the highest frequency that the memory (such as synchronous dynamic random access memory) can run. A smaller clock cycle means a higher operating frequency.

(4) Bit (binary digit, bit) is the smallest unit of information, which is the information contained in one bit of a binary number or the amount of information required to specify one of the two options. Generally speaking, the amount of information of n bits can show 2 n-th power options. For example: the word length of a computer is 16 bits, that is, 16 binary bits, the numerical information it represents is 0-65535.

(5) Decoding is the inverse process of encoding, and at the same time removes the noise mixed in the bit stream during the propagation process. The process of using a decoding table to translate text into a group of numbers or using a decoding table to translate a series of signals representing a certain item of information into text is called decoding.

(6) Refresh means that the capacitor used to record the logical value of DRAM has a significant leakage phenomenon (discharge phenomenon) due to technical difficulties in all aspects, and the potential drops, and the high-potential capacitor is periodically charged and maintained. Its a stable process.

(7) Registers are small storage areas used to store data. They are used to temporarily store data and calculation results involved in operations. They are a commonly used sequential logic circuit, but this sequential logic circuit only contains memory circuits. The storage circuit of the register is composed of latches or flip-flops. Because a latch or flip-flop can store a 1-bit binary number, N latches or flip-flops can form an N-bit register. The register is an integral part of the central processing unit. Registers are high-speed storage components with limited storage capacity. They can be used to temporarily store instructions, data, and addresses.

The following first describes a system architecture based on the embodiment of the present application. Please refer to Figure 1. Figure 1 is a schematic diagram of a data storage system architecture provided by an embodiment of the present application. As shown in Figure 1, the system architecture includes a controller. 10. The memory 20 and the temperature detection circuit 30. Optionally, the controller 10, the memory 20, and the temperature detection circuit 30 may be three independent logic circuits or devices; or, the memory 20 may include the temperature detection circuit 30 and the controller 10; or, the memory 20 may include a temperature detection circuit 30. The controller 10 may be an independent device independent of the memory 20; this is not limited in the embodiment of the present application. in,

The controller 10 is used to set a temperature detection cycle for the memory 20; before the controller 10 configures the temperature detection cycle, the temperature detection circuit 30 can detect the temperature of the memory 20 in real time and feed back detection information to the controller 10, or according to a preset fixed Detect and feedback periodically. When the controller 10 sets the temperature detection period and reaches the temperature detection period, the temperature detection circuit 30 (or temperature detection circuit) is triggered to detect the temperature of the memory and feedback corresponding detection information to the controller 10. The controller 10 adjusts the refresh frequency of the memory 20 according to the target detection information.

The memory 20 is used to store data and automatically refresh according to the refresh frequency set by the controller 10 (that is, the memory performs self-refresh), so as to maintain the data stored in the memory.

The temperature detection circuit 30 is configured to detect the temperature of the memory 20 according to the temperature detection period set by the controller 10 and feed back target detection information corresponding to the detected temperature to the controller 10. The controller 10 may analyze the target detection information to obtain the corresponding temperature range, and then determine the refresh frequency according to the temperature range. Alternatively, the controller 10 may directly determine the refresh frequency according to the target detection information.

It can be understood that the system architecture in FIG. 1 is only an exemplary implementation in the embodiment of the present application, and the system architecture in the embodiment of the present application includes but is not limited to the above system architecture.

The following is another system architecture involved in the embodiments of the present application. Please refer to Figures 2 and 3. Figure 2 is a schematic diagram of another data storage system architecture provided by an embodiment of the present application; Figure 3 is a schematic diagram of a data storage function corresponding to Figure 2 provided by an embodiment of the present application; Figure 2 As shown in Figure 3, the system architecture includes a memory 20 (taking DRAM as an example) and a controller 10; among them,

The memory 20 includes a register 201, a temperature detection circuit 30, and a counter 202; the register 201 is connected to the temperature detection circuit 30; the counter 202 is connected to the temperature detection circuit 30; specifically, the register 201 can store multiple detection information and the temperature range corresponding to the detection information It is sent to the temperature detection circuit 30 to configure the temperature detection range; when the temperature detection circuit 30 detects the current temperature of the memory 20, it is determined according to the received multiple temperature ranges that the current temperature is within the temperature range of the multiple temperature ranges Which range. The counter 202 is used to receive the temperature detection period configured by the controller, and when the count value reaches the temperature detection period, trigger the temperature detection circuit to perform temperature detection and feed back the temperature result to the controller 10.

The controller 10 includes a first circuit 101, a second circuit 102, and a third circuit 103; the first circuit 101 is used to set the temperature range matched by each detection information from a plurality of temperature ranges stored in the register; the second circuit 102 uses To receive the target detection information, and determine the refresh frequency according to the target detection information; send a refresh command to the temperature detection circuit according to the refresh frequency; the third circuit 103 is used to set the temperature detection period and send the temperature detection period to the counter.

It can be understood that the system architecture in FIG. 2 is only an exemplary implementation in the embodiments of the present application, and the application scenarios in the embodiments of the present application include but are not limited to the above application scenarios.

In the following, in conjunction with the system architecture shown in FIG. 2 above, the technical problems proposed in this application will be specifically analyzed and resolved.

Please refer to FIG. 4, which is a partial structural diagram of a data storage device provided by an embodiment of the present application; the data storage device can be applied to a data storage system architecture (including the system architecture shown in FIG. 2 above). Wherein, the data storage device includes DRAM 20 (ie, memory 20) and a controller 10; the controller 10 is connected to the DRAM 20; specifically, the DRAM includes a built-in temperature detection circuit 30 and a refresh command decoding module 203; the controller 10 includes The temperature structure receiving module 104 and the refresh operation management module (ie, the second circuit) 102. in,

The controller 10 is used to set the temperature detection period of the memory (ie, the timing period shown in the figure). Specifically, the controller may adjust the temperature detection period of the memory through a built-in circuit (such as a counting circuit or a counting module). Before setting a new temperature detection period by the controller, the temperature detection period is a preset default temperature detection period or a temperature detection period before the setting. Optionally, after a new temperature detection period is set by the controller, the controller may output a detection instruction (for example, an enable signal) according to the temperature detection period to instruct the temperature detection circuit to perform temperature detection on the memory. For example, after receiving the detection instruction, the temperature detection circuit ends the sleep state and starts to detect the temperature of the memory according to the preset detection frequency.

As shown in Figure 4, the temperature detection circuit 20 outputs a 3bit temperature result, and uses the corresponding interface to directly send a 3bit interface signal corresponding to the 3bit temperature result to the controller; optionally, the 3bit interface information can be obtained by encoding according to the 3bit temperature result data. After the controller 10 receives the 3bit interface signal sent by the DRAM through the interface or pin, it receives and parses the interface signal through the built-in temperature result receiving module. The controller obtains the corresponding 3bit temperature result through analysis, and determines the temperature range of the current temperature of the memory according to the 3bit temperature result; then adjusts the timing period according to the temperature range. The adjusted timing period data is sent to the refresh operation management module 102 (that is, the second circuit 102 shown in FIG. 2), and the refresh operation management module sends the new timing period data to the DRAM through the memory control interface in the controller. Cycle change instructions. After the DRAM receives the cycle change instruction including the new timing cycle data, the instruction decoding module 203 decodes the instruction. In the new timing period, control the built-in temperature detection circuit to detect its own temperature.

Optionally, the controller 10 is specifically configured to determine the target temperature range according to the detection information; and determine the refresh frequency of the memory according to the target temperature range. For example, the temperature range corresponding to the target detection information is 6-40°C, and the refresh frequency suitable for the memory is determined according to the temperature range 6-40°C. Wherein, the detection information may correspond to a specific temperature of the memory or a temperature range in which the specific temperature of the memory is located. For example, when the detection information corresponds to the specific temperature of the lung memory, the controller can obtain the specific temperature situation of the memory at a certain moment or within a certain period of time through the detection information. For another example, when the detection information corresponds to the temperature range of the memory temperature, the controller can determine the temperature range of the memory through the detection information, and then match with multiple preset temperature ranges to determine the refresh frequency of the memory.

Further optionally, the controller 10 is further configured to send a refresh instruction to the memory according to the refresh frequency; the memory is specifically configured to receive the refresh instruction, and automatically refresh according to the refresh instruction, To keep the data stored in the memory. For example, if the refresh frequency of the memory suitable for the current temperature is determined according to the target detection information (such as refreshing the data stored in the memory every 5s), then the data of the memory is refreshed every 5s to ensure that the data is not lost.

In a possible implementation manner, the controller is further configured to: shorten the temperature detection period when the degree of change of the target detection information within a preset number of temperature detection cycles is greater than a preset change threshold. The controller adjusts the temperature detection cycle of the memory according to the system demand or the historical temperature change trend of the DRAM. For example, in summer or in an environment where the temperature is relatively high, the temperature detection cycle is shortened to accurately obtain the temperature information of the memory (such as DRAM) to avoid data loss. In a low-temperature environment or the memory temperature changes slowly, the temperature detection cycle can be extended (for example, 128 clock cycles are set to 512 clock cycles) to reduce the energy consumption of the device without data loss.

In a possible implementation manner, the device further includes a counter connected to the controller; the counter is also connected to the temperature detection circuit; the controller sends the temperature detection period to the counter The counter is used to count cyclically until the count value reaches the temperature detection period; when the count value reaches the temperature detection period, send a detection instruction to the temperature detection circuit; the temperature detection circuit, Specifically, when receiving the detection instruction, detect the temperature of the memory, and send target detection information corresponding to the temperature to the controller. The temperature detection circuit is configured to detect the temperature of the memory when the count value reaches the temperature detection period; send target detection information corresponding to the temperature to the controller; the controller is also configured to The target detection information determines the refresh frequency of the memory; the memory is used to refresh according to the refresh frequency.

Please refer to FIG. 5. FIG. 5 is a partial structural diagram of another data storage device provided by an embodiment of the present application; as shown in FIG. 5, the data storage device can be applied to a data storage system architecture (including the system shown in FIG. 1 above). Architecture). Specifically, the controller 10 includes a counter 202, a temperature detection cycle configuration register (that is, a third circuit) 103, and an enable control module 105; wherein, the enable control module 105 is used to control the enable of DRAM memory temperature reading; for example, The enable control module 105 updates the memory temperature enable command to instruct the memory to stop or start temperature detection. The counter 202 is built in the controller 10 and is used for timing or counting according to the configured time period. Optionally, the counter 202, the temperature detection period configuration register 101, and the enable control module 105 may be devices independent of the controller 10. The controller 10 can be connected to the DRAM through a preset memory control interface.

Optionally, the counter 202 may be integrated in the memory or connected to the controller in other ways.

The DRAM 20 includes a temperature detection circuit 30, a temperature detection enable module 204, and a command decoding module 203. Among them, the command decoding module 203 is also used to decode the commands received by the memory, so as to control the operation of the temperature detection enabling module. Optionally, the DRAM may also decode the commands through other command decoding modules; this embodiment of the present application does not limit this.

Further optionally, the working enable period of the temperature detection circuit of the DRAM is configurable. The larger the detection period, the greater the power saving; for example, the temperature detection period can be 64 clock cycles, 128 clock cycles, and 256 clock cycles. , 512 clock cycles, 1024 clock cycles, 2048 clock cycles or 4096 clock cycles. For example, if the controller sends the cycle configuration parameter 000 to the counter (3Bit data is used as an example in this application), the counter monitors the temperature of the memory in real time; if the controller sends the cycle configuration parameter 001 to the counter, the counter every 64 clock cycles Check the temperature once. Please refer to Table 1 for specific other period configuration parameters, as shown in the following table:

Table 1

周期配置Period configuration	周期配置含义Period configuration meaning
000000	实时检测DRAM的温度Detect the temperature of DRAM in real time
001001	64时钟周期64clock cycle
010010	128时钟周期128clock cycle
011011	256时钟周期256clock cycle
100100	512时钟周期512clock cycle
101101	1024时钟周期1024clock cycle
110110	2048时钟周期2048clock period
111111	4096时钟周期4096clock cycle

As shown in Table 1, if the configuration is 4096 clock cycles and a temperature detection is performed, assuming that the temperature detection enable time is 8 cycles, the power consumption introduced by the temperature detection will be reduced to 1/512 compared with the real-time detection. . It should be noted that the embodiment of the present application does not limit the form of the period configuration parameter. Table 1 shows only an exemplary parameter form and meaning.

Configure the temperature detection cycle through the controller, and judge whether the configured cycle time is reached according to the counting result of the counter. After reaching the cycle time, the counter triggers the temperature detection circuit to perform temperature detection. Optionally, a high level (that is, a detection command) is sent to the temperature detection circuit through the counter, and the temperature detection circuit performs temperature detection after receiving the high level. It should be understood that the high level is an exemplary detection instruction; the embodiment of the present application does not limit the specific enabling mode.

The temperature detection circuit is specifically configured to determine the target temperature range in which the temperature is located from one or more first temperature ranges; determine the target detection information that matches the target temperature range; send to the controller The target detection information (the detection information in this embodiment of the application is 3bit data). Specifically, after the temperature detection circuit is enabled, it starts to detect the current temperature of the DRAM. The embodiment of the present application does not limit the specific circuit design inside the temperature detection circuit and the manner of detecting the temperature. For example, the temperature detection circuit can be composed of a comparator, a resistor divider circuit, a counter and other circuits. After the temperature detection circuit obtains the current temperature of the DRAM, the temperature range of the temperature is determined. When only one temperature range is set, then the current temperature can only correspond to the preset temperature range. When multiple temperature ranges are set, the temperature value can be used to determine which temperature range the temperature is in. For example, if it is detected that the current DRAM temperature is 10°C and the preset temperature range is 1-25°C, then it can be judged that the current temperature is in the temperature range 1-25°C. Optionally, the temperature detection circuit detects the temperature of the DRAM by detecting the voltage change of the circuit. The embodiment of the present application does not limit the specific method of detecting the temperature.

Please refer to FIG. 6, which is a schematic diagram of the cycle detection process of a temperature detection circuit provided by an embodiment of the present application; as shown in FIG. 6, after the temperature detection cycle is set by the controller, the counter receives the cycle of the temperature detection cycle. When counting, start counting until the count value reaches the corresponding number of cycles; the counter triggers the temperature detection circuit to detect the temperature; the temperature detection circuit detects the temperature and outputs the detection information (ie, the temperature detection result) to the controller, and then makes the temperature detection circuit enable invalid. Optionally, after configuring the temperature detection cycle, the counter can set an initial value of the count, start counting from the initial value, and compare with the preset number of cycles after each count is completed to determine whether to adjust the counting cycle.

Optionally, after determining the temperature range corresponding to the current DRAM temperature, the temperature detection circuit outputs detection information matching the temperature range to the controller. For example, the detection information corresponding to 1-25°C is 001, and the detection information 001 is sent to the controller. Optionally, the detection information may be 4 bits or other bits of data. When the detection information is 3bit data, 8 temperature ranges can be set. Set the number of bits of the detection information according to the actual temperature detection requirements and temperature range requirements.

It should be noted that the output result of the temperature detection circuit in the embodiment of this application uses the temperature range as an example; however, this application does not limit the actual output result, that is, the temperature detection circuit can output the actual temperature value of the memory or the temperature of the memory. temperature range.

The embodiment of the application mainly configures the temperature detection cycle of the memory by the controller, so that the controller can obtain the temperature of the memory according to a certain cycle (for example, the temperature range of the memory temperature at a certain moment); according to the temperature of the memory, pass The controller adjusts the refresh frequency in the memory. Specifically, the temperature detection cycle of the memory is set by the controller; when the count value reaches the temperature detection cycle (for example, the cycle is 50us, and the count value corresponding to 50us is reached after resetting the detection cycle), the temperature detection circuit detects the memory The current temperature, and the target detection information corresponding to the current temperature is sent to the controller; after the controller receives the target detection information, the corresponding refresh frequency is determined to instruct the memory to refresh the stored data. However, in the prior art, the temperature detection cycle cannot be changed by the controller, and is usually a fixed value or real-time temperature detection, which makes it difficult to obtain memory temperature information reasonably; and the acquisition of temperature information requires occupying a data bus, which causes an increase in overhead. By implementing the embodiments of the present application, not only can different temperature detection periods be configured according to system requirements, but also the energy consumption generated by real-time monitoring can be reduced. Further, the refresh frequency of the memory is adjusted in time according to the temperature information, and the data bus is not occupied to obtain the temperature detection result, which effectively improves the memory access efficiency.

In a possible implementation manner, the device further includes a register connected to the controller; the register is also connected to the temperature detection circuit; the register is used to store each of one or more detection information A plurality of first temperature ranges corresponding to one piece of detection information, the one or more pieces of detection information includes the target detection information; the controller is further configured to determine each of the plurality of first temperature ranges A first temperature range matched by the detection information; the register is also used to send the first temperature range matched by each detection information to the temperature detection circuit.

Please refer to FIG. 7. FIG. 7 is a partial structural diagram of another data storage device provided by an embodiment of the present application; as shown in FIG. 7, the data storage device can be applied to a data storage system architecture (including the above-mentioned FIG. 1 or FIG. 2). System architecture shown). specifically,

The controller 10 includes a temperature detection configuration management module (first circuit) 101. Optionally, the controller is configured to connect the temperature range configuration management module 101 and the temperature adjustment register 201 by configuring a corresponding interface. In the case that the total detection temperature range is -40 to 125°C, the temperature adjustment register can send seven temperature parameters to the temperature detection circuit 30, for example, temperature adjustment G1, temperature adjustment G2, ..., temperature adjustment G1. The embodiment of the present application takes the output of a 3-bit temperature value result and the 2-bit temperature adjustment parameter as an example. For example, temperature adjustment G7 is 2bit data, which can include four adjustment values of 00, 01, 10, and 11. Under the aforementioned assumptions, the number of output parameters for the 2-bit temperature adjustment parameter for the 3-bit temperature range (that is, including 8 temperature adjustable temperature ranges such as 000-111) is 7 types. The embodiments of the present application do not limit other digits and temperature ranges. It should be noted that the upper and lower limits of the total temperature range generally cannot be adjusted. The embodiment of the present application does not limit the upper or lower limit of the adjustable temperature range corresponding to the temperature adjustment parameter.

The DRAM 20 includes a temperature adjustment register 201 and a temperature detection circuit 30; the temperature detection circuit 30 is used to output a 3bit temperature value result after temperature detection, and send a 3bit interface signal to the corresponding interface of the controller 10, or directly send the 3bit temperature value result to the control器10. It is understandable that the controller 10 can obtain the current temperature range of the DRAM by analyzing the 3bit interface signal, which will not be repeated here.

In conjunction with Figure 7, the temperature adjustment register 201 describes the temperature range adjustment of the temperature detection circuit. Please refer to Table 2. As shown in Table 2, the register stores 8 detection information (ie 000～111), each of which is stored The candidate temperature ranges corresponding to one detection information (ie the output result of the temperature detection circuit) can be 4 types; for example, the candidate temperature ranges corresponding to 000 are -40～-10℃, -40～-15℃, -40～- 5℃, -40～0℃. The first column is the default temperature range, that is, the temperature range that the detection information output by the temperature detection circuit matches when the temperature range is not selected; for example, the default temperature range for 000 matching is -40 to -10°C. After the controller selects one of the four alternative temperature ranges of 000 (such as -40 to 0°C), the temperature detection circuit detects that the temperature of the DRAM falls within the range of -40 to 0°C, and then controls The output of the device is 000; the controller determines the current temperature range of the DRAM is -40 to 0°C through the temperature configuration parameter and 000, so as to determine the temperature refresh frequency within the temperature range.

It should be understood that the output results of the temperature detection circuit shown in Table 2 in the embodiments of the present application, the candidate temperature range, and 3bit data (such as 000) and 2bit data (such as 01) are all exemplary descriptions; embodiments of the present application There is no restriction on this. For example, 5bit data corresponds to 32 types of configuration options, which can be the configuration of the temperature range, the configuration of the detection period, or the configuration of the detection information.

Table 2

In a possible implementation manner, the controller adjusts the temperature range corresponding to the detection information through temperature configuration parameters. As shown in Table 2, 00-11 is part of the 2bit temperature configuration parameters, used to select the temperature range matched by the corresponding detection information. For example, the controller sends 5 bits of data (such as 00011) to the register. The first 3 bits are used to determine the detection information 000 among the 8 detection information stored in the register; the last 2 bits (ie 11) are used to determine the temperature range corresponding to the detection information 000. -40～0℃.

In a possible implementation manner, the temperature detection circuit is specifically configured to send the target detection information to the controller through a pin. For example, the pins of the temperature detection circuit responsible for outputting detection information are directly connected to the input pins of the controller. After the temperature detection circuit obtains the detection information, the pins directly output the detection information to the controller without passing through the bus.

Under the aforementioned system and device, in the embodiment of the present application, the data storage device is a DRAM as an example for description. The DRAM includes: a memory (that is, a memory array), a controller connected to the memory, the memory includes a temperature detection circuit; the controller is used to set a temperature detection period for the memory; the temperature detection circuit , Used to: when the count value reaches the temperature detection period, detect the temperature of the memory; send target detection information corresponding to the temperature to the controller; the controller is further used to: The target detection information determines the refresh frequency of the memory; the memory is configured to refresh according to the refresh frequency to maintain the data stored in the memory.

In a possible implementation manner, the memory further includes a register connected to the temperature detection circuit for storing multiple first temperature ranges corresponding to each detection information in one or more detection information, and The one or more detection information includes the target detection information; the controller is further configured to: determine a first temperature range matched by each of the detection information from the plurality of first temperature ranges; the register It is also used to send the first temperature range matched by each detection information to the temperature detection circuit.

In a possible implementation manner, the controller is specifically configured to: determine the target temperature range according to the target detection information; and determine the refresh frequency of the memory according to the target temperature range.

In a possible implementation manner, the temperature detection circuit is specifically configured to: send the target detection information to the controller through a pin.

In a possible implementation manner, the controller is further configured to: shorten the temperature detection period when the degree of change of the target detection information within a preset number of temperature detection cycles is greater than a preset change threshold.

The specific data storage device and application scenarios are described above, and the method embodiments involved in the present application are described below.

Please refer to FIG. 8. FIG. 8 is a schematic flowchart of a data storage method provided by an embodiment of the present application; the data storage method is applied to a data storage system (including the aforementioned system architecture). Wherein, the data storage system includes a controller, a memory, and a temperature detection circuit, which will be described from a single side of the controller with reference to FIG. 8. The method may include the following steps S801 to S803.

Step S801: Set a temperature detection period for the memory.

Specifically, the controller sets a temperature detection period for detecting the temperature of the memory by sending an instruction to the memory. The temperature detection period is a period during which the temperature detection circuit detects the temperature of the memory and sends target detection information corresponding to the temperature.

In a possible implementation manner, the setting the temperature detection period for the memory includes: sending the temperature detection period to a counter; counting cyclically through the counter until the count value reaches the temperature detection period; A detection instruction is sent to the temperature detection circuit through the counter, and the detection instruction is used to instruct the temperature detection circuit to send the target detection information.

Step S802: When the count value reaches the temperature detection period, receive the target detection information from the temperature detection circuit.

Specifically, when the time reaches the corresponding temperature detection period, the controller receives target detection information (or temperature detection result information) from the temperature detection circuit. The embodiment of the application does not limit this.

Step S803: Determine the refresh frequency of the memory according to the target detection information.

Specifically, the controller parses the received target detection information, and determines, according to the target detection information, that the current temperature range of the memory belongs to a certain range of the preset temperature range; determines the refresh frequency of the memory according to the temperature range; wherein, The refresh frequency is the frequency at which the memory is refreshed.

In a possible implementation manner, the method further includes: determining a first temperature range matched by each detection information from a plurality of first temperature ranges stored in a register; The circuit sends the first temperature range matched by each detection information.

In a possible implementation manner, the determining the refresh frequency of the memory according to the target detection information includes: determining the target temperature range according to the target detection information; determining the target temperature range according to the target temperature range The refresh frequency of the memory.

In a possible implementation manner, the receiving the target detection information from the temperature detection circuit includes: receiving the target detection information from the temperature detection circuit through a pin.

In a possible implementation manner, the method further includes: sending a refresh instruction to the memory according to the refresh frequency; the refresh instruction is used to instruct the memory to refresh so as to maintain the stored data.

In a possible implementation manner, the method further includes: shortening the temperature detection period when the degree of change of the target detection information within a preset number of temperature detection cycles is greater than a preset change threshold.

It should be noted that, for the data storage method described in the embodiment of the present application, reference may be made to the related description of the data storage device in the device embodiment described in FIG. 4 to FIG. 6, which will not be repeated here.

As shown in FIG. 9, FIG. 9 is a schematic structural diagram of a device provided by an embodiment of the present application. The data storage apparatus may be implemented with the structure in FIG. 9, and the device 90 includes at least one processor 901 and at least one memory 902. In addition, the device may also include general components such as a power supply, which will not be described in detail here.

The processor 901 may be a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits used to control the execution of the above program programs.

The memory 902 may be a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, random access memory (RAM), or other types that can store information and instructions The dynamic storage device can also be electrically erasable programmable read-only memory (Electrically Erasable Programmable Read-Only Memory, EEPROM), CD-ROM (Compact Disc Read-Only Memory, CD-ROM) or other optical disc storage, optical disc storage (Including compact discs, laser discs, optical discs, digital versatile discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or can be used to carry or store desired program codes in the form of instructions or data structures and can be used by a computer Any other media accessed, but not limited to this. The memory can exist independently and is connected to the processor through a bus. The memory can also be integrated with the processor.

Wherein, the memory 902 is used to store application program codes for executing the above solutions, and the processor 901 controls the execution. The processor 901 is configured to execute application program codes stored in the memory 902.

When the device shown in FIG. 9 is a data storage device (such as DRAM), the code stored in the memory 902 can execute the data storage method provided in FIG. 8, for example, setting a temperature detection cycle for the memory, the temperature detection cycle being temperature detection The circuit detects the temperature of the memory and sends the cycle of target detection information corresponding to the temperature; when the count value reaches the temperature detection cycle, receives the target detection information from the temperature detection circuit; according to the target detection information , Determine the refresh frequency of the memory; the refresh frequency is the frequency at which the memory refreshes data. In the embodiment of the present application, the hardware analysis circuit built in the memory can analyze the related instructions sent by the controller; the controller inputs the instructions into the memory, and the memory completes the analysis of the instructions through the corresponding hardware analysis circuit (ie command analysis circuit) , So as to complete the refresh operation and temperature detection operation. The embodiment of the present application does not limit the specific connection relationship between the device 90, the controller 901, and the memory 902.

It should be noted that, for the functions of the device 90 described in the embodiment of the present application, reference may be made to the related description in the device embodiment described in the above-mentioned FIG. 4 to FIG. 6, which will not be repeated here.

In the above-mentioned embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in an embodiment, reference may be made to related descriptions of other embodiments.

It should be noted that for the foregoing method embodiments, for the sake of simple description, they are all expressed as a series of action combinations, but those skilled in the art should know that this application is not limited by the described sequence of actions. Because according to this application, some steps may be performed in other order or at the same time. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by this application.

In the several embodiments provided in this application, it should be understood that the disclosed device may be implemented in other ways. For example, the device embodiments described above are only illustrative, for example, the division of the above-mentioned units is only a logical function division, and there may be other divisions in actual implementation, for example, multiple units or components can be combined or integrated. To another system, or some features can be ignored, or not implemented. In addition, the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical or other forms.

The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.

In addition, the functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or software functional unit.

If the above integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable storage medium. Based on this understanding, the technical solution of the present application essentially or the part that contributes to the existing technology or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium , Including several instructions to make a computer device (which may be a personal computer, a server, or a network device, etc., specifically a processor in a computer device) execute all or part of the steps of the foregoing methods of the various embodiments of the present application. Among them, the aforementioned storage media may include: U disk, mobile hard disk, magnetic disk, optical disk, read-only memory (Read-Only Memory, abbreviation: ROM) or Random Access Memory (Random Access Memory, abbreviation: RAM), etc. A medium that can store program codes.

As mentioned above, the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: The technical solutions recorded in the embodiments are modified, or some of the technical features are equivalently replaced; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

A data storage system is characterized in that it comprises:

Memory, controller and temperature detection circuit;

The controller is used to set the temperature detection period of the memory;

The temperature detection circuit is used for:

Detecting the temperature of the memory according to the temperature detection period;

Sending detection information corresponding to the temperature to the controller;

The controller is further configured to set the refresh frequency of the memory according to the detection information;

The memory is used for refreshing according to the refresh frequency.
The system according to claim 1, wherein the system further comprises a counter;

The controller is also used for:

Sending the temperature detection period to the counter;

The counter is used for:

Counting cyclically until the count value reaches the temperature detection period;

When the count value reaches the temperature detection period, sending a detection instruction to the temperature detection circuit;

The temperature detection circuit is specifically used for:

When the detection instruction is received, the temperature of the memory is detected, and the detection information corresponding to the temperature is sent to the controller.
The system according to claim 1, wherein the controller is further configured to:

Sending a detection instruction to the temperature detection circuit according to the temperature detection cycle;

The temperature detection circuit is specifically used for:

When the detection instruction is received, the temperature of the memory is detected, and the detection information corresponding to the temperature is sent to the controller.
The system according to any one of claims 1 to 3, wherein the temperature detection circuit is specifically used for:

Determining a target temperature range in which the temperature of the memory is located, where the target temperature range is one of a plurality of temperature ranges managed by the temperature detection circuit;

Sending the detection information corresponding to the target temperature range to the controller.
The system according to any one of claims 1 to 4, wherein the detection information includes information used to indicate a target temperature range in which the temperature of the memory is located, and the controller is specifically configured to:

Determining the target temperature range according to the detection information;

According to the target temperature range, the refresh frequency of the memory is determined.
The system according to any one of claims 1-5, wherein the temperature detection circuit is specifically used for:

The detection information is sent to the controller through a pin.
The system according to any one of claims 1-6, wherein:

The controller is further configured to send a refresh instruction to the memory according to the refresh frequency;

The memory is specifically configured to receive the refresh instruction, and perform refresh according to the refresh instruction.
The system according to any one of claims 1-7, wherein the temperature detection cycle is 64 clock cycles, 128 clock cycles, 256 clock cycles, 512 clock cycles, 1024 clock cycles, 2048 clock cycles, Clock cycles or 4096 clock cycles.
The system according to any one of claims 1-8, wherein the controller is further configured to:

When the degree of change of the detection information in the temperature detection period is greater than a preset change threshold, the temperature detection period is shortened.
A data storage method, characterized in that it comprises:

Setting a temperature detection period of the memory, the temperature detection period being a period during which the temperature detection circuit detects the temperature of the memory and sends detection information corresponding to the temperature;

Receiving the detection information from the temperature detection circuit according to the temperature detection period;

The refresh frequency of the memory is set according to the detection information.
The method according to claim 10, wherein the method further comprises:

Sending the temperature detection period to the counter;

Counting cyclically through the counter until the count value reaches the temperature detection period;

When the count value reaches the temperature detection period, a detection instruction is sent to the temperature detection circuit through the counter, and the detection instruction is used to instruct the temperature detection circuit to detect the temperature of the memory and send the Detection information corresponding to temperature.
The method according to claim 10, wherein the method further comprises:

Send a detection instruction to the temperature detection circuit according to the temperature detection cycle; the detection instruction is used to instruct the temperature detection circuit to detect the temperature of the memory, and send detection information corresponding to the temperature.
The method according to any one of claims 10-12, wherein the detection information includes information for indicating a target temperature range in which the temperature of the memory is located, and the detection information is used to set the The refresh frequency of the memory, including:

Determining the target temperature range according to the detection information;

According to the target temperature range, the refresh frequency of the memory is set.
The method according to any one of claims 10-13, wherein the method further comprises:

According to the refresh frequency, a refresh instruction is sent to the memory; the refresh instruction is used to instruct the memory to refresh.
The system according to any one of claims 10-14, wherein the temperature detection cycle is 64 clock cycles, 128 clock cycles, 256 clock cycles, 512 clock cycles, 1024 clock cycles, 2048 clock cycles, Clock cycles or 4096 clock cycles.
The system according to any one of claims 10-15, wherein the method further comprises:

When the degree of change of the detection information in the temperature detection period is greater than a preset change threshold, the temperature detection period is shortened.
The method according to any one of claims 10-16, wherein the receiving the detection information from the temperature detection circuit comprises:

The detection information is received from the temperature detection circuit through a pin.
A chip system, characterized in that the chip system is implemented by executing the method according to any one of claims 10-17.