WO2021144941A1 - Digital/analog synthesis integrator and δς modulator using same - Google Patents

Abstract

When a high-order bit portion and a low-order bit portion of a digital input Din are respectively defined as DinH and DinL (Din = DinH + DinL), this digital/analog synthesis integrator has a low-order bit digital integrator and a low-order bit D/A converter (DAC-L) for the low-order bit portion DinL. The digital/analog synthesis integrator has a high-order bit D/A converter (DAC-H) and a high-order bit analog integrator for the high-order bit portion DinH. In addition, the digital/analog synthesis integrator is characterized in that an output of the high-order bit analog integrator and an analog output of the low-order bit D/A converter (DAC-L) are added by an analog circuit in order to obtain a final integrator output Vo.

Description

Digital / analog composite integrator and delta-sigma modulator using it

The technology disclosed herein relates to a digital / analog synthetic integrator and a delta-sigma modulator using it.

The delta-sigma analog-to-digital converter (delta-sigma analog-to-digital converter, delta-sigma ADC) is widely known as an A / D conversion method capable of achieving high resolution (for example, a resolution of 14 bits or more), and has been put into practical use. There is. The ΔΣ type A / D converter is composed of a ΔΣ modulator in the front stage and a digital filter in the rear stage. The delta-sigma modulator samples the analog input, converts it into a coarsely quantized digital value (digital signal sequence) with a relatively small number of bits of 1 bit or several bits (for example, 2 to 6 bits), and outputs it. When the quantization noise component biased toward the high frequency side (noise shape) is removed from the digital signal sequence of this ΔΣ modulator output with a subsequent digital filter, the digital output is finally converted to high resolution A / D. To get.

In the delta-sigma modulator, the difference between the analog input value and the digital output value (to be exact, the analog input value and the digital output value are converted into an analog amount by the feedback digital / analog (D / A) converter (feedback DAC). It has an "integrator" that integrates the (difference from the converted value). Corresponding to the input of the A / D converter being an analog voltage, the integrator of the delta-sigma modulator is generally an "analog integrator" that realizes the integration process by analog circuit calculation. On the other hand, since the output of the delta-sigma modulator is a digital value, a DAC that converts it into an analog value is required. Generally, an analog integrator is shared by a circuit, and the difference between the analog input sampling value and the feedback DAC output value is integrated.

A capacitor element is an integrator that originally stores a voltage as an electric charge, and is therefore generally used in an analog integrator. For example, in Non-Patent Document 1, there are two types of integrators using operational amplifiers, a continuous-time integrator using a resistor as an input sampling element, and a discrete-time integrator using a capacitor as an input sampling element (a discrete-time integrator). There is a description of Discrete-time integrator). If the reference voltages Vref + and Vref- are switched according to the digital input value, it operates as a 1-bit DAC. Therefore, Vref + or Vref- is switched and input as Vin in Figure 12.56 of p441 of Non-Patent Document 1 to perform the integration calculation. If done, a 1-bit DAC and an integrator can be realized. If a plurality of capacitors are used as C1, it becomes a multi-bit DAC and an integrator.

On the other hand, the integrator used for the delta-sigma modulator may be not only an integrator using an operational amplifier (Active integrator) but also an integrator without an operational amplifier (passive integrator). For example, Patent Document 1 discloses such a ΔΣ modulator. The 1-bit digital output delta-sigma modulator has a 1-bit feedback DAC input and can be realized by switching 1 element (1 pair in the case of a differential circuit), the circuit scale is small, and the influence of element matching has an effect. It has often been used because it provides linear D / A conversion characteristics.

On the other hand, a multi-bit (2-bit or more) output delta-sigma modulator requires a feedback DAC with a multi-bit digital input, which generally complicates the circuit a little, but has many advantages that a 1-bit delta-sigma modulator does not have. , This is also often selected by design (see Chapter 6 of Non-Patent Document 2). In particular, as disclosed in Patent Document 1, when a passive integrator is used as an integrator, the integrator output amplitude becomes smaller due to multi-bitization, so that the input amplitude of the post-stage quantizer becomes smaller and the linearity is improved. , The integrator leak is reduced, and the characteristics of the A / D converter can be improved.

Japanese Unexamined Patent Publication No. 2016-100871

As mentioned above, a multi-bit output delta-sigma modulator requires a multi-bit DAC. In an actual integrated circuit, the multi-bit DAC has an error due to a mismatch of the element groups (for example, capacitor trains) constituting the multi-bit DAC. If there is an integrator after the DAC output, there is a drawback that the mismatch error is constantly integrated into the integrator and the linearity deteriorates.

Dynamic Element Matching (DEM) technology is known as a method for improving this. In this method, the selected elements are sequentially switched and averaged so that the error due to the element mismatch is not unevenly integrated. One of them is a technique called "Data-Weighted Averaging (DWA)" or "Element rotation method" described in Non-Patent Document 3.

A brief explanation of DWA. First, the digital binary code is converted into a thermometer code (Thermometer code), and a plurality of unit elements constituting the DAC are made to correspond to each bit of the thermometer code. Then, it has an internal pointer (digital value) for sequentially switching the elements, and the mismatch is averaged by periodically selecting the elements so as not to be biased. The element mismatch is canceled when the pointer goes around. In addition, some methods have been proposed as a method for canceling the element mismatch of the DAC. For example, Non-Patent Document 4 describes another example.

However, in the conventional DEM technology, as the number of bits increases, the number of elements of the MOS switch and the capacitor constituting the DAC increases exponentially, and in order to individually switch and control each element by the DEM, a circuit is required. It is complicated and difficult to design, and the chip area is increased, resulting in high cost. For example, in a DAC with a digital input of 6 bits 0000000 to 100,000 (0 to 32 in decimal), 32 unit capacitors (32 pairs of unit capacitor pairs in the case of a differential circuit configuration) and corresponding analog switches (MOS switches). )is necessary. As the number of bits of the DAC increases, the scale of the analog circuit becomes large and the wiring layout becomes complicated, errors due to parasitic capacitance of the wiring and the switch occur, and it is easy to cause non-linearity and unintended offset voltage generation. In general, in analog integrated circuits, unlike digital circuits, it is difficult to automatically generate layouts, and designers have to design and check layouts with their eyes and hands. For this reason, in order to obtain high linearity characteristics in a multi-bit DAC, design, evaluation, and design modification are often repeated, and development involves considerable difficulty, or development labor (labor cost), period, and prototyping. Development may be unsuccessful due to costs.

In view of the above circumstances, the technique disclosed in the present specification takes a digital value Din as an input and integrates this digital value sequence (Din (1), Din (2), ...) on the time axis or time series. It is embodied in a digital / analog composite integrator that converts a value (ΣDin) into an analog value (generally an analog voltage Vo) and outputs it.

In this digital / analog composite integrator, the upper bits of the digital input Din are set to DinH, the lower bits are set to DinL (Din = DinH + DinL), and the lower bits DinL are integrated by digital calculation (ΣDinL). Has an integrator. In this low-order bit digital integrator, if an overflow occurs as a result of digital integration of the low-order bit DinL, the carry (Carry) is output to the high-order bit DinH and added by digital calculation (DinH + Carry). At the same time, the same carry is subtracted from the lower-order bit digital integrator (Σ (DinL-Carry)). That is, after performing the carry processing from the result of the digital integration of the lower bit DinL to the upper bit, the lower bit digital integrator ignores the carry and sets its own output. The digital / analog composite integrator further has a low-order bit D / A converter (DAC-L) that converts the output (Σ (DinL-Carry)) of the low-order bit digital integrator into an analog value.

The digital / analog composite integrator is a high-order bit D / A converter (DAC-H) that converts the high-order bit digital value (DinH + Carry), which is the sum of the carry-ups, into an analog value for the high-order bit DinH. It has a high-order bit analog integrator that integrates the analog value after conversion by the high-order bit D / A converter by analog calculation (Σ (DinH + Carry)).

Then, in the digital / analog composite integrator according to the present technology, the output of the high-order bit analog integrator and the analog output of the low-order bit D / A converter (DAC-L) are added and calculated by an analog circuit, and the final integrator output Vo It is characterized by obtaining.

In the above configuration, the error due to the mismatch of the lower bits DAC-L is not integrated, so the average error appearing in the integrator output is dispersed on the time axis. For example, in an oversampling system, the error in the signal band appearing at the output is significantly reduced. Therefore, the mismatch canceling DEM usually required for a high-resolution multi-bit DAC can secure sufficient linearity with a small-bit DEM having only the high-order bit DAC-H, and a large-scale multi-bit DEM circuit is unnecessary. Therefore, the circuit scale can be significantly reduced. As a result, the circuit and layout design can be facilitated, and the chip area can be reduced to reduce the cost.

In one embodiment of the present technology, the high-order bit D / A converter may include one or a plurality of high-order capacitors according to the number of bits of the high-order bit DinH. When there are a plurality of upper capacitors, the plurality of upper capacitors may have equal capacities with each other. Further, the lower bit D / A converter may include one or more lower capacitors according to the number of bits of the lower bit DinL. When there are a plurality of lower capacitors, the plurality of lower capacitors may have different capacities depending on the position of the corresponding bit. Further, each of the upper capacitors is configured by connecting a plurality of capacitors having the same capacitance in parallel, and each of the lower capacitors is configured by connecting the plurality of capacitors having the same capacitance in parallel. It may be configured by. According to such a configuration, it is possible to reduce the mismatch error of a plurality of capacitors.

In one embodiment of the present technology, the number of bits of the lower bit DinL may be 4 bits or less. When the number of bits of DinL for the lower bits is increased, it is necessary to connect capacitors having a larger predetermined capacity in parallel when realizing a capacitor having a capacity corresponding to the bits. That is, since the number of capacitors having a predetermined capacity increases, it becomes difficult to design a circuit and a layout. In this regard, according to the above configuration, it is possible to suppress an excessive increase in the number of capacitors having a predetermined capacity when realizing a capacitor having a capacity corresponding to a bit. Therefore, the circuit and layout design becomes easy.

In addition to or instead of the above configuration, the high-order bit D / A converter may be controlled based on the linearity compensation algorithm when the high-order bit DinH is 2 bits or more. The linearity compensation algorithm referred to here is intended as an arbitrary algorithm capable of compensating for the linearity of the high-order bit D / A converter, and is not particularly limited, and includes, for example, Dynamic Element Matching (DEM). It may be. In this case, the number of bits of DinH for the high-order bits may be 5 bits or less. With such a configuration, the DEM circuit becomes relatively simple and the circuit scale can be reduced. As a result, the circuit and layout design can be facilitated, and the chip area can be reduced to reduce the cost.

A delta-sigma modulator that outputs a digital value to an input analog value and has a feedback circuit including the above digital / analog composite integrator is also new and useful.

Details and further improvements of the techniques disclosed herein will be described in the "Modes for Carrying Out the Invention" below.

It is a block diagram of the digital / analog composite integrator of an embodiment. It is a logic circuit diagram of a digital integrator and a digital adder. It is a circuit diagram of an analog adder, an analog integrator, and a low-order bit and a high-order bit digital / analog converter. It is a timing chart of an example of a clock. It is a circuit diagram of the ΔΣ modulator provided with the digital / analog composite integrator of an embodiment.

The digital / analog composite integrator (hereinafter referred to as “D / A synthetic integrator”) 100 of the embodiment will be described with reference to the drawings. The D / A composite integrator 100 takes a digital input Din as an input, and an analog value (ΣDin) obtained by integrating this digital value sequence (Din (1), Din (2), ...) On the time axis or time series. It is converted to a value (generally an analog voltage Vo) and output. As shown in FIG. 1, in the D / A synthetic integrator 100, the high-order bits of the digital input Din are DinH and the low-order bits are DinL (Din = DinH + DinL). Hereinafter, in this embodiment, the digital input Din is 6 bits (000000 to 100,000, decimal number is 0 to 32), the upper bit DinH is 3 bits (000 to 100), and the lower bit DinL is 3 bits (000 to 000 to). The case of 111) will be described. However, the number of bits of the digital input Din, the low-order bit DinL, and the high-order bit DinH is not limited to the above-mentioned number of bits.

The D / A composite integrator 100 has a low-order bit digital integrator 12 that integrates the low-order bit DinL by digital calculation (ΣDinL). In the low-order bit digital integrator 12, if an overflow occurs as a result of digital integration of the low-order bit DinL, the carry (Carry) is output to the high-order bit DinH and added by digital calculation (DinH + Carry). Processing is performed, and at the same time, the same carry is subtracted from the lower bit integrator 12 (Σ (DinL-Carry)). That is, after performing the carry processing from the result of the digital integration of the low-order bit DinL to the high-order bit, the low-order bit digital integrator 12 sets the output of the low-order bit digital integrator 12 ignoring the carry. The D / A composite integrator 100 is a low-order bit D / A converter (hereinafter referred to as "DAC-L") that converts the output (Σ (DinL-Carry)) of the low-order bit digital integrator 12 into an analog value. ) Has 14.

The D / A composite integrator 100 has a digital adder 22 that outputs a value (DinH + Carry) obtained by adding the carry amount of the upper bit for the upper bit DinH, and a digital value (DinH + Carry) for the upper bit output by the digital adder 22. ) To an analog value (hereinafter referred to as "DAC-H") 24 and the analog value converted by the DAC-H24 are integrated by analog calculation (Σ (DinH + Carry)). It has a high-order bit analog integrator 26.

Then, the D / A composite integrator 100 adds the output of the upper bit analog integrator 26 and the analog output of the DAC-L14 by an analog circuit (analog adder 30) to obtain the final integrator output Vo.

In FIG. 2, the digital input Din is 6 bits (000000 to 100,000, 0 to 32 in decimal), the upper bit portion DinH is 3 bits (000 to 100), and the lower bit portion DinL is 3 bits (000 to 111). This is an example of circuit design in the case of. Since the C (Carry) output of the most significant bit (MSB) b5 adder does not have to be used, it is indicated by a dotted line. Since the circuit configurations of the digital integrator 12 and the digital adder 22 shown in FIG. 2 are well known to those skilled in the art, detailed description thereof will be omitted.

When the high-order bit DinH is multi-bit (2 bits or more), an element mismatch canceling technique such as a dynamic element matching (DEM) technique may be used in the DAC-H24. FIG. 2 is an example of a circuit in this case. The lower 3 bits DinL are integrated using the lower bit digital integrator 12 and output in a 3 bit (000 to 111) binary code. The carry-up signal of the low-order bit digital integrator 12 is added to the high-order 3-bit DinH in the digital adder 22, and this is converted into a thermometer code (Thermometer code). Further, the DEM control logic is used for each capacitor constituting the DAC-H24. It is output as a DEM control signal that controls the connection. Since the internal logic of DEM control is well known to those skilled in the art, detailed description thereof will be omitted.

The DAC-H24 and the upper bit analog integrator (AnalogIntegrator) 26, and the DAC-L14 and the analog adder (AnalogAdder) 30 share the integrator CI and can be combined into a circuit configuration. FIG. 3 shows a fully differential circuit configuration using an integrator (passive integrator) composed of a capacitor and a switch as the high-order bit analog integrator 26 without using an operational amplifier, and a capacitor voltage divider circuit as an adder. This is an example of the circuit. In such a circuit, since there are no restrictions on the slew rate and oscillation stability of the operational amplifier, the high-order bit analog integrator 26 can be operated at a high operating frequency. Therefore, the D / A synthetic integrator 100 can be operated at a high operating frequency.

Corresponding to the digital circuit of FIG. 2, the digital input Din has a total of 6 bits (000000 to 100,000), the upper 3 bits control the DAC-H24 as a DEM control signal, and the lower 3 bits control the DAC-L14 with a binary code. do. The DAC-H24 is composed of capacitor pairs Crefp1 to 4 and Clefn1 to 4 having a differential circuit configuration, and the DAC-L14 is composed of Cadddp0 to 2 and Caddn0 to 2. Vref + and Vref− are reference potentials, and the potential difference Vref = (Vref +) − (Vref−) between them is the reference voltage for D / A conversion.

The capacitor pairs Crefp1 to 4 and Clefn1 to 4 constituting the DAC-H24 are all capacitors having the same capacitance value. For the DAC-L14 capacitor pair, Caddp2 = Caddn2 is designed to be 1/2 of the DAC-H24 capacitors Clef1 to 4, Caddp1 = Caddn1 is designed to be 1/4, and Cadddp0 = Caddn0 is designed to be 1/8.

In order to design DAC-H24 and DAC-L14 with good matching, it is desirable to use unit capacitors C0 with the same capacitance value and the same layout shape as basic elements and connect each capacitor in parallel. For example, it may be designed as Crefp1 to 4 = Crefn1 to 4 = 8 × C0, Cadddp2 = Caddn2 = 4 × C0, Caddp1 = Caddn1 = 2 × C0, Caddp0 = Caddn0 = C0.

The integrator circuit given as an example in FIG. 3 is a passive integrator that does not use an operational amplifier. In this case, in order to suppress the integrator leakage sufficiently small, it is desirable to design the capacitance value of the integrator capacitor CI to be sufficiently larger than the capacitance value of the DAC capacitor. That is, it is desirable to design CI >> Crefp1 to 4 and Clefn1 to 4.

FIG. 4 shows a timing chart of an example of a clock. This clock is a "non-overlapping clock" commonly known in switched capacitor circuit technology. Here, the integrator output is determined at the final timing of φ2, with phase φ1 as the zero sampling phase and φ2 as the integration phase.

In FIG. 3, the phases φ1A and φ2A of the circuit common mode potential Vicm side switch represent ON / OFF operation at a timing slightly earlier than φ1 and φ2, respectively. Here, it is assumed that the initial potentials of the outputs Vo + and Vo− of the integrating capacitor CI are the circuit common mode potential Vicm at the start of the circuit operation. Generally, this potential is not fixed before the circuit operation (immediately after the power is turned on, etc.), but as the zero sampling and integration operations described below are repeated, the midpoint potential of Vo + and Vo- gradually increases to the circuit common mode potential Vicm. Approaching.

First, the connection of the capacitor pairs Crefp1 to 4 and Clefn1 to 4 constituting the DAC-H24 and the operation of the integrator will be described. In phase φ1, the right electrodes of Crefp1 to 4 and Clefn1 to 4 are connected to the common mode potential Vicm, and the left (Vref side) electrode is the midpoint Vref0 (not shown in FIG. 3) of the reference potential (Vref +, Vref-). ). In this state, all the capacitors of the DAC-H24 are in the zero sampling state.

The reference potential midpoint Vref0 was used in the explanation to bring each capacitor constituting the DAC-H24 into a zero sampling state in the phase φ1, but in the actual design, zero sampling is performed even if this potential is not generated. It is possible to realize a midpoint sampling operation equivalent to. For example, in phase φ1, a plurality of capacitors pairs of Clef1 to 4 are connected to the reference potentials Vref + and Vref- every other time (alternately), or "Data-Weighted" (Data-Weighted).
If the elements are circulated and connected to Vref + and Vref- in the manner of Averaging: DWA) and averaged, it is equivalent to sampling the reference potential midpoint Vref0.

In the next phase φ2, the right electrodes of Crefp1 to 4 and Clefn1 to 4 are connected to the integrating capacitor CI, and the left (Vref side) electrode is connected to the reference potential Vref + or Vref- according to the DAC-H24 digital input (High-order bits). When the switch is connected to any of the above, the DAC-H24 output is charged to the CI via Crefp1 to 4 and Crefn1 to 4, and the integration operation is performed.

In a passive integrator as shown in the circuit example of FIG. 3, all the charges are not transferred to the integrator CI, and a part of the charges remains on the capacitor Clef side, which causes an integrator leak. With an active integrator with operational amplifiers, the DAC-H24 output is almost ideally charged to the integrator. Since the operation of an active integrator using an operational amplifier is widely known and apparent to those skilled in the art, the circuit diagram and operation description are omitted.

Next, the connection of the capacitor pairs Caddp0 to 2 and Caddn0 to 2 constituting the DAC-L14 and the operation of the adder will be described. The left electrodes of Caddp0 to 2 and Caddn0 to 2 are always connected to the integrating capacitor CI as shown in the circuit diagram of FIG. The right side (Vref side) electrode of CAD is in a connected state (zero sampling state, for example, CADdp0 to 2 are connected to Vref- and CADn0 to 2 are connected to Vref +) in the first phase φ1 corresponding to the DAC-L14 input “000”. .. Next, in phase φ2, if the right (Vref side) electrodes of Caddp0 to 2 and Cadddn0 to 2 are connected to Vref + or Vref- according to the DAC-L14 digital input (Low-order bits), the DAC-L14 output will be Caddp0 to 2. It is added to the voltage between CI terminals by the voltage division of the capacitor via Caddn0 to 2, and is added to the output voltage Vo (= (Vo +)-(Vo-)).

In DAC-L14, since the left electrode of the capacitor Cadd is always connected to the integrating capacitor CI, even if the DAC output is added to the output Vo via the Cad in the phase φ2, the Vref side electrode of the Cadd is again in the next phase φ1. If is returned to the zero sampling state, the added voltage is returned to the original state and is not integrated into the CI. That is, the DAC-L14 and the capacitor CI operate as an analog adder.

The characteristics of the DAC-L14 and the analog adder 30 work beneficially when there is an error in the DAC-L14. The DAC-L14 output has an error due to a capacitance mismatch between the capacitors Caddp0 to 2 and Caddn0 to 2, and the error due to this mismatch is also added to the integrator output as the DAC-L14 output is added. However, even if this error is temporarily added to the integrator output, it is not integrated into the integrator capacitor CI. When the DAC-L14 input returns to the original value and the CAD's Vref side connection state returns to the original value, the temporarily added error is subtracted and becomes zero. Due to this effect of the low-order bit integrator by the low-order bit digital integrator 12, DAC-L14, and analog adder 30, the influence of the error generated by DAC-L14 on the integrator output is generated by the high-order bit DAC-H24. The effect of error on the integrator output is significantly reduced. This will be described in detail later in "Effect of DAC output error on total integrator output Vo in the configuration according to the present technology".

Here, since the integrator output Vo may be determined at the final timing of the phase φ2, in the subsequent phase φ1, the Vref side electrode of the capacitor Cadd of the DAC-L14 does not have to be returned to the zero sampling state (or the Vref side electrode potential). If the connection on the Vref side of the Cadd is confirmed and the DAC-L14 output is determined at the time of phase φ2, the addition operation is normally performed and the integrator output Vo is determined.

As described above, in this design example, the digital input Din is defined as a total of 6 bits (000000 to 100,000), the upper bit DinH is defined as 3 bits (000 to 100), and the lower bit DinL is defined as 3 bits (000 to 111). It goes without saying that the number of bits is not limited to this example, and the design can be changed.

Further, it is described that the Vref side electrodes of Crefp and Clefn are connected to Vref + / Vref- or vice versa according to the DAC-H24 input digital value, but this is not the case. For example, depending on the input digital value, the Vref side electrodes of Crefp and Clefn may be connected to the intermediate potential between Vref + and Vref-, or the Vref side electrodes may be simply short-circuited (potential not fixed).

It has already been described that in order to improve the matching between the DAC-H24 and the DAC-L14, it is desirable that the layout of each capacitor is a parallel connection of unit capacitors C0 having the same capacitance value and the same layout shape. On the other hand, when the number of bits of the DAC-L14 increases, the size ratio between the basic capacitors Clef1 to 4 of the DAC-H24 and the capacitor Cadd0 for the least significant bit of the DAC-L14 increases, and the unit capacitor C0 decreases, or Clef1 to Clef1 to As the number of parallel elements of 4 increases, it becomes difficult to secure matching between the DAC-H24 and the DAC-L14. If the reference voltage Vref (= (Vref +)-(Vref-)) of the DAC-L14 can be reduced to half (1/2) Vref of the DAC-H24, this element size ratio will be reduced to half. For example, when the DAC-L14 input (that is, the lower bits) is 3 bits, the element size ratio is 8: 1 → 4: 1. This makes it easier to match the DAC-H24 and the DAC-L14, reduce the error due to the mismatch, or facilitate the design.

However, this method requires a separate circuit that generates a reference voltage (1/2) Vref for DAC-L14. Therefore, as another method, instead of switching the capacitor connection of the DAC-L14 to -Vref / + Vref corresponding to 0/1 of the input digital bit value, set one to 0 (voltage zero) and set it to -Vref / 0. By switching, the added voltage is halved even if the same capacitance value is designed, and the same effect as halving the reference voltage is obtained. The calculation of addition 0 (zero) can be realized by shorting the voltage between the Vref side terminals of the capacitor pairs (Cadpd0 to 2 and Caddn0 to 2) that make up the differential circuit with a zero voltage, that is, a switch (Vref0 and other reference potentials). It is not necessary to connect to and fix the potential).

Specifically, with DAC-H24 and DAC-L14, each capacitor is connected to the digital input as follows. That is, in the DAC-H24, when the value of each bit of the digital input is 0, the corresponding Crefp1 to 4 are connected to Vref-, and the Clefn1 to 4 are connected to Vref +. When the value of each bit of the digital input is 1, the corresponding Crefp1 to 4 are connected to Vref +, and the Clefn1 to 4 are connected to Vref−. On the other hand, in DAC-L14, when the value of each bit of the digital input is 0, the corresponding Cadddp0 to 2 are connected to Vref-, and Cadddn0 to 2 are connected to Vref + (that is, the same as DAC-H24). Further, when the value of each bit of the digital input is 1, the corresponding short circuit between the electrodes on the Vref side of Caddp0 to 2 and Cadddn0 to 2 is performed by a switch.

If the switch connection is designed as described above, even if the DAC-L14 input is 3 bits, the ratio of the basic capacitors between the DAC-H24 and the DAC-L14 is 4: 1, which is easier to design than the case of 8: 1. Therefore, improvement of matching can be expected. For example, the capacitance value of each capacitor is based on the unit capacitor C0 as a basic element, Crefp1 to 4 = Crefn1 to 4 = 4 × C0, Caddp2 = Cadddn2 = 4 × C0, Cadddp1 = Cadddn1 = 2 × C0, Cadddp0 = Cadddn0 = C0. Can be designed as

Next, the effect of the DAC output error on the total integrator output Vo in the configuration related to this technology will be described. The error of the DAC output is generated by the mismatch of the capacitor elements constituting the DAC. Here, for the high-order bits, the same DEM technology as the conventional one can be used in the DAC-H24, and the influence of the error due to the element mismatch can be sufficiently suppressed, so that it does not become the main factor of the error of the entire circuit. it is conceivable that. Next, the circuit for the lower bits is composed of the lower bit digital integrator 12, the DAC-L14, and the analog adder 30, of which the lower bit digital integrator 12 is a digital operation and no error occurs. Therefore, it is considered that the error appearing in the total integrator output Vo in this configuration is mainly due to the error due to the capacitor mismatch of the DAC-L14 (as a relative error with respect to the DAC-H24). This error occurs as each bit 0/1 of the DAC-L14 digital input is inverted, the Vref side connection of the corresponding capacitor is switched, and the DAC-L14 output changes.

Hereinafter, the influence of the error of the DAC-L14 output with respect to the DAC-H24 output on the integrator output Vo will be considered. The capacitors Caddp0 to 2 and Caddn0 to 2 constituting the DAC-L14 have a capacitance mismatch, and as the DAC-L14 output is added to the integrator output Vo, an error due to this mismatch is also added to the output. However, as shown in FIG. 3, since the left electrodes of Caddp0 to 2 and Caddn0 to 2 are always connected to the integrator capacitor CI, even if this error is temporarily added to the integrator output Vo, the integrator capacitor It is not integrated into CI. When the DAC-L14 input digital value returns to the original value and the CAD's Vref side connection state returns to the original value, the temporarily added error is subtracted and canceled. That is, it is considered that the error due to the DAC-L14 temporarily appears in the integrator output Vo when the digital integrator output value changes (transitions). Therefore, when the value of the lower bit digital integrator 12 output changes slowly while repeating count up / down, the average error amplitude per sample appearing in the integrator output Vo is the lower bit digital integrator 12 output. Is divided by the time (or the number of samples) required for the transition of that value. That is, the error of DAC-L14 is dispersed on the time axis and becomes small.

When the lower bit DinL of the digital input Din is a relatively large value, the lower bit digital integrator 12 repeats counting up / down and carry by integration, but the lower bit digital integrator 12 output value (= DAC-L14). When the digital input value) goes around and the element connection state of the DAC-L14 is restored, the error due to the DAC-L14 mismatch temporarily added to the integrator output Vo is subtracted and canceled, so the average value Is zero. When the low-order bit digital integrator 12 repeats laps and carry by integration, the output error repeatedly increases and decreases within a certain range, and the DAC-L14 error becomes periodic noise that appears periodically in the output.

Here, when applied to an oversampling system (when the signal band fsignal and the sampling frequency fs are fsignal << fs / 2), if the periodic noise component is outside the signal band handled by the system, it is removed by the subsequent filter processing. It is possible to do. For example, when this circuit is applied to the integrator of a delta-sigma A / D converter, there is generally a digital LPF (low-pass filter) after the delta-sigma modulator, and high-frequency noise components exceeding the signal band are removed by this digital LPF. Therefore, it does not appear in the digital output after this. On the other hand, if this periodic noise component is within the signal band, it may appear in the output as an idle tone (Idle Tone).

However, in the oversampling system, the noise component appearing in the output is limited to the one whose frequency is sufficiently lower than the sampling frequency fs, that is, the period is long. When converted per sample, the error amplitude is suppressed to a small value.

Due to this effect of the lower bit digital integrator 12, DAC-L14, and analog adder 30 of this configuration, the influence of the error generated by the lower bit DAC-L14 on the overall integrator output Vo is the upper bit DAC-H24. It is significantly reduced compared to the one due to the error of.

According to the above configuration, since the error due to the mismatch of DAC-L14 is not integrated, the average error appearing at the integrator output is dispersed on the time axis, and the error of the signal band appearing at the output is significantly reduced in the oversampling system. NS. Therefore, the mismatch canceling DEM usually required for a high-resolution multi-bit DAC can secure sufficient linearity with a small-bit DEM of only the DAC-H24, and a large-scale multi-bit DEM circuit becomes unnecessary. The circuit scale can be significantly reduced. As a result, the circuit and layout design can be facilitated, and the chip area can be reduced to reduce the cost.

According to this configuration, only DAC-H24 uses DEM among the multi-bit digital inputs, and the number of bits is small after deducting the lower bits (for example, when all 6 bits are used and the lower bits are 3 bits). Since the upper level requires only 6-3 = 3 bits of DEM, it can be realized with a significantly smaller circuit configuration. For example, in the example given above, when a DEM is used in a differential circuit configuration DAC having a digital input of 6 bits of 6,000,000 to 100,000, 32 pairs of unit capacitor pairs and a MOS switch for controlling the Vref connection are required. If the upper bit DinH is designed to be 3 bits 000 to 100 and the lower bit DinL is designed to be 3 bits 000 to 111 using the configuration according to the present technology, the required capacitor pair is the upper bit (DAC-) using DEM. H24) 4 pairs, 3 pairs of low-order bits (DAC-L14), and a total of 7 pairs of capacitor pairs and a corresponding MOS switch are sufficient. It is also possible to design the high-order bit DinH to 1 bit, and in this case, it is not necessary to use a DEM for the high-order bit DinH. The D / A composite integrator 100 according to the present technology can be widely applied to a multi-bit output ΔΣ modulator.

Further, according to the above configuration, the effect of testability can be obtained. As described above, if the mismatch of the DAC-L14 with respect to the DAC-H24 is large in this configuration, an error occurs when each bit of the DAC-L14 is inverted by 0/1, and the periodic noise synchronized with the rotation of the digital integrator 12 occurs. May appear in the output. When this periodic noise becomes a problem, it is easy to perform non-defective product / defective product selection or characteristic ranking in the IC shipping test.

Specifically, since the pattern and period of the periodic noise appearing in the output can be designed and predicted from the digital input to the integrator, a digital value such that each bit of the DAC-L14 is periodically inverted by 0/1 is input. By measuring the periodic fluctuations appearing in the output, the mismatch of the elements corresponding to each bit can be measured individually. If a bandpass filter is placed after the output, it is possible to extract only the error component of a specific period that occurs when each bit of DAC-L14 is inverted, and the mismatch of each capacitor is measured individually to determine the capacitance value. Trimming adjustment can also be performed.

When this technology is applied to a delta-sigma A / D converter, the same shipping test is easy. The ADC digital output may be monitored, the analog input may be adjusted so that a predetermined periodic noise appears, and the periodic noise appearing in the digital output may be measured.

FIG. 5 is an example of a circuit in which the above D / A composite integrator 100 is applied to a “Passive-Digital ΔΣ modulator”. For "Passive-Digital ΔΣ modulator", refer to Patent Document 1. The digital output (Digital Out) of the ΔΣ modulator 40 is input to the D / A composite integrator 100 so as to have the opposite polarity to the input Vin, and is used as a feedback DAC and an integrator. Vin + and Vin− are analog inputs of the ΔΣ modulator, and are input as a differential voltage Vin (= (Vin +) − (Vin−)). Csp and Csn are added as input sampling capacitors.

The digital output of the delta-sigma modulator 40 is divided into high-order bits and low-order bits, and the low-order bits are integrated by the digital integrator, and the DAC-L14 is controlled by this output. Carry of the digital integrator 12 and the high-order bits are added, and the DAC-H24 is controlled by this added value. A feedback DAC and an integrator are constructed by combining these, and the difference between the analog input Vin and the D / A conversion value of the ΔΣ modulator 40 digital output is integrated. In FIG. 5, since the polarity of the input Vin of the ΔΣ modulator 40 is displayed as a reference, the display of the integrator outputs Vo + and Vo− is opposite to that in FIG. This is because the integrator of the ΔΣ modulator 40 integrates the difference between the input Vin and the feedback DAC output, so that the polarities are opposite when considering the polarity of the input Vin.

If this technology is applied to a Passive-Digital ΔΣ modulator using a passive integrator, the number of bits of the feedback DAC, that is, the resolution is increased and the integrator output amplitude can be suppressed to be smaller, so that the input range of the quantizer in the subsequent stage can be increased. It can be kept smaller, the linearity of the quantizer is improved, and the integrator leak can be reduced. As a result, the characteristics of the A / D converter can be improved, or the scale of the entire circuit can be simplified and the cost can be reduced.

The points to keep in mind regarding the technology explained in the examples will be described. This time, as an integrator circuit, a passive integrator with a fully differential circuit configuration, which is a typical application, was explained as an example, but even an integrator using an operational amplifier (active integrator) or an integrator of a single-ended circuit can be used. , It is easy to design a circuit with a similar idea. An active integrator can be easily designed and realized with high accuracy without integrator leakage.

Although the D / A converter has been described as being composed of a series of capacitors, a resistor or other element may be used for one or both of the DAC-H24 and the DAC-L14.

There is a finite value limit determined by the number of elements in the range that can be added or subtracted by the digital integrator and the corresponding analog adder. If you continue to integrate a certain input, the digital integrator and analog adder will eventually reach this limit (calculation overflow) and you will not be able to integrate any more. On the other hand, in the case of an analog integrator, such an overflow does not occur. Therefore, a digital integrator is used for the lower bits, and if it overflows, a carry is issued and added to the upper bits to absorb the overflow, and the carry is integrated by the upper bit side analog integrator. By doing so, the integrator as a whole can continue the integrating operation without causing a calculation overflow. For the above reasons, it is necessary to secure one bit or more of Carry as the high-order bits to be integrated by the analog integrator (in other words, another Carry part for arithmetic processing when the digital integrator overflows). I need a way). Therefore, a configuration in which all bits are integrated by a digital integrator is not preferable. Similarly, it is not preferable to integrate the upper bits with a digital integrator and the lower bits with an analog integrator.

For DAC-H24, DEM is required to cancel the mismatch of each capacitor (in the case of multi-bit). When the number of bits of DinH is increased by the upper bits, the number of unit capacitors is increased by a power of 2, and the DEM logic is also complicated, so that the circuit is complicated and the design becomes difficult. Therefore, it is appropriate that the high-order bit DinH is set to, for example, 5 bits or less.

On the other hand, for the lower bit DinL, the error due to the capacitor mismatch of the DAC-L14 causes periodic noise, and especially if there is a mismatch with the DAC-H24, the effect of this error will be significant when carrying. .. As described above, the constituent elements of the DAC-H24 and the DAC-L14 should be circuits that can be layout-matched by using unit elements having the same element shape. If the number of bits of the DAC-L14 is increased, the unit element size becomes smaller, and it becomes rather difficult to match the layout. Considering the matching between the DAC-H24 and the DAC-L14, it seems that, for example, 4 bits or less is appropriate as the lower bit DinL. Actually, the optimum number of bits is determined by performing a system simulation in consideration of the minimum capacitor size and matching data determined by the IC process, and the OSR (Oversampling Ratio) and linearity specifications required by the system.

Capacitor Clef, capacitor CAD, and unit capacitor C0 correspond to examples of "upper capacitor", "lower capacitor", and "capacitor having the same capacity", respectively.

The specific examples of the technology disclosed in the present specification have been described in detail above, but these are merely examples and do not limit the scope of claims. The techniques described in the claims include various modifications and modifications of the specific examples illustrated above. The technical elements described herein or in the drawings exhibit their technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the techniques illustrated in this specification or drawings can achieve a plurality of purposes at the same time, and achieving one of the purposes itself has technical usefulness.

12: Lower bit digital integrator 14: DAC-L
22: Digital adder 24: DAC-H
26: High-order bit analog integrator 30: Analog adder 40: ΔΣ modulator 100: D / A composite integrator

Claims (13)

1. Digital value Din is input, and the value (ΣDin) obtained by integrating this digital value sequence (Din (1), Din (2), ...) On the time axis or time series is converted into an analog value and output. An input / analog output digital / analog composite integrator
   The upper bit of the digital input Din is DinH, the lower bit is DinL (Din = DinH + DinL), and the lower bit DinL is digitally integrated (ΣDinL) with a lower bit digital integrator.
   If an overflow occurs as a result of the digital integration of the low-order bit DinL, the carry (Carry) is output to the high-order bit DinH and added by digital calculation (DinH + Carry), and at the same time, the carry process is performed. The same carry is subtracted from the low-order bit digital integrator (Σ (DinL-Carry)), that is, after the carry-up process to the high-order bit is performed from the result of the digital integration of the low-order bit DinL, the carry is performed. The low-order bit digital integrator ignores the carry and uses its own output.
   It also has a low-order bit D / A converter (DAC-L) that converts the output (Σ (DinL-Carry)) of the low-order bit digital integrator into an analog value.
   Regarding the high-order bit DinH, a high-order bit D / A converter (DAC-H) that converts the high-order bit digital value (DinH + Carry) obtained by adding the carry amount into an analog value, and the high-order bit D / A conversion. It has a high-order bit analog integrator that integrates the analog value after conversion by the instrument by analog calculation (Σ (DinH + Carry)).
   Then, the output of the high-order bit analog integrator and the analog output of the low-order bit D / A converter (DAC-L) are added and calculated by an analog circuit to obtain the final integrator output Vo.
   Digital / analog composite integrator.
2. The digital / analog composite integrator according to claim 1, wherein the high-order bit D / A converter includes one or a plurality of high-order capacitors according to the number of bits of the high-order bit DinH.
3. The high-order bit D / A converter includes a plurality of high-order capacitors according to the number of bits of the high-order bit DinH.
   The digital / analog composite integrator according to claim 1, wherein the plurality of upper capacitors have equal capacities with each other.
4. The digital / analog composite integrator according to claim 2 or 3, wherein each of the upper capacitors is configured by connecting a plurality of capacitors having the same capacitance in parallel.
5. The digital / analog composite integrator according to any one of claims 1 to 4, wherein the low-order bit D / A converter includes one or a plurality of low-order capacitors according to the number of bits of the low-order bit DinL.
6. The low-order bit D / A converter includes a plurality of low-order capacitors according to the number of bits of the low-order bit DinL.
   The digital / analog composite integrator according to any one of claims 1 to 4, wherein the plurality of lower capacitors have different capacitances depending on the position of the corresponding bit.
7. The digital / analog composite integrator according to claim 5 or 6, wherein each of the lower capacitors is configured by connecting a plurality of capacitors having the same capacitance in parallel.
8. The high-order bit D / A converter includes a plurality of high-order capacitors according to the number of bits of the high-order bit DinH.
   The plurality of upper capacitors have equal capacities with each other and have equal capacitances.
   The low-order bit D / A converter includes a plurality of low-order capacitors according to the number of bits of the low-order bit DinL.
   The plurality of lower capacitors have different capacitances depending on the position of the corresponding bit.
   Each of the upper capacitors is configured by connecting a plurality of capacitors having the same capacitance in parallel, and each of the lower capacitors is connected to a plurality of capacitors having the same capacitance in parallel. The digital / analog composite integrator according to claim 1, wherein the digital / analog composite integrator is configured by the above.
9. The digital / analog composite integrator according to claim 8, wherein the number of bits of the lower bit DinL is 4 bits or less.
10. The digital / according to any one of claims 1 to 9, wherein the high-order bit D / A converter is controlled based on the linearity compensation algorithm when the high-order bit DinH is 2 bits or more. Analog composite integrator.
11. The digital / analog synthetic integrator according to claim 10, wherein the linearity compensation algorithm includes Dynamic Element Matching (DEM).
12. The digital / analog composite integrator according to claim 11, wherein the number of bits of the high-order bit DinH is 5 bits or less.
13. A delta-sigma modulator that outputs a digital value with respect to the input analog value.
    A feedback circuit for calculating the difference between the analog value and the digital value is provided.
    The feedback circuit is a delta-sigma modulator comprising the digital / analog composite integrator according to any one of claims 1 to 12.

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