WO2021144145A1

WO2021144145A1 - Circuit arrangement of an electronic seal

Info

Publication number: WO2021144145A1
Application number: PCT/EP2021/025006
Authority: WO
Inventors: Klaus Finkenzeller; Stephan RASCH; Hans-Jürgen ROTH; Jens Grosse; Rüdiger MALSCH
Original assignee: Giesecke+Devrient Currency Technology Gmbh
Priority date: 2020-01-17
Filing date: 2021-01-14
Publication date: 2021-07-22
Also published as: DE102020000303A1

Abstract

The present invention relates to a circuit arrangement which is designed to detect tampering of an electronic seal in an efficient manner such that little technical effort is involved. Any such tampering is detected fully automatically. The present invention further relates to a corresponding method for manufacturing the circuit arrangement according to the invention.

Description

Circuit arrangement of an electronic seal The present invention is directed to a circuit arrangement which is set up to carry out a detection of a manipulation of the electronic seal in an efficient manner in such a way that little technical effort arises. Such attempts at manipulation can also be recognized fully automatically. The present invention is also directed to a correspondingly set up method for producing the proposed circuit arrangement and to a computer program product with control commands which implement the proposed method.

DE 102025005556 A1 shows an electronic seal, a computing unit being used to record different physical properties. However, it does not describe how complex signals can be generated in order to use them to address individual conductor loops, and in particular it is not shown how several computing units can interact with one another in the proposed context.

EP 3009967 A1 shows an RFID chip which has a mini controller and an antenna. Furthermore, locking units are shown here, which are configured long Lich. In this case, however, a known RFID chip is typically used that does not have the computing units as proposed in the present context.

In order to ensure the authenticity and integrity of a good, the good is usually provided with a seal. The seal, often also called a seal, can be used to determine whether the goods have been tampered with. was taken. The intactness of the goods shows at the same time its intactness and is often considered as proof of its authenticity. The good can be a container in which an object to be secured is arranged.

As a rule, the seal does not prevent manipulation of the good and / or the object in the good; it usually only serves as evidence of manipulation. For example, the seal proves that a container for sensitive content, e.g. a transport box for valuables, an envelope or the housing of a calibrated instrument, e.g. a meter, has not been (unauthorized) opened. If the seal has not been destroyed (broken, attacked), it can be assumed that the sensitive content has not been tampered with. Usually only authorized persons are allowed to attach and remove seals.

In general, it is thus known that conductor loops are arranged on processing units, where if such conductor loops are cut, feedback to the processing units is no longer possible. It is generally known that different physical properties of a blocking unit can be queried by means of the conductor loops. Such conductor loops are typically elongated in such a way that they, together with a further locking device, can seal a lock or a container. Such physical properties are, for example, electrical properties such. B. an electrical conductance, a capacitance or phase shift, or even optical properties, such as. B. a light refraction index or acoustic properties.

A disadvantage of the known seals is that here only the status of the circuit formed by the filament is determined, a distinction only being made between the statuses open / closed can. Since the determined state is stored in a tamper bit, which can also be read out unencrypted contactlessly, it is easy for an attacker to electrically connect a severed filament (steel cable) and thus to pretend a closed seal to a reader. For this purpose, only a single electrically conductive connection is arranged between the two separated sections of the filament.

A disadvantage of the chips according to the prior art is that the simple resistance measurement that is carried out is measured against ground, that is against ground. If several conductor loops were used here, they would all be measured against ground. Here it would be sufficient for an attacker to simply connect all the existing lines with one another so that they automatically come to ground. The method used today is therefore not suitable for use with several conductor loops.

According to the prior art, it is particularly disadvantageous that un different chip or microcontrollers are provided, which mean a great deal of technical effort, and also provide redundant components. There is thus a need for a simplified circuit arrangement which makes it possible to check a large number of the described conductor loops with regard to their status and thus to automatically recognize whether a seal has been tampered with.

Compared to a further prior art, there is a problem that, although generally several conductor loops are provided for sealing, these are, however, each connected separately to a single processing unit. Thus, when combining known sealing devices, known seals which are used multiple times are always used. What is not shown, however, is that several conductor loops are advantageously combined in such a way that, although the security of the seal is increased overall, the technical effort does not increase linearly.

Accordingly, it is an object of the present invention to provide an efficient circuit arrangement with arithmetic units for detecting manipulation of an electronic seal, which can be provided with little technical effort and yet prevents an attempt to manipulate a seal from being hidden. It is also an object of the present invention to provide a correspondingly set up method for producing the circuit arrangement and a computer program product with control commands which implement the proposed method.

The object is achieved by means of a circuit arrangement for the detection of a manipulation of an electronic seal with the features of Pa tentanspruchs 1. Further advantageous embodiments are given in the claims.

Accordingly, a circuit arrangement with arithmetic units for the detection of a manipulation of an electronic seal is proposed, with a plurality of conductor loops which are arranged on arithmetic units in such a way that the conductor loops enable feedback to the arithmetic units, with at least two arithmetic units being provided, and the loop loops are connected to the processing units by means of configurable interfaces.

The circuit arrangement is integrated into an electronic seal in such a way that a plurality of conductor loops are arranged on computing units. In particular, additional components are used here that, for example, implement data communication in such a way that the results of the manipulation check can be read out wirelessly. A conductor loop is typically an elongated conductive element which, for. B. forms a loop, thus a closing effect can be achieved by means of the loop and possibly by means of other locking devices. The function of the conductor loops is that they provide a communication channel with regard to feedback in the individual processing units and also provide a physical blocking function, for example in cooperation with other elements.

The conductor loops are arranged on the computing units in such a way that the two ends of the conductor loops represent a communication interface to the respective computing unit. The conductor loops are therefore a communication channel or a feedback channel that provides information about whether the conductor loop is intact or not. The arithmetic units can execute certain arithmetic functions which provide that at least one value is provided here by means of a conductor loop. If the conductor loop is cut through in the process, the processing units can no longer work properly and there is no output or an incorrect output. It can thus be recognized that the conductor loops are being tampered with, as these are typically severed by.

The majority of the conductor loops ensure that a very specific interconnection of the individual arithmetic units is created in such a way that precisely this interconnection is necessary in order to guarantee that the arithmetic units work properly. If an attacker now manipulates the seal, so the conductor loops are cut, as these implement a blocking function at least in conjunction with another blocking element. The primary goal here is not to prevent the manipulation itself, but rather to establish that the seal has been manipulated at all. Since a plurality of conductor loops is provided, there are also a corresponding number of inputs and outputs on the computing unit. If the attacker now wants to reconnect the disconnected conductor loops to the processing units, he must do this in the exact order in which he disconnected them from the processing units. To do this, it is therefore necessary to restore exactly the interconnection that prevailed before the manipulation attempt.

The individual arithmetic units typically have a synchronicity such that they always deterministically execute a test algorithm, and if an interconnection is no longer present in the desired manner, they arrive at an incorrect result because, for example, a start value cannot be transferred. It may therefore be necessary to provide a computing unit which at least indirectly evaluates the physical properties of the conductor loops. Such an indirect evaluation can now take place, for example, in such a way that the calculations are carried out as a function of the feedback and thus it is recognized on the basis of the feedback if a conductor loop is severed.

For this purpose, at least two computing units are provided, with one computing unit being able to check a plurality of conductor loops. This already differs from known methods in that different arithmetic units can be provided which can be interconnected in such a way that feedback from a first arithmetic unit to a second arithmetic unit is possible. This means that at least two processing units can be connected in series in such a way that an incorrect output value would be noticed immediately. With regard to known methods, this is particularly advantageous in that the known method only operates dynamically at runtime, a single arithmetic unit that detects parameters with respect to the conductor loop or the conductor loops and compares these parameters with reference parameters.

By contrast, the at least two processing units can be used to ensure that calculations can be carried out dynamically at runtime which, based on the same starting value, must be able to deterministically produce the same results. Thus, no static reference value has to be read out, but a reference value can be calculated in a specially secured area and thus an output sequence can be generated over the entire lifetime of the sealing device, which must match the output sequence that was generated using a conductor loop .

It is advantageous here to dynamically configure the interfaces of the conductor loops or the computing units in such a way that an attacker cannot see at what point in time he has to grind the severed conductors and how to arrange them. The proposed circuit arrangement is initially in a certain interconnection state. If the conductor loops are now severed, an attacker would have to re-establish exactly the original interconnection in order to conceal the manipulation. This is the only way to ensure that the processing units can operate again in accordance with the initial interconnection and that a manipulation attempt is not noticed. Using the configurable interfaces, however, it is possible to change the assignment of the individual interfaces in such a way that a different input value is now expected at an input or a PIN or port in a further calculation iteration. For example, it is also possible to change the direction of the respective interface in such a way that an input becomes an output or vice versa.

So if an attacker wants to restore the intended interconnection between computing units and conductor loops, he cannot be sure at any point in time which is the expected interconnection and can therefore not reproduce it. This prevents the attacker from measuring the individual interfaces using technical aids in such a way that he receives information about the occupancy of an interface as an input or an output.

It is also possible, for example, for the individual computing units to generate deterministic pseudo-random numbers depending on a feedback by means of the conductor loops. Thus, the individual computing units each generate the same number sequences if these are properly interconnected. If the correct interconnection is solved, at least one arithmetic unit fails or supplies an incorrect value. This is known because the individual processing units no longer run synchronously or generate different output sequences. An attempt to manipulate an electronic seal is thus recognized.

In order to make it more difficult for an attacker to interconnect correctly after cutting through the conductor loops, instead of one chip for all conductor loops, several chips, e.g. B. per conductor loop can be used. Instead of the large number of chips, only one chip can be used, whereby the other chips are replaced by diode arrays. Reading out and assigning ends of cut conductor loops is therefore hardly possible. Thus, at least two arithmetic units are proposed, the prior art sometimes providing only one arithmetic unit. This has the advantage that the correct interconnection is made more difficult, so that with the several chips there are also several possible combinations of connecting the conductor loops to the computing units. With an increasing number of computing units or conductor loops, the possible combinations are increased and it is thus made more difficult for an attacker to set a desired interface configuration. Thus, the security level of the electronic seal can also be set in a particularly advantageous manner.

It is therefore advantageous to provide several computing units. However, it was surprisingly recognized that it is not absolutely necessary to provide particularly complex computing units which, for example, have individual components redundantly.

It is sufficient that one processing unit is configured as a chip or a microcontroller and further processing units are configured as circuits or diodes in a hardware-efficient manner. It is therefore proposed to use differently designed computing units, in particular a computing unit that is designed to be particularly high-performance and also has additional components or is communicatively connected to them. This separate computing unit can be designed in such a way that it has a communication interface for reading out the manipulation attempt. It is therefore not necessary to provide a communication interface with regard to all the processing units used, but rather the individual processing units can be internally connected to the separate arithmetic unit are interconnected in such a way that these wire-bound output values transmit to this separate arithmetic unit and only the separate arithmetic unit communicates with a reader by means of the air interface. Thus, it is possible to design the proposed circuit arrangement so efficiently that not complete individual chips are installed, for example RFID chips, but rather a single full-fledged chip that takes over operations for further computing units and has a leaner hardware design is sufficient.

It is thus possible to use a first computing unit which has an air interface and further computing units which only provide these preferred computing units via wired communication interfaces. Thus, individual arithmetic units are not simply combined or connected in series, but it was recognized that hardware capacities can be saved in this case and that a function only has to be carried out by a single arithmetic unit. This means that further processing units can be designed in such a hardware-efficient manner that they only have to manage the feedback by means of a wire loop or the execution of operations as a function of the feedback. The at least two computing units are thus designed differently in such a way that they vary in their functional scope. It is also possible to design the individual computing units differently with regard to their performance or their storage capacities. For example, a computing unit can be designed to execute control commands using software, and further computing units can only be implemented as logic circuits or gates. Here it is possible to confi gure the interfaces by means of a computing unit, or to keep a separate configuration unit available for this purpose. The configurations of the interfaces can be randomly selected configurations which, however, must be known to the computing units in advance. This means that the processing units have information about how which interface must be interpreted, but what the attacker does not know. The individual interfaces, that is to say the inputs and outputs of the processing units, can thus also be varied dynamically during runtime, and the interfaces can be reconfigured or reconfigured.

According to one aspect of the present invention, a plurality of conductor loops are arranged per computing unit. This has the advantage that not only several computing units are provided, but rather on several conductor loops, which increases the possibility of combination options for connecting a conductor loop to at least one computing unit. For example, a conductor loop is typically connected to at least one processing unit by means of an input and an output, and when the conductor loop is severed, the number of interfaces to be provided increases.

According to a further aspect of the present invention, the configurable interfaces are set up to provide an input and an output from a single processing unit or an input from a first processing unit or an output from a second processing unit for each conductor loop. This has the advantage that the interfaces can be set with respect to a communication direction in such a way that the possible combinations of connecting a conductor loop do not only relate to the interfaces themselves, but also to the interfaces a distinction is made between input and output. It is also possible to implement the feedback in such a way that an output of a computing unit also represents an input of the same computing unit by means of the conductor loop. Alternatively or in addition, conductor loops can be provided which represent an output from a computing unit and the feedback takes place by means of an input in a further, different computing unit. In this case it is possible for a conductor loop to report back a single processing unit, or also for a conductor loop to connect two computing units in series.

According to a further aspect of the present invention, a connection matrix is provided which stores an interface configuration which provides an indication of how a physical interface is to be interpreted by means of control commands. This has the advantage that the physical interfaces can be adjusted with regard to their connections in such a way that different input signals or output signals can be expected on a physical interface. In this way, signals can be assigned to the individual interfaces without the need to physically adapt the interface. For example, a first interface serves as the input of a first conductor loop. In further process steps, such an assignment can be reconfigured in such a way that this interface now represents the output of a second conductor loop. Thus, the virtual assignment of the existing physical interfaces is varied in such a way that an attacker cannot recognize how he actually has to connect disconnected conductor loops. Even if an attacker who cut the conductor loops has measured the original combination, the connection matrix can, however, be used to modify the interface configuration in such a way that a different configuration prevails in further process steps, and a measured interface configuration is no longer valid. This makes it even more difficult for an attacker to hide manipulation of the electronic seal by cutting through the conductor loop.

According to a further aspect of the present invention, at least one computing unit is provided as a plurality of diodes. This has the advantage that expensive chips do not always have to be used, but rather the multiple chips can be replaced by a large number of diodes. It is particularly advantageous here that only a single chip, for example a UHF chip (UHF - Ultra-High-Frequency), is to be provided, and furthermore only certain arrangements of diodes. The proposed circuit arrangement is therefore particularly hardware-efficient and can therefore be implemented with little technical effort.

According to a further aspect of the present invention, several computing units are present as a single diode array. This has the advantage that components that are already available can be used and thus the proposed circuit arrangement can be provided particularly efficiently. It is thus possible to provide an electronic seal with little technical effort and, in addition, to use only components that are light in weight and can be operated in a power-saving manner. This is particularly advantageous because the electronic seal can be supplied with power by means of an induction coil. Only low current intensities are achieved here and in this respect the proposed diode array is particularly advantageous. According to a further aspect of the present invention, at least one computing unit is present as a chip and / or a UHF chip. This has the advantage that only at least one arithmetic unit, that is to say a selection of the arithmetic units, has to be present as a chip, it being possible to provide further arithmetic units that are less powerful. This means that not all computing units have to be present as a chip, which again saves technical effort.

According to a further aspect of the present invention, at least one computing unit is present as a chip that is communicatively coupled to an antenna. This has the advantage that, in turn, only one arithmetic unit has to be connected to further components, and that, for example, an antenna does not always have to be kept available for each arithmetic unit. It is particularly preferred that precisely one computing unit is present as a chip that is communicatively coupled to an antenna. A communicative coupling does not only relate to a message transmission, but rather it is also possible to induce a current by means of the antenna in such a way that the processing unit and possibly other components can be supplied with current.

According to a further aspect of the present invention, at least one computing unit is provided as a diode array which is communicatively coupled to a chip. This has the advantage that there can be both a computing unit as a chip and a diode array which can be integrated into an existing chip or at least can be coupled to this chip. A circuit arrangement is thus provided in which both separate chips and chips that are combined with diode arrays can be used. According to a further aspect of the present invention, the configurable interfaces are each available as a pin or a port. This has the advantage that known interfaces of the electronic components can be reused and the advantageous effect described is set in such a way that the configuration of the individual pins can be changed.

According to a further aspect of the present invention, at least one selection of the configurable interfaces is provided with a protective diode and / or an ESD protective diode. This has the advantage that a protective circuit can be provided on each pin of a diode array in order to simulate a real chip. This arrangement makes it possible for an attacker not to gain knowledge of the hardware structure actually used.

According to a further aspect of the present invention, a ground connection of a first computing unit is connected to a ground connection of a second computing unit. This has the advantage that an attacker from outside the electronic seal can no longer differentiate between a real and a simulated chip.

According to a further aspect of the present invention, the sealing device can be read out contactlessly. This has the advantage that the circuit arrangement can have at least one RFID chip and also, for example, an antenna can be provided that can indicate an attempted manipulation. It is thus possible, for example, for the circuit arrangement to automatically transmit a signal in the event of a manipulation attempt, or for a reader to be held in front of the circuit arrangement contactless, ie by means of an air interface, reads. It is therefore possible, please include to save a corresponding error, if a manipulation has been known, and to read this error using a reader. A fully automated check of any manipulation of the electronic seal thus takes place.

The object is also achieved by a method for producing a circuit arrangement with computing units for detecting manipulation of an electronic seal, comprising providing a plurality of conductor loops which are arranged on computing units in such a way that the conductor loops enable feedback to the computing units, where at at least two processing units are provided and the conductors are looped by means of configurable interfaces on the processing units.

It is an aspect of the present invention that at least one computing unit is provided as a diode array. This has the advantage that the proposed circuit arrangement can be provided in a particularly hardware-efficient manner and, in particular, that not only fully-fledged chips have to be used, but at least one diode array can also be used. The chips are thus simplified in such a way that the computing units can be provided either as a chip, as a diode array or a combination thereof.

The object is also achieved by a computer program product with control commands which implement the proposed method or initiate the individual method steps if they are executed on a computer. It is particularly advantageous here that the proposed structural features can also be implemented as a method step. In this way, each process step can emulate a structural feature of the proposed circuit arrangement.

Further advantageous embodiments are explained in more detail with reference to the accompanying Figures. Show it:

1: a connection of a multiplicity of conductor loops with at least two chips according to an aspect of the present invention;

Fig. 2: a protection circuit of a chip, which is held at each pin of a diode array according to one aspect of the present invention;

Fig. 3: an interface circuit through which it is possible to operate both connections to conductor loops alternately as a signal input or signal output, according to a further aspect of the present invention; and

Fig. 4: a schematic flow diagram of a method for the produc- tion of a circuit arrangement for detecting a manipulation of an electronic seal according to a further aspect of the present invention.

Fig. 1 shows to illustrate the underlying application scenario, the connection of a plurality of conductor loops with at least two chips in the state before, during and after an attack on the electronic seal. In the top figure, an initial interconnection of conductor loops in computing units is indicated. It can be seen here that each conductor loop has two ends, which are attached to a computing unit by means of interfaces or pins. This takes place a Contacting the conductor loop and reporting back to the processing unit. Corresponding computing units are arranged on the left-hand side, which, for example, execute a deterministic computing routine and always achieve the same results due to the intact interconnection by means of the conductor loops. This is the case as long as the conductor loops are intact and thus provide a communication channel.

As shown in the middle of FIG. 1, the seal is now loosened, the corresponding conductor loops being severed. In this way, manipulation of the electronic seal can generally be recognized. Here, however, an attacker may intend to repair the seal in order to conceal a manipulation. In this case, it would be necessary for the attacker to arrange the destroyed conductor loops or the severed conductor loops again in such a way that they restore the desired interconnection, as shown, for example, in the upper area of FIG. 1. This is made more difficult by the fact that at least two arithmetic units are provided and, in addition, a plurality of conductor loops are arranged on the arithmetic units. Thus, the attacker can only restore the original connection or the arrangement of the plurality of conductor loops on the computing units if he has knowledge of the interface configuration.

An exemplary embodiment is shown in FIG. In order to make it more difficult for a potential attacker to correctly interconnect the conductor loops after they have been severed, a large number of conductor loops are connected to at least two or more chips. Here at only one chip has to be connected to an antenna, so that only one of the several chips has to be read by the reader. It is but it is also conceivable to read out all three chips one after the other in order to check the status of the conductor loops. In the latter case, all chips would have to report the status "ok" so that such an electronic seal can be regarded as undamaged.

Fig. 2 shows an analog circuit according to FIG. 1, however, for reasons of efficiency, no full-fledged chips are arranged on the left side, but rather only a single chip is provided and further functionality is brought about using a diode array. The attacker typically does not recognize such an arrangement even if he has technical aids with which he can read out the individual pins of the computing units. In the present case, the computing units are provided by means of a UHF chip and a diode array. A person skilled in the art recognizes that various chips or various diode arrays can also be used.

In order not to have to use a large number of expensive chips, a preferred development provides for the multiple chips to be replaced by a large number of diodes (diode array) so that only a single "real" UHF chip has to be used potential attackers who have measuring equipment (ohmmeter, characteristic curve recorder) to simulate a real chip, each connection for one of the conductor loops is wired with diodes, as is the case with a real chip in the form of ESD protection diodes - (Ground) connection of one UHF chip can be connected to the ground (ground) connection of the diode array. This means that an attacker from outside can no longer differentiate between "real" and simulated chip connections. It goes without saying that the diode array is in a second, independent chip can be integrated (see Figure 2), which can be produced in a different, possibly cheaper semiconductor technology than the UHF chip. Each connection is equipped with an ESD protection diode, as well as at least one common Vcc voltage control (Zener diode).

3 shows an exemplary arrangement which can be used in the present case. For this purpose, a computing unit is arranged in the upper region of FIG. 3, which has an elongated conductor loop. Further computing units are arranged in the lower area, which can be implemented, for example, as a diode array. Furthermore, FIG. 3 shows a plurality of conductor loops, which can contact a single arithmetic unit in such a way that feedback is provided from this arithmetic unit and into this arithmetic unit, as shown above in the present FIG. 3. The lower conductor loops connect individual computing units in series such that an output of a first computing unit is connected to an input of a second computing unit by means of a conductor loop. Here it is generally possible to loop the individual inputs and outputs of the conductors or to configure the computing units in such a way that they can be varied by means of a connection matrix. In this case, an attacker would therefore always have to arrange the severed conductor loops in such a way as the connection matrix provides in order to conceal a manipulation. However, since the attacker has no knowledge of the connection matrix, he cannot establish the desired interface configuration even after cutting through the conductor loops.

FIG. 4 shows a schematic flow diagram of a method for producing a circuit arrangement with computing units for detecting manipulation of an electronic seal, having a provision 100 a plurality of conductor loops which are arranged on computing units in such a way that the conductor loops enable feedback to the computing units, at least two computing units being provided 101 and the conductor loops being connected 102 by means of configurable interfaces in the computing units.

To make it difficult for an attacker to grind proper interconnection after cutting the conductor, instead of one chip for all Lei terschleifen several chips, eg. B. per conductor loop can be used. Instead of the large number of chips, only one chip can be used, the other chips being replaced by diode arrays. Reading out and assigning ends of cut conductor loops is therefore hardly possible.

Claims

P a te nt claims

1. Circuit arrangement with computing units for detecting manipulation of an electronic seal, comprising:

a plurality of conductor loops which are arranged on computing units in such a way that the conductor loops enable feedback to the computing units, characterized in that the conductor loops are connected to the computing units by means of configurable interfaces.

2. Circuit arrangement according to claim 1, wherein a plurality of conductor loops is arranged per arithmetic unit.

3. Circuit arrangement according to claim 1, wherein the configurable interfaces are set up to provide an input and an output of a single arithmetic unit or an input of a first arithmetic unit and an output of a second arithmetic unit for each conductor loop.

4. Circuit arrangement according to one of the preceding claims, wherein at least one computing unit is designed as a diode array.

5. Circuit arrangement according to one of the preceding claims, wherein at least one computing unit is designed as a UHF chip.

6. Circuit arrangement according to one of the preceding claims, wherein at least one computing unit is designed as a chip which is communicatively coupled to an antenna.

7. Circuit arrangement according to one of the preceding claims, wherein the configurable interfaces are each designed as a pin.

8. Circuit arrangement according to one of the preceding claims, wherein at least one of the configurable interfaces has a protective diode.

9. Circuit arrangement according to one of the preceding claims, wherein a ground connection of a first arithmetic unit is connected to a ground connection of a second arithmetic unit.

10. Circuit arrangement according to one of the preceding claims, wherein the sealing device is designed to be read out without contact.

11. A method for producing a circuit arrangement with arithmetic units for the detection of a manipulation of an electronic seal with the following steps:

- Providing (100) a plurality of conductor loops on computing units; - Feedback to at least one of the computing units via at least one of the conductor loops, characterized in that

- The conductor loops are connected to the computing units by means of configurable interfaces (102).