WO2021142745A1

WO2021142745A1 - Level shifting circuit, control method therefor, and driving circuit

Info

Publication number: WO2021142745A1
Application number: PCT/CN2020/072620
Authority: WO
Inventors: 王晶晶; 陈焱沁; 张兵照; 吴春标; 刘永旺
Original assignee: 华为技术有限公司
Priority date: 2020-01-17
Filing date: 2020-01-17
Publication date: 2021-07-22
Also published as: CN114930720A

Abstract

Provided in the present application are a level shifting circuit, a control method therefor, and a driving circuit, related to the technical field of level shifting. The level shifting circuit comprises a first input end, a first output end, an alternating-current coupling subcircuit, and a positive feedback subcircuit. The alternating-current coupling subcircuit comprises a first coupling input end and a first coupling output end. The first coupling input end is connected to the first input end. The first coupling output end is connected to a first node. The alternating-current coupling subcircuit is used for the alternating-current coupling of a signal of the first coupling input end to the first coupling output end. The positive feedback subcircuit comprises a first feedback input end and a first feedback output end. The first feedback input end and the first feedback output end are connected to the first node. The first node is connected to the first output end. The level shifting circuit is applicable in level shifting of a full frequency band or a wide frequency band.

Description

Level shift circuit and its control method and drive circuit

Technical field

This application relates to the technical field of level shifting, and in particular to a level shifting circuit and its control method and drive circuit.

Background technique

Drive circuit (DC), also known as IC drive circuit, is an important module that determines the performance of the transmitting circuit. It is widely used in various signal transmission systems such as display, monitoring, and audio. With the increase of high-speed data transmission services , The requirements for IC drive circuits are getting higher and higher.

The existing IC drive circuit includes an internal circuit, a level shift circuit, and an output circuit. Among them, the internal circuits mostly use core transistors (core MOS) with faster speed and smaller parasitic capacitance for internal data processing. Since core MOS is not high voltage resistant, the internal circuit works in the low voltage domain; and the output circuit needs to achieve a large scale The output or output common mode voltage is adjustable (supports multiple protocols) and needs to work in the high voltage domain; therefore, the low voltage domain signal output by the internal circuit needs to be moved to the appropriate voltage domain through the level shift circuit, and then input to the output Circuit to ensure that the core mos in the output circuit is not overvoltage, or the input and output transistors (IO mos) work in the appropriate voltage domain.

However, the existing level shifting circuit focuses on the level shifting of low-frequency or high-frequency signals, and cannot perform the level shifting of full-band or wide-band signals, which limits the application of IC drive circuits.

Summary of the invention

The present application provides a level shift circuit, a control method thereof, and a driving circuit, which can be applied to a full frequency band or a wide frequency band level shift.

The embodiment of the application provides a level shift circuit, including a first input terminal, a first output terminal, an AC coupling sub-circuit, and a positive feedback sub-circuit; the AC coupling sub-circuit includes a first coupling input terminal and a first coupling output terminal Wherein, the first coupling input terminal is connected to the first input terminal, the first coupling output terminal is connected to the first node; the AC coupling sub-circuit is used to AC couple the signal of the first coupling input terminal to the first node A coupling output terminal; the positive feedback sub-circuit includes a first feedback input terminal and a first feedback output terminal; wherein the first feedback input terminal and the first feedback output terminal are both connected to the first node; the first node Connect with the first output terminal.

The level shift circuit of the present application AC-couples the signal input from the first input terminal to the first node through the AC coupling sub-circuit, and the positive feedback sub-circuit can feed the first feedback output terminal through the positive feedback of the first feedback input terminal to the first feedback output terminal. One node provides common-mode voltage and differential-mode voltage, so that AC signals (or high-frequency signals) can be transmitted through the AC coupling sub-circuit, and DC signals (or low-frequency signals) can be stabilized through the positive feedback sub-circuit. Whether the signal input by an input terminal is an AC signal or a DC signal can achieve the purpose of level shifting. In addition, the application adopts the combination of the AC coupling sub-circuit and the positive feedback sub-circuit, so that the level shift circuit can support a higher frequency, and at the same time, the complexity of the circuit is reduced.

In some possible implementations, the level shift circuit further includes a second input terminal and a second output terminal; the AC coupling sub-circuit further includes a second coupling input terminal and a second coupling output terminal; the second coupling input terminal Is connected to the second input terminal, the second coupling output terminal is connected to the second node; the AC coupling sub-circuit is also used for AC coupling the signal of the second coupling input terminal to the second coupling output terminal; the positive feedback sub-circuit The circuit further includes a second feedback input terminal and a second feedback output terminal; wherein the second feedback input terminal and the second feedback output terminal are both connected to the second node; the second node is connected to the second output terminal. In this case, the level shift circuit can simultaneously shift the level of a group of signals input from the first input terminal and the second input terminal; for example, shift the level of a group of differential signals.

In some possible implementations, the AC coupling sub-circuit includes a first capacitor; a first pole of the first capacitor is connected to the first coupling input terminal, and a second pole of the first capacitor is connected to the first coupling output terminal. connect.

The AC coupling sub-circuit utilizes the AC-DC blocking characteristic of the first capacitor to AC-couple the input signal from the first coupling input terminal to the first coupling output terminal, and cut off the DC signal input from the first input terminal.

In some possible implementations, the positive feedback sub-circuit includes a first resistor, a second resistor, a first transistor, a second transistor, and a current source; one end of the first resistor is connected to the first voltage terminal, and the first resistor The other end of the first transistor is connected to the control node; the gate of the first transistor is connected to the first feedback input end, the first electrode of the first transistor is connected to the control node, and the second electrode of the first transistor passes through the current source Connected to the second voltage terminal; one end of the second resistor is connected to the first voltage terminal, the other end of the second resistor is connected to the first feedback output terminal; the gate of the second transistor is connected to the control node, The first pole of the second transistor is connected to the first feedback output terminal, and the second pole of the second transistor is connected to the second voltage terminal through the current source.

In this case, when a high level is input to the first feedback input terminal, the first transistor is turned on, the control node is at a low level, and the second transistor is turned off. At this time, the voltage of the first feedback output terminal is equal to the voltage of the first voltage terminal; when the first feedback input terminal inputs a low level, the first transistor is turned off, the control node is at a high level, the second transistor is turned on, and the first feedback output The voltage at the terminal is equal to the voltage at the first voltage terminal minus the divided voltage of the second resistor; in this way, in the DC phase, the first node can be locked at a fixed level through the positive feedback of the first feedback output terminal to the first feedback input terminal .

In some possible implementation manners, the resistance values of the first resistor and the second resistor are the same. In this way, the rate at which the first node flips from the low level to the high level and from the high level to the low level can be made equal, thereby optimizing the eye diagram of the output signal of the first signal output terminal.

In some possible implementations, the AC coupling sub-circuit includes a second capacitor; a first pole of the second capacitor is connected to the second coupling input terminal, and a second pole of the second capacitor is connected to the second coupling output.端连接。 End connection.

The AC coupling sub-circuit utilizes the AC-DC blocking characteristic of the second capacitor to AC-couple the input signal from the second coupling input terminal to the second coupling output terminal, and isolate the DC signal input from the second input terminal.

In some possible implementations, the positive feedback sub-circuit includes a first resistor, a second resistor, a first transistor, a second transistor, and a current source; one end of the first resistor is connected to the first voltage terminal, and the first resistor The other end of the first transistor is connected to the second feedback output end; the gate of the first transistor is connected to the first feedback input end, the first electrode of the first transistor is connected to the second feedback output end, the first transistor The second electrode of the second resistor is connected to the second voltage terminal through the current source; one end of the second resistor is connected to the first voltage terminal, and the other end of the second resistor is connected to the first feedback output terminal; The gate is connected to the second feedback input terminal, the first electrode of the second transistor is connected to the first feedback output terminal, and the second electrode of the second transistor is connected to the second voltage terminal through the current source.

In this case, when the first feedback input terminal inputs a high level, the second feedback input terminal inputs a low level, the first transistor is turned on, the second transistor is turned off, and the voltage at the first feedback output terminal is equal to the voltage at the first voltage terminal , The voltage at the second feedback output terminal is equal to the voltage at the first voltage terminal minus the divided voltage of the second resistor; when the first feedback input terminal inputs a low level, the second feedback input terminal inputs a high level, the first transistor is turned off, and the second The transistor is turned on, the voltage at the first feedback output terminal is equal to the voltage at the first voltage terminal minus the divided voltage of the first resistor, and the voltage at the second feedback output terminal is equal to the voltage at the first voltage terminal. In this way, in the DC stage, the first node and the second node are locked at a fixed level through the positive feedback of the first feedback output terminal to the first feedback input terminal.

In some possible implementations, the first transistor and the second transistor are both N-type transistors; the voltage at the first voltage terminal is greater than the voltage at the second voltage terminal; or, the first transistor and the second transistor are both P-type transistor; the voltage of the second voltage terminal is greater than the voltage of the first voltage terminal.

In some possible implementation manners, the signals input by the first input terminal and the second input terminal are a set of differential signals.

In some possible implementations, the capacitance of the first capacitor and the second capacitor are the same. In this way, the signals input from the first input terminal and the second input terminal have the same AC differential mode amplitude after level shifting.

In some possible implementations, the resistance of the first resistor and the second resistor are the same. In this way, on the one hand, it is possible to make the first node flip from low level to high level and from high level to low level at the same rate, and the second node to flip from low level to high level and from high level. The rate of flipping to a low level is the same, thereby optimizing the eye diagrams of the output signal of the first signal output terminal and the second signal output terminal; A group of differential signals) have the same DC differential mode amplitude after level shifting.

An embodiment of the present application further provides a control method of any of the foregoing level shift circuits, including: inputting a first input data signal to a first input terminal to output a first output data signal through the first output terminal; wherein , The first data signal is in a first voltage domain, the first output data signal is in a second voltage domain, and the second voltage domain is different from the first voltage domain.

In some possible implementation manners, the control method further includes: while inputting the first input data signal to the first input terminal and outputting the first output data signal through the first output terminal, simultaneously The input data signal is input to the second input terminal to respectively output the second output data signal through the second output terminal; wherein, the second input data signal is in the third voltage domain, and the second output data signal is in the fourth voltage domain ; The fourth voltage domain is different from the third voltage domain.

In some possible implementation manners, the third voltage domain and the first voltage domain are the same voltage domain; the fourth voltage domain and the second voltage domain are the same voltage domain.

The embodiment of the present application also provides a driving circuit, including an internal circuit, an output circuit, and any level shift circuit as described above; the first input terminal of the level shift circuit is connected to the first output terminal of the internal circuit, the The first output terminal of the level shift circuit is connected to the first input terminal of the output circuit.

In some possible implementations, the second input terminal of the level shift circuit is connected to the second output terminal of the internal circuit, and the second output terminal of the level shift circuit is connected to the second input terminal of the output circuit.

An embodiment of the present application also provides an electronic device, including any of the aforementioned driving circuits.

Description of the drawings

FIG. 1 is a schematic structural diagram of a level shift circuit provided by an embodiment of the application;

2 is a schematic structural diagram of a positive feedback sub-circuit provided by an embodiment of the application;

3 is a schematic structural diagram of a level shift circuit provided by an embodiment of the application;

4 is a schematic structural diagram of a positive feedback sub-circuit provided by an embodiment of the application;

FIG. 5 is a schematic structural diagram of a level shift circuit provided by an embodiment of the application;

FIG. 6 is a schematic structural diagram of a positive feedback sub-circuit provided by an embodiment of the application;

FIG. 7 is a schematic diagram of a signal for level shifting according to an embodiment of the application;

FIG. 8 is a schematic structural diagram of a driving circuit provided by an embodiment of the application;

FIG. 9 is a schematic structural diagram of a driving circuit provided by an embodiment of the application;

FIG. 10 is a schematic structural diagram of an internal circuit provided by an embodiment of the application;

FIG. 11 is a timing control diagram of the internal circuit of FIG. 10;

FIG. 12 is a schematic structural diagram of an output circuit provided by an embodiment of the application.

Detailed ways

In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in this application will be described clearly and completely in conjunction with the accompanying drawings in this application. Obviously, the described embodiments are part of the embodiments of this application. , Not all examples. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of this application.

The terms "first", "second", etc. in the specification embodiments, claims, and drawings of this application are only used for the purpose of distinguishing description, and cannot be understood as indicating or implying relative importance, nor can it be understood as indicating Or imply the order. In addition, the terms "including" and "having" and any variations of them are intended to cover non-exclusive inclusions, for example, including a series of steps or units. The methods and circuits are not necessarily limited to those clearly listed steps or circuits, but may include other steps or circuits that are not clearly listed or are inherent to these processes, methods, and circuits.

The embodiment of the present application provides a level shift circuit. As shown in FIG. 1, the level shift circuit 2 includes a first input terminal IN1, a first output terminal OUT1, an AC coupling sub-circuit 10 and a positive feedback sub-circuit 20.

As shown in FIG. 1, the AC coupling sub-circuit 10 includes a first coupling input terminal a1 and a first coupling output terminal b1. The first coupling input terminal a1 is connected to the first input terminal IN1, and the first coupling output terminal b1 is connected to the first node N1. The AC coupling sub-circuit 10 is used to AC-couple the signal input from the first coupling input terminal a1 (that is, the first input terminal IN1) to the first coupling output terminal b1 (or the first node N1).

As shown in FIG. 1, the positive feedback sub-circuit 20 includes a first feedback input terminal c1 and a first feedback output terminal d1. Wherein, the first feedback input terminal c1 and the first feedback output terminal d1 are both connected to the first node N1; the first node N1 is connected to the first output terminal OUT1. The positive feedback sub-circuit 20 returns the output signal (that is, the feedback signal) of the first feedback output terminal d1 to the first feedback input terminal c1, and the feedback signal interacts with the original input signal of the first feedback input terminal c1. , Provide the first common mode voltage and the first differential mode voltage to the first node N1.

Regarding the first feedback input terminal c1, the first feedback output terminal d1, the first output terminal OUT1 and the first node N1, it can be understood that the first feedback input terminal c1, the first feedback output terminal d1, and the first node N1 An output terminal OUT1 has the same potential. It can also be understood that a node in a circuit is a junction of three or more branches, and multiple nodes directly connected by wires can be equivalently regarded as one node. In this case, for the above-mentioned first node N1, the first node N1 is a circuit equivalent node, which is not necessarily one node, but may also be multiple nodes; for example, as shown in FIG. 1, the first node N1 is a circuit equivalent node. A feedback input terminal c1 and a first feedback output terminal d1 are connected to the same node, and are connected to the first output terminal OUT1 through another node; for another example, as shown in FIG. 3, the first feedback input terminal c1 and the first feedback input terminal d1 are connected to the same node. The feedback output terminal d1 is connected to different nodes, and the two nodes are both connected to the first output terminal OUT1; for another example, the first feedback input terminal c1, the first feedback output terminal d1, and the first output terminal OUT1 are directly connected to the same node ; The foregoing several connection modes can all be regarded as equivalent connection modes. In the actual process design, it can be set according to requirements, and the same is true for the second node N2 (refer to Figure 3) in the following text, which will not be repeated here.

In summary, the level shift circuit of the present application AC-couples the signal input from the first input terminal to the first node through the AC coupling sub-circuit, and the positive feedback sub-circuit connects the positive feedback of the first feedback output terminal through the first feedback input terminal. Feedback can provide common mode voltage and differential mode voltage to the first node, so that AC signals (also high-frequency signals) can be transmitted through the AC coupling sub-circuit, and DC signals (also low-frequency signals) can be stabilized through the positive feedback sub-circuit That is, regardless of whether the signal input by the first input terminal is an AC signal or a DC signal, the purpose of level shifting can be achieved. In addition, the application adopts the combination of the AC coupling sub-circuit and the positive feedback sub-circuit, so that the level shift circuit can support a higher frequency, and at the same time, the complexity of the circuit is reduced.

Illustratively, when a DC signal is input at the first input terminal, the AC coupling sub-circuit blocks the DC signal, the positive feedback sub-circuit provides the DC common mode voltage and the DC differential mode voltage to the first node for level shifting, and the first output Maintaining the DC voltage at the terminal corresponds to the non-DC balanced signal transmission, which is to maintain the signal level of long 0 or long 1. When an AC signal is input at the first input terminal, the AC signal is output to the first node through the AC coupling sub-circuit, and the AC common-mode voltage provided by the positive feedback sub-circuit to the first node is level shifted and performed through the first output terminal. Output.

Illustratively, the following provides a specific circuit of a level shift circuit using single-ended input and single-ended output; that is, the level shift circuit includes an input terminal (IN1) and an output terminal (OUT1).

In some possible implementations, as shown in FIG. 1, the AC coupling sub-circuit 10 may include a first capacitor C1. The first pole of the first capacitor C1 is connected to the first coupling input terminal a1, and the second pole of the first capacitor C1 is connected to the first coupling output terminal b1. Illustratively, the first capacitor C1 may be one capacitor, or may be composed of multiple capacitors connected in series or in parallel, which is not specifically limited in this application.

It can be understood that the first capacitor C1 itself has the characteristic of passing AC and blocking DC, so that under the action of the first capacitor C1, the signal input by the first input terminal N1 can be AC coupled; that is to say; Through the first capacitor C1, the AC signal input from the first input terminal N1 can be coupled and output to the first node N1, and the DC signal input from the first input terminal N1 can be blocked.

In some possible implementations, the AC coupling sub-circuit 10 may adopt an electromagnetic induction coupling circuit to AC-couple the signal input from the first coupling input terminal a1 to the first coupling output terminal b1. In this application, the electromagnetic induction coupling circuit The specific setting structure is not limited, and you can choose the setting according to your needs in practice.

In some possible implementations, as shown in FIG. 1 and FIG. 2, the positive feedback sub-circuit 20 may include a first resistor R1, a second resistor R2, a first transistor T1, a second transistor T2, and a current source S (for example, it may Is a constant current source). One end of the first resistor R1 is connected to the first voltage terminal AVHH, and the other end of the first resistor R1 is connected to the control node O. The gate of the first transistor T1 is connected to the first feedback input terminal c1, the first electrode of the first transistor T1 is connected to the control node O, and the second electrode of the first transistor T1 is connected to the second voltage terminal AVSS through the current source S; One end of the second resistor R2 is connected to the first voltage terminal AVHH, and the other end of the second resistor R2 is connected to the first feedback output terminal d1; the gate of the second transistor T2 is connected to the control node O, and the first The electrode is connected to the first feedback output terminal d1, and the second electrode of the second transistor T2 is connected to the second voltage terminal AVSS through the current source S; that is, the first transistor T1 and the second transistor T2 have a common mode current source S. Illustratively, the first transistor T1 and the second transistor T2 may both be P-type transistors, or the first transistor T1 and the second transistor T2 are both N-type transistors; in practice, they can be selected and set according to needs.

In the case where the first transistor T1 and the second transistor T2 are both N-type transistors (such as NMOS transistors), the first pole of the first transistor T1 and the second transistor T2 has a source and a second pole has a drain; The voltage at the terminal AVHH may be a high-level voltage, and the voltage at the second voltage terminal AVSS is a low-level voltage; that is, the voltage at the second voltage terminal AVSS is less than the voltage at the first voltage terminal AVHH. Illustratively, the first voltage terminal AVHH is connected to the high-level voltage terminal, and the second voltage terminal AVSS is connected to the ground terminal (that is, the voltage of the second voltage terminal AVSS is the ground voltage).

In the case where the first transistor T1 and the second transistor T2 are both P-type transistors (such as PMOS transistors), the first pole of the first transistor T1 and the second transistor T2 has a drain, and the second pole has a source; the second voltage The voltage at the terminal may be a high-level voltage, and the voltage at the first voltage terminal is a low-level voltage; that is, the voltage at the second voltage terminal is greater than the voltage at the first voltage terminal. Illustratively, the second voltage terminal is connected to the high-level voltage terminal, and the first voltage terminal is connected to the ground terminal (that is, the voltage at the first voltage terminal is the ground voltage).

In some possible implementations, the resistance values of the first resistor R1 and the second resistor R2 in FIG. 2 can be set to be the same, so that the first node N1 flips from a low level to a high level and from a high level to a low level. The rates of the levels are equal, thereby optimizing the eye diagram of the output signal of the first signal output terminal. It is understandable that the eye diagram refers to the graphics displayed by the output data signal of the transmitting circuit accumulated on the oscilloscope. The eye diagram can reflect the size of the crosstalk and noise between the codes, and reflect the characteristics of the signal as a whole; the quality of the eye diagram is also a measure of the emission An important indicator of circuit performance.

Schematically, the working process of the positive feedback sub-circuit 20 shown in FIG. 2 will be schematically described below. Taking the first transistor T1 and the second transistor T2 in FIG. 2 as an example, the current provided by the current source S is I; R1=R2=R.

When the first feedback input terminal c1 inputs a high level, the first transistor T1 is turned on, the control node O is at a low level, and the second transistor T2 is turned off. At this time, the voltage of the first feedback output terminal d1 is equal to the voltage V _{AVHH of the} first voltage terminal AVHH; when the first feedback input terminal c1 inputs a low level, the first transistor T1 is turned off, and the control node O is at a high level. The two transistors T2 are turned on, and the voltage of the first feedback output terminal d1 is equal to V _AVHH- IR; where V _AVHH is the voltage of the first voltage terminal AVHH. In this case, in the DC stage, the first node N1 can be locked at a fixed level (V _AVHH or V _AVHH- IR) through the positive feedback of the first feedback output terminal d1 to the first feedback input terminal c1. Regarding the potential control of the first node N1 in the AC phase, reference may be made to the subsequent embodiments.

In some embodiments, in order to move the voltage domains of two signals (such as a group of differential signals) at the same time, as shown in FIG. 3, the level shift circuit 2 includes a first input terminal IN1 and a first output terminal OUT1. On the basis of, it may also include a second input terminal IN2 and a second output terminal OUT2.

In this case, as shown in FIG. 3, the AC coupling sub-circuit 10 includes the first coupling input terminal a1 and the first coupling output terminal b1, and also includes a second coupling input terminal a2 and a second coupling output terminal. b2. Wherein, the second coupling input terminal a2 is connected to the second input terminal IN2, and the second coupling output terminal b2 is connected to the second node N2. The AC coupling sub-circuit 10 is also used to AC-couple the signal input from the second coupling input terminal a2 (that is, the second input terminal IN2) to the second coupling output terminal b2.

In addition to the aforementioned first feedback input terminal c1 and the first feedback output terminal d1, the positive feedback sub-circuit 20 further includes a second feedback input terminal c2 and a second feedback output terminal d2. Wherein, the second feedback input terminal c2 and the second feedback output terminal d2 are both connected to the second node N2; the second node N2 is connected to the second output terminal OUT2. The positive feedback sub-circuit 20 returns the output signal (that is, the feedback signal) of the second feedback output terminal d2 to the second feedback input terminal c2, and the feedback signal interacts with the original input signal of the second feedback input terminal c2, The second node N2 is provided with a second common mode voltage and a second differential mode voltage.

Of course, in the actual production of the level shift circuit itself, as shown in Figure 5, parasitic capacitances Cp1 and Cp2 will inevitably be formed at the first node N1 and the second node N2; for example, the parasitic capacitances Cp1 and Cp2 are formed at the first node N1 and the second node N2; The capacitor plates and wires connected to N2 will generate parasitic capacitance. Illustratively, in some possible implementation manners, the capacitances of the two parasitic capacitors Cp1 and Cp2 can be equal, which can be expressed as Cp1=Cp2.

For illustration, the following provides a specific circuit of a level shift circuit using double-ended input and double-ended output, that is, the level shift circuit includes two input terminals (IN1, IN2) and two output terminals (OUT1, OUT2). ).

For the AC coupling sub-circuit 10:

In some possible implementations, as shown in FIG. 3, the AC coupling sub-circuit 10 may include a first capacitor C1 and a second capacitor C2.

The first pole of the first capacitor C1 is connected to the first coupling input terminal a1, and the second pole of the first capacitor C1 is connected to the first coupling output terminal b1. The first pole of the second capacitor C2 is connected to the second coupling input terminal a2, and the second pole of the second capacitor C2 is connected to the second coupling output terminal b2. Illustratively, the first capacitor C1 may be one capacitor, or may be respectively composed of multiple capacitors connected in series or in parallel; the same is true for the second capacitor C2; this application does not specifically limit this.

In some possible implementations, the AC coupling sub-circuit 10 may adopt an electromagnetic induction coupling circuit; through the electromagnetic induction coupling circuit, the signal input from the first coupling input terminal a1 is AC coupled and output to the first coupling output terminal b1, and the second The signal input from the coupling input terminal a2 is AC-coupled and output to the second coupling output terminal b2. The specific configuration of the magnetic induction coupling circuit is not limited in this application, and it can be selected and configured according to actual needs.

In some possible implementation manners, in order to make the signals input from the first input terminal IN1 and the second input terminal IN2 have the same AC differential mode amplitude after level shifting, the voltage of the second capacitor C2 in FIG. 3 can be set The capacity is the same as that of the first capacitor C1, which can be expressed as C1=C2.

For the positive feedback sub-circuit 20:

In some possible implementations, the positive feedback sub-circuit 20 may adopt two independently arranged feedback circuits (a first feedback circuit and a second feedback circuit); the first feedback circuit (as shown in FIG. 2) passes through the first feedback input terminal c1 And the first feedback output terminal d1 to provide the first common-mode voltage and the first differential-mode voltage to the first node N1, and the second feedback circuit (as shown in Fig. 4) transmits to the second feedback input terminal c2 and the second feedback output terminal d2 The second node N2 provides a second common mode voltage and a second differential mode voltage. For the connection relationship and related working process of the feedback circuit shown in FIG. 4, reference may be made to the foregoing description of the feedback circuit in FIG. 2, which will not be repeated here.

It should be noted that the circuit structures of the above two feedback circuits may be the same (refer to FIG. 2 and FIG. 4) or different. Wherein, the first common mode voltage provided by the first feedback circuit to the first node N1 and the second common mode voltage provided by the second feedback circuit to the second node N2 may be the same or different; for the same reason, such as the first differential mode The voltage and the second differential mode voltage can be the same or different.

Illustratively, taking the positive feedback sub-circuit 20 using the two feedback circuits shown in FIG. 2 and FIG. 4 as an example, in the actual circuit design, the first resistors in the first feedback circuit and the second feedback circuit can be set. The resistance of R1, the resistance of the second resistor R2, the voltage of the first voltage terminal AVHH, the voltage of the second voltage terminal AVSS, and the current of the current source S can be the same or different; in practice, it can Select the settings according to your needs.

In some possible implementations, as shown in FIG. 5, the positive feedback sub-circuit 20 may adopt a DC positive feedback differential operational amplifier circuit; the first feedback input terminal c1 is connected to the forward input terminal of the operational amplifier circuit, and the first feedback The output terminal d1 is connected to the forward output terminal of the operational amplifier circuit; the second feedback input terminal c2 is connected to the reverse input terminal of the operational amplifier circuit, and the second feedback output terminal d2 is connected to the reverse output terminal of the operational amplifier circuit. It can be understood that the current of the DC positive feedback differential operational amplifier circuit usually comes from the mirror image of the reference current, which is generated by a fixed voltage and resistance.

Illustratively, in some embodiments, the above-mentioned differential operational amplifier circuit may adopt a current mode logic circuit (current mode logic, CML), that is, a CML differential operational amplifier circuit. As shown in FIG. 6, the CML differential operational amplifier circuit may include a first resistor R1, a second resistor R2, a first transistor T1, a second transistor T2, and a current source S (for example, it may be a constant current source). One end of the first resistor R1 is connected to the first voltage terminal AVHH, and the other end of the first resistor R1 is connected to the second feedback output terminal d2; the gate of the first transistor T1 is connected to the first feedback input terminal c1, The first pole of the transistor T1 is connected to the second feedback output terminal d2, and the second pole of the first transistor T1 is connected to the second voltage terminal AVSS through the current source S. One end of the second resistor R2 is connected to the first voltage terminal AVHH, and the other end of the second resistor R2 is connected to the first feedback output terminal d1; the gate of the second transistor T2 is connected to the second feedback input terminal c2, and the second transistor T2 The first electrode of the second transistor T2 is connected to the first feedback output terminal d1, and the second electrode of the second transistor T2 is connected to the second voltage terminal AVSS through the current source S; that is, the first transistor T1 and the second transistor T2 have a common mode current source S.

Illustratively, the first transistor T1 and the second transistor T2 may both be P-type transistors, or the first transistor T1 and the second transistor are both N-type transistors, which can be selected and set according to actual needs.

In the case where the first transistor T1 and the second transistor T2 can be both N-type transistors, the first transistor T1 and the second transistor T2 have a source at the first pole and a drain at the second pole; the voltage at the first voltage terminal AVHH It may be a high-level voltage, and the voltage of the second voltage terminal AVSS is a low-level voltage (for example, a ground voltage).

In the case where the first transistor T1 and the second transistor T2 are both P-type transistors (such as PMOS transistors), the first transistor T1 and the second transistor T2 have a drain at the first pole and a source at the second pole; The voltage may be a high-level voltage, and the voltage at the first voltage terminal is a low-level voltage (for example, a ground voltage).

In some possible implementation manners, it can be set that the resistance values of the first resistor R1 and the second resistor R2 in FIG. 6 can be the same, or can be expressed as R1=R2. In this way, on the one hand, the rate at which the first node N1 flips from low level to high level and from high level to low level can be made equal, and the second node N2 flips from low level to high level and from high level. The rate of level flipping to low level is the same, thereby optimizing the eye diagram of the output signal of the first signal output terminal and the second signal output terminal; on the other hand, it can also make the first input terminal IN1 and the second input terminal IN2 input The signal (such as a group of differential signals) has the same DC differential mode amplitude after level shifting.

In some possible implementations, the capacitances of the first capacitor C1 and the second capacitor C2 in FIG. 6 can be set to be the same, or it can be expressed as C1=C2. In this way, the signals (for example, a group of differential signals) input by the first input terminal IN1 and the second input terminal IN2 can have the same AC differential mode amplitude after level shifting.

Schematically, the working process of the positive feedback sub-circuit 20 shown in FIG. 6 is schematically described below. Taking the first transistor T1 and the second transistor T2 in FIG. 6 as an example, the current provided by the current source S is I; R1=R2=R. The first input terminal N1 and the second input terminal N2 of the level shift circuit input a set of differential signals (Data_p and Data_n in FIG. 7). In this case, the signals input by the first feedback input terminal c1 and the second feedback input terminal c2 are also a set of differential signals.

When the first feedback input terminal c1 inputs a high level, the second feedback input terminal c2 inputs a low level, the first transistor T1 is turned on, the second transistor T2 is turned off, and the voltage at the first feedback output terminal d1 is equal to the first voltage terminal The voltage of AVHH is V _AVHH , and the voltage of the second feedback output terminal d2 is equal to V _AVHH- IR; where, V _AVHH is the voltage of the first voltage terminal AVHH. When the first feedback input terminal c1 inputs a low level, the second feedback input terminal c2 inputs a high level, the first transistor T1 is turned off, the second transistor T2 is turned on, and the voltage at the first feedback output terminal d1 is equal to V _AVHH -IR , The voltage at the second feedback output terminal d2 is equal to V _AVHH .

In this case, in the DC stage, through the positive feedback of the first feedback output terminal d1 to the first feedback input terminal c1, the first node N1 is locked at the fixed level V _AVHH -IR (or V _AVHH ), and the second The positive feedback of the feedback output terminal d2 to the second feedback input terminal c2 locks the second node N2 at the fixed level V _AVHH (or V _AVHH -IR). Regarding the potential control of the first node N1 and the second node N2 in the AC phase, see the subsequent embodiments.

It is understandable that the differential mode of the CML differential operational amplifier circuit shown in FIG. 6 is usually determined by the AC differential mode, and the power supply voltage of the CML differential operational amplifier circuit (that is, the voltage of the first voltage terminal AVHH) can be adjusted, The common mode voltage of the first node N1 and the second node N2 is adjustable. And the use of the CML differential operational amplifier circuit can achieve the purpose of narrow bandwidth and low power consumption.

It should be noted that the double-ended input (c1, c2) and double-ended output (d1, d2) CML differential operational amplifier circuits shown in Figure 6 can also be applied to the aforementioned single-ended input and single-ended output circuits. In the translation circuit, in this case, it is only necessary to connect the first feedback input terminal c1 and the first feedback output terminal d1 to the first node N1, and input a fixed level to the second feedback input terminal c2. It can be the output common mode voltage of the CML differential operational amplifier circuit, and the second feedback output terminal d2 is in a floating state.

Referring to Figure 5, the level shift circuit includes two input terminals (first input terminal IN1 and second input terminal IN2) and two output terminals (first output terminal OUT1 and second output terminal OUT2), a positive feedback sub-circuit 20 Take the CML differential operational amplifier circuit in Figure 6 as an example, set C1=C2=C _AC ; R1=R2=R; the current provided by the current source S is I; the parasitic capacitances of the first node N1 and the second node N2 Cp1=Cp2=C _PAR , the level shift of the level shift circuit will be schematically described below in conjunction with specific numerical calculations.

Referring to Figures 5 and 7, suppose the set of differential signals input by the first input terminal IN1 and the second input terminal IN2 are Data_n and Data_p, and the set of differential signals output by the first output terminal OUT1 and the second output terminal OUT2 are: Pre_n And Pre_p; among them, Data_n and Data_p include AC phase HF and DC phase LF.

Referring to Figure 7, the high and low levels of Data_n and Data_p are V _avddl and 0 respectively; in this case, the amplitude between the high and low levels of Data_n and Data_p after passing through the first capacitor C1 and the second capacitor C2

_{Referring to FIG. 7, the DC common mode voltage V CM} and the DC differential mode voltage V _DM provided by the positive feedback sub-circuit 20 to the first node N1 and the second node N2 are respectively the same; where the DC common mode voltage V _CM =V _AVHH -IR /2: DC differential mode voltage V _DM =IR.

In the AC phase HF, a set of differential signals (Data_n and Data_p) input from the first input terminal IN1 and the second input terminal IN2 are AC-coupled by the AC coupling sub-circuit 10, and the DC common mode voltage V of the positive feedback sub-circuit 20 _{Under the action of CM} , the signals (Pre_n and Pre_p) output by the first output terminal OUT1 and the second output terminal OUT2 are controlled to move to the AC high level V _{ac_vhh} and the AC low level V _{ac_vll} ; where the AC high level V _{ac_vhh} = V _CM +V _AC /2, AC low level V _{ac_vll} =V _CM -V _AC /2.

In the DC stage LF, under _{the combined action of the DC common mode voltage V CM} and the DC differential mode voltage V _DM of the positive feedback sub-circuit 20, the signals (Pre_n and Pre_p) output by the first output terminal OUT1 and the second output terminal OUT2 are controlled _Move to DC high level V dc_vhh and DC low level V _{dc_vll} ; among them, DC high level V _{dc_vhh} =V _AVHH , DC low level V _{dc_vll} =V _AVHH -IR.

In practice, you can set the relevant parameters (the capacitance of the capacitors C1 and C2 in Figure 5, the resistance of the resistors R1 and R2 in Figure 6, and the voltage of the first voltage terminal AVHH, etc.) to make the DC differential mode amplitude It is close to the AC differential mode amplitude (that is, V _{ac_vhh} and V _{dc_vhh} are close, and V _{ac_vll} and V _{dc_vll} are close), so as to ensure the best effect of data signal level shifting.

In addition, it can be understood that when the signals (Data_n and Data_p) input from the input terminals (IN1, IN2) of the level shift circuit of the present application are in the DC phase LF, the positive feedback sub-circuit 20 is used to control the high and low levels of the first node N1 and Both the high and low levels of the second node N2 reach the high and low levels of the CML differential operational amplifier circuit, which can not only solve the transmission of non-DC balanced code stream signals, but also can handle ultra-low frequency signals.

In addition, when the level shift circuit includes two input terminals (first input terminal IN1 and second input terminal IN2) and two output terminals (first output terminal OUT1 and second output terminal OUT2), the first input terminal The terminal IN1 and the second input terminal IN2 can input a group of differential signals.

In this case, in some possible implementations, the set of differential signals can be moved to different level ranges by setting a level shifting circuit; for example, one of a set of differential signals located at 0～1.1V can be moved. The signal is moved to 0～1.5V, and the other signal is moved to 0～1.8V. In some possible implementations, the set of differential signals can be moved to the same level range by setting a level shift circuit (that is, the first output terminal OUT1 and the second output terminal OUT2 also output a set of differential signals); for example, It is possible to move both signals in a group of differential signals of 0～1.1V to 0～1.5V.

The embodiment of the present application also provides a control method of any of the foregoing level shift circuits, and the control method includes:

The first input data signal is input to the first input terminal IN1 to output the first output data signal through the first output terminal OUT1.

The first data signal is in a first voltage domain, the first output data signal is in a second voltage domain, and the second voltage domain is different from the first voltage domain.

That is, the first input data signal in the first voltage domain is moved to the first output data signal in the second voltage domain after the level shift circuit. Illustratively, the first input data signal at 0˜1.1V can be moved to the first output data signal at 0˜1.5V after the level shift circuit.

In the case where the level shift circuit includes a first input terminal IN1, a second input terminal IN2, a first output terminal OUT1, and a second output terminal OUT2, the above control method further includes:

While the first input data signal is input to the first input terminal IN1 and the first output data signal is output through the first output terminal OUT1, the second input data signal can be input to the second input terminal IN2 to pass the second output terminal IN2. The terminal OUT2 outputs the second output data signal; wherein, the second input data signal is in the third voltage domain, and the second output data signal is in the fourth voltage domain.

In other words, the first input data signal in the first voltage domain is moved to the first output data signal in the second voltage domain after the level shift circuit, and the second input data signal in the third voltage domain is level-shifted The circuit is then moved to the second output data signal in the fourth voltage domain.

In some possible implementation manners, the above-mentioned first voltage domain and the third voltage domain may be the same voltage domain, and the second voltage domain and the fourth voltage domain are the same voltage domain. For example, a group of differential signals (that is, the first input data signal and the second input data signal) in the same voltage domain (0～1.1V) are moved to another voltage domain (0～1.5 V) a set of differential signals (that is, the first output data signal and the second output data signal).

The embodiment of the present application also provides a driving circuit. As shown in FIG. 8, the driving circuit includes an internal circuit 1, any of the aforementioned level shifting circuits 2, and an output circuit 3. As shown in FIG. The first input terminal IN1 of the level shift circuit 2 is connected to the first output terminal of the internal circuit 1, and the first output terminal OUT1 of the level shift circuit 2 is connected to the first input terminal of the output circuit 3.

In the case where the level shift circuit includes two input terminals (first input terminal IN1 and second input terminal IN2) and two output terminals (first output terminal OUT1 and second output terminal OUT2), as shown in FIG. 9 , The internal circuit 1 includes two output terminals, and the output circuit 3 includes two input terminals. The two input terminals (IN1, IN2) of the level shift circuit 2 are respectively connected with the two output terminals of the internal circuit, and the two output terminals (OUT1, OUT2) of the level shift circuit are respectively connected with the two input terminals of the output circuit 3. connect.

For the above-mentioned level shift circuit including two input terminals (IN1, IN2) and two output terminals (OUT1, OUT2), the following schematic provides a specific internal circuit 1 and output circuit 3 (but internal circuit 1 The sum output circuit 3 is not limited to this), and the driving process of the driving circuit is schematically described in conjunction with the level shift circuit 2.

The internal circuit 1 as shown in FIG. 10 is an internal signal processing circuit commonly used by serializers (serdes), and includes a core module 11, a half frequency divider 12, and a flip-flop 13 (D flip-flop). Among them, the core module 11 includes two D flip-flops and selectors; the input terminals D of the two D flip-flops respectively input two parallel data signals Data (D0, D1), and the output terminals Q of the two D flip-flops and the selector The output of the selector is connected to the input D of the flip-flop 13, and the two output ends Q and QB of the flip-flop 13 are respectively connected to the two input ends of the level shift circuit 2 (the first input IN1 is connected to the second input terminal IN2). The high-frequency clock signal terminal CLK is connected to the clock control terminal CK of the flip-flop 13 and the input terminal of the half frequency divider 12, and the output terminal of the half frequency divider 12 is triggered by the two Ds in the core module 11. And the clock control terminal CK of the selector is connected.

As shown in FIG. 11, the clock signal (CLK) of the high-frequency clock signal terminal is divided by a half frequency divider 12 into a clock signal of one half of the original frequency (CLK/2). For the sake of conciseness and clarity in the drawings and the following, the clock signal terminal and the signal of the clock signal terminal are all represented by the same symbol, which should not be understood as unclear. In this case, the two D flip-flops in the core module 11 respectively sample the two parallel data signals Data (D0, D1) under the control of the clock signal (CLK/2), and sample the two channels through the selector The latter signal is mixed into a channel of high-frequency data, and then sampled under the control of the clock signal CLK through the flip-flop 13, and a set of differential outputs are respectively output to the first input terminal IN1 and the second input terminal IN2 through the two output terminals Q and QB. The signals Data_p and Data_n.

The output circuit 3 shown in Figure 12 is an output stage drive circuit with common mode feedback, including a first switching transistor S1, a second switching transistor S2, a first matching resistor Ra, a second matching resistor Rb, and a control transistor. S3; wherein one end of the first matching resistor Ra is connected to the power terminal AVDDRX, the other end of the first matching resistor Ra is connected to the first output terminal outp, one end of the second matching resistor Rb is connected to the power terminal AVDDRX, and the second matching resistor The other end of Rb is connected to the second output terminal outn; the gate of the first switch transistor S1 is connected to the first output terminal OUT1 of the level shift circuit, the source of the first switch transistor S1 is connected to the first output terminal outp, and the first switch transistor S1 is connected to the first output terminal outp. The drain of a switching transistor S1 is connected to the source of the control transistor S3; the gate of the second switching transistor S2 is connected to the second output terminal OUT2 of the level shift circuit, and the source of the second switching transistor S2 is connected to the second output terminal Outn is connected, the drain of the second switching transistor S2 is connected to the source of the control transistor S3; the gate of the control transistor S3 is connected to the control terminal V_nbias, and the drain of the control transistor S3 is connected to the ground terminal. A load Rterm can be connected between the first output terminal outp and the second output terminal outn.

The above-mentioned first switch transistor S1 and second switch transistor S2 are switch pairs, using N-type input and output transistors (i.e. IO nmos) and control transistor S3 as NMOS transistors; the voltage of the power supply terminal AVDDRX exceeds the high voltage of the core mos withstand voltage.

Using the output circuit 3 with common mode feedback in Figure 12, although the output stage switch tube (the first switch transistor S1, the second switch transistor S2) is IO mos, the level shift circuit 2 can output the output of the internal circuit 1. The potentials of the differential signals Data_p and Data_n are moved, which not only protects the IO mos from overvoltage, but also ensures that the IO mos works in a suitable voltage domain to adapt to different output common modes.

The application of the level shifting circuit in the embodiment of the present application includes but is not limited to the driving circuit, and other circuits that need to perform level shifting can all adopt the above-mentioned level shifting circuit.

The above are only specific implementations of this application, but the protection scope of this application is not limited to this. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in this application. Should be covered within the scope of protection of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims

A level shift circuit, characterized by comprising a first input terminal, a first output terminal, an AC coupling sub-circuit and a positive feedback sub-circuit;

The AC coupling sub-circuit includes a first coupling input terminal and a first coupling output terminal; wherein the first coupling input terminal is connected to the first input terminal, and the first coupling output terminal is connected to a first node;

The AC coupling sub-circuit is used for AC coupling the signal of the first coupling input terminal to the first coupling output terminal;

The positive feedback sub-circuit includes a first feedback input terminal and a first feedback output terminal; wherein the first feedback input terminal and the first feedback output terminal are both connected to the first node;

The first node is connected to the first output terminal.
The level shift circuit according to claim 1, wherein the level shift circuit further comprises a second input terminal and a second output terminal; the AC coupling sub-circuit further comprises a second coupling input terminal and a second output terminal; Coupled output

The second coupling input terminal is connected to the second input terminal, and the second coupling output terminal is connected to a second node;

The AC coupling sub-circuit is also used to AC couple the signal from the second coupling input terminal to the second coupling output terminal;

The positive feedback sub-circuit further includes a second feedback input terminal and a second feedback output terminal; wherein the second feedback input terminal and the second feedback output terminal are both connected to the second node;

The second node is connected to the second output terminal.
The level shift circuit according to claim 1 or 2, characterized in that:

The AC coupling sub-circuit includes a first capacitor; a first pole of the first capacitor is connected to the first coupling input terminal, and a second pole of the first capacitor is connected to the first coupling output terminal.
The level shift circuit according to any one of claims 1-3, wherein:

The positive feedback sub-circuit includes a first resistor, a second resistor, a first transistor, a second transistor, and a current source;

One end of the first resistor is connected to a first voltage terminal, and the other end of the first resistor is connected to a control node;

The gate of the first transistor is connected to the first feedback input terminal, the first electrode of the first transistor is connected to the control node, and the second electrode of the first transistor is connected to the first terminal through the current source. Two voltage terminals are connected;

One end of the second resistor is connected to the first voltage terminal, and the other end of the second resistor is connected to the first feedback output terminal;

The gate of the second transistor is connected to the control node, the first electrode of the second transistor is connected to the first feedback output terminal, and the second electrode of the second transistor is connected to the current source through the current source. The second voltage terminal is connected.
The level shift circuit according to any one of claims 2-3, wherein:

The AC coupling sub-circuit includes a second capacitor; a first pole of the second capacitor is connected to the second coupling input terminal, and a second pole of the second capacitor is connected to the second coupling output terminal.
The level shift circuit according to any one of claims 2-3 and 5, wherein:

The positive feedback sub-circuit includes a first resistor, a second resistor, a first transistor, a second transistor, and a current source;

One end of the first resistor is connected to a first voltage terminal, and the other end of the first resistor is connected to the second feedback output terminal;

The gate of the first transistor is connected to the first feedback input terminal, the first electrode of the first transistor is connected to the second feedback output terminal, and the second electrode of the first transistor passes the current The source is connected to the second voltage terminal;

One end of the second resistor is connected to the first voltage terminal, and the other end of the second resistor is connected to the first feedback output terminal;

The gate of the second transistor is connected to the second feedback input terminal, the first electrode of the second transistor is connected to the first feedback output terminal, and the second electrode of the second transistor passes the current The source is connected to the second voltage terminal.
The level shift circuit according to claim 4 or 6, characterized in that:

The first transistor and the second transistor are both N-type transistors; the voltage of the first voltage terminal is greater than the voltage of the second voltage terminal;

Alternatively, the first transistor and the second transistor are both P-type transistors; the voltage of the second voltage terminal is greater than the voltage of the first voltage terminal.
7. The level shift circuit according to any one of claims 2, 3, and 5-7, wherein the signals input by the first input terminal and the second input terminal are a set of differential signals.
8. The level shift circuit according to any one of claims 5-8, wherein the capacitance of the first capacitor and the second capacitor are the same.
The level shift circuit according to any one of claims 4-9, wherein:

The resistance values of the first resistor and the second resistor are the same.
A method for controlling a level shift circuit according to any one of claims 1-10, characterized in that it comprises:

Inputting the first input data signal to the first input terminal to output the first output data signal through the first output terminal;

Wherein, the first data signal is in a first voltage domain, the first output data signal is in a second voltage domain, and the second voltage domain is different from the first voltage domain.
The control method of the level shift circuit according to claim 11, characterized in that it comprises:

While the first input data signal is input to the first input terminal and the first output data signal is output through the first output terminal, the second input data signal is input to the second input terminal to pass the The second output terminal outputs a second output data signal;

Wherein, the second input data signal is in a third voltage domain, and the second output data signal is in a fourth voltage domain; the fourth voltage domain is different from the third voltage domain.
A drive circuit, characterized by comprising an internal circuit, an output circuit, and the level shift circuit according to any one of claims 1-10; the first input terminal of the level shift circuit and the internal circuit The first output terminal is connected, and the first output terminal of the level shift circuit is connected with the first input terminal of the output circuit.
The driving circuit of claim 13, wherein the second input terminal of the level shift circuit is connected to the second output terminal of the internal circuit, and the second output terminal of the level shift circuit is connected to the second output terminal of the internal circuit. The second input terminal of the output circuit is connected.