WO2021139166A1

WO2021139166A1 - Error page identification method based on three-dimensional flash storage structure

Info

Publication number: WO2021139166A1
Application number: PCT/CN2020/110817
Authority: WO
Inventors: 黄敏; 杜雅芝; 肖仲喆; 吴迪; 顾济华
Original assignee: 苏州大学
Priority date: 2020-01-07
Filing date: 2020-08-24
Publication date: 2021-07-15
Also published as: CN111240887A

Abstract

An error page identification method based on a three-dimensional flash storage structure. The read speeds of all physical pages in a three-dimensional flash storage system OCSSD structure represent the error rates of the physical pages. All physical pages are classified according to the reliability levels by a machine learning method. The lower the level, the higher the error rate. A physical page having a high error rate is selected for real-time data migration, thereby effectively reducing the error rate and improving the reliability of the three-dimensional flash storage system.

Description

Error page recognition method based on three-dimensional flash memory storage structure

Technical field

The invention relates to the field of three-dimensional flash memory storage structures, in particular to an error page identification method based on the three-dimensional flash memory storage structure.

Background technique

Compared with SLC (Single Level Cell) and MLC (Multiple Level Cell) flash memory devices, TLC (Triple Level Cell) flash memory devices have higher storage density and lower cost, especially when used in three-dimensional flash memory storage systems The land is more extensive. The use of 3D stacking technology in the three-dimensional flash memory storage system, that is, the vertical stacking of TLC flash memory basic units, makes the storage density of flash memory rapidly increase while the reliability is constantly decreasing.

Traditional technology has the following technical problems:

In order to be able to reduce the error rate stored in the 3D flash memory storage system, the current research status mainly relies on the error correction code and does not rely on the error correction code to solve the problem of increasing error rate in the 3D flash memory storage system and improve the storage system Overall reliability performance. The use of error correction codes is one of the effective means to reduce the increase in the error rate of flash memory storage systems. Hamming codes are the earliest used in flash memory devices, which can sufficiently meet the error correction requirements of SLC flash memory devices. With the advent of MLC flash memory devices, the Hamming code error correction capability cannot meet the demand. RS codes and BCH codes have been proposed in the field of flash storage systems, but with the increase in the density of basic storage units and the structural characteristics of the basic storage units of flash memory, the probability of data storage errors cannot be met. However, three-dimensional flash memory storage systems generally use TLC as the storage medium, and the demand for error correction codes has become greater. In order to ensure the reliability of data in today’s flash-based solid-state storage systems, powerful correction algorithms (such as low-density parity) are used. Checksum (LDPC)) has become critical.

For the strategy of suppressing the error rate without relying on the error correction code to study the error characteristics of NAND flash memory, redundant backup technology is an effective measure to improve the error rate of the storage system. RAID (Redundant Array of Indepent Disks) technology is in the flash storage system It is widely used to increase the redundant data to extend the data retention time, reduce the error rate and improve the reliability of the storage system. At the same time, considering that due to the mixing of "hot data" blocks and "cold data" blocks, which may cause very high costs, a method of separating "hot data" blocks and "cold data" is carried out. There is also the advantage of combining redundant backup and cold and hot data separation to improve the durability and reliability of the system.

Although the prior art reduces the error rate of data storage to a certain extent and improves the reliability of the three-dimensional flash memory storage system, there are still problems such as low space utilization, low practicability, and high hardware cost.

Summary of the invention

The technical problem to be solved by the present invention is to provide an error page identification method based on the three-dimensional flash memory storage structure, called error page identification technology, which can accurately identify the error rate of all physical pages in the current three-dimensional flash memory storage system, and can effectively improve Reliability of 3D flash storage system. The basic storage unit of 3D flash memory storage system is mainly based on TLC as the storage medium. Compared with SLC and MLC, TLC has the worst reliability and service life due to its own structural characteristics. The reading speed of all physical pages in the OCSSD structure of the three-dimensional flash memory storage system characterizes the error rate of the physical page. The machine learning method is used to classify the reliability of all physical pages. The lower the level, the higher the error rate. The physical pages with high error rates are removed for real-time data migration, thereby effectively reducing the error rate and achieving the purpose of improving the reliability of the 3D flash memory storage system.

In order to solve the above technical problems, the present invention provides an error page identification method based on a three-dimensional flash memory storage structure, including:

Data collection: When the user space is working under different workloads, the data of the read speed of each physical page is collected, and the load characteristics of the current work are collected at the same time;

Error page detection: According to the current speed and the initial speed of the current reading speed of each physical page, the reliability of all physical pages is divided into five categories from high to low, and one of the two types of physical pages with a relatively high error rate Signs with higher error rates;

Real-time data migration: modify the basic command copyback operation of NAND flash at the MTD layer, without modifying other software and hardware other than the MTD layer; use the copyback operation to specify the target address for programming operations.

In one of the embodiments, the read speed includes the initial speed of the physical page, the current speed of the physical page, and the overall average speed of the flash memory.

In one of the embodiments, the load characteristics of the current work include random requests and sequential requests.

In one of the embodiments, if the current speed of the physical page is already greater than the overall average speed, there is no need to perform identification with a higher error rate.

In one of the embodiments, the reliability of all physical pages is classified into five categories from high to low: Best, Good, Normal, Weak, and Worst.

In one of the embodiments, the copyback operation includes a copyback read instruction and a copyback programming instruction.

In one of the embodiments, two types of physical pages with high error rates are stored in the list, and the real-time data migration operation is performed on them during the idle time of the storage system.

In one of the embodiments, the copy target address of the physical page with the highest error rate is released to the NAND flash memory controller; the next physical page with the next highest error rate can be loaded into the NAND flash memory controller at the same time.

Based on the same inventive concept, this application also provides a computer device, including a memory, a processor, and a computer program stored in the memory and capable of running on the processor. When the processor executes the program, any item is implemented. The steps of the method.

Based on the same inventive concept, the present application also provides a solid-state hard disk, which applies an error page recognition method based on a three-dimensional flash memory storage structure.

Based on the same inventive concept, this application also provides a computer including the solid-state hard disk.

The beneficial effects of the present invention:

The present invention can efficiently identify physical pages with a higher error rate, and combine the machine learning algorithms to classify the physical pages in the current three-dimensional flash memory storage system. While reducing the error rate of the 3D flash memory storage system, the copyback operation used in the real-time data migration operation is performed to improve the response time of the system.

Description of the drawings

FIG. 1 is a diagram of the overall structure of error page identification in the error page identification method based on the three-dimensional flash memory storage structure of the present invention.

Fig. 2 is a schematic diagram of a data collection strategy in the error page identification method based on the three-dimensional flash memory storage structure of the present invention.

FIG. 3 is an error page detection model in the error page identification method based on the three-dimensional flash memory storage structure of the present invention.

FIG. 4 is a schematic diagram of real-time data migration in the error page identification method based on the three-dimensional flash memory storage structure of the present invention.

FIG. 5 is an example diagram of an error page identification method in the error page identification method based on the three-dimensional flash memory storage structure of the present invention.

Detailed ways

The present invention will be further described below with reference to the accompanying drawings and specific embodiments, so that those skilled in the art can better understand and implement the present invention, but the examples cited are not intended to limit the present invention.

In order to improve the reliability of the 3D flash memory storage system, the problem of increased error rate is particularly obvious. Taking Open-Channel SSD (OCSSD) as an example in the 3D flash storage system, it moves the Flash Translation Layer (FTL) in the flash storage structure to the Host side, and uses the dedicated interface PPA (Physical Page Address) I/O The interface directly exposes the physical structure information of the bottom device to the upper user space. The underlying physical information is known before the underlying device is used in the upper space. However, under the traditional flash storage system structure, it is impossible to obtain the underlying device information exactly. You can only operate on the logical address and cannot read the physical address information. Therefore, under the OCSSD structure, the error rate can be accurately identified through the physical page read speed of the flash memory storage system. At the same time, the structure can also meet the requirements of the machine learning algorithm for the amount of calculation and the calculation rate.

This patent proposes a method for identifying error pages, which is a strategy for enhancing system reliability. The physical page read speed of the OCSSD structure of the three-dimensional flash memory storage system is used to characterize the physical page error rate. The slower the read speed of the physical page, the higher the error rate, otherwise, vice versa. The machine learning method is used to classify the reliability levels of all physical pages, and the physical pages with high error rates are removed for real-time data migration, which reduces the error rate and improves the reliability of the 3D flash memory storage system.

As shown in the overall scheme of error page recognition in Figure 1, we propose an effective error recognition management unit design on the host side, which works with the file system and FTL. Three strategies are adopted to realize error rate identification and real-time data migration for each physical page in the 3D flash memory storage system:

(1) Data collection, as shown in Figure 2, when the user space is working under different workloads, the read speed of each physical page (the initial speed of the physical page, the current speed of the physical page, and the overall average speed of the flash memory) Data is collected, and the load characteristics of the current work (random request or sequential request) are collected at the same time.

(2) Error page detection, input the collected data into the machine learning training model shown in Figure 3. According to the current speed and initial speed of the current reading speed of each physical page, the reliability level of all physical pages is changed from High to low is divided into five categories (Best, Good, Normal, Weak, and Worst). Among them, the physical pages of Weak and Worst have a relatively high error rate, which means that they have exceeded the error correction code. The scope of capability is the problem of the increase in error rate in the 3D flash memory storage system. Therefore, we need to identify these two types of physical pages with a higher error rate. However, taking into account issues such as excessive resource power consumption and system delay caused by excessive operations, if the current speed of the physical page is already greater than the overall average speed, there is no need to perform identification with a higher error rate.

(3) Real-time data migration, modify the basic command copyback operation of NAND flash at the MTD (Memory Technology Device) layer, without the need to modify other software and hardware other than the MTD layer. Use copyback operation to include two parts of read operation and programming operation, you can specify the target address for programming operation. As shown in Figure 4, two types of physical pages with high error rates are stored in the list, and real-time data migration operations are performed on them when the storage system is idle. Release the target address of the copy of the physical page with the highest error rate (for example, page2#) to the NAND flash memory controller. The next physical page with the next highest error rate (eg page4) can be loaded into the NAND flash controller at the same time. After waiting for the end of page2# programming, continue with other operations of page4 programming, which reduces page read and write operations during the rewriting process, improves the I/O performance of the storage system and reduces storage system consumption.

Figure 5 shows an example of the error page identification method. In this example, we assume that there are two channels (Channel0 and Channel1) in the three-dimensional flash memory storage system OCSSD, each channel has 1 Plane, and each Plane has 4 Physical blocks (Block0, Block1, Block2, and Block3), each block has n physical pages (Page0, Page1...Pagen). First of all, the need is to collect the read speed data of all physical pages in the 3D flash memory system, mainly the data collection of the read speed of a physical page (the initial speed of the physical page, the current speed of the physical page and the average speed of the flash memory as a whole) ; Then, the collected data is divided into five categories (Best, Good, Normal, Weak, and Worst) through the training model, and physical pages with higher error rates are identified. The physical pages referred to here are Weak and Worst with higher error rates; Finally, using the copyback operation method, in idle time, the identified physical pages are stored in a list and sorted according to the error rate, and the data migration operation is performed first with the highest error rate. The page2 with the highest error rate currently shown in FIG. 5 will require a copy of the physical page with the highest error rate (for example, page2#) to perform a copyback operation in the storage register. page2# is released to the NAND flash memory controller at the specified target address, and the next page4 with the next highest error rate can be loaded into the NAND flash memory controller at the same time. After waiting for the end of page2# programming, continue with other operations of page4 programming, which reduces page read and write operations during the rewriting process, improves the I/O performance of the storage system and reduces the consumption of the storage system.

The error page recognition method based on the three-dimensional flash memory storage structure provided by the present invention has been described in detail above, and the following points need to be explained:

Based on the three-dimensional flash storage system structure, that is, the OCSSD structure, it can accurately identify the physical page with a higher error rate through the physical page read speed of the flash storage system. At the same time, the structure can meet the calculation and calculation requirements of the machine learning algorithm. Speed requirements and real-time data migration methods using copyback operations. The error page identification method proposed by the present invention effectively identifies physical pages with a higher error rate, and performs real-time data migration operations on them, thereby improving the reliability of the overall system and the system response time.

The above-mentioned embodiments are only preferred embodiments for fully explaining the present invention, and the protection scope of the present invention is not limited thereto. Equivalent substitutions or alterations made by those skilled in the art on the basis of the present invention are all within the protection scope of the present invention. The protection scope of the present invention is subject to the claims.

Claims

An error page identification method based on a three-dimensional flash memory storage structure, which is characterized in that it includes:

Data collection: When the user space is working under different workloads, the data of the read speed of each physical page is collected, and the load characteristics of the current work are collected at the same time.

Error page detection: According to the current speed and the initial speed of the current reading speed of each physical page, the reliability of all physical pages is divided into five categories from high to low, and one of the two types of physical pages with a relatively high error rate Signs with higher error rates;

Real-time data migration: The basic command copyback operation to modify the NANDflash at the MTD layer does not need to modify other software and hardware other than the MTD layer; use the copyback operation to program the target address.
The method for identifying error pages based on a three-dimensional flash memory storage structure according to claim 1, wherein the read speed includes the initial speed of the physical page, the current speed of the physical page, and the overall average speed of the flash memory.
The method for identifying error pages based on a three-dimensional flash memory storage structure according to claim 1, wherein the load characteristics of the current work include random requests and sequential requests.
The method for identifying error pages based on a three-dimensional flash memory storage structure as claimed in claim 1, wherein if the current speed of the physical page is already greater than the overall average speed, there is no need to perform identification with a higher error rate.
The method for identifying error pages based on a three-dimensional flash memory storage structure according to claim 1, wherein the reliability of all physical pages is divided into five categories from high to low: Best, Good, Normal, Weak, and Worst.
The method for identifying error pages based on a three-dimensional flash memory storage structure according to claim 1, wherein the copyback operation includes a copyback read command and a copyback programming command.
The method for identifying error pages based on a three-dimensional flash memory storage structure according to claim 1, wherein the two types of physical pages with high error rates are stored in the list, and the physical pages are processed in real time when the storage system is idle. Data migration operation.
The error page identification method based on the three-dimensional flash memory storage structure of claim 7, wherein the copy target address of the physical page with the highest error rate is released to the NAND flash memory controller; the next physical page with the second highest error rate can be Simultaneously load into the NAND flash memory controller.
A solid-state hard disk, characterized by applying the error page identification method based on a three-dimensional flash memory storage structure according to any one of claims 1 to 8.
A computer, characterized by comprising the solid-state hard disk according to claim 9.