WO2021129755A1 - 时钟时间同步方法、装置、设备和存储介质 - Google Patents

时钟时间同步方法、装置、设备和存储介质 Download PDF

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Publication number
WO2021129755A1
WO2021129755A1 PCT/CN2020/139083 CN2020139083W WO2021129755A1 WO 2021129755 A1 WO2021129755 A1 WO 2021129755A1 CN 2020139083 W CN2020139083 W CN 2020139083W WO 2021129755 A1 WO2021129755 A1 WO 2021129755A1
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Prior art keywords
time
signal
slave
master
delay
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PCT/CN2020/139083
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English (en)
French (fr)
Inventor
魏新建
乔海军
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中兴通讯股份有限公司
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Publication of WO2021129755A1 publication Critical patent/WO2021129755A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0682—Clock or time synchronisation in a network by delay compensation, e.g. by compensation of propagation delay or variations thereof, by ranging
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0658—Clock or time synchronisation among packet nodes
    • H04J3/0661—Clock or time synchronisation among packet nodes using timestamps

Definitions

  • This application relates to a wired communication network, and in particular to a clock time synchronization method, device, system and storage medium.
  • the synchronization method of the existing clock time in the communication network is mainly based on the PTP1588 technology.
  • One of the two connected nodes is used as the master node and the other is used as the slave node.
  • the slave node synchronizes the clock of the master node, and the same clock is used between the nodes.
  • the master and slave nodes communicate through 1588 messages to send and receive data packets to achieve clock time synchronization between nodes.
  • This clock time synchronization method consumes time when 1588 messages are transmitted between the master node and the slave node.
  • the clock time synchronization is performed, the master There is a time difference between the slave nodes, and the accuracy of the clock time is poor.
  • the synchronization time is prone to sudden changes, which will affect the business.
  • This application provides a clock time synchronization method, device, equipment and storage medium.
  • the embodiment of the present application provides a clock time synchronization method, which is applied to a master node, and includes: sending a delay determination signal to a signal transceiver port in a slave node; obtaining a delay feedback signal from the slave node; The feedback signal and the time delay determination signal determine the master-slave time difference; send the master-slave time difference to the slave node, and perform clock time synchronization with the slave node according to the master-slave time difference.
  • the embodiment of the present application provides a clock time synchronization method applied to a slave node, including: receiving a delay determination signal from a signal transceiver port in the master node; sending a delay feedback signal to the master node; receiving the master node The master-slave time difference determined according to the time delay determination signal and the time delay feedback signal, and clock time synchronization with the master node according to the master-slave time difference.
  • the embodiment of the application provides a clock and time synchronization device, which is applied to a master node, and includes: an information sending module for sending a delay determination signal to a signal receiving and sending port in a slave node; a signal receiving module for slave The node obtains the delay feedback signal; the delay determination module is used to determine the master-slave time difference according to the delay feedback signal and the delay determination signal; the clock synchronization module is used to send the master-slave time difference to the slave And synchronize the clock time with the slave node according to the master-slave time difference.
  • the embodiment of the application provides a clock time synchronization device, which is applied to a slave node, and includes: a signal receiving module for receiving a delay determination signal from a signal transceiver port in the master node; a signal feedback module for sending a signal to the master node The node sends a delay feedback signal; a clock synchronization module is used to receive the master-slave time difference determined by the master node according to the delay determination signal and the delay feedback signal, and according to the master-slave time difference and the master node Perform clock time synchronization.
  • the embodiment of the present application provides a device, including: one or more processors; a memory, used to store one or more programs; when the one or more programs are executed by the one or more processors, so that The one or more processors implement the clock time synchronization method described in any of the embodiments of the present application.
  • An embodiment of the present application provides a computer-readable storage medium on which a computer program is stored, where the program is executed by a processor to implement the clock time synchronization method described in any of the embodiments of the present application.
  • FIG. 1 is a flowchart of a clock time synchronization method provided by an embodiment of the present application
  • Figure 2 is a topological structure diagram of a network element provided by an embodiment of the present application.
  • FIG. 3 is a flowchart of a clock time synchronization method provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a master node provided by an embodiment of the present application.
  • FIG. 5 is an exemplary diagram of a clock time synchronization method provided by an embodiment of the present application.
  • Fig. 6 is a flowchart of a clock time synchronization method provided by an embodiment of the present application.
  • FIG. 7 is a flowchart of a clock time synchronization method provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a clock time synchronization device provided by an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a clock time synchronization device provided by an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a device provided by an embodiment of the present application.
  • FIG. 1 is a flowchart of a clock time synchronization method provided by an embodiment of the present application.
  • the embodiment of the present application may be applicable to the case of synchronizing the clock time of a network element in a communication network.
  • the method may be implemented by the clock time synchronization apparatus in the embodiment of the present application.
  • the device can be implemented by software and/or hardware, and can generally be integrated in the master node of the network element device.
  • the clock time synchronization method of the embodiment of the present application includes:
  • Step 101 Send a delay determination signal to the signal transceiver port in the slave node.
  • the master node may be a network element node that sends clock time during clock synchronization
  • the slave node may be a network element node that receives clock time during clock synchronization.
  • the master node and the slave node may be connected in a wired or wireless manner.
  • Figure 2 is a topology diagram of a network element provided by an embodiment of the present application. Referring to Figure 2, when network element A sends the clock time to network element B for clock synchronization, network element A can be the master node, and network element B It can be a slave node; when the network element B sends the clock time to the network element C for clock synchronization, the network element B can be the master node, and the network element C can be the slave node.
  • the information transceiving port can be a port that receives signals in the slave node, for example, it can be an optical monitoring port on an interface board in a network element, and the master node can send a delay determination signal to the signal transceiving port of the slave node to obtain The internal time error between the master node and the slave node, where the delay determination signal may be a service signal transmitted between the master node and the slave node, for example, a GE optical signal or a 10GE signal, etc.
  • the delay determination signal may be in the master node.
  • the transfer between the node and the slave node can be used to determine the internal time error of the network element such as the master node and the slave node.
  • Step 102 Obtain a time delay feedback signal from the slave node.
  • the delay feedback signal can be a service signal sent from the node to the master node, for example, a GE optical signal or a 10GE signal, etc.
  • the delay feedback signal can include custom-encoded TOD information, and the TOD information can be delayed by Determine the transmission time and reception time of the signal and the transmission time and reception time of the delay feedback information.
  • the delay feedback signal may include the reception time of the delay determination information at the slave node and the transmission time of the delay feedback signal at the slave node. .
  • the delay feedback signal sent by the slave node can be obtained, for example, the optical monitoring port in the interface board of the slave node can be monitored, and the delay feedback signal sent by the slave node can be obtained.
  • Step 103 Determine a master-slave time difference according to the time delay feedback signal and the time delay determination signal.
  • the master-slave time difference may be the error time between the clocks of the master node and the slave node
  • the master-slave time difference may be the time deviation between the master node and the slave node due to transmission processing within the network element node
  • the time spent in the master node and the time spent in the slave node can be determined according to the time delay feedback signal and the time delay to determine the signal reception time and transmission time, so that the master and slave nodes are performing clock synchronization.
  • Reduce time deviation caused by internal time consumption It can parse the delay determination signal, obtain the message transmission time and message reception time of the master node in the delay determination signal, analyze the delay feedback signal, and obtain the message transmission time and message reception time in the slave node.
  • the message sending time and message receiving time of the node and the slave node determine the internal time deviation of the message sent and received by the master node and the internal time deviation of the message sent and received by the slave node, which is determined by the above deviation
  • Step 104 Send the master-slave time difference to the slave node, and perform clock time synchronization with the slave node according to the master-slave time difference.
  • the master node can send the master-slave time difference to the slave node, and the slave node can compensate the local clock time of the slave node according to the master-slave time difference.
  • the time of the slave node’s local clock can be added to the master-slave time difference as The new time can also be compensated by the master node during clock synchronization, and the slave node can use the acquired clock time as the clock time of the slave node.
  • the delay determination signal is sent to the slave node, and the delay feedback signal of the slave node is obtained, and the master node and the slave node are determined by the delay determination signal and the delay feedback information.
  • Time difference according to the master-slave time difference to synchronize the clock, reduce the time error caused by the time consumption during internal transmission, improve the accuracy of the clock time, solve the problem of time sudden change caused by the change of node status, and enhance the stability of the business .
  • FIG. 3 is a flowchart of a clock time synchronization method provided by an embodiment of the present application.
  • the master node in the embodiment of the present application uses the clock at the interface board as a standard to determine the master-slave time difference of data, see FIG. 3, the clock time synchronization method of the embodiment of the present application includes:
  • Step 201 Determine the signal transceiving port according to the board number and port number of the slave node.
  • the slave node can include interface boards, main control boards and service boards.
  • the number of the single board can identify the information of the interface board, the main control board and the service board.
  • the interface board can include one or more optical monitoring ports, and the port number can be Identify different optical monitoring ports.
  • an optical monitoring port in the slave node can be determined in advance by means of a single board number and a port number, and this port can be used as an access point for the master node and the slave node to determine the master-slave time difference.
  • the port status flag can be automatically or artificially set in the optical monitoring port.
  • Step 202 Send the delay determination signal from the optical monitoring port of the interface board to the signal transceiving port.
  • the optical monitoring port of the interface board may be a port in the master node that sends a delay determination signal.
  • the master node can establish a connection from the optical port of the interface board to the predetermined signal transceiving port, and can send the delay determination signal to the transceiving port through the optical monitoring port of the interface.
  • FIG. 4 is a schematic structural diagram of a master node provided by an embodiment of the present application. Referring to FIG. 4, since the delay determination signal is generated in the master control, the delay determination signal is in the optical monitoring of the interface board in the master node. Port transmission, in order to reduce the error of the master-slave time difference, you can add a time stamp to the delay determination signal on the optical monitoring port of the interface board. The time of the time stamp can be the time of the FPGA in the interface board.
  • Step 203 Determine the first transmission time of the delay determination signal at the optical monitoring port of the interface board.
  • the first transmission time may be the time when the delay determination signal is sent from the optical monitoring port of the interface board of the master node.
  • the first transmission time may be added to the delay determination signal for transmission, and the first transmission time may also be stored in the master node. .
  • FIG. 4 is a schematic structural diagram of a master node provided by an embodiment of the present application.
  • the delay determination signal is generated in the master control, and the delay determination signal is in the interface board optical fiber of the master node.
  • a time stamp can be added to the delay determination signal on the optical monitoring port of the interface board.
  • the time of the time stamp can be the time of the FPGA in the interface board.
  • the determining the first transmission time of the delay determination signal at the optical monitoring port of the interface board includes: acquiring the delay determination signal and entering the signal processing device in the optical monitoring port of the interface board Obtain the first output clock phase output from the signal processing device of the delay determination signal; use the phase difference between the first output clock phase and the first input clock phase as the The delay determines the first transmission compensation time of the signal, and the first transmission time is determined according to the port clock of the optical monitoring port of the interface board and the first transmission compensation time.
  • the signal processing device can be, for example, a serdes, which can record the phase of the system clock of the master node when the delay determination signal enters the signal processing device as the first incoming clock phase, and can record the delay determination signal from the signal
  • the phase of the system clock output by the processing device is used as the first output clock phase
  • the phase difference between the first output clock phase and the first incoming clock phase can be calculated
  • the length of time corresponding to the phase difference can be used as the first processing delay determination signal.
  • the sending compensation time can be added to the first sending time obtained by the master node, and the real sending time of the signal can be determined by the sending delay in the master node.
  • Step 204 Receive the delay feedback signal sent by the signal transceiving port of the slave node through the optical monitoring port of the interface board.
  • the optical monitoring port of the interface board of the master node can monitor the transceiver port of the slave node.
  • the delay feedback in the transceiver port can be obtained.
  • the delay feedback signal may include the time when the delay determination information is received from the node.
  • Step 205 Determine the second receiving time of the delay feedback signal at the optical monitoring port of the interface board.
  • the second receiving time may be the time for the master node to receive the delay feedback signal, which may be determined by the FPGA in the interface board.
  • the master node when the master node receives the delay feedback signal, it can generate a time stamp to mark the second receiving time of the delay feedback signal, and the determination of the time stamp can be performed by the FPGA in the master node interface board. Further, since the delay feedback signal can only determine the message reception time after passing through the signal processing device of the optical monitoring port, the processing time can be determined by the clock phase difference between the input and output of the delay feedback signal from the signal processing device. The processing time is subtracted from the second receiving time to obtain the true second receiving time when the master node receives the delay feedback signal.
  • Step 206 Obtain the first sending time of the delay determination signal and the second receiving time of the delay feedback signal in the master node.
  • the first sending time and the second receiving time can be stored in the master node.
  • they can be stored in the FPGA of the interface board.
  • the first sending time and the second receiving time can be Sent by the interface board to the master control of the master node.
  • Step 207 Analyze the delay feedback signal to obtain the first reception time of the delay determination signal and the second transmission time of the delay feedback signal.
  • the delay feedback information may include the first receiving time and the second sending time at which the delay determination signal is received from the node. It can be understood that the first receiving time and the second sending time may be within the slave node. The time at the optical monitoring port of the interface board.
  • Step 208 Determine a master-slave time difference according to the first sending time, the first receiving time, the second sending time, and the second receiving time.
  • the difference between the first reception time and the first transmission time may be used as the transmission time of the delay determination signal, and the difference between the second reception time and the second transmission time may be used as the transmission time of the delay feedback signal
  • the transmission time error of the message between the master node and the slave node may not be considered.
  • single-fiber bidirectional transmission can be used to ensure that the data transmission time of the master node and the slave node are the same, and the delay can be determined by the signal
  • the average value of the transmission time and the transmission time of the delay feedback signal is regarded as the master-slave time difference.
  • Step 209 Send the master-slave time difference to the slave node, and perform clock time synchronization with the slave node according to the master-slave time difference.
  • the master-slave time difference is encapsulated into a transmission signal in a preset format; the transmission signal is sent to the slave node, so that the slave node synchronizes clock time according to the master-slave time difference.
  • the master-slave time difference can be encapsulated in a preset format, for example, it can be encapsulated as TOD information, and each TOD information can include 4 time information, which can be the first sending time, the first receiving time, For the second sending time and the second receiving time, each time information is 10 bytes, 2 CRCs, and 8 bytes reserved information.
  • the TOD information can be sent 1000 times or more per second so that the master node and the slave node can obtain the time error inside the network element in time, so that the slave node can realize the accurate time synchronization between the master node and the slave node according to the master-slave time difference.
  • the signal transceiver port is determined by obtaining the board number and port number of the slave node, and the delay determination signal is sent from the optical monitoring port of the receiving board to the information transceiver port, and the delay determination signal is determined to be on the interface board.
  • the first sending time of the optical monitoring port determining the second receiving time of the delay feedback signal at the optical monitoring end of the interface board, analyzing the delay feedback signal to obtain the first receiving time of the delay determining signal and the delay feedback signal
  • Time synchronization realizes precise synchronization of clock time, reduces errors caused by transmission path asymmetry, and improves business stability.
  • FIG. 5 is an example diagram of a clock time synchronization method provided by an embodiment of the present application.
  • the delay feedback signal may be, for example, a GE signal 0, which can recover the processed GE from the optical monitoring port of the interface board.
  • Signal 0 is modified, adding custom-coded TOD signal 1, which can periodically send TOD signals to 1000 times or higher frequency TOD information per second.
  • Each TOD information can include 4 time information, which can be respectively time
  • the delay determines the sending time and receiving time of the signal and the sending time and receiving time of the delay feedback signal.
  • Each time information is 10 bytes, 2 CRCs, and 8 bytes of reserved information, which are generated from the number 5 in Figure 5 Define the coded TOD information.
  • Serdes pins can be introduced for GE signals
  • reference clock 2 can use 250M system clock
  • FPGA serdes can extract 125M CDR clock from the connected GE signal 0 and divide the frequency and send it to the SEC chip as possible clock source 4, and measure at the same time
  • the phase difference between the 250M system clock 2 and the 125M CDR clock 4 (the phase difference of the clock edge ⁇ p) is obtained.
  • the phase relationship between the system clock 2 and the edge of the GE signal sent by the FPGA is measured, and the serdes input pin 5 is measured at the same time.
  • the delay from the GE signal 0 to the received internal GE signal 6, and the delay from the transmitted GE signal 8 to the GE signal 7 of the serdes output pin is measured.
  • GE_RX_DATA represents the sampled GE signal
  • a RX_GE_OFFSET signal is generated to represent the actual position of the GE signal relative to The deviation value of the rising edge of RX_GE_CLK.
  • RX_GE_CLK adds normal signal to get 125M clock equal to GE recovered clock.
  • the logic calculates the phase difference between RX_GE_CLK and the 250M system clock, and at the same time, the phase difference between the GE signal and the 250M system clock can be calculated according to RX_GE_OFFSET.
  • FIG. 6 is a flowchart of a clock time synchronization method provided by an embodiment of the present application.
  • the embodiment of the present application may be applicable to the case of synchronizing the clock time of a network element in a communication network.
  • the method may be implemented by the clock time synchronization apparatus in the embodiment of the present application.
  • the device can be implemented by software and/or hardware, and can generally be integrated in a slave node of a network element device.
  • the clock time synchronization method of the embodiment of the present application includes:
  • Step 301 Receive a delay determination signal from the signal transceiving port in the master node.
  • the signal transceiver port can be an optical monitoring port in the interface board of the master node, which can be pre-identified with the slave node through the board number and port number.
  • the slave node and the master node send and receive signals, it can be pre-identified The signal is sent and received through the port.
  • the slave node may monitor the signal transceiving port and obtain the delay determination signal sent by the master node through the signal transceiving port, where the delay determination signal may be used to determine the communication delay between the master node and the slave node.
  • Step 302 Send a delay feedback signal to the master node.
  • the slave node can also send a delay feedback signal to the master node, which can be used to determine the transmission time from the slave node to the master node. It is understood that the slave node can determine the delay after receiving the delay sent by the master node. After the signal is sent, the delay feedback signal is sent to the master node, and the delay feedback signal may include the time when the slave node sends the delay feedback signal.
  • Step 303 Receive the master-slave time difference determined by the master node according to the time delay determination signal and the time delay feedback signal, and perform clock time synchronization with the master node according to the master-slave time difference.
  • the slave node can receive the master node to determine the signal based on the delay and the delay feedback signal.
  • the master-slave time difference is due to the time consumed by the internal processing of the signal by the network element node, and there is a deviation between the synchronized clock time and the real clock time.
  • the delay determination signal and the delay feedback signal respectively determine the time error of the signal processed by the internal processing of the master node and the slave node.
  • the internal time deviation causes the time difference between the master and slave nodes, which can be determined by the delay determination signal and the delay feedback signal
  • the master-slave time difference for example, the master-slave time difference determined by the master node can be used for clock synchronization, and the master-slave time difference can be supplemented on the basis of the clock time sent by the master node, for example, the clock time is added or subtracted from the master
  • the slave time difference is used as the clock time of the slave node.
  • the technical solution of the embodiment of the present application receives the delay determination signal from the signal transceiver port of the master node, sends the delay feedback signal to the master node, and receives the master-slave determined by the master node according to the delay determination signal and the delay feedback signal Time difference, and synchronize the clock with the master node according to the master-slave time difference, which realizes the high-precision synchronization of the clock time of the master node and the slave node, reduces the error caused by the time consumption during internal transmission, and can enhance the stability of the business.
  • FIG. 7 is a flowchart of a clock time synchronization method provided by an embodiment of the present application.
  • the clock time for determining the master-slave time difference is specified.
  • the clock time synchronization method of the embodiment of the present application includes:
  • Step 401 Obtain the board number and port number of the master node.
  • an optical monitoring port in the master node can be determined in advance by a board number and a port number, and the port can be used as an access point for the master node and the slave node to determine the master-slave time difference.
  • Step 402 Use the optical monitoring port corresponding to the board number and the port number in the master node as a signal transceiving port.
  • the corresponding interface board in the master node can be found according to the board number, and the corresponding optical monitoring port can be determined in the found interface board according to the port number.
  • the optical monitoring port can be used as the master node and the slave node.
  • the signal transceiving port for signal transmission, and the slave node can monitor the signal transceiving port to obtain communication signals.
  • Step 403 Receive the delay determination signal sent by the signal transceiving port.
  • the slave node may monitor the signal transceiver port on the interface board of the master node, and obtain the delay determination signal sent by the master node, where the delay determination signal may include the optical monitoring port in the master node Time of sending.
  • Step 404 Determine the first receiving time for receiving the delay determination signal from the optical monitoring port of the interface board of the node.
  • the optical monitoring port of the interface board of the slave node can receive the delay determination signal sent by the master node.
  • the slave node receives the delay determination signal, it can determine the first receiving time according to the clock at the interface board of the slave node.
  • the first receiving time may be the time when the delay determination signal is received by the slave node.
  • the determining the first receiving time for receiving the delay determination signal from the optical monitoring port of the interface board of the node includes: acquiring the delay determination signal and entering it into the optical monitoring port of the interface board for signal processing The second input clock phase of the device; the second output clock phase output from the signal processing device of the delay determination signal is acquired; the phase difference between the second output clock phase and the second input clock phase is taken as the phase difference between the second output clock phase and the second input clock phase
  • the time delay determines the first receiving compensation time of the signal, and the first receiving time is determined according to the port clock of the optical monitoring port of the interface board and the first receiving compensation time.
  • the signal processing device may be, for example, a serdes, which can record the phase of the system clock of the slave node when the delay determination signal enters the signal processing device as the second incoming clock phase, and it can record the delay determination signal from the signal
  • the phase of the system clock output by the processing device is used as the second output clock phase
  • the phase difference between the second output clock phase and the second incoming clock phase can be calculated
  • the time length corresponding to the phase difference can be used as the slave node processing delay determination signal
  • the first receiving compensation time may be subtracted from the first receiving time obtained by the master node, and the real receiving time of the signal may be determined from the receiving time delay from the node.
  • Step 405 Send the delay feedback signal from the optical monitoring port of the interface board to the signal transceiving port.
  • the delay feedback signal may be a signal to determine the signal transmission time from the node to the master node.
  • the delay feedback signal may be sent to the master node by the optical monitoring port of the interface board of the slave node, and the master node may receive it through the signal transceiver port Time delay feedback signal.
  • Step 406 Determine the second sending time of the delay feedback signal at the optical monitoring port of the interface board.
  • the second sending time of the optical monitoring port of the interface board can be determined.
  • the second sending time can be, for example, the clock time from the interface board of the node. Further, the second sending time may be added to the delay feedback signal in the form of time stamp information and sent together, or the second sending time may be sent separately to the master node.
  • the determined delay feedback signal sending time is earlier than the time of sending the delay feedback signal from the slave node, and the delay feedback signal can be passed through the delay feedback.
  • the clock phase difference between the input and output of the signal from the signal processing device determines the processing time, and the processing time can be added to the second sending time to obtain the real time when the delay feedback signal is sent from the node.
  • Step 407 Receive the master-slave time difference determined by the master node according to the time delay determination signal and the time delay feedback signal, and perform clock time synchronization with the master node according to the master-slave time difference.
  • the slave node can receive the master node to determine the signal based on the delay and the delay feedback signal.
  • the master-slave time difference due to the asymmetry of the communication and transmission between the master node and the slave node, the signal and the delay can be determined by the delay
  • the feedback signal respectively determines the communication delay of the signal from the master node to the slave node and the communication delay of the signal from the slave node to the master node.
  • the master-slave time difference can be determined at the master node through the communication delay in the two directions. When the clock time of the node is synchronized, it can be compensated based on the master-slave time difference based on the clock time sent by the master node.
  • the optical monitoring port in the master node is determined as the signal transceiver port according to the board number and port number, and the delay determination signal sent by the signal transceiver port is received, And determine the first receiving time to receive the delay determination signal, send the delay feedback signal to the master node, and determine the second transmission time to send the delay feedback signal, the receiving master node determines the signal and the delay feedback according to the delay
  • the master-slave time difference determined by the signal, and the clock time synchronization is performed according to the master-slave time difference, which realizes the high-precision synchronization of the clock time of the master node and the slave node, reduces the time error caused by the internal signal processing and transmission of the network element, and can improve the service The stability.
  • FIG. 8 is a schematic structural diagram of a clock time synchronization device provided by an embodiment of the present application.
  • the embodiment of the present application can be applied to the case of network element clock time synchronization.
  • the clock time synchronization method provided by any embodiment of the present application can be executed, and it can execute The corresponding functional modules and beneficial effects of the method.
  • the device can be implemented by software and/or hardware, and can be integrated in the master node of the network element. Referring to FIG. 8, the device in the embodiment of the present application includes: an information sending module 501, a signal receiving module 502, a delay determining module 503, and a clock Synchronization module 504.
  • the information sending module 501 is configured to send a delay determination signal to the signal transceiver port in the slave node.
  • the signal receiving module 502 is configured to obtain a delay feedback signal from the slave node.
  • the time delay determining module 503 is configured to determine the master-slave time difference according to the time delay feedback signal and the time delay determination signal.
  • the clock synchronization module 504 is configured to send the master-slave time difference to the slave node, and perform clock time synchronization with the slave node according to the master-slave time difference.
  • the delay determination signal is sent to the slave node through the information sending module, the signal receiving module obtains the delay feedback signal of the slave node, and the delay determination module determines the master through the delay determination signal and the delay feedback information.
  • the clock synchronization module performs time synchronization according to the master-slave time difference, which reduces the time difference caused by the time uncertainty inside the master node, improves the accuracy of the clock time, and can solve the problem of node status changes.
  • the problem of sudden changes in time has enhanced the stability of the business.
  • the device of the embodiment of the present application further includes: a port determination module, configured to determine the signal receiving and sending port according to the board number and the port number of the slave node.
  • the information sending module 501 includes: a signal sending unit, configured to send the delay determination signal from the optical monitoring port of the interface board to the signal transceiver port; a sending time unit, configured to determine the delay Determine the first sending time of the signal at the optical monitoring port of the interface board.
  • the sending time unit is used to: obtain the first incoming clock phase of the time delay determination signal entering the signal processing device in the optical monitoring port of the interface board; to obtain the time delay determination signal from the signal processing The first output clock phase output by the device; the phase difference between the first output clock phase and the first incoming clock phase is used as the first transmission compensation time of the delay determination signal, according to the optical monitoring port of the interface board
  • the port clock of and the first sending compensation time determine the first sending time.
  • the signal receiving module 502 includes: a signal receiving unit, configured to receive the delay feedback signal sent by the signal transceiver port of the slave node through the optical monitoring port of the interface board; and a receiving time unit for Determine the second receiving time of the delay feedback signal at the optical monitoring port of the interface board.
  • the delay determination module 503 includes: a time acquisition unit configured to acquire the first transmission time of the delay determination signal and the second reception time of the delay feedback signal in the master node; a signal analysis unit , Used to analyze the time delay feedback signal to obtain the first reception time of the time delay determination signal and the second transmission time of the time delay feedback signal; and a master-slave time difference unit, configured to transmit according to the first The time, the first receiving time, the second sending time, and the second receiving time determine the master-slave time difference.
  • the clock synchronization module 504 includes: a signal packaging unit for encapsulating the master-slave time difference into a transmission signal in a preset format; and a signal sending unit for sending the transmission signal to the slave Node, so that the slave node synchronizes clock time according to the master-slave time difference.
  • FIG. 9 is a schematic structural diagram of a clock time synchronization device provided by an embodiment of the present application.
  • the embodiment of the present application may be applicable to the case of network element clock time synchronization, and the clock time synchronization method provided by any embodiment of the present application can be executed.
  • the device may be implemented by software and/or hardware, and may be integrated in the slave node of the network element. Referring to FIG. 9, the device in the embodiment of the present application includes: a signal receiving module 601, a signal feedback module 602, and a clock synchronization module 603.
  • the signal receiving module 601 is configured to receive the time delay determination signal from the signal receiving and sending port in the master node.
  • the signal feedback module 602 is configured to send a delay feedback signal to the master node.
  • the clock synchronization module 603 is configured to receive the master-slave time difference determined by the master node according to the time delay determination signal and the time delay feedback signal, and perform clock time synchronization with the master node according to the master-slave time difference.
  • the signal receiving module receives the delay determination signal from the signal transceiver port of the master node, the signal feedback module sends the delay feedback signal to the master node, and the clock synchronization module receives the master node according to the delay determination signal
  • the master-slave time difference determined by the delay feedback signal and the clock synchronization with the master node according to the master-slave time difference realizes the high-precision synchronization of the clock time of the master node and the slave node, reduces the error caused by the internal transmission time consumption, and can enhance The stability of the business.
  • the device provided by the embodiment of the present application further includes: a port determination module, configured to: obtain the board number and port number of the master node; and compare the board number and the port number in the master node The optical monitoring port corresponding to the port number is used as the signal receiving and sending port.
  • a port determination module configured to: obtain the board number and port number of the master node; and compare the board number and the port number in the master node The optical monitoring port corresponding to the port number is used as the signal receiving and sending port.
  • the signal receiving module 601 includes: a delay signal unit for receiving the delay determination signal sent by the signal transceiving port; and a delay time unit for determining reception from the optical monitoring port of the interface board of the node The time delay determines the first reception time of the signal.
  • the delay time unit is used to: obtain the second incoming clock phase of the delay determination signal into the signal processing device in the optical monitoring port of the interface board; and acquire the delay determination signal from the signal processing The second output clock phase output by the device; the phase difference between the second output clock phase and the second incoming clock phase is used as the first receiving compensation time of the delay determination signal, according to the optical monitoring port of the interface board
  • the port clock of and the first receiving compensation time determine the first receiving time.
  • the signal feedback module 602 includes: a feedback signal unit for sending the delay feedback signal from the optical monitoring port of the interface board to the signal transceiving port; and a feedback time unit for determining the time Delay the second sending time of the feedback signal at the optical monitoring port of the interface board.
  • the clock synchronization module 603 includes: a signal receiving unit for receiving a transmission signal in a preset format sent by the master node; a signal extraction unit for extracting the master-slave time difference in the transmission signal; and The clock synchronization unit is used to synchronize the local clock time of the slave node according to the master-slave time difference.
  • FIG. 10 is a schematic structural diagram of a device provided by an embodiment of the present application.
  • the device includes a processor 50, a memory 51, an input device 52, and an output device 53; the number of processors 50 in the device may be one Or more, one processor 50 is taken as an example in FIG. 10; the device processor 50, the memory 51, the input device 52, and the output device 53 may be connected by a bus or other means. In FIG. 10, the connection by a bus is taken as an example.
  • the memory 51 can be used to store software programs, computer-executable programs, and modules, such as the modules corresponding to the clock and time synchronization device in the embodiment of the present application (the information sending module 501, the signal receiving module 502, the time Delay determination module 503 and clock synchronization module 504, or signal receiving module 601, signal feedback module 602, and clock synchronization module 603).
  • the processor 50 executes various functional applications and data processing of the device by running the software programs, instructions, and modules stored in the memory 51, that is, realizes the above-mentioned clock time synchronization method.
  • the memory 51 may mainly include a program storage area and a data storage area.
  • the program storage area may store an operating system and an application program required by at least one function; the data storage area may store data created according to the use of the terminal, and the like.
  • the memory 51 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one magnetic disk storage device, a flash memory device, or other non-volatile solid-state storage devices.
  • the memory 51 may further include a memory remotely provided with respect to the processor 50, and these remote memories may be connected to the device through a network. Examples of the aforementioned networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.
  • the input device 52 can be used to receive inputted numeric or character information, and generate key signal input related to user settings and function control of the device.
  • the output device 53 may include a display device such as a display screen.
  • An embodiment of the present application also provides a storage medium containing computer-executable instructions, which are used to perform a clock time synchronization method when executed by a computer processor, and the method includes:
  • a storage medium containing computer-executable instructions provided by the embodiments of the present application and the computer-executable instructions are not limited to the method operations described above, and can also execute the clock time synchronization method provided in any embodiment of the present invention. Related operations.
  • the technical solution of the embodiment of the present application determines the time deviation between the master node and the slave node by sending the delay determination signal to the slave node, and obtains the delay feedback signal of the slave node, and synchronizes the time with the slave node according to the time deviation.
  • the time error caused by time consumption during internal transmission is reduced, the accuracy of the master node and slave node synchronization clock time can be improved, the time sudden change caused by the change of node status is solved, and the business impact is reduced.
  • the present invention can be implemented by software and necessary general-purpose hardware, of course, it can also be implemented by hardware, but in many cases the former is a better implementation.
  • the technical solution of the present invention essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as a computer floppy disk.
  • ROM Read-Only Memory
  • RAM Random Access Memory
  • FLASH Flash memory
  • hard disk or optical disk etc., including several instructions to make a computer device (which can be a personal computer) , A server, or a network device, etc.) execute the method described in each embodiment of the present application.
  • user terminal encompasses any suitable type of wireless user equipment, such as a mobile phone, a portable data processing device, a portable web browser, or a vehicle-mounted mobile station.
  • the various embodiments of the present application can be implemented in hardware or dedicated circuits, software, logic or any combination thereof.
  • some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software that may be executed by a controller, microprocessor, or other computing device, although the present application is not limited thereto.
  • Computer program instructions can be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source code written in any combination of one or more programming languages or Object code.
  • ISA instruction set architecture
  • the block diagram of any logic flow in the drawings of the present application may represent program steps, or may represent interconnected logic circuits, modules, and functions, or may represent a combination of program steps and logic circuits, modules, and functions.
  • the computer program can be stored on the memory.
  • the memory can be of any type suitable for the local technical environment and can be implemented using any suitable data storage technology, such as but not limited to read only memory (ROM), random access memory (RAM), optical storage devices and systems (digital multi-function optical discs) DVD or CD) etc.
  • Computer-readable media may include non-transitory storage media.
  • the data processor can be any type suitable for the local technical environment, such as but not limited to general-purpose computers, special-purpose computers, microprocessors, digital signal processors (DSP), application-specific integrated circuits (ASIC), programmable logic devices (FGPA) And processors based on multi-core processor architecture.
  • DSP digital signal processors
  • ASIC application-specific integrated circuits
  • FGPA programmable logic devices

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Abstract

本申请提出了一种时钟时间同步方法、装置、设备和存储介质，其中，该方法包括：向从节点内的信号收发端口发送时延确定信号；从所述从节点获取时延反馈信号；根据所述时延反馈信号和所述时延确定信号确定主从时间差；将所述主从时间差发送给所述从节点，并根据所述主从时间差与所述从节点进行时钟时间同步。

Description

时钟时间同步方法、装置、设备和存储介质
相关申请的交叉引用
本申请基于申请号为201911371412.5、申请日为2019年12月26日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此以引入方式并入本申请。
技术领域
本申请涉及有线通信网络，具体涉及一种时钟时间同步方法、装置、系统和存储介质。
背景技术
通信网络中现有时钟时间的同步方法主要基于PTP1588技术，相连接的两个节点一个作为主节点，一个作为从节点，正常情况下，从节点同步主节点的时钟，节点间等同使用同一时钟，主从节点通过1588报文进行通信以收发数据包而实现节点间的时钟时间同步，这种时钟时间同步方式1588报文在主节点和从节点内部传输时存在时间消耗，进行时钟时间同步时主从节点存在时间差，时钟时间的精度较差，节点状态变化时容易发生同步时间突变，对业务产生影响。
发明内容
本申请提供了一种时钟时间同步方法、装置、设备和存储介质。
本申请实施例提供了一种时钟时间同步方法，应用于主节点，包括：向从节点内的信号收发端口发送时延确定信号；从所述从节点获取时延反馈信号；根据所述时延反馈信号和所述时延确定信号确定主从时间差；将所述主从时间差发送给所述从节点，并根据所述主从时间差与所述从节点进行时钟时间同步。
本申请实施例提供了一种时钟时间同步方法，应用于从节点，包括：从主节点内的信号收发端口接收时延确定信号；向所述主节点发送时延反馈信号；接收所述主节点根据所述时延确定信号和所述时延反馈信号确定的主从时间差，并根据所述主从时间差与所述主节点进行时钟时间同步。
本申请实施例提供了一种时钟时间同步装置，应用于主节点，包括：信息发送模块，用于向从节点内的信号收发端口发送时延确定信号；信号接收模块，用于从所述从节点获取时延反馈信号；时延确定模块，用于根据所述时延反馈信号和所述时延确定信号确定主从时间差；时钟同步模块，用于将所述主从时间差发送给所述从节点，并根据所述主从时间差与所述从节点进行时钟时间同步。
本申请实施例提供了一种时钟时间同步装置，应用于从节点，包括：信号接收模块，用于从主节点内的信号收发端口接收时延确定信号；信号反馈模块，用于向所述主节点发送时延反馈信号；时钟同步模块，用于接收所述主节点根据所述时延确定信号和所述时延反馈信号确定的主从时间差，并根据所述主从时间差与所述主节点进行时钟时间同步。
本申请实施例提供了一种设备，包括：一个或多个处理器；存储器，用于存储一个或多个程序；当所述一个或多个程序被所述一个或多个处理器执行，使得所述一个或多个处理器实现如本申请实施例中任一所述的时钟时间同步方法。
本申请实施例提供了一种计算机可读存储介质，其上存储有计算机程序，其中，该程序被处理器执行时实现如本申请实施例中任一所述的时钟时间同步方法。
关于本申请的以上实施例和其他方面以及其实现方式，在附图说明、具体实施方式和权利要求中提供更多说明。
附图说明
图1是本申请实施例提供的一种时钟时间同步方法的流程图；
图2是本申请实施例提供的一种网元的拓扑结构图；
图3是本申请实施例提供的一种时钟时间同步方法的流程图；
图4是本申请实施例提供的一种主节点的结构示意图；
图5是本申请实施例提供的一种时钟时间同步方法的示例图；
图6是本申请实施例提供的一种时钟时间同步方法的流程图；
图7是本申请实施例提供的一种时钟时间同步方法的流程图；
图8是本申请实施例提供的一种时钟时间同步装置的结构示意图；
图9是本申请实施例提供的一种时钟时间同步装置的结构示意图；
图10是本申请实施例提供的一种设备的结构示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚明白，下文中将结合附图对本申请的实施例进行详细说明。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互任意组合。
图1是本申请实施例提供的一种时钟时间同步方法的流程图，本申请实施例可以适用于通信网络中同步网元时钟时间的情况，该方法可以由本申请实施例中的时钟时间同步装置来执行，该装置可以通过软件和/或硬件的方式实现，并一般可以集成在网元设备的主节点中，参见图1，本申请实施例的时钟时间同步方法包括：
步骤101、向从节点内的信号收发端口发送时延确定信号。
其中，主节点可以是进行时钟同步时发送时钟时间的网元节点，从节点可以是进行时钟同步时接收时钟时间的网元节点，主节点和从节点可以通过有线或者无线的方式进行连接。图2是本申请实施例提供的一种网元的拓扑结构图，参见图2，当网元A将时钟时间发送给网元B进行时钟同步时，网元A可以为主节点，网元B可以为从节点；当网元B将时钟时间发送给网元C进行时钟同步时，此时网元B可以为主节点，网元C可以为从节点。
在一个示例中，信息收发端口可以是从节点内接收信号的端口，例如可以是网元中接口板上的光监控端口，主节点可以向从节点的信号收发端口发送时延确定信号以获取到主节点和从节点节点内部的的时间误差，其中，时延确定信号可以是主节点和从节点之间传输的业务信号，例如可以是GE光信号或者10GE信号等，时延确定信号可以在主节点和从节点之间进行传递，可以用于确定主节点和从节点等网元内部的时间误差。
步骤102、从所述从节点获取时延反馈信号。
其中，时延反馈信号可以是从节点到主节点的发送的业务信号，例如可以是GE光信号或者10GE信号等，时延反馈信号内可以包括自定义编码的TOD 信息，TOD信息可以由时延确定信号的发送时间和接收时间以及时延反馈信息的发送时间和接收时间构成，时延反馈信号可以包括时延确定信息在从节点处的接收时间和时延反馈信号在从节点处的发送时间。
在本申请实施例中，可以获取从节点发送的时延反馈信号，例如可以对从节点的接口板内的光监控端口进行监听，获取到从节点发送的时延反馈信号。
步骤103、根据所述时延反馈信号和所述时延确定信号确定主从时间差。
其中，主从时间差可以是主节点与从节点时钟的误差时间，主从时间差可以是主节点和从节点由于在网元节点内部传输处理导致的时间偏差。
在一个示例中，可以根据时延反馈信号和时延确定信号接收时间和发送时间确定出报文分别在主节点内部消耗的时间和从节点内部消耗的时间，使得主从节点在进行时钟同步时减少内部时间消耗导致的时间偏差。可以解析时延确定信号，获取时延确定信号中主节点报文发送时间和报文接收时间，可以解析时延反馈信号，获取到从节点中报文发送时间和报文接收时间，可以通过主节点和从节点的报文发送时间和报文接收时间确定出中主节点发送报文和接收报文的内部时间偏差以及从节点发送报文和接收报文的内部时间偏差，通过上述偏差确定出主节点时钟时间与从节点时钟时间的主从时间差。
步骤104、将所述主从时间差发送给所述从节点，并根据所述主从时间差与所述从节点进行时钟时间同步。
在一个示例中，主节点可以将主从时间差发送给从节点，从节点可以根据主从时间差对从节点本地的时钟时间进行补偿，例如，可以将从节点本地时钟的时间加上主从时间差作为新的时间，也可以由主节点在进行时钟同步时，对同步的时钟时间进行补偿，从节点可以将获取到的时钟时间作为从节点的时钟时间。
本申请实施例的技术方案，通过向从节点发送时延确定信号，以及获取从节点的时延反馈信号，通过时延确定信号和时延反馈信息确定出主节点和从节点之间的主从时间差，根据主从时间差进行时钟同步，减小了内部传输时存在时间消耗导致的时间误差，提高了时钟时间的精确度，可解决节点状态改变带来的时间突变问题，增强了业务的稳定性。
图3是本申请实施例提供的一种时钟时间同步方法的流程图，为进一步提 高时钟时间的精度，本申请实施例中主节点以接口板处的时钟为标准确定数据的主从时间差，参见图3，本申请实施例的时钟时间同步方法包括：
步骤201、根据获取到所述从节点的单板编号和端口编号确定信号收发端口。
其中，从节点中可以包括接口板、主控板和业务板，单板编号可以标识接口板、主控板和业务板的信息，接口板上可以包括一个或多个光监控端口，端口编号可以标识不同的光监控端口。
在一个示例中，可以预先通过单板编号和端口编号的方式确定从节点中一个光监控端口，可以将该端口作为主节点和从节点进行主从时间差确定的接入点。示例性的，可以自动或者人为的在光监控端口中设置端口状态标记，当光监控端口中端口状态标记为1时，可以标识该光监控端口属于主节点，当光监控端口中端口状态标记为0时，可以标识该光监控端口属于从节点。
步骤202、将所述时延确定信号从接口板光监控端口发送到所述信号收发端口。
其中，接口板光监控端口可以是主节点内发送时延确定信号的端口。
在本申请实施例中，主节点可以从接口板光端口与预先确定的信号收发端口建立连接，可以将时延确定信号通过接口光监控端口发送到收发端口。进一步的，图4是本申请实施例提供的一种主节点的结构示意图，参见图4，由于时延确定信号在主控中生成，而时延确定信号又在主节点内的接口板光监控端口发送，为了减小主从时间差的误差，可以在接口板光监控端口为时延确定信号增加时间戳，时间戳的时间可以是接口板内FPGA的时间。
步骤203、确定所述时延确定信号在所述接口板光监控端口的第一发送时间。
其中，第一发送时间可以是时延确定信号从主节点的接口板光监控端口发送的时间，第一发送时间可以添加到时延确定信号中发送，第一发送时间也可以存储在主节点内。
在一个示例中，时延确定信号在接口板光监控端口发送时，可以生成该时延确定信号的时间戳，可以将该时间戳对应的时间作为延时确定信号的第一发送时间。示例性的，图4是本申请实施例提供的一种主节点的结构示意图，参 见图4，由于时延确定信号在主控中生成，而时延确定信号又在主节点内的接口板光监控端口发送，为了减小主从时间差的误差，可以在接口板光监控端口为时延确定信号增加时间戳，时间戳的时间可以是接口板内FPGA的时间。
一种实施方式中，所述确定所述时延确定信号在所述接口板光监控端口的第一发送时间，包括：获取所述时延确定信号进入所述接口板光监控端口中信号处理装置的第一进入时钟相位；获取所述时延确定信号从所述信号处理装置输出的第一输出时钟相位；将所述第一输出时钟相位和所述第一进入时钟相位的相位差作为所述时延确定信号的第一发送补偿时间，根据所述接口板光监控端口的端口时钟和所述第一发送补偿时间确定第一发送时间。
在本发明实施例中，由于网元内部中需要对接收到的时延确定信号进行处理，只有在处理后才能获取到报文准确的接收时间，因此需要对处理时延确定信号的时间进行补偿以提高时钟的精确度，其中，信号处理装置例如可以是serdes，可以记录时延确定信号进入信号处理装置时主节点的系统时钟的相位作为第一进入时钟相位，可以记录时延确定信号从信号处理装置输出的系统时钟的相位作为第一输出时钟相位，可以计算第一输出时钟相位与第一进入时钟相位的相位差，可以将该相位差对应的时间长度作为处理时延确定信号的第一发送补偿时间，可以在主节点获取到第一发送时间的基础上加上第一发送补偿时间，可以主节点中发送时延确定信号的真正发送时间。
步骤204、通过接口板光监控端口接收所述从节点所述信号收发端口发送的所述时延反馈信号。
在本申请实施例中，主节点的接口板光监控端口可以对从节点的收发端口进行监听，当从节点将时延反馈信号从收发端口发送时，可以获取到该收发端口内的时延反馈信号，时延反馈信号中可以包括从节点接收到时延确定信息的时间。
步骤205、确定所述时延反馈信号在所述接口板光监控端口的第二接收时间。
其中，第二接收时间可以是主节点接收时延反馈信号的时间，可以由接口板内FPGA确定。
在一个示例中，主节点在接受到时延反馈信号时，可以生成时间戳用于标 识时延反馈信号的第二接收时间，时间戳的确定可以由主节点接口板内的FPGA执行。进一步的，由于时延反馈信号在经过光监控端口的信号处理装置后才能确定报文接收时间，可以通过时延反馈信号从信号处理装置中进入和输出的时钟相位差确定出处理时间，可以在第二接收时间的基础上减去处理时间，可以得到主节点接收时延反馈信号的真实的第二接收时间。
步骤206、获取主节点内所述时延确定信号的第一发送时间和所述时延反馈信号的第二接收时间。
在一个示例中，第一发送时间和第二接收时间可以存储在主节点内，例如，可以存储在接口板的FPGA内，在确定主从时间差时，可以将第一发送时间和第二接收时间由接口板发送给主节点的主控。
步骤207、解析所述时延反馈信号获取到所述时延确定信号的第一接收时间和所述时延反馈信号的第二发送时间。
在一个示例中，时延反馈信息内可以包括从节点接收到时延确定信号的第一接收时间以及第二发送时间，可以理解的是，第一接收时间和第二发送时间可以是从节点内接口板光监控端口处的时间。
步骤208、根据所述第一发送时间、所述第一接收时间、所述第二发送时间和所述第二接收时间确定主从时间差。
在一个示例中，可以将第一接收时间与第一发送时间的差值作为时延确定信号的传输时间，可以将第二接收时间与第二发送时间的差值作为时延反馈信号的传输时间，在本发明实施例中可以不考虑主节点和从节点之间报文的传输时间误差，例如可以使用单纤双向传输的方式保证主节点和从节点数据传输时间相同，可以将时延确定信号的传输时间与时延反馈信号的传输时间的平均值作为主从时间差。
步骤209、将所述主从时间差发送给所述从节点，并根据所述主从时间差与所述从节点进行时钟时间同步。
一种实施方式中，将所述主从时间差封装为预设格式的传输信号；将所述传输信号发送到所述从节点，以使所述从节点根据所述主从时间差同步时钟时间。
在一个示例中，可以将主从时间差按照预设的格式进行封装，例如，可以 封装为TOD信息，每个TOD信息可以包括4个时间信息，可以分别是第一发送时间、第一接收时间、第二发送时间和第二接收时间，每个时间信息为10个字节，2个CRC，8字节保留信息。可以每秒发送1000次或更高频率的TOD信息使得主节点和从节点及时获取到网元内部的时间误差，使得从节点可以根据主从时间差实现主节点和从节点的精确时间同步。本申请实施例的技术方案，通过获取到从节点的单板编号和端口编号确定信号收发端口，将时延确定信号从接收板光监控端口发送到信息收发端口，确定时延确定信号在接口板光监控端口的第一发送时间，确定时延反馈信号在所述接口板光监控端的第二接收时间，解析时延反馈信号获取到时延确定信号的第一接收时间和所述时延反馈信号的第二发送时间，根据第一发送时间、第一接收时间、第二发送时间和第二接收时间确定主从时间差，将主从时间差发送给从节点，并根据主从时间差与从节点进行时钟时间同步，实现了时钟时间的精准同步，降低传输路径不对称引起的误差，提高了业务的稳定性。
示例性的，图5是本申请实施例提供的一种时钟时间同步方法的示例图，参见图5，时延反馈信号例如可以为GE信号0，可以对接口板光监控端口恢复处理出来的GE信号0进行改造，增加自定义编码的TOD信号1，可以周期性向发送TOD信号，可以每秒发送1000次或更高频率的TOD信息，每个TOD信息可以包括4个时间信息，可以分别是时延确定信号的发送时间和接收时间以及时延反馈信号的发送时间和接收时间，每个时间信息为10个字节，2个CRC，8字节保留信息，在图5中标号5处产生自定义编码的TOD信息。可以针对GE信号引入serdes管脚，参考时钟2可以使用250M系统时钟，FPGA的serdes可以对接入的GE信号0提取出125M CDR时钟并分频送给SEC芯片作为可能的时钟源4，同时测量出250M系统时钟2和125M CDR时钟4的相位差(时钟沿的相位差△p)，同时FPGA内部测量系统时钟2和发送的GE信号的边沿的相位关系，同时测量出serdes输入管脚5的GE信号0到接收的内部GE信号6的延迟，测量出发送的GE信号8到serdes输出管脚的GE信号7的延迟，这些延迟属于变化值，通过测量出变化值可以将这部分的变化值补偿掉。对于使用serdes采样，可以使用250M系统时钟作为serdes参考时钟，125M信号当做被采样信号处理，这样serdes rx的数据是250M RX_GE_CLK时钟加上32bit 宽度的数据，注意这里的250M时钟RX_GE_CLK和250M系统时钟同步但不同相，RX_GE_CLK可以是由FPGA内部提供的，根据RX_GE_CLK和32bit的数据通过算法可以得到一个normal信号和一个数据GE_RX_DATA表示采样得到的GE信号，同时产生一个RX_GE_OFFSET信号表示GE信号的实际位置相对于RX_GE_CLK的上升沿的偏差值。RX_GE_CLK加normal信号得到125M时钟等于GE的恢复时钟。逻辑计算出RX_GE_CLK和250M系统时钟的相位差，同时再根据RX_GE_OFFSET就可以计算出GE信号和250M系统时钟的相位差。
图6是本申请实施例提供的一种时钟时间同步方法的流程图，本申请实施例可以适用于通信网络中同步网元时钟时间的情况，该方法可以由本申请实施例中的时钟时间同步装置来执行，该装置可以通过软件和/或硬件的方式实现，并一般可以集成在网元设备的从节点中，参见图6，本申请实施例的时钟时间同步方法包括：
步骤301、从主节点内的信号收发端口接收时延确定信号。
其中，信号收发端口可以是主节点接口板内的光监控端口，可以通过单板编号和端口编号的方式预先与从节点进行标识，当从节点与主节点进行信号收发时，可以通过预先标识的信号收发端口进行。
在一个示例中，从节点可以对信号收发端口进行监听，获取主节点通过信号收发端口发送的时延确定信号，其中，时延确定信号可以用于确定主节点与从节点之间的通信延迟。
步骤302、向所述主节点发送时延反馈信号。
本申请实施例中，从节点还可以向主节点发送时延反馈信号，可以用于确定从节点到主节点的传输时间，可以理解的是，从节点可以在接收到主节点发送的时延确定信号后，将时延反馈信号发送到主节点，时延反馈信号内可以包括从节点发送时延反馈信号的时间。
步骤303、接收所述主节点根据所述时延确定信号和所述时延反馈信号确定的主从时间差，并根据所述主从时间差与所述主节点进行时钟时间同步。
在一个示例中，从节点可以接收主节点根据时延确定信号和时延反馈信号主从时间差，由于网元节点内部处理信号消耗时间，同步的时钟时间和真正的 时钟时间存在偏差，可以通过时延确定信号和时延反馈信号分别确定出信号由主节点和从节点的内部处理信号的时间误差，内部时间的偏差导致主从节点存在时间差，可以通过时延确定信号和时延反馈信号确定出主从时间差，例如可以通过主节点确定出的主从时间差进行时钟同步，可以在主节点发送来的时钟时间的基础上再根据主从时间差进行补充，例如，在时钟时间加上或者减去主从时间差作为从节点的时钟时间。
本申请实施例的技术方案，通过从主节点的信号收发端口接收时延确定信号，向主节点发送时延反馈信号，接收所述主节点根据时延确定信号和时延反馈信号确定的主从时间差，并根据主从时间差与主节点进行时钟同步，实现了主节点和从节点时钟时间的高精度同步，减少了内部传输时存在时间消耗导致的误差，可增强了业务的稳定性。
图7是本申请实施例提供的一种时钟时间同步方法的流程图，对确定主从时间差的时钟时间进行了具体化，参见图7，本申请实施例的时钟时间同步方法包括：
步骤401、获取所述主节点的单板编号和端口编号。
在一个示例中，可以预先通过单板编号和端口编号的方式确定主节点中一个光监控端口，可以将该端口作为主节点和从节点进行主从时间差确定的接入点。
步骤402、将所述主节点内所述单板编号和所述端口编号对应的光监控端口作为信号收发端口。
在一个示例中，可以根据单板编号查找主节点内对应的接口板，可以根据端口编号在查找到的接口板中确定对应的光监控端口，可以将该光监控端口作为主节点内与从节点进行信号传输的信号收发端口，从节点可以对该信号收发端口进行监测以获取通信信号。
步骤403、接收所述信号收发端口发送的所述时延确定信号。
在本申请实施例中，从节点可以对主节点内接口板上的信号收发端口进行监听，获取到主节点发送的时延确定信号，其中，时延确定信号可以包括从主节点中光监控端口发送的时间。
步骤404、确定从节点的接口板光监控端口接收所述时延确定信号的第一 接收时间。
在一个示例中，从节点的接口板光监控端口可以接收主节点发送的时延确定信号，从节点在接收到时延确定信号时，可以根据从节点接口板处的时钟确定出第一接收时间，其中，第一接收时间可以是从节点接收到时延确定信号的时间，通过以接口板处时钟时间作为第一接收时间，可以进一步提高主节点和从节点时钟时间同步的准确性。
一种实施方式中，所述确定从节点的接口板光监控端口接收所述时延确定信号的第一接收时间，包括：获取所述时延确定信号进入所述接口板光监控端口中信号处理装置的第二进入时钟相位；获取所述时延确定信号从所述信号处理装置输出的第二输出时钟相位；将所述第二输出时钟相位和所述第二进入时钟相位的相位差作为所述时延确定信号的第一接收补偿时间，根据所述接口板光监控端口的端口时钟和所述第一接收补偿时间确定第一接收时间。
在本发明实施例中，由于网元内部中需要对接收到的时延确定信号进行处理，只有在处理后才能获取到报文准确的接收时间，因此需要对处理时延确定信号的时间进行补偿以提高时钟的精确度，其中，信号处理装置例如可以是serdes，可以记录时延确定信号进入信号处理装置时从节点的系统时钟的相位作为第二进入时钟相位，可以记录时延确定信号从信号处理装置输出的系统时钟的相位作为第二输出时钟相位，可以计算第二输出时钟相位与第二进入时钟相位的相位差，可以将该相位差对应的时间长度作为从节点处理时延确定信号的第一接收补偿时间，可以在主节点获取到第一接收时间的基础上减去第一接收补偿时间，可以从节点中接收时延确定信号的真正接收时间。
步骤405、将所述时延反馈信号从接口板光监控端口发送到所述信号收发端口。
在一个示例中，时延反馈信号可以是确定从节点到主节点信号传输时间的信号，时延反馈信号可以由从节点的接口板光监控端口发送到主节点，主节点可以通过信号收发端口接收到时延反馈信号。
步骤406、确定所述时延反馈信号在所述接口板光监控端口的第二发送时间。
在本申请实施例中，从节点在发送时延反馈信号时，可以确定出接口板光 监控端口的第二发送时间，第二发送时间例如可以是从节点接口板出的时钟时间。进一步的，第二发送时间可以以时间戳信息的形式添加到时延反馈信号中一并发送，还可以将第二发送时间单独发送到主节点内。
进一步的，由于时延反馈信号在经过光监控端口的信号处理装置后才能被从节点，确定的时延反馈信号发送时间要早于从节点中发送时延反馈信号的时间，可以通过时延反馈信号从信号处理装置中进入和输出的时钟相位差确定出处理时间，可以在第二发送时间的基础上加上处理时间，可以得到从节点发送时延反馈信号的真实时间。
步骤407、接收所述主节点根据所述时延确定信号和所述时延反馈信号确定的主从时间差，并根据所述主从时间差与所述主节点进行时钟时间同步。
在一个示例中，从节点可以接收主节点根据时延确定信号和时延反馈信号主从时间差，由于主节点和从节点之间通信传输存在不对称的问题，可以通过时延确定信号和时延反馈信号分别确定出信号由主节点到从节点的通信延迟和信号由从节点到主节点的通信延迟，可以在主节点处通过两个方向的通信延迟确定出主从时间差，从节点在根据主节点的时钟时间进行同步时，可以在主节点发送来的时钟时间的基础上再根据主从时间差进行补偿。
本申请实施例的技术方案，通过获取主节点的单板编号和端口编号，根据单板编号和端口编号确定主节点内光监控端口作为信号收发端口，接收信号收发端口发送的时延确定信号，并确定接收该时延确定信号的第一接收时间，将时延反馈信号发送到主节点，并确定发送该时延反馈信号的第二发送时间，接收主节点根据时延确定信号和时延反馈信号确定的主从时间差，并根据该主从时间差进行时钟时间同步，实现了主节点和从节点的时钟时间的高精度同步，减少网元内部信号处理和传输导致的时间误差，可提高了业务的稳定性。
图8是本申请实施例提供的一种时钟时间同步装置的结构示意图，本申请实施例可以适用于网元时钟时间同步的情况，可执行本申请任意实施例提供的时钟时间同步方法，具备执行方法相应的功能模块和有益效果。该装置可以由软件和/或硬件实现，可以集成在网元的主节点中，参见图8，本申请实施例的装置包括：信息发送模块501、信号接收模块502、时延确定模块503和时钟同步模块504。
信息发送模块501用于向从节点内的信号收发端口发送时延确定信号。
信号接收模块502用于从所述从节点获取时延反馈信号。
时延确定模块503用于根据所述时延反馈信号和所述时延确定信号确定主从时间差。
时钟同步模块504用于将所述主从时间差发送给所述从节点，并根据所述主从时间差与所述从节点进行时钟时间同步。
本申请实施例的技术方案，通过信息发送模块向从节点发送时延确定信号，信号接收模块获取从节点的时延反馈信号，时延确定模块通过时延确定信号和时延反馈信息确定出主节点和从节点之间的主从时间差，时钟同步模块根据主从时间差进行时间同步，减少了主节点内部由于时间不确定导致的时间差，提高了时钟时间的精确度，可解决节点状态改变带来的时间突变问题，增强了业务的稳定性。
一种实施方式中，本申请实施例的装置还包括：端口确定模块，用于根据获取到所述从节点的单板编号和端口编号确定信号收发端口。
一种实施方式中，信息发送模块501包括：信号发送单元，用于将所述时延确定信号从接口板光监控端口发送到所述信号收发端口；发送时间单元，用于确定所述时延确定信号在所述接口板光监控端口的第一发送时间。
一种实施方式中，发送时间单元用于：获取所述时延确定信号进入所述接口板光监控端口中信号处理装置的第一进入时钟相位；获取所述时延确定信号从所述信号处理装置输出的第一输出时钟相位；将所述第一输出时钟相位和所述第一进入时钟相位的相位差作为所述时延确定信号的第一发送补偿时间，根据所述接口板光监控端口的端口时钟和所述第一发送补偿时间确定第一发送时间。
一种实施方式中，信号接收模块502包括：信号接收单元，用于通过接口板光监控端口接收所述从节点所述信号收发端口发送的所述时延反馈信号；以及接收时间单元，用于确定所述时延反馈信号在所述接口板光监控端口的第二接收时间。
一种实施方式中，时延确定模块503包括：时间获取单元，用于获取主节点内所述时延确定信号的第一发送时间和所述时延反馈信号的第二接收时间； 信号解析单元，用于解析所述时延反馈信号获取到所述时延确定信号的第一接收时间和所述时延反馈信号的第二发送时间；以及主从时间差单元，用于根据所述第一发送时间、所述第一接收时间、所述第二发送时间和所述第二接收时间确定主从时间差。
一种实施方式中，时钟同步模块504包括：信号封装单元，用于将所述主从时间差封装为预设格式的传输信号；以及信号发送单元，用于将所述传输信号发送到所述从节点，以使所述从节点根据所述主从时间差同步时钟时间。
图9是本申请实施例提供的一种时钟时间同步装置的结构示意图，本申请实施例可以适用于网元时钟时间同步的情况，可执行本申请任意实施例提供的时钟时间同步方法，具备执行方法相应的功能模块和有益效果。该装置可以由软件和/或硬件实现，可以集成在网元的从节点中，参见图9，本申请实施例的装置包括：信号接收模块601、信号反馈模块602和时钟同步模块603。
信号接收模块601用于从主节点内的信号收发端口接收时延确定信号。
信号反馈模块602用于向所述主节点发送时延反馈信号。
时钟同步模块603用于接收所述主节点根据所述时延确定信号和所述时延反馈信号确定的主从时间差，并根据所述主从时间差与所述主节点进行时钟时间同步。
本申请实施例的技术方案，信号接收模块通过从主节点的信号收发端口接收时延确定信号，信号反馈模块向主节点发送时延反馈信号，时钟同步模块接收所述主节点根据时延确定信号和时延反馈信号确定的主从时间差，并根据主从时间差与主节点进行时钟同步，实现了主节点和从节点时钟时间的高精度同步，减少内部传输时间消耗带来的误差，可增强了业务的稳定性。
一种实施方式中，本申请实施例提供的装置还包括：端口确定模块，用于：获取所述主节点的单板编号和端口编号；将所述主节点内所述单板编号和所述端口编号对应的光监控端口作为信号收发端口。
一种实施方式中，信号接收模块601包括：延迟信号单元，用于接收所述信号收发端口发送的所述时延确定信号；以及延迟时间单元，用于确定从节点的接口板光监控端口接收所述时延确定信号的第一接收时间。
一种实施方式中，延迟时间单元用于：获取所述时延确定信号进入所述接 口板光监控端口中信号处理装置的第二进入时钟相位；获取所述时延确定信号从所述信号处理装置输出的第二输出时钟相位；将所述第二输出时钟相位和所述第二进入时钟相位的相位差作为所述时延确定信号的第一接收补偿时间，根据所述接口板光监控端口的端口时钟和所述第一接收补偿时间确定第一接收时间。
一种实施方式中，信号反馈模块602包括：反馈信号单元，用于将所述时延反馈信号从接口板光监控端口发送到所述信号收发端口；以及反馈时间单元，用于确定所述时延反馈信号在所述接口板光监控端口的第二发送时间。
一种实施方式中，时钟同步模块603包括：信号接收单元，用于接收所述主节点发送的预设格式的传输信号；信号提取单元，用于提取所述传输信号中的主从时间差；以及时钟同步单元，用于根据所述主从时间差对从节点的本地时钟时间进行同步。
图10是本申请实施例提供的一种设备的结构示意图，如图10所示，该设备包括处理器50、存储器51、输入装置52和输出装置53；设备中处理器50的数量可以是一个或多个，图10中以一个处理器50为例；设备处理器50、存储器51、输入装置52和输出装置53可以通过总线或其他方式连接，图10中以通过总线连接为例。
存储器51作为一种计算机可读存储介质，可用于存储软件程序、计算机可执行程序以及模块，如本申请实施例中的时钟时间同步装置对应的模块(信息发送模块501、信号接收模块502、时延确定模块503和时钟同步模块504，或者信号接收模块601、信号反馈模块602和时钟同步模块603)。处理器50通过运行存储在存储器51中的软件程序、指令以及模块，从而执行设备的各种功能应用以及数据处理，即实现上述的时钟时间同步方法。
存储器51可主要包括存储程序区和存储数据区，其中，存储程序区可存储操作系统、至少一个功能所需的应用程序；存储数据区可存储根据终端的使用所创建的数据等。此外，存储器51可以包括高速随机存取存储器，还可以包括非易失性存储器，例如至少一个磁盘存储器件、闪存器件、或其他非易失性固态存储器件。在一些实例中，存储器51可进一步包括相对于处理器50远程设置的存储器，这些远程存储器可以通过网络连接至设备。上述网络的实例包括 但不限于互联网、企业内部网、局域网、移动通信网及其组合。
输入装置52可用于接收输入的数字或字符信息，以及产生与设备的用户设置以及功能控制有关的键信号输入。输出装置53可包括显示屏等显示设备。
本申请实施例还提供一种包含计算机可执行指令的存储介质，所述计算机可执行指令在由计算机处理器执行时用于执行一种时钟时间同步方法，该方法包括：
向从节点内的信号收发端口发送时延确定信号；从所述从节点获取时延反馈信号；根据所述时延反馈信号和所述时延确定信号确定主从时间差；将所述主从时间差发送给所述从节点，并根据所述主从时间差与所述从节点进行时钟时间同步。
或者，
从主节点内的信号收发端口接收时延确定信号；向所述主节点发送时延反馈信号；接收所述主节点根据所述时延确定信号和所述时延反馈信号确定的主从时间差，并根据所述主从时间差与所述主节点进行时钟时间同步。
当然,本申请实施例所提供的一种包含计算机可执行指令的存储介质,其计算机可执行指令不限于如上所述的方法操作，还可以执行本发明任意实施例所提供的时钟时间同步方法中的相关操作。
本申请实施例的技术方案，通过向从节点发送时延确定信号，获取从节点的时延反馈信号确定出主节点与从节点之间的时间偏差，根据时间偏差与从节点进行时间同步，减小了内部传输时存在时间消耗导致的时间误差，可以提高主节点和从节点同步时钟时间的精确度，解决了节点状态改变带来的时间突变问题，降低业务影响。
通过以上关于实施方式的描述，所属领域的技术人员可以清楚地了解到，本发明可借助软件及必需的通用硬件来实现，当然也可以通过硬件实现，但很多情况下前者是更佳的实施方式。基于这样的理解，本发明的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品可以存储在计算机可读存储介质中，如计算机的软盘、只读存储器(Read-Only Memory,ROM)、随机存取存储器(Random Access Memory,RAM)、闪存(FLASH)、硬盘或光盘等，包括若干指令用以使得一台计算机设备(可以 是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述的方法。
值得注意的是，上述时钟时间同步装置的实施例中，所包括的各个单元和模块只是按照功能逻辑进行划分的，但并不局限于上述的划分，只要能够实现相应的功能即可；另外，各功能单元的具体名称也只是为了便于相互区分，并不用于限制本申请的保护范围。
以上所述，仅为本申请的示例性实施例而已，并非用于限定本申请的保护范围。
本领域内的技术人员应明白，术语用户终端涵盖任何适合类型的无线用户设备，例如移动电话、便携数据处理装置、便携网络浏览器或车载移动台。
一般来说，本申请的多种实施例可以在硬件或专用电路、软件、逻辑或其任何组合中实现。例如，一些方面可以被实现在硬件中，而其它方面可以被实现在可以被控制器、微处理器或其它计算装置执行的固件或软件中，尽管本申请不限于此。
本申请的实施例可以通过移动装置的数据处理器执行计算机程序指令来实现，例如在处理器实体中，或者通过硬件，或者通过软件和硬件的组合。计算机程序指令可以是汇编指令、指令集架构(ISA)指令、机器指令、机器相关指令、微代码、固件指令、状态设置数据、或者以一种或多种编程语言的任意组合编写的源代码或目标代码。
本申请附图中的任何逻辑流程的框图可以表示程序步骤，或者可以表示相互连接的逻辑电路、模块和功能，或者可以表示程序步骤与逻辑电路、模块和功能的组合。计算机程序可以存储在存储器上。存储器可以具有任何适合于本地技术环境的类型并且可以使用任何适合的数据存储技术实现，例如但不限于只读存储器(ROM)、随机访问存储器(RAM)、光存储器装置和系统(数码多功能光碟DVD或CD光盘)等。计算机可读介质可以包括非瞬时性存储介质。数据处理器可以是任何适合于本地技术环境的类型，例如但不限于通用计算机、专用计算机、微处理器、数字信号处理器(DSP)、专用集成电路(ASIC)、可编程逻辑器件(FGPA)以及基于多核处理器架构的处理器。
通过示范性和非限制性的示例，上文已提供了对本申请的示范实施例的详细描述。但结合附图和权利要求来考虑，对以上实施例的多种修改和调整对 本领域技术人员来说是显而易见的，但不偏离本发明的范围。因此，本发明的恰当范围将根据权利要求确定。

Claims (17)

  1. 一种时钟时间同步方法，应用于主节点，包括：
    向从节点内的信号收发端口发送时延确定信号；
    从所述从节点获取时延反馈信号；
    根据所述时延反馈信号和所述时延确定信号确定主从时间差；以及
    将所述主从时间差发送给所述从节点，并根据所述主从时间差与所述从节点进行时钟时间同步。
  2. 根据权利要求1所述的方法，还包括：
    根据获取到所述从节点的单板编号和端口编号确定信号收发端口。
  3. 根据权利要求1所述的方法，其中，所述向从节点内的信号收发端口发送时延确定信号，包括：
    将所述时延确定信号从接口板光监控端口发送到所述信号收发端口；以及
    确定所述时延确定信号在所述接口板光监控端口的第一发送时间。
  4. 根据权利要求3所述的方法，其中，所述确定所述时延确定信号在所述接口板光监控端口的第一发送时间，包括：
    获取所述时延确定信号进入所述接口板光监控端口中信号处理装置的第一进入时钟相位；
    获取所述时延确定信号从所述信号处理装置输出的第一输出时钟相位；以及
    将所述第一输出时钟相位和所述第一进入时钟相位的相位差作为所述时延确定信号的第一发送补偿时间，根据所述接口板光监控端口的端口时钟和所述第一发送补偿时间确定第一发送时间。
  5. 根据权利要求1所述的方法，其中，所述从所述从节点获取时延反馈信号，包括：
    通过接口板光监控端口接收所述从节点所述信号收发端口发送的所述 时延反馈信号；以及
    确定所述时延反馈信号在所述接口板光监控端口的第二接收时间。
  6. 根据权利要求1所述的方法，其中，所述根据所述时延反馈信号和所述时延确定信号确定主从时间差，包括：
    获取主节点内所述时延确定信号的第一发送时间和所述时延反馈信号的第二接收时间；
    解析所述时延反馈信号获取到所述时延确定信号的第一接收时间和所述时延反馈信号的第二发送时间；以及
    根据所述第一发送时间、所述第一接收时间、所述第二发送时间和所述第二接收时间确定主从时间差。
  7. 根据权利要求1所述的方法，其中，所述将所述主从时间差发送给所述从节点，并根据所述主从时间差与所述从节点进行时钟时间同步，包括：
    将所述主从时间差封装为预设格式的传输信号；以及
    将所述传输信号发送到所述从节点，以使所述从节点根据所述主从时间差同步时钟时间。
  8. 一种时钟时间同步方法，应用于从节点，包括：
    从主节点内的信号收发端口接收时延确定信号；
    向所述主节点发送时延反馈信号；以及
    接收所述主节点根据所述时延确定信号和所述时延反馈信号确定的主从时间差，并根据所述主从时间差与所述主节点进行时钟时间同步。
  9. 根据权利要求8所述的方法，其中，在所述从主节点内的信号收发端口接收时延确定信号之前，还包括：
    获取所述主节点的单板编号和端口编号；以及
    将所述主节点内所述单板编号和所述端口编号对应的光监控端口作为信号收发端口。
  10. 根据权利要求8所述的方法，其中，所述从主节点内的信号收发 端口接收时延确定信号，包括：
    接收所述信号收发端口发送的所述时延确定信号；以及
    确定从节点的接口板光监控端口接收所述时延确定信号的第一接收时间。
  11. 根据权利要求10所述的方法，其中，所述确定从节点的接口板光监控端口接收所述时延确定信号的第一接收时间，包括：
    获取所述时延确定信号进入所述接口板光监控端口中信号处理装置的第二进入时钟相位；
    获取所述时延确定信号从所述信号处理装置输出的第二输出时钟相位；以及
    将所述第二输出时钟相位和所述第二进入时钟相位的相位差作为所述时延确定信号的第一接收补偿时间，根据所述接口板光监控端口的端口时钟和所述第一接收补偿时间确定第一接收时间。
  12. 根据权利要求8所述的方法，其中，所述向所述主节点发送时延反馈信号，包括：
    将所述时延反馈信号从接口板光监控端口发送到所述信号收发端口；以及
    确定所述时延反馈信号在所述接口板光监控端口的第二发送时间。
  13. 根据权利要求8所述的方法，其中，所述接收所述主节点根据所述时延确定信号和所述时延反馈信号确定的主从时间差，并根据所述主从时间差与所述主节点进行时钟时间同步，包括：
    接收所述主节点发送的预设格式的传输信号；
    提取所述传输信号中的主从时间差；以及
    根据所述主从时间差对从节点的本地时钟时间进行同步。
  14. 一种时钟时间同步装置，应用于主节点，包括：
    信息发送模块，用于向从节点内的信号收发端口发送时延确定信号；
    信号接收模块，用于从所述从节点获取时延反馈信号；
    时延确定模块，用于根据所述时延反馈信号和所述时延确定信号确定主从时间差；以及
    时钟同步模块，用于将所述主从时间差发送给所述从节点，并根据所述主从时间差与所述从节点进行时钟时间同步。
  15. 一种时钟时间同步装置，应用于从节点，包括：
    信号接收模块，用于从主节点内的信号收发端口接收时延确定信号；
    信号反馈模块，用于向所述主节点发送时延反馈信号；以及
    时钟同步模块，用于接收所述主节点根据所述时延确定信号和所述时延反馈信号确定的主从时间差，并根据所述主从时间差与所述主节点进行时钟时间同步。
  16. 一种设备，包括：
    一个或多个处理器；以及
    存储器，用于存储一个或多个程序；
    当所述一个或多个程序被所述一个或多个处理器执行，使得所述一个或多个处理器实现如权利要求1-13中任一所述的时钟时间同步方法。
  17. 一种计算机可读存储介质，其上存储有计算机程序，其中，该程序被处理器执行时实现如权利要求1-13中任一所述的时钟时间同步方法。
PCT/CN2020/139083 2019-12-26 2020-12-24 时钟时间同步方法、装置、设备和存储介质 WO2021129755A1 (zh)

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