WO2021128703A1 - 一种信息防篡改系统及方法 - Google Patents

一种信息防篡改系统及方法 Download PDF

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Publication number
WO2021128703A1
WO2021128703A1 PCT/CN2020/089728 CN2020089728W WO2021128703A1 WO 2021128703 A1 WO2021128703 A1 WO 2021128703A1 CN 2020089728 W CN2020089728 W CN 2020089728W WO 2021128703 A1 WO2021128703 A1 WO 2021128703A1
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Prior art keywords
information
module
otp
switch
otp switch
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PCT/CN2020/089728
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English (en)
French (fr)
Inventor
张�雄
史刚
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澜起电子科技(昆山)有限公司
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Priority to US16/959,148 priority Critical patent/US11538540B2/en
Publication of WO2021128703A1 publication Critical patent/WO2021128703A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09C—CIPHERING OR DECIPHERING APPARATUS FOR CRYPTOGRAPHIC OR OTHER PURPOSES INVOLVING THE NEED FOR SECRECY
    • G09C1/00—Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/22—Safety or protection circuits preventing unauthorised or accidental access to memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/18—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/24—Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
    • H04L9/0643—Hash functions, e.g. MD5, SHA, HMAC or f9 MAC
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/32—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials
    • H04L9/3226—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using a predetermined code, e.g. password, passphrase or PIN
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/4402—Internal storage of test result, quality data, chip identification, repair information
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/006—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation at wafer scale level, i.e. wafer scale integration [WSI]

Definitions

  • the present invention relates to the technical field of information security, in particular to an information anti-tampering system and method.
  • the Chinese patent application number 201910034802.7 discloses a method for preventing information tampering, which is applied to a device server, including: receiving identification information, an application public key and a first signature sent by the application server, where the identification information is the identification of the device terminal Information, the application public key is generated by the device terminal and sent to the application server, and the first signature is used by the device terminal to sign the application public key in a trusted execution environment using the device private key Obtained, the information stored in the trusted execution environment cannot be modified by an untrusted application; according to the identification information, the public key corresponding to the device private key is searched to obtain the device public key, and the device public key is Corresponding to the device private key stored in the device terminal; if the first signature is verified by using the device public key, the verification result is sent to the application server.
  • Another example is the Chinese patent of 201611166091.1 which discloses a method for preventing information tampering, including: generating a random key when a request for writing information for built-in information is detected by an information modification tool with authority, and authorization is required for the modification operation of the built-in information
  • Use a preset public key to encrypt the random key and the information to be written to obtain the first encrypted data, and transmit the first encrypted data to the server through the information modification tool, so that the server generates according to the first encrypted data Second encrypted data; obtain the second encrypted data, use the random key to decrypt the second encrypted data to obtain the information to be written, and modify the built-in information according to the information to be written.
  • the purpose of the present invention is to provide an information tamper-proof system and method, by using a one-time programmable (One Time Programmable, OTP) switch to control the limited number of writing and reading of information , Effectively avoiding the theft and tampering of information.
  • a one-time programmable switch to control the limited number of writing and reading of information , Effectively avoiding the theft and tampering of information.
  • the present invention provides an information tamper-proof system.
  • the system includes a storage module, a writing module, a first reading module, and a second reading module;
  • the storage module is connected to write source information into the storage module;
  • the first reading module is connected to the storage module through a second OTP switch, and is used to read the written information in the storage module, and After confirming that the written information is correct, turn off the first OTP switch and the second OTP switch;
  • the second reading module is connected to the storage module through the third OTP switch, and is used to connect to the storage module through the third OTP switch.
  • the storage information in the storage module is read after the switch is closed; wherein, the first OTP switch, the second OTP switch, and the third OTP switch can only perform a closing operation or an opening operation once.
  • the system is applied in a chip manufacturing and use process, and the security information of the chip is used as the source information;
  • the writing module is used to write the source information into the storage module during the chip CP or FT testing phase;
  • the first reading module is used to read the written information in the storage module during the CP or FT test phase of the chip, and turn off the first OTP switch and the first OTP switch after confirming that the written information is correct.
  • the second reading module is used to read the storage information in the storage module after the third OTP switch is closed during the chip use phase.
  • the writing module is further configured to generate a first hash code according to the source information; the second reading module is further configured to generate a second hash code according to the stored information, and compare Determine whether the source information and the stored information are consistent with the first hash code and the second hash code.
  • the first reading module and the second reading module are integrated into one body, and are connected to the storage module through the second OTP switch and the third OTP switch.
  • the storage module adopts an OTP storage module or an MTP storage module.
  • the initial state of the first OTP switch and the second OTP switch is closed; the initial state of the third OTP switch is open.
  • the first OTP switch, the second OTP switch, and the third OTP switch all use efuse memory.
  • the present invention provides an information anti-tampering method, the method is applied to an information anti-tampering system, the information anti-tampering system includes a storage module, a writing module, a first reading module, and a second reading module; the writing module , The first reading module and the second reading module are respectively connected to the storage module through a first OTP switch, a second OTP switch, and a third OTP switch;
  • the information tamper-proof method includes the following steps:
  • the first OTP switch, the second OTP switch, and the third OTP switch can only perform a closing operation or an opening operation at a time.
  • the method is applied in a chip manufacturing and use process, and the security information of the chip is used as the source information;
  • the writing module writes the source information into the storage module during the chip CP or FT test phase
  • the first reading module reads the written information in the storage module during the CP or FT test phase of the chip, and turns off the first OTP switch and the second OTP after confirming that the written information is correct switch;
  • the second reading module reads the storage information in the storage module after the second OTP switch is closed during the chip use phase.
  • the writing module is further configured to generate a first hash code according to the source information; the second reading module is further configured to generate a second hash code according to the stored information, and compare Determine whether the source information and the stored information are consistent with the first hash code and the second hash code.
  • the first reading module and the second reading module are integrated into one body, and are connected to the storage module through the second OTP switch and the third OTP switch.
  • the storage module adopts an OTP storage module or an MTP storage module.
  • the initial state of the first OTP switch and the second OTP switch is closed; the initial state of the third OTP switch is open.
  • the first OTP switch, the second OTP switch, and the third OTP switch all use efuse memory.
  • the information tamper-proof system and method of the present application realizes the safe writing and reading of information by using OTP switches, and guarantees the security of information transmission through the hash encryption algorithm, so that it can be used from wafer manufacturing to end users. Effectively avoid and prevent information from being stolen and tampered in all processes, and has low hardware configuration requirements and has a wide range of application scenarios.
  • FIG. 1 shows a schematic diagram of the structure of the information tamper-proof system in an embodiment of the present invention
  • FIG. 2 shows a schematic diagram of the state of the information tamper-proof system of the present invention during a write operation
  • Fig. 3 is a schematic diagram showing the state of the information anti-tampering system of the present invention during the first read operation
  • FIG. 4 is a schematic diagram showing the state of the information tamper-proof system of the present invention when it is read again;
  • FIG. 5 shows a flowchart of an embodiment of the information tamper-proof method of the present invention.
  • the information tamper-proof system of the present invention includes a storage module 1, a writing module 2, a first reading module 3, and a second reading module 4.
  • the writing module 2 is connected to the storage module 1 through a first OTP switch 5,
  • the first reading module 3 is connected to the storage module 1 through a second OTP switch 6, and
  • the second reading module 4 is connected to the storage module 1 through a third OTP switch.
  • the OTP switch 7 is connected to the storage module 1. Wherein, in the initial state, the first OTP switch 5 and the second OTP switch 6 are both in the closed state, and the third OTP switch 7 is in the open state.
  • the OTP switch is a switch capable of performing only one closing operation or opening operation through programming, and the closing operation and the opening operation are physically irreversible. Specifically, the OTP switch can only be programmed once, and it can be rewritten from 1 to 0, or from 0 to 1; after one rewrite is completed, it is not possible to rewrite 0 to 1 and 1 to 0.
  • the first OTP switch, the second OTP switch, and the third OTP switch all use efuse memory.
  • efuse memory is similar to EEPROM. The difference is that efuse memory is a one-time programmable memory, programmed through a fuse. Among them, a 10 mA DC pulse lasting 200 microseconds is sufficient to program a single fuse. The on and off of the switch can be realized by the on and off of the fuse.
  • the writing module 2 directly writes the source information into the storage module 1.
  • the first reading module 3 directly reads the written information in the storage module 1 from the storage module 1 to verify the written information Whether it is consistent with the source information. As shown in Figure 3, if the two are consistent, it means that the write operation is correct, and the first OTP switch 5 and the second OTP switch 6 are disconnected; if the two are inconsistent, it means that the write operation is incorrect.
  • the third OTP switch 7 when the storage information in the storage module 1 needs to be read, since the third OTP switch 7 is in the open state, the third OTP switch 7 needs to be closed first, and then pass The second reading module 4 reads the storage information thereon from the storage module 1. Since the third OTP switch 7 can only be closed once, the information in the storage module 1 can only be read once, effectively avoiding the theft of information. If the third OTP switch 7 is closed before the storage information is read, it can be proved that the storage data in the storage module 1 has been illegally read.
  • the security information of the chip directly affects the usability of the chip itself, so secure transmission is required.
  • CP Chip Probe, wafer test
  • packaging packaging
  • FT Fluor test
  • the CP test is to test the chip at the wafer stage before packaging
  • the FT test is the test performed after the packaging is completed.
  • the information tamper-proof system of the present invention is applied to the chip manufacturing process.
  • the security information of the chip is used as the source information.
  • the writing module is used to write the source information into the storage module during the chip CP or FT testing phase; the first reading module is used to read the storage module during the chip CP or FT testing phase Write information, and after confirming that the written information is correct, turn off the first OTP switch and the second OTP switch; the second reading module is used to close the third OTP switch during the chip use phase Read the storage information in the storage module. Therefore, no matter in the CP test stage or the FT test stage of the chip, the first OTP switch and the second OTP switch can be used to achieve accurate writing of safety information, and only the end user can pass the first OTP switch. Three OTP switches realize the readout of the safety information.
  • This method can monitor and confirm whether there is illegal information writing in the previous process (wafer manufacturing, transportation, etc.) when the CP or FT writes and confirms the information; at the end user, it can monitor the CP or FT to the end user All the processes (encapsulation, transportation, initialization, etc.) have information tampering, and prevent the theft of information in all intermediate processes, and achieve the purpose of anti-theft and anti-tampering.
  • the writing module 2 is further configured to generate a first hash code according to the source information;
  • the second reading module 4 is also configured to generate a second hash code according to the storage information, and compare the first hash code and the second hash code to determine whether the source information and the storage information are Unanimous. That is to say, when the writing module 2 writes the source information, it first converts the source information into a corresponding hash code through a hash encryption algorithm.
  • the hash encryption algorithm can transform an input of any length into a fixed-length output through a hash algorithm, and the output is the hash value.
  • This conversion is a compression mapping, that is, the space of the hash value is usually much smaller than the space of the input.
  • the source data can be compressed into a unique first hash code.
  • the second reading module 4 After the second reading module 4 reads the storage information, it also uses the hash encryption algorithm to encrypt the storage information, and then obtains the second hash code. Among them, the first hash code is transmitted to the end user in plain text, and the second hash code is generated at the end user. By comparing the first hash code and the second hash code, it can be determined whether the stored information is consistent with the source information. If the stored information is consistent with the source information, it means that the source information is transmitted accurately and without tampering; if the stored information is inconsistent with the source information, it means that the source information has occurred. tamper.
  • the first reading module 3 and the second reading module 4 may be integrated into one body, and the second OTP switch 6 and the third OTP switch 7 are connected to the storage module 1 connection.
  • the information anti-tampering system only needs to provide a reading module, which has two data reading functions, one for verifying the accuracy of the written information, and one for reading the stored information.
  • the storage module 1 adopts an OTP storage module or an MTP (Multi Time Program) or a flash storage module, which can be selected according to different application scenarios.
  • the information anti-tampering method of the present invention is applied to an information anti-tampering system
  • the information anti-tampering system includes a storage module, a writing module, a first reading module, and a second reading module;
  • the writing module, the first reading module, and the second reading module are connected to the storage module through a first OTP switch, a second OTP switch, and a third OTP switch, respectively.
  • the first OTP switch and the second OTP switch are both in a closed state
  • the third OTP switch is in an open state.
  • the information tamper-proof method includes the following steps:
  • Step S1 Write source information into the storage module through the first OTP switch based on the writing module.
  • the writing module directly writes the source information into the storage module.
  • Step S2 Read the written information in the storage module through the second OTP switch based on the first reading module, and turn off the first OTP switch and the second OTP switch after confirming that the written information is correct. Two OTP switch.
  • the first reading module directly reads the written information in the storage module from the storage module to verify whether the written information is consistent with the The source information is consistent. As shown in Figure 3, if the two are consistent, it means that the write operation is correct, and the first OTP switch and the second OTP switch are disconnected; if the two are inconsistent, it means that the write operation is incorrect, and you can re-based
  • the writing module writes the source information, and reads the written information based on the first reading module until the source information is consistent with the written information, and disconnects the first OTP switch and second OTP switch.
  • Step S3 Read the stored information in the storage module based on the second reading module after the second OTP switch is closed.
  • the third OTP switch since the third OTP switch is in the open state, the third OTP switch must be closed first, and then the third OTP switch must be closed.
  • the second reading module reads the storage information on the storage module from the storage module. Since the third OTP switch can only be closed once, the information in the storage module can only be read once, effectively avoiding the theft of information. If the third OTP switch has been closed before the storage information is read, it can be proved that the storage data in the storage module has been illegally read.
  • the security information of the chip directly affects the usability of the chip itself, so secure transmission is required.
  • CP Chip Probe, wafer test
  • packaging packaging
  • FT Fluor test
  • the CP test is to test the chip at the wafer stage before packaging
  • the FT test is the test performed after the packaging is completed.
  • the information tamper-proof system of the present invention is applied to the chip manufacturing process.
  • the security information of the chip is used as the source information.
  • the writing module is used to write the source information into the storage module during the chip CP or FT testing phase; the first reading module is used to read the storage module during the chip CP or FT testing phase Write information, and after confirming that the written information is correct, turn off the first OTP switch and the second OTP switch; the second reading module is used to close the third OTP switch during the chip use phase Read the storage information in the storage module. Therefore, no matter in the CP test stage or the FT test stage of the chip, the first OTP switch and the second OTP switch can be used to achieve accurate writing of safety information, and only the end user can pass the first OTP switch. Three OTP switches realize the readout of the safety information.
  • This method can monitor and confirm whether there is illegal information writing in the previous process (wafer manufacturing, transportation, etc.) when the CP or FT writes and confirms the information; at the end user, it can monitor the CP or FT to the end user All the processes (encapsulation, transportation, initialization, etc.) have information tampering, and prevent the theft of information in all intermediate processes, and achieve the purpose of anti-theft and anti-tampering.
  • the writing module further generates a first hash code according to the source information; the second reading The module also generates a second hash code according to the storage information, and compares the first hash code with the second hash code to determine whether the source information and the storage information are consistent. That is, when the writing module writes the source information, it first converts the source information into a corresponding hash code through a hash encryption algorithm.
  • the hash encryption algorithm can transform an input of any length into a fixed-length output through a hash algorithm, and the output is the hash value.
  • This conversion is a compression mapping, that is, the space of the hash value is usually much smaller than the space of the input.
  • the source data can be compressed into a unique first hash code.
  • the second reading module also uses the hash encryption algorithm to encrypt the storage information, and then obtains the second hash code.
  • the first hash code is transmitted to the end user in plain text, and the second hash code is generated at the end user.
  • the first hash code and the second hash code it can be determined whether the stored information is consistent with the source information. If the stored information is consistent with the source information, it means that the source information is transmitted accurately and without tampering; if the stored information is inconsistent with the source information, it means that the source information has occurred. tamper.
  • the first reading module and the second reading module may be integrated into one body, and are connected to the storage module through the second OTP switch and the third OTP switch.
  • the information anti-tampering system only needs to provide a reading module, which has two data reading functions, one for verifying the accuracy of the written information, and one for reading the stored information.
  • the storage module adopts an OTP storage module, an MTP storage module, or a flash storage module, which can be selected according to different application scenarios.
  • the information anti-tampering system and method of the present invention uses OTP switches to control the limited number of writes and reads of information; the hash encryption algorithm ensures the security of information transmission; it has low requirements for hardware configuration, Has a wide range of application scenarios; effectively avoids the theft and tampering of information, and ensures the safe transmission of information. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial value.

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  • Computer Security & Cryptography (AREA)
  • Computer Networks & Wireless Communication (AREA)
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Abstract

一种信息防篡改系统及方法，所述系统包括存储模块（1）、写模块（2）、第一读模块（3）和第二读模块（4）；所述写模块（2）通过第一OTP开关（5）与所述存储模块（1）连接，用于将源信息写入所述存储模块（1）；所述第一读模块（3）通过第二OTP开关（6）与所述存储模块（1）连接，用于读出所述存储模块（1）中的写入信息，并在确认所述写入信息准确无误后断开所述第一OTP开关（5）及第二OTP开关（6）；所述第二读模块（4）通过第三OTP开关（7）与所述存储模块（1）连接，用于在所述第三OTP开关（7）闭合后读出所述存储模块（1）中的存储信息；所述第一OTP开关（5）、所述第二OTP开关（6）和所述第三OTP开关（7）仅能够单次执行闭合操作或断开操作。该方法通过采用OTP开关来控制信息的有限次数的写入和读出，有效避免了信息的窃取和篡改。

Description

一种信息防篡改系统及方法 技术领域
本发明涉及信息安全的技术领域，特别是涉及一种信息防篡改系统及方法。
背景技术
随着信息技术的飞速发展，信息的安全传输越来越受到人们的重视。传输过程中的信息一旦发生窃取或篡改，轻则导致后续的流程无法进行，重则可能带来不可估量的损失。特别地，在芯片制造流程中，从晶圆流片、封装、测试到终端客户使用环节，都存在芯片的安全信息被窃取和/或篡改的隐患，严重影响了芯片的可用性。
现有技术中，通常通过签名、加密等方式避免信息的篡改。如申请号为201910034802.7的中国专利公开了一种防止信息篡改的方法，应用于设备服务器，包括：接收应用服务器发送的标识信息、应用公钥和第一签名，所述标识信息为设备终端的标识信息，所述应用公钥是由所述设备终端生成并发送给所述应用服务器的，所述第一签名是由所述设备终端在可信执行环境中使用设备私钥对应用公钥进行签名获得的，所述可信执行环境中存储的信息无法被不可信的应用程序修改；根据所述标识信息查找与所述设备私钥对应的公钥，获得设备公钥，所述设备公钥是与存储在设备终端的设备私钥对应的；若使用所述设备公钥对所述第一签名进行验证通过，则将验证结果发送给所述应用服务器。再如201611166091.1的中国专利公开一种信息防篡改方法，包括：在检测到具有权限的信息修改工具对内置信息的写信息请求，且对于所述内置信息的修改操作需要授权时，生成随机密钥；采用预设公钥加密所述随机密钥和待写入信息得到第一加密数据，通过所述信息修改工具传输所述第一加密数据至服务器，以使服务器根据所述第一加密数据生成第二加密数据；获取所述第二加密数据，采用所述随机密钥解密所述第二加密数据得到所述待写入信息，根据所述待写入信息修改所述内置信息。
然而，上述信息防篡改方法具有以下不足：
(1)算法复杂，对系统硬件要求较高；
(2)需占用较多的系统资源，应用场景有限。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种信息防篡改系统及方法，通过采用一次可编程(One Time Programmable，OTP)开关来控制信息的有限次数的写入和读 出，有效避免了信息的窃取和篡改。
为实现上述目的及其他相关目的，本发明提供一种信息防篡改系统，所述系统包括存储模块、写模块、第一读模块和第二读模块；所述写模块通过第一OTP开关与所述存储模块连接，用于将源信息写入所述存储模块；所述第一读模块通过第二OTP开关与所述存储模块连接，用于读出所述存储模块中的写入信息，并在确认所述写入信息准确无误后断开所述第一OTP开关及第二OTP开关；所述第二读模块通过第三OTP开关与所述存储模块连接，用于在所述第三OTP开关闭合后读出所述存储模块中的存储信息；其中，所述第一OTP开关、所述第二OTP开关和所述第三OTP开关仅能够单次执行闭合操作或断开操作。
于本发明一实施例中，所述系统应用于芯片制造使用流程中，芯片的安全信息作为所述源信息；
所述写模块用于在芯片CP或FT测试阶段将所述源信息写入所述存储模块；
所述第一读模块用于在所述芯片CP或FT测试阶段读出所述存储模块中的写入信息，并在确认所述写入信息准确无误后断开所述第一OTP开关及第二OTP开关；
所述第二读模块用于在芯片使用阶段在所述第三OTP开关闭合后读出所述存储模块中的存储信息。
于本发明一实施例中，所述写模块还用于根据所述源信息生成第一哈希码；所述第二读模块还用于根据所述存储信息生成第二哈希码，并比对所述第一哈希码和所述第二哈希码以确定所述源信息和所述存储信息是否一致。
于本发明一实施例中，所述第一读模块和所述第二读模块集成为一体，通过所述第二OTP开关和所述第三OTP开关与所述存储模块连接。
于本发明一实施例中，所述存储模块采用OTP存储模块或MTP存储模块。
于本发明一实施例中，所述第一OTP开关和所述第二OTP开关的初始状态为闭合；所述第三OTP开关的初始状态为断开。
于本发明一实施例中，所述第一OTP开关、所述第二OTP开关和所述第三OTP开关均采用efuse存储器。
对应地，本发明提供一种信息防篡改方法，所述方法应用于信息防篡改系统，所述信息防篡改系统包括存储模块、写模块、第一读模块和第二读模块；所述写模块、所述第一读模块和所述第二读模块分别通过第一OTP开关、第二OTP开关和第三OTP开关与所述存储模块连接；
所述信息防篡改方法包括以下步骤：
基于所述写模块通过所述第一OTP开关将源信息写入所述存储模块；
基于所述第一读模块通过所述第二OTP开关读出所述存储模块中的写入信息，并在确认所述写入信息准确无误后断开所述第一OTP开关及第二OTP开关；
基于所述第二读模块在所述第二OTP开关闭合后读出所述存储模块中的存储信息；
其中，所述第一OTP开关、所述第二OTP开关和所述第三OTP开关仅能够单次执行闭合操作或断开操作。
于本发明一实施例中，所述方法应用于芯片制造使用流程中，芯片的安全信息作为所述源信息；
所述写模块在芯片CP或FT测试阶段将所述源信息写入所述存储模块；
所述第一读模块在所述芯片CP或FT测试阶段读出所述存储模块中的写入信息，并在确认所述写入信息准确无误后断开所述第一OTP开关及第二OTP开关；
所述第二读模块在芯片使用阶段在所述第二OTP开关闭合后读出所述存储模块中的存储信息。
于本发明一实施例中，所述写模块还用于根据所述源信息生成第一哈希码；所述第二读模块还用于根据所述存储信息生成第二哈希码，并比对所述第一哈希码和所述第二哈希码以确定所述源信息和所述存储信息是否一致。
于本发明一实施例中，所述第一读模块和所述第二读模块集成为一体，通过所述第二OTP开关和所述第三OTP开关与所述存储模块连接。
于本发明一实施例中，所述存储模块采用OTP存储模块或MTP存储模块。
于本发明一实施例中，所述第一OTP开关和所述第二OTP开关的初始状态为闭合；所述第三OTP开关的初始状态为断开。
于本发明一实施例中，所述第一OTP开关、所述第二OTP开关和所述第三OTP开关均采用efuse存储器。
本申请的一种信息防篡改系统及方法通过采用OTP开关来实现信息的安全写入和读出，以及通过哈希加密算法来保证信息传输的安全性，从而可以从晶圆制造到终端用户的所有流程中有效避免和防止信息被窃取和篡改，而且对硬件配置要求低，具有广泛的应用场景。
附图说明
图1显示为本发明的信息防篡改系统于一实施例中的结构示意图；
图2显示为本发明的信息防篡改系统在写入操作时的状态示意图；
图3显示为本发明的信息防篡改系统在首次读出操作时的状态示意图；
图4显示为本发明的信息防篡改系统在再次读出操作时的状态示意图；
图5显示为本发明的信息防篡改方法于一实施例中的流程图。
元件标号说明
1        存储模块
2        写模块
3        第一读模块
4        第二读模块
5        第一OTP开关
6        第二OTP开关
7        第三OTP开关
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。需说明的是，在不冲突的情况下，以下实施例及实施例中的特征可以相互组合。
需要说明的是，以下实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
如图1所示，于一实施例中，本发明的信息防篡改系统包括存储模块1、写模块2、第一读模块3和第二读模块4。所述写模块2通过第一OTP开关5与所述存储模块连接1，所述第一读模块3通过第二OTP开关6与所述存储模块1连接，所述第二读模块4通过第三OTP开关7与所述存储模块1连接。其中，在初始状态下，所述第一OTP开关5和所述第二OTP开关6均为闭合状态，所述第三OTP开关7为断开状态。
所述OTP开关是通过编程仅能够执行一次闭合操作或断开操作的开关，所述闭合操作和所述断开操作在物理上是不可逆的。具体地，所述OTP开关仅能够进行一次编程，其可以从1改写成0，也可以从0改写成1；一次改写完成之后，无法再将0改写成1，将1改写成0。 于本发明一实施例中，所述第一OTP开关、所述第二OTP开关和所述第三OTP开关均采用efuse存储器。efuse存储器类似于EEPROM。不同的是，efuse存储器是一次性可编程存储器，通过一根熔丝进行编程。其中，一个持续200微秒的10毫安直流脉冲就足以编程单根熔丝。通过所述熔丝的通断能够实现开关的闭合和断开。
如图2所示，当需要进行信息的写入时，由于所述第一OTP开关5处于闭合状态，所述写模块2直接将源信息写入所述存储模块1。同时，由于所述第二OTP开关6也处于闭合状态，所述第一读模块3直接从所述存储模块1中读出所述存储模块1中的写入信息，以验证所述写入信息是否与所述源信息一致。如图3所示，若二者一致，则表示此次写操作无误，断开所述第一OTP开关5及第二OTP开关6；若二者不一致，则表示此次写操作有误，可重新基于所述写模块2进行所述源信息的写入，基于所述第一读模块3进行所述写入信息的读出，直至所述源信息和所述写入信息一致，并断开所述第一OTP开关5及第二OTP开关6。通过上述操作，可保证所述源信息的准确写入，且由于所述第一OTP开关5及第二OTP开关6的断开，无法对所述存储模块1进行再次写入，从而避免了信息的篡改和窃取。
如图4所示，当需要对所述存储模块1中的存储信息进行读出时，由于所述第三OTP开关7处于断开状态，故首先需闭合所述第三OTP开关7，再通过所述第二读模块4从所述存储模块1中读出其上的存储信息。由于所述第三OTP开关7仅可单次闭合，故所述存储模块1中的信息仅可被读出一次，有效避免了信息的窃取。若在读出所述存储信息之前，所述第三OTP开关7已经闭合，则可证明所述存储模块1中的存储数据被非法读取。
特别地，在芯片制造使用流程中，芯片的安全信息直接影响到芯片本身的可用性，故需要进行安全传输。在芯片制造使用流程中，通常需要进行CP(Chip Probe，晶圆测试)测试、封装、FT(Final test，最终测试)测试后送达终端用户。其中，CP测试是封装前在晶圆阶段对芯片测试；FT测试是封装完成后进行的测试。于本发明一实施例中，本发明的信息防篡改系统应用于芯片制造使用流程中。其中，芯片的安全信息作为所述源信息。所述写模块用于在芯片CP或FT测试阶段将所述源信息写入所述存储模块；所述第一读模块用于在所述芯片CP或FT测试阶段读出所述存储模块中的写入信息，并在确认所述写入信息准确无误后断开所述第一OTP开关及第二OTP开关；所述第二读模块用于在芯片使用阶段在所述第三OTP开关闭合后读出所述存储模块中的存储信息。因此，无论是在芯片的CP测试阶段还是FT测试阶段，均可以通过所述第一OTP开关及所述第二OTP开关实现安全信息的准确写入，且仅能够在终端用户处通过所述第三OTP开关实现所述安全信息的读出。该方法在CP或FT写入及确认信息的时候可以监控并确认之前的流程(晶圆制造、运输等)中有无非法 的信息写入；在终端用户处可以监控CP或FT之后到终端用户的所有流程(封装、运输、初始化等)有无信息的篡改，并且防止了所有中间流程中信息的窃取，实现防窃取和防篡改的目的。
为了进一步保证本发明的信息防篡改系统中的源信息的传输的安全性，于本发明一实施例中，所述写模块2还用于根据所述源信息生成第一哈希码；所述第二读模块4还用于根据所述存储信息生成第二哈希码，并比对所述第一哈希码和所述第二哈希码以确定所述源信息和所述存储信息是否一致。也就是说，所述写模块2在写入所述源信息时，首先通过哈希加密算法将所述源信息转换为对应的哈希码。哈希加密算法能够将任意长度的输入通过散列算法变换成固定长度的输出，该输出就是散列值。这种转换是一种压缩映射，也就是，散列值的空间通常远小于输入的空间。通过所述哈希加密函数，能够将所述源数据压缩为唯一的第一哈希码。所述第二读模块4在读出所述存储信息之后，同样采用所述哈希加密算法对所述存储信息进行加密，进而获取所述第二哈希码。其中，第一哈希码通过明文传送给终端用户，第二哈希码在终端客户处生成。通过比对所述第一哈希码和所述第二哈希码，可以判断所述存储信息是否与所述源信息相一致。若所述存储信息与所述源信息相一致，表示所述源信息准确无误地进行传输，没有发生篡改；若所述存储信息与所述源信息不相一致，则表明所述源信息发生了篡改。
于本发明一实施例中，所述第一读模块3和所述第二读模块4可集成为一体，通过所述第二OTP开关6和所述第三OTP开关7与所述存储模块1连接。也就是说，所述信息防篡改系统只需提供一个读模块即可，该读模块具有两次数据读出功能，一次用于验证写入信息的准确性，一次用于读出存储信息。通过上述结构，进一步简化了系统架构，降低了成本。
于本发明一实施例中，所述存储模块1采用OTP存储模块或MTP(Multi Time Program，多次编程)或闪存(flash)存储模块，可根据不同的应用场景进行选择。
如图5所示，于一实施例中，本发明的信息防篡改方法应用于信息防篡改系统，所述信息防篡改系统包括存储模块、写模块、第一读模块和第二读模块；所述写模块、所述第一读模块和所述第二读模块分别通过第一OTP开关、第二OTP开关和第三OTP开关与所述存储模块连接。其中，在初始状态下，所述第一OTP开关和所述第二OTP开关均为闭合状态，所述第三OTP开关为断开状态。
所述信息防篡改方法包括以下步骤：
步骤S1、基于所述写模块通过所述第一OTP开关将源信息写入所述存储模块。
如图2所示，当需要进行信息的写入时，由于所述第一OTP开关处于闭合状态，所述写 模块直接将源信息写入所述存储模块。
步骤S2、基于所述第一读模块通过所述第二OTP开关读出所述存储模块中的写入信息，并在确认所述写入信息准确无误后断开所述第一OTP开关及第二OTP开关。
同时，由于所述第二OTP开关6也处于闭合状态，所述第一读模块直接从所述存储模块中读出所述存储模块中的写入信息，以验证所述写入信息是否与所述源信息一致。如图3所示，若二者一致，则表示此次写操作无误，断开所述第一OTP开关及第二OTP开关；若二者不一致，则表示此次写操作有误，可重新基于所述写模块进行所述源信息的写入，基于所述第一读模块进行所述写入信息的读出，直至所述源信息和所述写入信息一致，并断开所述第一OTP开关及第二OTP开关。通过上述操作，可保证所述源信息的准确写入，且由于所述第一OTP开关及第二OTP开关的断开，无法对所述存储模块进行再次写入，从而避免了信息的篡改和窃取。
步骤S3、基于所述第二读模块在所述第二OTP开关闭合后读出所述存储模块中的存储信息。
如图4所示，当需要对所述存储模块中的存储信息进行读出时，由于所述第三OTP开关处于断开状态，故首先需闭合所述第三OTP开关，再通过所述第二读模块从所述存储模块中读出其上的存储信息。由于所述第三OTP开关仅可单次闭合，故所述存储模块中的信息仅可被读出一次，有效避免了信息的窃取。若在读出所述存储信息之前，所述第三OTP开关已经闭合，则可证明所述存储模块中的存储数据被非法读取。
特别地，在芯片制造使用流程中，芯片的安全信息直接影响到芯片本身的可用性，故需要进行安全传输。在芯片制造使用流程中，通常需要进行CP(Chip Probe，晶圆测试)测试、封装、FT(Final test，最终测试)测试后送达终端用户。其中，CP测试是封装前在晶圆阶段对芯片测试；FT测试是封装完成后进行的测试。于本发明一实施例中，本发明的信息防篡改系统应用于芯片制造使用流程中。其中，芯片的安全信息作为所述源信息。所述写模块用于在芯片CP或FT测试阶段将所述源信息写入所述存储模块；所述第一读模块用于在所述芯片CP或FT测试阶段读出所述存储模块中的写入信息，并在确认所述写入信息准确无误后断开所述第一OTP开关及第二OTP开关；所述第二读模块用于在芯片使用阶段在所述第三OTP开关闭合后读出所述存储模块中的存储信息。因此，无论是在芯片的CP测试阶段还是FT测试阶段，均可以通过所述第一OTP开关及所述第二OTP开关实现安全信息的准确写入，且仅能够在终端用户处通过所述第三OTP开关实现所述安全信息的读出。该方法在CP或FT写入及确认信息的时候可以监控并确认之前的流程(晶圆制造、运输等)中有无非法的信息写 入；在终端用户处可以监控CP或FT之后到终端用户的所有流程(封装、运输、初始化等)有无信息的篡改，并且防止了所有中间流程中信息的窃取，实现防窃取和防篡改的目的。
为了进一步保证本发明的信息防篡改系统中的源信息的传输的安全性，于本发明一实施例中，所述写模块还根据所述源信息生成第一哈希码；所述第二读模块还根据所述存储信息生成第二哈希码，并比对所述第一哈希码和所述第二哈希码以确定所述源信息和所述存储信息是否一致。也就是说，所述写模块在写入所述源信息时，首先通过哈希加密算法将所述源信息转换为对应的哈希码。哈希加密算法能够将任意长度的输入通过散列算法变换成固定长度的输出，该输出就是散列值。这种转换是一种压缩映射，也就是，散列值的空间通常远小于输入的空间。通过所述哈希加密函数，能够将所述源数据压缩为唯一的第一哈希码。所述第二读模块在读出所述存储信息之后，同样采用所述哈希加密算法对所述存储信息进行加密，进而获取所述第二哈希码。其中，第一哈希码通过明文传送给终端用户，第二哈希码在终端客户处生成。通过比对所述第一哈希码和所述第二哈希码，可以判断所述存储信息是否与所述源信息相一致。若所述存储信息与所述源信息相一致，表示所述源信息准确无误地进行传输，没有发生篡改；若所述存储信息与所述源信息不相一致，则表明所述源信息发生了篡改。
于本发明一实施例中，所述第一读模块和所述第二读模块可集成为一体，通过所述第二OTP开关和所述第三OTP开关与所述存储模块连接。也就是说，所述信息防篡改系统只需提供一个读模块即可，该读模块具有两次数据读出功能，一次用于验证写入信息的准确性，一次用于读出存储信息。通过上述结构，进一步简化了系统架构，降低了成本。
于本发明一实施例中，所述存储模块采用OTP存储模块或MTP存储模块或闪存(flash)存储模块，可根据不同的应用场景进行选择。
综上所述，本发明的信息防篡改系统及方法通过采用OTP开关来控制信息的有限次数的写入和读出；通过哈希加密算法保证了信息传输的安全性；对硬件配置要求低，具有广泛的应用场景；有效避免了信息的窃取和篡改，保证了信息的安全传输。所以，本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (14)

  1. 一种信息防篡改系统，其特征在于，所述系统包括存储模块、写模块、第一读模块和第二读模块；
    所述写模块通过第一OTP开关与所述存储模块连接，用于将源信息写入所述存储模块；
    所述第一读模块通过第二OTP开关与所述存储模块连接，用于读出所述存储模块中的写入信息，并在确认所述写入信息准确无误后断开所述第一OTP开关及第二OTP开关；
    所述第二读模块通过第三OTP开关与所述存储模块连接，用于在所述第三OTP开关闭合后读出所述存储模块中的存储信息；
    其中，所述第一OTP开关、所述第二OTP开关和所述第三OTP开关仅能够单次执行闭合操作或断开操作。
  2. 根据权利要求1所述的信息防篡改系统，其特征在于：所述系统应用于芯片制造使用流程中，所述芯片的安全信息作为所述源信息；
    所述写模块用于在芯片CP或FT测试阶段将所述源信息写入所述存储模块；
    所述第一读模块用于在所述芯片CP或FT测试阶段读出所述存储模块中的写入信息，并在确认所述写入信息准确无误后断开所述第一OTP开关及第二OTP开关；
    所述第二读模块用于在芯片使用阶段在所述第三OTP开关闭合后读出所述存储模块中的存储信息。
  3. 根据权利要求2所述的信息防篡改系统，其特征在于：所述写模块还用于根据所述源信息生成第一哈希码；所述第二读模块还用于根据所述存储信息生成第二哈希码，并比对所述第一哈希码和所述第二哈希码以确定所述源信息和所述存储信息是否一致。
  4. 根据权利要求2所述的信息防篡改系统，其特征在于：所述第一读模块和所述第二读模块集成为一体，通过所述第二OTP开关和所述第三OTP开关与所述存储模块连接。
  5. 根据权利要求2所述的信息防篡改系统，其特征在于：所述存储模块采用OTP存储模块或MTP存储模块。
  6. 根据权利要求2所述的信息防篡改系统，其特征在于：所述第一OTP开关和所述第二 OTP开关的初始状态为闭合；所述第三OTP开关的初始状态为断开。
  7. 根据权利要求2所述的信息防篡改系统，其特征在于：所述第一OTP开关、所述第二OTP开关和所述第三OTP开关均采用efuse存储器。
  8. 一种信息防篡改方法，其特征在于：所述方法应用于信息防篡改系统，所述信息防篡改系统包括存储模块、写模块、第一读模块和第二读模块；所述写模块、所述第一读模块和所述第二读模块分别通过第一OTP开关、第二OTP开关和第三OTP开关与所述存储模块连接；
    所述信息防篡改方法包括以下步骤：
    基于所述写模块通过所述第一OTP开关将源信息写入所述存储模块；
    基于所述第一读模块通过所述第二OTP开关读出所述存储模块中的写入信息，并在确认所述写入信息准确无误后断开所述第一OTP开关及第二OTP开关；
    基于所述第二读模块在所述第二OTP开关闭合后读出所述存储模块中的存储信息；
    其中，所述第一OTP开关、所述第二OTP开关和所述第三OTP开关仅能够单次执行闭合操作或断开操作。
  9. 根据权利要求8所述的信息防篡改方法，其特征在于：所述方法应用于芯片制造使用流程中，所述芯片的安全信息作为所述源信息；
    所述写模块在芯片CP或FT测试阶段将所述源信息写入所述存储模块；
    所述第一读模块在所述芯片CP或FT测试阶段读出所述存储模块中的写入信息，并在确认所述写入信息准确无误后断开所述第一OTP开关及第二OTP开关；
    所述第二读模块在芯片使用阶段在所述第二OTP开关闭合后读出所述存储模块中的存储信息。
  10. 根据权利要求9所述的信息防篡改方法，其特征在于：所述写模块还用于根据所述源信息生成第一哈希码；所述第二读模块还用于根据所述存储信息生成第二哈希码，并比对所述第一哈希码和所述第二哈希码以确定所述源信息和所述存储信息是否一致。
  11. 根据权利要求9所述的信息防篡改方法，其特征在于：所述第一读模块和所述第二读模块集成为一体，通过所述第二OTP开关和所述第三OTP开关与所述存储模块连接。
  12. 根据权利要求9所述的信息防篡改方法，其特征在于：所述存储模块采用OTP存储模块或MTP存储模块。
  13. 根据权利要求9所述的信息防篡改方法，其特征在于：所述第一OTP开关和所述第二OTP开关的初始状态为闭合；所述第三OTP开关的初始状态为断开。
  14. 根据权利要求9所述的信息防篡改方法，其特征在于：所述第一OTP开关、所述第二OTP开关和所述第三OTP开关均采用efuse存储器。
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