WO2021128217A1 - Système et procédé de recherche de données - Google Patents

Système et procédé de recherche de données Download PDF

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Publication number
WO2021128217A1
WO2021128217A1 PCT/CN2019/128897 CN2019128897W WO2021128217A1 WO 2021128217 A1 WO2021128217 A1 WO 2021128217A1 CN 2019128897 W CN2019128897 W CN 2019128897W WO 2021128217 A1 WO2021128217 A1 WO 2021128217A1
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target
data
area
memory
length
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PCT/CN2019/128897
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English (en)
Chinese (zh)
Inventor
王锦
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华为技术有限公司
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Priority to CN201980102169.9A priority Critical patent/CN114730322B/zh
Priority to PCT/CN2019/128897 priority patent/WO2021128217A1/fr
Publication of WO2021128217A1 publication Critical patent/WO2021128217A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks

Definitions

  • This application relates to the field of electronic science and technology, and in particular to a data search system and a data search method.
  • Branch accelerators are mostly used to provide auxiliary functions for branch acceleration for processors that support multithreading.
  • the branch accelerator includes a first memory and a second memory.
  • the first memory is used to store multiple key entries (keys) that may exist for multiple conditional instructions.
  • the second memory is used to store multiple associated data (AD) corresponding to the multiple key entries in a one-to-one manner.
  • the multiple key entries of each conditional instruction have a one-to-one correspondence with the multiple AD data of the conditional instruction in the second memory through multiple position indexes.
  • the multiple location indexes may respectively indicate the storage addresses of the multiple AD data in the second memory.
  • the processor When the processor reaches the target conditional instruction, it can send the target key entry to the branch accelerator.
  • the branch accelerator can find the storage location of the target key entry in the first memory, and then obtain the target location index corresponding to the target key entry according to the maximum storage length mapping relationship between the first memory and the second memory. After that, the branch accelerator may obtain the target data from the plurality of AD data stored in the second memory according to the target position index. Then, the branch accelerator can send the target data to the processor.
  • the processor can process other threads in parallel during the execution of the above actions by the branch accelerator, and after receiving the target data returned by the branch accelerator, continue to execute the thread where the target conditional instruction is located according to the target data, thereby realizing branch acceleration.
  • the maximum storage length of the first memory is 40 bits
  • the maximum storage length of the second memory is 16 bits. It is assumed that a storage space of 40 ⁇ 20 bit 2 is configured in the first memory, and the storage width of the storage space is 20 bits. Then, according to the mapping relationship, a 16 ⁇ 20 bit 2 storage space will be configured in the second memory. If the first memory stores both a 40-bit key entry and an 80-bit key entry, each of the 80-bit key entry will occupy a storage width of 2 bits. Each 80-bit key entry actually corresponds to only one AD data, which only needs to occupy a storage space with a storage width of 1 bit in the second memory. In this case, each 80-bit key entry will waste storage space with a storage width of 1 bit in the second memory.
  • the maximum storage length of the first memory is configured to be 80 bits, and the maximum storage length of the second memory is 16 bits.
  • the first memory stores both 40-bit key entries and 80-bit key entries, although the storage resources of the second memory can be fully utilized, each A 40-bit length key entry will also occupy 80 ⁇ 1bit 2 storage space, so the storage space in the first memory will be wasted.
  • the storage density of the memory (the first memory and/or the second memory) in the current branch accelerator is not high, and further research is needed.
  • This application provides a data search system and a data search method to improve the storage density of the memory in the data search system.
  • an embodiment of the present application provides a data search system.
  • the data search system may be a branch accelerator or a chip integrated with the branch accelerator.
  • the data search system provided in the embodiments of the present application may include: a controller, a first memory, and a second memory, where the first memory is a content addressable memory (CAM); the first memory includes Multiple key key areas, where each key area includes multiple key entries; the second memory includes multiple associated data AD areas, where each AD area includes multiple AD data; the controller can receive for searching The target key entry and location indication information of the target data, the location indication information can indicate the target key area and the target AD area associated with the target data; the controller can use the target key entry to perform a matching search in the target key area to obtain a match The position of the entry; the controller can then obtain the target data from the target AD area according to the position of the matching entry.
  • CAM content addressable memory
  • the controller can determine the target key area from the first memory according to the location indication information, and then the relative position of the target key entry in the target key area can be obtained. It is the position of the matching table entry.
  • the position indication information may indicate the target AD area, so the controller may determine the target AD area from the second memory according to the position indication information.
  • the first memory in the embodiment of the present application is a CAM memory
  • the matching entry position of the target key entry in the target key area may be equivalent to the relative position of the target data in the target AD area.
  • the controller can obtain the target data from the target AD area according to the position of the matched entry.
  • the controller no longer needs to calculate the location index of the target data according to the mapping relationship between the maximum storage length of the first memory and the maximum storage length of the second memory. Therefore, the first memory can be flexibly configured according to actual application scenarios.
  • the storage space of the memory and the second memory further helps to increase the storage density of the first memory and/or the second memory when the lengths of the key entries in the first memory are inconsistent.
  • the above-mentioned target key entry can be used to execute the target conditional instruction.
  • the data search system provided by the embodiment of the present application further includes a processor.
  • the processor can obtain the above-mentioned position indication information according to the configuration information of the first memory and the second memory, and the target condition instruction, wherein the configuration information includes multiple conditions.
  • the corresponding relationship between the instruction, multiple key areas and multiple AD areas, the key area corresponding to the target conditional instruction is the aforementioned target key area, and the AD area corresponding to the target conditional instruction is the aforementioned target AD area;
  • the processor further controls The device sends the target key entry and location indication information.
  • the controller, the first memory, and the second memory can be used as branch accelerators to provide auxiliary functions of branch acceleration for the processor.
  • the controller may also send target data to the processor. After receiving the target data, the processor can continue to execute the above-mentioned target conditional instruction according to the target data.
  • the target data may be an instruction counter
  • the target conditional instruction includes multiple branch instructions
  • the processor may obtain the branch instruction corresponding to the target data in the target conditional instruction, and continue to execute the branch instruction.
  • the processor may also receive the foregoing configuration information.
  • the storage space of the first memory and the second memory may be configured by a device installed with a compiler according to multiple conditional instructions that may be executed by the processor.
  • the device installed with the compiler may be the processor itself, or other devices other than the processor, which is not limited in the embodiment of the present application.
  • the device can send the configuration information of the first memory and the second memory to the processor, and the processor can according to the received configuration The information instructs the controller to look for data.
  • the configuration information may also include depth information of multiple key areas; the processor may also obtain the depth information of the target key area according to the configuration information, and send the depth information to the controller; the controller may also According to the position indication information and the depth information, the target key area is determined from the first memory, and the target AD area is determined from the second memory.
  • the depth information can be understood as the number of key entries in the target key area.
  • the number of key entries in the target key area is the same as the number of AD data in the target AD area, so the depth information can also be understood as the number of AD data in the target AD area. Therefore, when the controller searches for the target key area, it can respectively determine the target key area from the first memory and the target AD area from the second memory according to the position indication information and the depth information.
  • the configuration information further includes the storage length of multiple key areas; the processor may also determine the storage length corresponding to the target key area according to the configuration information, and send the first length indication information to the controller.
  • the first length indication information may indicate the storage length of the target key area; the controller may determine the target key area from the first memory according to the position indication information, the depth information, and the first length indication information.
  • each AD area one or more AD data are located in the same row of memory cells in the second memory. Adopting the storage method provided by the embodiment of the present application is beneficial to further increase the storage density of the second memory.
  • the configuration information further includes length information of each AD data in each AD area; the processor may also obtain an AD length message corresponding to the target AD area according to the configuration information, where the AD length The message includes data length information of one or more AD data in the target AD area, and each data length information is used to indicate the data length of the AD data corresponding to each data length information; the AD length message is sent to the controller.
  • the processor in the embodiment of the present application sends an AD length message to the controller, so that the controller can distinguish the target data from other data according to the AD length message, so that the target data can be obtained.
  • the configuration information may also include the starting storage address of each key area and the starting storage address of each AD area; the above position indication information may include the starting storage address of the target key area and The start storage address of the target AD area.
  • the controller can obtain the data length of the AD data before the target data in the AD length message according to the position of the matched entry; according to the start storage address of the target AD area, and the AD before the target data
  • the data length of the data determines the starting storage address of the target data; according to the starting storage address of the target data, the target data is obtained from the target AD area.
  • the processor may also determine the data length of the target data according to the configuration information, and send second length indication information to the controller, where the second length indication information may indicate the data length of the target data;
  • the controller can obtain the target data from the target AD area according to the starting storage address of the target data and the data length of the target data.
  • an embodiment of the present application provides a data search method, which can be applied to the data search system provided in any one of the first aspects.
  • the data search method provided in the embodiment of the present application mainly includes: the controller receives a target key entry used to search the target data and position indication information, and the position indication information is used to indicate the data associated with the target data in the first memory.
  • the first memory is the content addressable memory CAM.
  • the first memory includes multiple key key areas, where each key area includes multiple key tables.
  • the second memory includes multiple associated data AD areas, where each AD area includes multiple AD data; the controller uses the target key entry to perform a matching search in the target key area to obtain the location of the matching entry; the controller According to the position of the matched entry, the target data is obtained from the target AD area.
  • the target key entry is used to execute the target conditional instruction
  • the controller receives the target key entry and the position indication information used to find the target data
  • it further includes: the processor according to the first memory and the first memory 2.
  • the configuration information includes the correspondence between multiple conditional instructions, multiple key areas and multiple AD areas.
  • the key area corresponding to the target conditional instruction is the target key area.
  • the AD area corresponding to the target conditional instruction is the target AD area; the processor sends the target key entry and position indication information to the controller.
  • the method further includes: the controller sends the target data to the processor.
  • the method before the processor obtains the location indication information according to the configuration information of the first memory and the second memory and the target condition instruction, the method further includes: the processor receives the configuration information.
  • the configuration information further includes depth information of multiple key areas; the controller uses the target key entry to perform a matching search in the target key area, and before obtaining the position of the matching entry, it also includes: a processor According to the configuration information, obtain the depth information of the target key area and send the depth information to the controller; the controller determines the target key area from the first memory and the target AD area from the second memory according to the position indication information and the depth information .
  • the configuration information further includes the storage length of multiple key areas; the controller uses the target key entry to perform a matching search in the target key area, and before obtaining the position of the matching entry, it also includes: a processor According to the configuration information, the storage length corresponding to the target key area is determined, and the first length indication information is sent to the controller.
  • the first length indication information is used to indicate the storage length of the target key area; the controller reads from the position indication information and depth information. Determining the target key area in the first memory includes: the controller determines the target key area from the first memory according to the position indication information, the depth information, and the first length indication information.
  • each AD area one or more AD data are located in the same row of memory cells in the second memory.
  • the configuration information also includes length information of each AD data in each AD area; before the controller obtains the target data from the target AD area according to the matching entry position, it also includes: processing The device obtains the AD length message corresponding to the target AD area according to the configuration information.
  • the AD length message includes data length information of one or more AD data in the target AD area, where each data length information is used to indicate each data length information The data length of the corresponding AD data; the processor sends an AD length message to the controller.
  • the configuration information also includes the starting storage address of each key area and the starting storage address of each AD area; the location indication information includes the starting storage address of the target key area and the target AD area The starting storage address.
  • the controller obtains the target data from the target AD area according to the position of the matching entry, including: obtaining the data length of the AD data before the target data in the AD length message according to the position of the matching entry ; According to the starting storage address of the target AD area and the data length of the AD data before the target data, the starting storage address of the target data is determined; according to the starting storage address of the target data, the target data is obtained from the target AD area.
  • the controller before the controller obtains the target data from the target AD area according to the position of the matched table entry, it further includes: the processor determines the data length of the target data according to the configuration information, and sends the first data length to the controller. Two length indication information, the second length indication information is used to indicate the data length of the target data; obtaining the target data from the target AD area according to the starting storage address of the target data, including: the controller according to the starting storage address of the target data, According to the data length of the target data, the target data is obtained from the target AD area.
  • FIG. 1 is a schematic structural diagram of a data search system provided by an embodiment of this application.
  • FIG. 2 is a schematic diagram of a storage structure of a first memory provided by an embodiment of the application
  • FIG. 3 is a schematic diagram of a storage structure of a key area provided by an embodiment of the application.
  • FIG. 4 is a schematic diagram of a storage structure of a second memory provided by an embodiment of the application.
  • FIG. 5 is a schematic flowchart of a data search method provided by an embodiment of the application.
  • FIG. 6 is a schematic diagram of a correspondence relationship between a data length and a length identifier provided by an embodiment of this application;
  • FIG. 7 is a schematic structural diagram of an AD length message provided by an embodiment of this application.
  • FIG. 8 is a schematic diagram of a Kswitch instruction structure provided by an embodiment of the application.
  • the memory in the embodiments of the present application can be understood as a two-dimensional storage array
  • the storage length of any data can be understood as the number of bits occupied by the data in the length direction of the storage array (the row direction of the storage array) .
  • the storage width corresponding to the storage length can be understood as the number of bits occupied by data in the width direction of the storage array (column direction of the storage array).
  • the storage length and storage width of any data define the storage space of the data.
  • the following embodiments of this application use a ⁇ b bit 2 to represent the size of the storage space, where a represents the number of bits in the length direction of the storage space, that is, the storage length, and b represents the number of bits in the width direction of the storage space. It is the storage width.
  • Fig. 1 exemplarily shows a schematic structural diagram of a data search system provided by an embodiment of the present application.
  • the data search system can be a branch accelerator, a chip integrated with a branch accelerator, or a system-on-chip.
  • the data search system in the embodiment of the present application may be a processing chip with a large amount of calculation such as a central processing unit (CPU), a graphics processing unit (GPU), the processor 100, and a branch accelerator. 200 is integrated in the chip to increase the computing speed of the chip.
  • CPU central processing unit
  • GPU graphics processing unit
  • 200 is integrated in the chip to increase the computing speed of the chip.
  • the data search system includes a controller 201, a first memory 202 and a second memory 203.
  • the controller 201 is connected to the first memory 202 and the second memory 203 respectively.
  • the controller 201 includes a control circuit of the first memory 202 and a control circuit of the second memory 203.
  • the controller 201 can search for the first memory 202 and the second memory 203. Storage 203.
  • the data search system may further include a processor 100.
  • the processor 100 may be a logic circuit with computing capability.
  • the processor 100 may include an arithmetic and logic unit (ALU), and arithmetic operations, logic operations, and other operational functions can be implemented through the ALU.
  • ALU arithmetic and logic unit
  • the processor 100 and the controller 201 may be interconnected through a control bus, so that information can be transferred between the processor 100 and the branch accelerator 200.
  • conditional instruction may include multiple branch instructions.
  • Common conditional instructions include switch instructions, multiple nested instructions composed of multiple if (if) and otherwise (else), and so on.
  • switch instructions multiple nested instructions composed of multiple if (if) and otherwise (else), and so on.
  • multi-level nested instruction composed of multiple if and else as an example its pseudo code can be expressed as:
  • the conditional instruction includes 4 key entries, which are key entries 1 to 4, respectively.
  • the key entry 4 can be understood as the only entry after the key entries 1 to 3 are excluded, so it is not directly shown in the embodiment of the present application.
  • key entry 1 corresponds to branch instruction 1
  • key entry 2 corresponds to branch instruction 2
  • key entry 3 corresponds to branch instruction 3
  • key entry 4 (else) corresponds to branch instruction 4. .
  • the processor 100 often obtains the target key entry before running the above-mentioned conditional instruction. For example, the processor 100 may generate the target key entry, or may receive the target key entry input by other devices. No restrictions.
  • the processor 100 may execute a CMP (compare) instruction to match the target key table entry with key table entries 1 to 4 one by one until the matching is successful.
  • CMP compute
  • the processor 100 can continue to execute the branch instruction 2.
  • the use of a data search system integrated with a branch accelerator can save the computational pressure on the processor 100 caused by conditional instructions and help improve the computational speed and multi-thread processing capability of the processor 100.
  • the controller 201 may receive the target key entry sent by the processor 100, and search the first memory 202 and the second memory 203 according to the received target key entry, so as to obtain the target data corresponding to the target key entry.
  • the target data corresponding to the target key entry may be a target branch instruction corresponding to the target key entry, or an instruction counter (program counter, PC) corresponding to the target key entry and the target branch instruction in a possible embodiment. ), the embodiment of the application does not limit this.
  • the target data is a PC
  • the processor 100 stores multiple branch instructions. After receiving the target data returned by the controller 201, the processor 100 can read and execute the target data from the stored branch instructions according to the target data.
  • the corresponding branch instruction is the target branch instruction.
  • the first memory 202 may be a content addressable memory (Content Addressable Memory, CAM), and currently more common is a ternary content addressable memory (TCAM).
  • CAM Content Addressable Memory
  • TCAM ternary content addressable memory
  • a plurality of groups are stored in the first memory 202. Each group corresponds to a conditional instruction. For each group, multiple key entries of the conditional command corresponding to the group are included. Exemplarily, assuming that the conditional instruction is a switch instruction, the storage structure of the first memory may be as shown in Table 1 below:
  • M groups are stored in the first memory 202, such as group 1, group 2, ..., group M, where M is an integer greater than 1.
  • M groups correspond to M switch commands, for example, group 1 corresponds to switch command 1, group 2 corresponds to switch command 2, and group M corresponds to switch command M.
  • the key of the switch instruction may have multiple key entries, and the multiple key entries respectively correspond to multiple branch instructions of the switch instruction.
  • the switch instruction 1 in Table 1 Take the switch instruction 1 in Table 1 as an example.
  • the key of switch instruction 1 includes 16 key entries (key entry 11, key entry 12, ..., key entry 116), and the 16 key entries are the same as switch
  • the 16 branch instructions of instruction 1 correspond one-to-one. The same is true for switch instruction 2 to switch instruction M, and will not be repeated here.
  • each key entry in each group can achieve a one-to-one correspondence with the AD data in the second memory 203 through a location index.
  • the key entry 11 in group 1 can correspond to the AD data 11 in the second storage 203 through the position index 11, that is, the key entry 11 is stored in the first storage 202.
  • the key entry 11 corresponds to the position index 11.
  • AD data 11 is stored, and the AD data 11 also corresponds to the position index 11.
  • the correspondence between the key entry 11 and the position index 11 may be the storage address of the controller 201 according to the key entry 11, and between the maximum storage length of the first memory 202 and the maximum storage length of the second memory 203
  • the mapping relationship is calculated.
  • the corresponding relationship between the position index 11 and the AD data 11 can be understood as that the position index 11 can indicate the storage address of the AD data 11 in the second memory 203, that is, the controller 201 can determine the AD data according to the position index 11. 11 is the storage address in the second memory 203, so that the AD data 11 can be read.
  • the processor 100 When the processor 100 executes the conditional instruction, it can send the target key entry to the branch accelerator 200, and the controller 201 can search the first memory 202 according to the target key entry. After hitting the target key entry, assuming that the key entry 11 hits the target key entry, according to the storage address of the key entry 11 in the first memory 202, and the maximum storage length of the first memory 202 and the second memory 203 The mapping relationship between the maximum storage length of, the position index 11 is calculated. The controller 201 reads the AD data 11 from the second memory 203 according to the position index 11.
  • the controller 201 returns the AD data 11 to the processor 100, and the processor 100 can obtain the branch instruction corresponding to the AD data 11 according to the AD data 11, and continue to execute the branch instruction. It can be seen from the above process that the branch accelerator 200 can replace the processor 100 to determine the AD data corresponding to the target key entry, so the process of executing the CMP instruction by the processor 100 can be omitted, which is beneficial to reduce the calculation of the processor 100 when executing conditional instructions. pressure.
  • the data length of multiple key entries therein is the same.
  • the data length of the key table entry may be different.
  • the mapping relationship between the maximum storage length of the first memory 202 and the maximum storage length of the second memory 203 needs to be maintained.
  • the data lengths of the key entries stored in the first memory 202 are not the same, which will result in the first memory 202.
  • the storage resources of the first memory 202 and/or the second memory 203 are wasted, and the storage density of the first memory 202 and/or the second memory 203 needs to be further improved.
  • the first storage 202 is configured with a maximum storage length, and the maximum storage length limits the storage length of a key entry in the first storage 202.
  • the maximum storage length limits the storage length of a key entry in the first storage 202.
  • the maximum storage length is 40 bits
  • the maximum storage length For an 80-bit key entry, it occupies 40 ⁇ 2bit 2 storage space.
  • the second memory 203 is also configured with a maximum storage length, which limits the maximum storage length of AD data in the second memory 203, and a 1-bit storage width can only store one AD data.
  • the mapping relationship between the maximum storage length of the first storage 202 and the maximum storage length of the second storage 203 will limit the first storage 202 and/or The storage density of the second memory is further improved.
  • the data length of key entries 11 to 116 in group 1 is 40 bits
  • the length of key entries 21 to 216 in group 2 is 80 bits.
  • the first memory 202 is configured with a 2000bit 2 storage space, where the maximum storage width is 50bit, and can store a total of 2000bit key entry data.
  • the second memory 203 is configured with 800bit 2 (16 ⁇ 50bit 2 ) storage space.
  • group 1 is mapped to the second memory 203 with a 16 ⁇ 16 bit 2 storage space
  • group 2 is mapped to the second memory 203 with a 16 ⁇ 32 bit 2 storage space.
  • Table 1 it can be seen that both group 1 and group 2 include 16 key entries, that is, group 2 only needs to use the storage space of 16 ⁇ 16bit 2 in the second memory 203. Therefore, some storage resources in the second memory 203 are wasted, resulting in a lower storage density of the second memory 203.
  • the maximum storage length of the first memory 202 is 80 bits, and the maximum storage length of the second memory 203 is 16 bits.
  • the second memory 203 is configured with a storage space of 800 bit 2 (16 ⁇ 50 bit 2 ), and the first memory 202 is configured with a storage space of 4000 bit 2 (80 ⁇ 50 bit 2 ).
  • group 1 is mapped in the second memory 203 has a memory space of 16 ⁇ 16bit 2
  • group2 mapped in the second memory 203 has a memory space of 16 ⁇ 16bit 2.
  • the storage resources of the second memory 203 are not wasted, in the first memory 202, the total amount of data in group 1 is 40 ⁇ 16bit, but it occupies the storage space of 80 ⁇ 16bit 2 , so it will waste the first memory.
  • the storage resources of the memory 202 cause the storage density of the first memory 202 to be low.
  • the storage density of the memory (the first memory 202 and/or the second memory 203) in the current data search system needs to be further improved.
  • the embodiment of the present application provides a data search system. Even if the maximum storage length of the first memory 202 and the maximum storage length of the second memory 203 no longer need to maintain a mapping relationship, the controller 201 can still find the target key table. According to the target data corresponding to the item, the storage structure of the first memory 202 and the second memory 203 can be configured more flexibly. Therefore, the embodiment of the present application is beneficial to improve the storage density of the first memory 202 and/or the second memory 203.
  • the first memory 202 in the embodiment of the present application stores multiple key areas (key areas A, B, C, D, XX, and YY), and each key area includes Multiple key entries.
  • the multiple key areas correspond to multiple conditional instructions. It should be pointed out that the multiple key areas and multiple conditional instructions can be one-to-one, one-to-many, and many-to-one. Any one of the corresponding relationships.
  • one-to-many can be understood as a key area corresponding to multiple conditional instructions.
  • multiple conditional instructions have the same key entry.
  • multiple conditional instructions can correspond to the same key area.
  • multiple conditional instructions corresponding to the same key area may have different branch instructions, that is, multiple conditional instructions corresponding to the same key area may also correspond to different AD areas.
  • Many-to-one can be understood as multiple key areas corresponding to the same conditional command.
  • multiple key entries of a conditional instruction can be divided into multiple key areas for storage.
  • key area A corresponds to instruction A
  • key area B corresponds to instruction B
  • key area C corresponds to instruction C
  • key area D corresponds to instruction D
  • key area XX corresponds to instruction XX
  • key area YY corresponds to instruction YY corresponds, where instruction A, instruction B, instruction C, instruction D, instruction XX, and instruction YY are all conditional instructions.
  • the second memory 203 stores multiple associated data (AD) areas, and each AD area includes multiple AD data.
  • AD associated data
  • the multiple AD areas correspond to multiple key areas in the first memory 202. It should be pointed out that there can be one-to-one or one-to-one relationship between multiple AD areas and multiple key areas. Either the corresponding relationship between many-to-many and many-to-one.
  • one-to-many can be understood as one AD area corresponding to multiple key areas.
  • multiple conditional instructions have different key entries but the same branch instruction.
  • the key areas corresponding to the multiple conditional instructions can correspond to the same AD area.
  • AD areas corresponding to the same key area.
  • multiple conditional instructions have the same key entry but different branch instructions.
  • the multiple conditional instructions can correspond to the same key area, but the key area can correspond to multiple ADs. area.
  • AD area corresponds to one key area.
  • key area A corresponds to AD area A
  • key area B corresponds to AD area B
  • key area C corresponds to AD area C
  • key area D corresponds to AD area D
  • key area XX corresponds to AD area XX
  • the key area YY corresponds to the AD area.
  • the key area A stores N key entries of the command A, and N is an integer greater than or equal to.
  • the AD area A stores N AD data of instruction A, and the N AD data corresponds to the N branch instructions of instruction A one-to-one.
  • the i-th key entry in the key area A corresponds to the i-th AD data in the AD area A, and i is an integer in [1,N]. That is to say, the N key entries in the key area A correspond to the N AD data in the AD area A, and the relative position of the i-th key entry in the key area A is the same as the i-th AD data The relative position in AD area A is the same.
  • FIG. 3 exemplarily shows the storage order of 8 key entries in the key area A.
  • the key area A includes 8 key entries, and the 8 key entries are sequentially stored in the order of A1 to A8.
  • FIG. 4 exemplarily shows the storage order of the 8 AD data (AD data 1 to 8) in the AD area A.
  • the 8 AD data in the AD area A are sequentially stored in the order of 1 to 8.
  • AD data 1 to 8 correspond to key entries A1 to A8 respectively, that is, key entry A1 corresponds to AD data 1, key entry A2 corresponds to AD data 2, and so on.
  • the foregoing storage order is defined on the basis of the reading order of the first memory 202 and the second memory 203.
  • the reading order of the first memory 202 and the second memory 203 is from left to right and from top to bottom.
  • the first memory 202 shown in FIG. 3 and the second memory 203 shown in FIG. 4 Have the same storage order.
  • the reading order of the first memory 202 and the second memory 203 may also be from right to left, from bottom to top, etc., which are not listed one by one in the embodiment of the present application.
  • the processor 100 may instruct the controller 201 to search for data according to the first memory 202 and the second memory 203.
  • the processor 100 may configure the storage structures of the first memory 202 and the second memory 203, or other devices may configure the storage structures of the first memory 202 and the second memory 203.
  • the storage structure of the first memory 202 and the second memory 203 may be configured by another device installed with a compiler. In this case, the device may send the configuration information of the first memory 202 and the second memory 203 to The processor 100 enables the processor 100 to instruct the controller 201 to search for data according to the configuration information.
  • the data search method provided in the embodiment of the present application may be as shown in FIG. 5, and mainly includes the following steps:
  • the processor 100 sends the target key entry and location indication information to the controller 201.
  • the target key entry may be a key entry used to execute the target conditional instruction.
  • the location indication information may indicate the target key area and the target AD area.
  • the target key area can be understood as the key area corresponding to the target conditional instruction in the first memory 202
  • the target AD area can be understood as the AD area corresponding to the target key area in the second memory.
  • the configuration information includes the correspondence between multiple conditional instructions, multiple key areas, and multiple AD areas.
  • the processor 100 may determine, according to the configuration information, the key area corresponding to the target conditional instruction as the target key area, and the AD area corresponding to the target conditional instruction as the target AD area. Since the position indication information in the embodiment of the present application can directly indicate the target key area and the target AD area, even if there is no one-to-one correspondence between a conditional command, multiple key areas, and multiple AD areas, it does not affect the control.
  • the device 201 searches for the target data according to the position indication information.
  • the controller 201 uses the target key entry to perform a matching search in the target key area to obtain the location of the matching entry.
  • the position of the matched entry can be understood as the relative position of the target key entry in the target key area, and can also be understood as the storage order of the target key entry in the target key area.
  • the controller 201 obtains target data from the target AD area according to the matched entry position.
  • the relative position of the i-th key entry in the target key area in the target key area is the same as the relative position of the i-th AD data in the target AD area. Therefore, according to the position of the matched entry
  • the AD data corresponding to the target key entry can be obtained from the position of the matching entry in the target AD area, that is, the target data.
  • the controller 201 may continue to execute S504 and return the target data to the processor 100.
  • the processor 100 can continue to execute the target branch instruction corresponding to the target data.
  • the location indication information may include the area identifiers of the target key area and the target AD area, or may include the start storage addresses of multiple key areas and the start storage addresses of multiple AD areas. That is, the processor 100 can indicate the target key area and the target AD area to the controller 201 through the initial storage address.
  • instruction A corresponds to key area A and AD area A.
  • the initial storage address of key area A is address A
  • the initial storage address of AD area A is address a.
  • the location indication information corresponding to instruction A may indicate address A and address a.
  • instruction B corresponds to key area B and AD area B, as shown in Table 2, the initial storage address of key area B is address B, and the initial storage address of AD area B is address b.
  • the location indication information corresponding to instruction B may indicate address B and address b.
  • Table 2 the corresponding relationship between other conditional instructions and the initial storage address can refer to instruction A and instruction B, which will not be repeated.
  • the processor 100 can obtain the start storage addresses of the target key area and the target AD area according to the configuration information, and directly indicate the start storage addresses of the target key area and the target AD area to the controller 201 through the position indication information. This allows the controller 201 to directly determine the storage location of the target key area and the target AD area according to the location indication information.
  • the storage address of the upper left bit of the key area A is ad11
  • the storage address of the upper right bit is ad18
  • the storage address of the lower left bit is ad81, right
  • the storage address of the lower corner bit is ad88.
  • the key area A includes 8 key entries, so the depth information of the key area A is 8.
  • the initial storage address of the key area A can be any one of ad11, ad18, ad81, and ad88 in FIG. 3. The same is true for the starting position information of AD area A, and will not be repeated.
  • the controller 201 may determine the target key area from the first memory 202 according to the initial storage address of the target key area, and further determine the entry position of the target key entry in the target key area.
  • the controller 201 may start to match and search the target key area from the initial storage address of the target key area, thereby determining the position of the matching entry of the target key entry in the target key area.
  • the target key area is the key area A shown in FIG. 3, and the controller 201 may start from the starting storage address of the target key area (address A is ad11), and sequentially connect the target key entry and the key entry A1 to A8 match. Assuming that the target key entry matches the key entry A5 successfully, it can also be understood that the target key entry is the key entry A5, then the match of the target key entry in the target key area (key area A) can be determined The entry position of is 5.
  • the controller 201 can then determine the target AD area from the second memory 203 according to the initial storage address of the target AD area, and further obtain target data from the target AD area according to the matching entry position. For example, the controller 201 may start from the initial storage address of the target AD area, and determine that the AD data whose relative position is consistent with the position of the matched entry is the target data.
  • the controller 201 can start from the starting storage address (address a) of the target AD area, and determine that the fifth AD data thereafter is the target data. Therefore, the controller 201 It can be determined that the fifth AD data (AD data 5) in the AD area A is the target data.
  • the controller 201 in the embodiment of the present application can directly determine the target key area from the first memory 202 and determine the target AD area from the second memory 203 according to the location indication information.
  • the target data is obtained from the target AD area by using the matching entry position of the target key entry in the target key area.
  • the controller 201 no longer needs to calculate the position index of the target data according to the mapping relationship between the maximum storage length of the first memory 202 and the maximum storage length of the second memory 203, so the first memory can be configured more flexibly.
  • the storage structure of the first memory 202 and the second memory 203 further helps to increase the storage density of the first memory 202 and/or the second memory 203 when the lengths of the key entries in the first memory 202 are inconsistent.
  • the processor 100 can directly indicate the target key area and the target AD area through the position indication information, so that the controller 201 can determine the target key area from the first memory 202 according to the position indication information, and from the second The target AD area is determined in the memory 203, eliminating the need for the controller 201 to traverse the first memory 202 and the second memory 203, thereby helping to increase the search speed of the controller 201 and improve the performance of the data search system as a whole.
  • key areas that are not the target key area may also contain the same key entry as the target key entry. If the controller 201 directly traverses the first memory 202 to find it, a mismatch may also occur. However, in the embodiment of the present application, the key area is indicated by the position indication information, which is also beneficial to prevent the controller 201 from misjudgment, thereby improving the accuracy of the data search system.
  • the configuration information may also include depth information of multiple key regions in the first memory 202.
  • the depth information of each key area can be understood as the number of key entries in the key area. It can be understood that between the key area and the AD area that have a corresponding relationship, the number of key entries in the key area is the same as the number of AD data in the AD area, so the depth information can also be understood as the number of AD data in the AD area.
  • the controller 201 When the controller 201 matches and searches the target key area, it may determine the number of key entries in the target key area according to the depth information. When searching for the target AD area, the controller 201 may also determine the amount of AD data in the target AD area according to the depth information. Therefore, the controller 201 can more accurately determine the target key area and the target AD area.
  • the key entry has a flexible storage manner in the first memory 202.
  • one or more key entries can occupy a storage width of 1 bit, that is, one or more key entries can be located in the same row of storage units in the first memory 202, or one key entry can occupy multiple bits.
  • the storage width is 1 bit, that is, one or more key entries can be located in the same row of storage units in the first memory 202, or one key entry can occupy multiple bits.
  • the maximum storage length of the first memory 202 is 40 bits. If the data length of the key entry in the key area is 20 bits, the storage area of 40 ⁇ 1 bit 2 can be occupied by two key entries in the key area, where the storage width is 1 bit. If the data length of the key entry in the key area is 80 bits, one key entry in the key area occupies a 40 ⁇ 2bit 2 storage area, where the storage width is 2 bits. With the foregoing storage method, the storage space of the first memory 202 can be used more flexibly, which is beneficial to further increase the storage density of the first memory 202.
  • the storage length of the key entry and the data length may be the same or different.
  • the maximum storage length of the first memory 202 is 40 bits
  • the storage length is also 20 bits.
  • the storage length is 40 bits.
  • the configuration information may also include the storage length of multiple key areas.
  • the processor 100 may obtain the storage length of the target key area according to the configuration information, and send the first length information to the controller.
  • the first length information may indicate the storage length of the target key area in the first memory 202.
  • the storage length of the target key area is indicated by the first length indication information, so that the controller 201 can accurately identify the storage area of the target key area from the first memory 202 according to the storage length indicated by the location indication information. It helps to improve the accuracy of the data search system as a whole.
  • the data length of the N pieces of AD data in the same AD area may be the same or different.
  • one or more AD data may be located in the same row of storage cells of the second memory 203, that is to say, the one or more Each AD data occupies a storage width of 1bit.
  • the 8 AD data of the AD area A can be stored in the order from left to right and top to bottom.
  • the address in the upper left corner of AD area A is the initial storage address of AD area A.
  • AD data 1 is stored in the first row (the largest storage area of the first unit)
  • the first row has no space to store the AD data 4
  • the AD data 4 continues to be stored on the left side of the second row (the second unit largest storage area).
  • the AD data 4 is stored in the second row, there is still room for the second row to continue to store the AD data 5 to 7.
  • the AD data 7 is stored in the second row, the second row has no space to store the AD data 8, and then the AD data 8 is stored in the third row.
  • the AD area A occupies a total of 3bit storage width. If the current storage method in which each AD data individually occupies 1 bit storage width is adopted, the AD area A will occupy 8 bits of storage width. It can be seen that the storage method provided by the embodiment of the present application can further increase the storage density of the second memory 203.
  • the configuration information may also include length information of each AD data in each AD area.
  • the processor 100 may also obtain the AD length message corresponding to the target AD area according to the configuration information.
  • the AD length message may include data length information of one or more AD data in the target AD area.
  • the processor 100 sends the AD length information to the controller 201.
  • the configuration information may include length identifiers corresponding to different data lengths.
  • the AD data stored in the second memory 203 has four data lengths, and the length identifiers corresponding to the four data lengths in the configuration information may be as shown in FIG. 6.
  • the length identifier corresponding to the first data length is 0, and the AD data belonging to the first data length includes control information (ctrl in Figure 6) and two instruction counter information (PC in Figure 6), where 9b represents control information A total of 9 bits, 21b represents a total of 21 bits of information about an instruction counter.
  • the length identifier corresponding to the second type of data length is 1, and the AD data belonging to the second type of data length includes ctrl information, 4 pieces of PC information, and one piece of reserved (RSV in FIG. 6) information.
  • the RSV information is 9 bits.
  • the third data length and the fourth data length are similar to the foregoing, and will not be repeated.
  • FIG. 6 also exemplarily shows the storage structure of an AD area.
  • the AD area includes a total of 20 AD data, among which one or more AD data occupies a storage width of 1 bit.
  • the AD length message sent by the processor 100 may carry the data length identifier of the 20 AD data.
  • the AD length message may include a bitmap as shown in FIG. 7, where each indicator bit occupies 2 bits, which may represent a length identifier of AD data.
  • the bitmap shown in FIG. 7 has a total of 20 indicator bits (AT0 to AT19), which can carry the length identifiers of the first to the 20th AD data in the AD area in order from left to right.
  • the bitmap carried in the AD length message corresponding to the AD area may be 0000000000000100010001000001010010100011.
  • the AD length message may indicate the data length of each AD data in the target AD area.
  • the redundant AD data in the AD area can be configured as a uniform data length. For example, for the AD length message shown in FIG. 7, the data length of 20 AD data is indicated at most. Then, if the depth information of the AD area is greater than 20, for example, the AD area B includes 25 AD data, the first 20 AD data can be flexibly configured with a storage structure, and the last 5 AD data can be configured with a uniform storage length.
  • multiple AD length messages may also be sent to indicate the data length of each AD data in the target AD area.
  • the AD area B includes 25 AD data, and one AD length message can indicate the data length of 13 AD data at most.
  • the processor 100 can send two AD length messages. One of the AD length messages indicates the data length of the first to thirteenth AD data, and the other AD length message indicates the data length of the 14th to the 25th AD data.
  • the AD length message may also be referred to as an associated data type (AD Type, ADT) command.
  • Fig. 7 exemplarily shows a specific structure of the AD length message, and 1 to 49 indicate the number of bits of the AD length message.
  • the AD length message carries initial indication information (pocode), which is used to indicate that this message is an AD length message.
  • the AD length message also carries start indication position information (Ad_start), which is used to indicate the start storage address of the first AD data indicated by the ADT instruction.
  • the processor 100 sends two AD length messages.
  • Ad_start in one AD length message is used to indicate the starting storage address of the first AD data in the target AD area
  • Ad_start in the other AD length message is used It indicates the starting storage address of the 14th AD data in the target AD area.
  • the AD length message can be carried by a null instruction to reduce instruction overhead.
  • the controller 201 may obtain the target data from the target AD area according to the AD length message and the matching entry position. Exemplarily, the controller 201 may determine the data length of the AD data before the target data in the target AD area according to the matched entry position and the AD length message. Furthermore, the starting storage address of the target data can be determined according to the starting storage address of the target AD area and the data length of the AD data located before the target data.
  • the controller 201 can obtain the data length of AD data 1 to 4 according to the AD length message, and according to the data length of AD data 1 to 4 The sum can determine the address interval between the target data (AD data 5) and the start storage address of the target AD area. Therefore, the starting storage address of the target data can be obtained according to the starting storage address of the target AD area.
  • the processor 100 may also obtain data length information of the target data according to the configuration information, and send second length indication information to the controller 201, where the second length indication information may indicate the data of the target data length.
  • the controller 201 determines the initial storage address of the target data, it determines the target data from the second memory 203 according to the length information of the target data. It can be understood that the processor 100 may not send the second length indication information. In this case, the controller 201 may also determine the length information of the target data according to the AD length message.
  • the controller 101 can determine that the initial storage address of the target data (AD data 5) is a 0 +75bit. The controller 101 further determines that the target data is 15 bits according to the length information of the target data. Then, the controller 101 can determine to obtain the target data from a 0 +75 bit to a 0 +90 bit.
  • controller 201 may execute the following pseudo code to find the target data:
  • AD_START is the starting storage address of the target AD area
  • offset is the performance position of the target key entry in the target key area
  • AD_TYPE[i] represents the length information of the i-th AD data.
  • AD_INDEX represents the current search position.
  • AD_INDEX AD_INDEX>>2, that is, one row (maximum storage length) of the target AD area includes 4 basic lengths, which can be understood as the greatest common divisor of different data lengths configured for AD data.
  • AD_TYPE length information of the target data
  • AD_INDEX[1:0] representing the basic length
  • the data length of the target data is 1 basic length
  • the data length of the target data is 2 basic lengths
  • the length information of the target data If it is 2, the data length of the target data is 3 basic lengths, and if the length information of the target data is 3, the data length of the target data is 4 basic lengths.
  • the starting storage address of the target key area the starting storage address of the target AD area, depth information, the storage width of the target key entry, the second length indication information, etc.
  • the information can be carried by the Kswitch command shown in Figure 8.
  • the opcode of the Kswitch command is used to indicate that the command is a Kswitch command, where the second length indication information is used to indicate the data length of the target data, and the bucket start is used to indicate the starting storage address of the target key area.
  • AD_Start is used to indicate the starting storage address of the target AD area
  • k_sz is the first length indication information, used to indicate the storage width of the target key area
  • Bucket depth is used to indicate depth information.
  • the processor 100 may be a multi-core processor, and multiple cores of the processor 100 may instruct the controller 201 to search for target data in parallel.
  • the Kswitch instruction may also include a core identifier (Slice ID, SLID), so that the controller 201 can search for target data for multiple cores at the same time.

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Abstract

Sont divulgués un système et un procédé de recherche de données. Le système de recherche de données peut comprendre un contrôleur, une première mémoire et une seconde mémoire. La première mémoire est une mémoire adressable par le contenu (CAM). Le contrôleur peut effectuer les opérations consistant à : recevoir une entrée de clé cible et des informations d'indication de position permettant de rechercher des données cibles, les informations d'indication de position pouvant indiquer une zone de clé cible et une zone AD cible en association avec les données cibles ; effectuer une recherche de correspondance dans la zone de clé cible en utilisant l'entrée de clé cible de façon à obtenir une position d'entrée en correspondance ; et obtenir les données cibles provenant de la zone AD cible d'après la position d'entrée en correspondance. Dans les modes de réalisation de la présente invention, plus aucune relation de correspondance ne doit être maintenue entre la longueur de stockage maximale de la première mémoire et la longueur de stockage maximale de la seconde mémoire, ce qui contribue à l'augmentation de la densité de stockage de la première mémoire et/ou de la seconde mémoire.
PCT/CN2019/128897 2019-12-26 2019-12-26 Système et procédé de recherche de données WO2021128217A1 (fr)

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