WO2021121275A1

WO2021121275A1 - Message processing method and apparatus for clock synchronization, and clock synchronization method and apparatus

Info

Publication number: WO2021121275A1
Application number: PCT/CN2020/136845
Authority: WO
Inventors: 何涛; 石兴建; 孟凡顺; 李�浩
Original assignee: 华为技术有限公司
Priority date: 2019-12-16
Filing date: 2020-12-16
Publication date: 2021-06-24
Also published as: CN112994819B; CN112994819A

Abstract

Disclosed in embodiments of the present application is a message processing method. In the method, when obtaining a first message for clock synchronization, a first device may record a first timestamp, the first timestamp being used for indicating the moment when the first device obtains the first message. After obtaining the first message, the first device may determine, according to the first message, a port for forwarding the first message, and records a second timestamp, the second timestamp being used for indicating the moment when the first device determines the port. The first device may generate, according to the first message, a second message comprising the third timestamp, and send the second message to the second device, the third timestamp being determined according to the difference between the second timestamp and the first timestamp. The step of determining the port may be performed by a switching module in the first device, that is, the third timestamp may reflect the residence time of the first message in the switching module. Therefore, when a sink device performs clock synchronization, the packet delay variation introduced by the switching module can be removed, thereby improving the accuracy of clock synchronization.

Description

Message processing method, clock synchronization method and device for clock synchronization

This application requires the priority of a Chinese patent application filed with the Chinese Patent Office on January 22, 2020, the application number is 202010075071.3, and the invention title is "a message processing method, clock synchronization method and device for clock synchronization", And the priority of the Chinese patent application filed with the Chinese Patent Office on December 16, 2019, with the application number 201911295200.3, and the invention titled "Methods, Processors, Equipment, and Network Systems for Reducing Packet Delay Variation", with all contents Incorporated in this application by reference.

Technical field

This application relates to the field of clock synchronization, and in particular to a message processing method, clock synchronization method and device for clock synchronization.

Background technique

Clock synchronization means that the clock frequency of each device remains the same, and the clock phase can maintain a certain phase difference. At present, some methods for clock synchronization can be used between devices for clock synchronization, for example, a circuit emulation service adaptive clock recovery (CESACR) method is used for clock synchronization. Currently, a variety of devices, such as routers and switches in telecommunications networks, can use the CESACR method to synchronize clocks.

When two devices use the CESACR method to synchronize their clocks, they can synchronize their clocks in the form of messages. However, the effect of clock synchronization in this way is not good. Therefore, a solution is needed to solve the above-mentioned problems.

Summary of the invention

The embodiments of the present application provide a message processing method and a clock synchronization method for clock synchronization, which can improve the effect of clock synchronization using the CESACR method.

In the first aspect, the embodiments of the present application provide a message processing method for clock synchronization. The method may be executed by a first device, and the first device may be a source device or an intermediate device that uses the CESACR method for clock transfer. In the traditional technology, when the source device sends a message for clock synchronization to the sink device, the intermediate device transparently transmits the message for clock synchronization, and when the intermediate device transparently transmits the message for clock synchronization, the intermediate device transparently transmits the message for clock synchronization. The switching module in the device introduces packet delay variation (PDV) when processing messages used for clock synchronization, and the introduced packet delay variation will affect the accuracy of clock synchronization. In view of this, in the embodiment of the present application, after the first device obtains the first message, it can generate a second message based on the first message, and the second message can reflect the residence time of the first message in the exchange module of the first device , Instead of simply transparently transmitting the first message. Specifically, when the first device obtains the first message, the first time stamp may be recorded, and the first time stamp is used to indicate the moment when the first device obtains the first message. Wherein, the first message is a message used for clock synchronization. After obtaining the first message, the first device may determine the port for forwarding the first message according to the first message, and record a second time stamp, which is used to indicate the time when the first device determines the port. When forwarding the first message, the first device may generate a second message including the third time stamp according to the first message, and send the second message to the second device. Wherein, the third time stamp is determined according to the difference between the aforementioned second time stamp and the first time stamp. Determining the port for forwarding the first message may be performed by the switching module in the first device, that is, the third timestamp may reflect the residence time of the aforementioned first message in the switching module. It can be seen that, using the solution in the embodiment of the present application, the message for clock synchronization received by the sink device can carry the residence time of the message for clock synchronization in the switching module, and the sink device performs clock synchronization. During synchronization, the packet delay variation introduced by the switching module can be removed, thereby improving the accuracy of the sink device using the received clock synchronization message to perform clock synchronization.

In a possible implementation, if the first device is the source device, the first message may be a message generated by the first device for clock synchronization, and the first time stamp may be used to instruct the first device to generate the first device. The moment of the news. The difference between the second time stamp and the first time stamp is the residence time of the first message in the switching module of the first device. The first message may have a field for carrying timestamp data. If the first message is a message generated by the first device, the first device may determine the difference between the second timestamp and the first timestamp as the third timestamp, and add the third timestamp to this field, thereby It is realized that the second message including the third time stamp is generated according to the first message.

In a possible implementation manner, the first message may also be a message for clock synchronization received by the first device from another device. For example, when the first device is the source device, the first message may be a message for clock synchronization received by the first device from the device as the clock source. When the first device is an intermediate device, the first message may be obtained by the first device from the third device, where the first device is the next hop device of the third device. If the first message is a message obtained by the first device from another device, the first message may carry a fourth timestamp, and the first device may determine the sum of the fourth timestamp and the aforementioned difference as the third timestamp, And the third time stamp is added to this field, so that the second message including the third time stamp is generated according to the first message.

In the second aspect, the embodiments of the present application also provide a clock synchronization method, which can be executed by a second device as a sink device. Specifically, the second device can obtain a second message from the first device. The second device is the next hop device of the first device. When the second device acquires the second message, it can record a fifth timestamp indicating the moment when the second device acquires the second message. The second message includes the third timestamp , The third time stamp is determined according to the method provided in the above first aspect. After recording the fifth time stamp, the second device may perform clock synchronization according to the difference between the fifth time stamp and the third time stamp. Since the third time stamp can reflect the sum of the residence time of the synchronization message used for the clock in the switching modules of one or more devices, the difference between the fifth time stamp and the third time stamp also removes the aforementioned one or The amount of packet delay variation introduced by the switching modules of multiple devices. Therefore, with this method, the accuracy of clock synchronization can be improved.

In a third aspect, an embodiment of the present application provides a message processing device for clock synchronization. The device includes an acquiring unit, a recording unit, a determining unit, a generating unit, and a sending unit. The obtaining unit is used for obtaining the first message; the recording unit is used for recording the first time stamp indicating the time when the first message is obtained; the determining unit is used for determining the port for forwarding the first message according to the first message The recording unit is also used to record a second time stamp used to indicate the time at which the port is determined; the generating unit is used to generate a second message including a third time stamp according to the first message, and the third time The stamp is determined according to the difference between the second time stamp and the first time stamp; the sending unit is configured to send the second message to the second device.

In a possible implementation manner, the acquiring unit is specifically configured to generate the first message; the recording unit is specifically configured to record the first timestamp indicating the moment when the first message is generated.

In a possible implementation manner, the acquiring unit is specifically configured to: acquire the first message from a third device, where the first message carries a fourth timestamp; the third timestamp is equal to the The sum of the difference and the fourth time stamp.

In a fourth aspect, an embodiment of the present application provides a clock synchronization device, which includes an acquisition unit, a recording unit, and a synchronization unit. The acquiring unit is configured to acquire a second message from the first device, where the second message includes a third time stamp, the third time stamp being determined according to the apparatus according to any one of the above third aspects; the recording unit is configured to A fifth time stamp used to indicate the time when the second message is acquired is recorded; the synchronization unit is used to perform clock synchronization according to the difference between the fifth time stamp and the third time stamp.

In the fifth aspect, an embodiment of the present application provides a device. The device includes a processor and a memory. The memory is used to store instructions or computer programs. The processor is configured to execute the instructions or computer programs in the memory, execute the method described in any one of the first aspect above, or execute the method described in any one of the second aspect above.

In a sixth aspect, the embodiments of the present application provide a computer-readable storage medium, including instructions or computer programs, which when run on a computer, cause the computer to execute the method described in any one of the first aspects above, or execute the above The method of any one of the second aspect.

In the seventh aspect, the embodiments of the present application provide a computer program product containing instructions or computer programs, which when run on a computer, cause the computer to execute any of the methods described in the first aspect, or execute the second The method of any one of the aspects.

Description of the drawings

In order to more clearly describe the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only These are some embodiments described in this application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work.

FIG. 1 is a schematic diagram of an application scenario provided by an embodiment of the application;

Figure 2 is another schematic diagram provided by an embodiment of the application;

3 is a schematic flowchart of a message processing method for clock synchronization provided by an embodiment of the application;

FIG. 4 is a schematic structural diagram of a first device provided by an embodiment of this application;

FIG. 5 is a schematic structural diagram of a message processing apparatus for clock synchronization provided by an embodiment of the application;

FIG. 6 is a schematic structural diagram of a clock synchronization device provided by an embodiment of this application;

FIG. 7 is a schematic structural diagram of a device provided by an embodiment of the application.

Detailed ways

To facilitate understanding, firstly, possible application scenarios of the embodiments of the present application are introduced.

A constant bit rate (constant bit rate, CBR) service is a real-time service, and the clock synchronization of the equipment processing the service is the basis for ensuring the normal operation of the service. Therefore, the network supporting the CBR service needs to synchronize the clock of the equipment processing the CBR service. The network supporting the CBR service may be, for example, an asynchronous transfer mode (ATM) network. Specifically, the CESACR method can be used to synchronize clocks of devices that process CBR services. Next, the principle of clock synchronization using the CESACR method is briefly introduced. CBR services may include Gigabit Ethernet (GE), synchronous digital hierarchy (SDH), common public radio interface (CPRI), and so on.

Refer to FIG. 1, which is a schematic diagram of an application scenario provided by an embodiment of the application.

In the scenario shown in FIG. 1, the device 101 and the device 102 are included, and the device 101 and the device 102 need to realize clock synchronization. The device 101 may send a message for clock synchronization to the device 102, and the message for clock synchronization sent by the device 101 to the device 102 may be forwarded by the device 103, where the device 103 may be, for example, an optical transport network (optical transport network, OTN) equipment. The device 101 that sends the message for clock synchronization can also be called the source device, and the destination receiving device of the clock synchronization message, that is, the device 102 can also be called the sink device. A device that transmits a message for clock synchronization, for example, the device 103 shown in FIG. 1 may also be referred to as an intermediate device.

When the device 101 sends a message for clock synchronization, it can record a timestamp T1, and carry the timestamp T1 in the message for clock synchronization. The timestamp T1 is used to instruct the device 101 to send the message for clock synchronization. The moment of the news. After the device 103 receives the message for clock synchronization sent by the device 101, it transparently transmits the message for clock synchronization. FIG. 1 is only shown for the convenience of understanding. The number of intermediate devices used for forwarding the message for clock synchronization may also be multiple, and the multiple devices are all used for transparently transmitting the message for clock synchronization. After the device 102 receives the message for clock synchronization, it may record a time stamp T2, which is used to indicate the time when the device 102 receives the message for clock synchronization. Further, the device 102 can perform clock synchronization by combining T2 with the time stamp T1 carried in the aforementioned message for clock synchronization. Specifically, the device 102 can input the aforementioned time stamp T1 and time stamp T2 into adaptive clock recovery (adaptive clock recovery). , ACR) algorithm, so as to realize the clock synchronization of the device 101 and the device 102. The ACR algorithm can synchronize the clocks of the device 101 and the device 102 according to the difference between T2 and T1. The principle of the ACR algorithm is briefly introduced below in conjunction with Figure 2.

Refer to FIG. 2, which is another schematic diagram provided by an embodiment of the application. As shown in FIG. 2, the device 101 periodically sends a message for clock synchronization to the device 102. T1_i represents the timestamp carried in the ith message for clock synchronization sent by the device 101 to the device 102, and T1_i is used to indicate the time of the ith message for clock synchronization sent by the device 101 to the device 102. T2_i represents the time stamp recorded when the device 102 receives the i-th message for clock synchronization, and T2_i is used to indicate the time when the device 102 receives the i-th message for clock synchronization. If the clocks of the device 101 and the device 102 are synchronized, and the transmission delay of each message used for clock synchronization is the same, then:

T2_1–T2_0=T1_1–T1_0,

T2_2–T2_1=T1_2–T1_1,

T2_n–T2_n-1=T1_n–T1_n-1,

By analogy, T2_n–T2_0=T1_n–T1_0, if T2_n–T2_0 is greater than T1_n–T1_0, it means that the frequency of the device 102 is higher than that of the device 101, and the frequency of the device 102 needs to be reduced, and vice versa, the frequency of the device 102 needs to be increased. The formula transformation of T2_n–T2_n-1=T1_n–T1_n-1 can be obtained: T2_n–T1_n=T2_n-1–T1_n-1, therefore, the ACR algorithm can realize the clock of device 101 and device 102 according to the difference of T2_n–T1_n Synchronize.

It can be seen from the above description that the ideal condition of the ACR algorithm is: the transmission delay of each message used for clock synchronization is the same, that is, the packet delay variation is zero. However, in fact, the forwarding delay of the message synchronized with the user's clock is greatly affected by the forwarding device, such as the device 103 in FIG. 1. In addition to forwarding the message for clock synchronization, the device 103 can also forward other messages. Therefore, when the device 103 forwards the clock synchronization message, the residence time of the clock synchronization message in the device 103 is affected by the current state of the device 103. However, the state of the device 103 cannot be kept the same all the time. Therefore, the residence time of multiple messages used for clock synchronization in the device 103 may be different, that is, the packet delay variation is not zero. Moreover, in some embodiments, the packet delay variation is relatively large, for example, it can reach the level of microseconds, such as 2 microseconds. This makes it difficult for the transmission delays of multiple messages used for clock synchronization to be exactly the same, which further makes the accuracy of clock synchronization using the ACR algorithm not high.

The residence time of the message used for clock synchronization in the device 103 includes multiple parts, which are:

1. The time used by the switching module in the device 103 to process messages used for clock synchronization, where the switching module is used to determine the port for forwarding and scheduling messages used for clock synchronization, and the switching module can be a hardware chip or Software module

2. The time used for queuing messages for clock synchronization in the message exit queue;

3. The time used for path redirection due to network emergencies;

4. The residence time caused by other factors, such as the optical attenuation in the optical transmission network.

The inventor found that the packet delay variation introduced by the switching module for the time used for processing clock synchronization messages is the largest, which is greater than the packet delay variation introduced by the other three factors mentioned above. Therefore, if the packet delay variation introduced by the time used by the switching module to process the clock synchronization message can be removed, the accuracy of clock synchronization by the sink device using the received clock synchronization message can be improved.

In view of this, the embodiments of the present application provide a message processing method and a clock synchronization method for clock synchronization, which will be introduced below with reference to the accompanying drawings.

Refer to FIG. 3, which is a schematic flowchart of a message processing method for clock synchronization according to an embodiment of the application. The message processing method for clock synchronization shown in FIG. 3 can be implemented by the following S101-S103.

S101: The first device acquires the first message, and records a first time stamp, where the first time stamp is used to indicate the moment when the first device acquires the first message.

The first message in the embodiment of the present application may be a message used for clock synchronization. The first device in the embodiment of the present application may be the device 101 shown in FIG. 1 or the device 103. The first device may be a device for processing CBR services. The message structure of the first message and the transmission rate of the first message may be determined according to the CBR service processed by the first device, which is not specifically limited in the embodiment of the present application.

In this embodiment of the present application, the first device may use the local clock of the first device to perform counting to obtain the first time stamp.

In the embodiment of the present application, if the first device is the source device, such as the device 101 shown in FIG. 1, the first message may be a message generated by the first device for clock synchronization. In this case, the first time stamp It can be used to indicate the moment when the first device generates the first message. The first message may also be a message for clock synchronization received by the first device from another device. For example, the first message may be a message for clock synchronization received by the first device from a device that is a clock source.

If the first device is an intermediate device, the first message may be obtained by the first device from the third device, and the first device is the next hop device of the third device. In this case, the first message may carry a fourth timestamp, and the fourth timestamp may be added to the first message by the third device.

S102: The first device determines a port for forwarding the first message according to the first message, and records a second timestamp, where the second timestamp is used to indicate the time when the first device determines the port.

In the embodiment of the present application, the first message may be a layer 2 forwarding message or a layer 3 forwarding message. If the first message is a layer 2 forwarding message, the first device may determine the port for forwarding the first message according to a locally stored media access control (MAC) forwarding table. Specifically, the corresponding relationship between the MAC address and the port is stored in the forwarding table. The first device can parse the first message to obtain the destination MAC address, and determine the port for forwarding the first message according to the destination MAC address and the MAC forwarding table. If the first message is a Layer 3 forwarding message, the first device may determine a port for forwarding the first message according to a forwarding information table (forward information database, FIB) stored locally. Specifically, the forwarding information table stores the correspondence between Internet Protocol (IP) addresses, ports, and next hops. The first device can parse the first message to obtain the destination IP address, and based on the destination IP address and The forwarding information table forwarding table determines the port for forwarding the first message. In some embodiments, S102 may be performed by the switching module of the first device.

When the first device determines the port for forwarding the first message, it can use the local clock of the first device to count to obtain the second timestamp.

S103: The first device generates a second message including a third time stamp according to the first message, and sends the second message to the second device, where the third time stamp is based on the difference between the second time stamp and the first time stamp determine.

The difference between the second time stamp and the first time stamp is the residence time of the first message in the switching module of the first device. After obtaining the residence time, the first device may generate a second message according to the residence time and the first message. Among them, the first message may have a field for carrying timestamp data, and the first device may add a third timestamp to this field, so as to achieve the effect of generating a second message including the third timestamp according to the first message . Specifically, if the first message is generated by the first device, the third time stamp is equal to the difference between the second time stamp and the first time stamp. If the first message is obtained by the first device from the third device, the first message carries a fourth time stamp. In this case, the third time stamp is equal to the sum of the fourth time stamp and the aforementioned difference.

After the first device generates the first message, the first message can be sent to the second device. If the second device is not the sink device, the second device can perform steps similar to those of the first device, that is, modify the third timestamp carried in the second message, and modify the third timestamp so that the second message is in the first The sum of the residence time of the switching module of the second device and the third time stamp. If the second device is a sink device, the second device may record a fifth timestamp. The fifth timestamp is used to indicate the time when the second device obtains the second message. The second device may use the third The time stamp and the fifth time stamp perform clock synchronization. Specifically, the second device may use the difference between the fifth time stamp and the third time stamp as the input of the ACR algorithm, so as to achieve clock synchronization.

When the second device is the sink device, since the third time stamp can reflect the sum of the residence time of the synchronization message used for the clock in the switching modules of one or more devices, the fifth time stamp and the third time stamp The difference is equal to the sum of the fifth time stamp minus the residence time of the synchronization message used for the clock in the switching module of one or more devices. Correspondingly, the difference between the fifth time stamp and the third time stamp also removes the packet delay variation introduced by the switching module of one or more devices. Since the packet delay variation introduced by the switching module is removed, the solution of the embodiment of the present application can be used to improve the accuracy of clock synchronization. The one or more devices mentioned here are part or all of the source device and the intermediate device.

In some embodiments, if the message used for clock synchronization is in the forwarding process, the source device and each intermediate device both execute the message processing method for clock synchronization shown in FIG. , You can remove the packet delay variation introduced by the switching modules of the source device and all intermediate devices, thereby effectively improving the accuracy of clock synchronization.

In some embodiments, the first device may include multiple functional modules, for example, including a first module and a second module, and the first module and the second module may be connected through an optical fiber or connected through an optical relay. When the first module and the second module are connected by optical fiber or optical relay, if the first module of the first device receives a message for clock synchronization and the switching module is located on the second module, the first device can The message for clock synchronization is sent to the second module through an optical fiber or an optical relay, and the second module determines the port for forwarding the message for clock synchronization. In some embodiments, the first device may be used to transmit messages for clock synchronization corresponding to various CBR services. Unlike CBR services, the format and transmission rate of the message for clock synchronization received by the first device may also be possible. different. When messages are transmitted through optical fibers or optical relays, there are also certain requirements on the transmission rate and message format of the messages. For example, optical fibers or optical relays can transmit messages in the first format at the first rate. Assuming that the message for clock synchronization received by the first module is a message corresponding to the first CBR service, the first module receives the message for clock synchronization, converts the clock synchronization message, and obtains a message that conforms to the first format And transmit the converted clock synchronization message to the second module at the first rate using optical fiber or optical relay. In this case, the aforementioned first message may be a message after conversion. In some embodiments, when the first message is a converted message, the first message may also be referred to as an information element. Correspondingly, in this case, after the second module receives the cell, it can perform inverse conversion on the cell to obtain a message that meets the requirements of the first CBR service, and determine the forwarding of the first message based on the message obtained by the inverse conversion. port.

In the embodiment of the present application, the port mentioned in S102 is a physical port. Specifically, the first device may include one or more boards, and one board may include multiple physical ports. Among them, the board card can also be called a daughter card, and the board card can be divided into a branch card and a line card. The switch module can be located on the line card. In some embodiments, when the first message is a message obtained by the first device from the third device, the first device can obtain the first message through the first port on the first board. Correspondingly, the first board The clock on the card counts to get the first time stamp. Then, the first device can determine the port for forwarding the first message through the switching module, and the second time stamp is obtained by counting the clock on the board to which the switching module belongs. The switching module may be located on the first board, or may be located on a second board different from the first board, which is not specifically limited in the embodiment of the present application. It should be noted that when the switching module is located on the second board, although the clocks used to obtain the first time stamp and the second time stamp are located on different boards, the two clocks are both located on the first device. The frequencies of the two clocks are synchronized. Therefore, the difference between the second time stamp and the first time stamp can accurately represent the residence time of the first message in the exchange module. In addition, the port for forwarding the first message may be located on the second board, or may be located on a third board different from the second board, which is not specifically limited in the embodiment of the present application.

It can be understood with reference to FIG. 4, which is a schematic structural diagram of a first device provided by an embodiment of the application. As shown in FIG. 4, the first device 400 includes a board 401, a board 402, and a board 403. The board 401, the board 402, and the board 403 can communicate through a backplane (not shown in FIG. 4). Among them, the board 401 includes a port 401a and a crystal oscillator 401b, the board 402 includes a switch module 402a and a crystal oscillator 402b, and the board 403 includes a port 403a and a crystal oscillator 403b. The first device 400 obtains the first message through the port 401a and uses The clock count generated by the crystal oscillator 401b obtains the first time stamp. The switching module 402a of the first device 400 determines the port for forwarding the first message, and uses the clock count generated by the crystal oscillator 402b to obtain the second time stamp. It is assumed here that the port for forwarding the first message is 403a. The first device 400 sends the second message to the second device through the port 403a, and the crystal oscillator 403b is used to generate the working clock of the board 403. In some embodiments, the working clocks of the board 401, the board 402, and the board 403 may not be directly generated by the crystal oscillator, but may also be generated indirectly by the crystal oscillator, or may be generated by other real-time clocks (RTC). Yes, it is shown here only for the convenience of understanding, and it does not constitute a limitation to the embodiments of the present application.

In some embodiments, the intermediate device or the source device may also introduce a certain amount of packet delay variation when performing the foregoing S101 and S102. The introduced packet delay variation will reduce the accuracy of clock synchronization. The following combined theoretical analysis shows that the packet delay variation introduced by S101 and S102 is smaller than the packet delay variation removed by the method shown in FIG. 3. Therefore, the above method is theoretically feasible to improve the accuracy of clock synchronization.

The reason why the aforementioned S101 and S102 introduce the packet delay variation mainly includes the following two factors.

The first factor is that the clocks used for counting to obtain the time stamp are not synchronized between the devices. The devices mentioned here include various devices used to transmit messages for clock synchronization. The second factor is: there is a certain error in the time stamp obtained from the real-time clock count. The real-time clock mentioned here can be, for example, a clock directly generated by a crystal oscillator.

Regarding the first factor, it should be noted that the timestamp is essentially a counter, and the timestamp can represent time only if the clocks used by each device to count are consistent.

For the j-th device that transmits a message for clock synchronization, the first time stamp recorded by the j-th device is TS1 _j , and the second time stamp _{recorded by the j-th device is TS2 j} , then the message for clock synchronization is _{The residence time T stay_j} of the switching module of the j-th device can be calculated by the following formula (1):

T _{stay_j} = TS2 _j- TS1 _j formula (1)

Assuming that the end-to-end delay of the message used for clock synchronization from the source device to the sink device is Delay _e2e , where the unit of the end-to-end delay is milliseconds (ms), then Delay _e2e contains the message in The sum of the residence time of the switching module of each device except the sink device, and the optical fiber delay between the devices, etc. Therefore, the message resides in the switching module of each device except the sink device The time accumulated value is less than the terminal delay Delay _e2e , as shown in formula (2).

Where N is the sum of the number of source-end devices and intermediate devices, for example, N is equal to 20, which means that the source-end device sends the message for clock synchronization to the sink-end device and has been forwarded by 19 intermediate devices.

For the jth device, TS1 _j and TS2 _{j are} counted, which are affected by the local clock. According to the International Telecommunication Union Telecommunication Standardization Sector (ITU-T) G.813 standard, in general, the clock of the j-th device is a tertiary clock, and the maximum frequency deviation of the clock frequency between devices is foffset _max , where the unit of the maximum frequency offset is parts per million (ppm), and formula (3) can be obtained:

-foffset _max ≤foffset _j ≤+foffset _max formula (3)

Therefore, in the j-th device, _{the maximum value of the change in residence time T stay_j} can be calculated by the following formula (4):

PDV _j,max = 2*foffset _max ×T _{stay_j} (ns) formula (4)

Among them, _{the unit of PDV j,max} is nanosecond (nanosecond, ns).

For the long-chain networking scenario, the message used for clock synchronization is forwarded by N devices to the sink device, then the end-to-end delay variation PDV _{e2e of} the long-chain networking can be expressed by the following formula (5) :

Combining formula (2), formula (3) and formula (5), we can know:

which is:

PDV _e2e ≤2*foffset _max × Delay _e2e (ns) formula (7)

For OTN networks, the end-to-end delay of long-chain networking is small, for example, Delay _e2e ≤1ms, and the maximum frequency deviation of the clock frequency between devices foffset _max is 4.6ppm, that is: -4.6ppm≤foffset _j ≤+4.6 ppm.

According to formula (7), it can be known that PDV _e2e ≤ 2*4.6ppm×1ms=9.2ns.

Regarding the second factor, there is a certain error in the time stamp counted by the real-time clock. It should be noted that the frequency of the clock used to record the first time stamp and the second time stamp is F _rtc , where the unit of frequency is megahertz (MHz), the error of calculating the timestamp is ±1000/F _rtc (ns), and the maximum error introduced by a device in calculating the timestamp is 1000/F _rtc (ns). Assuming that the aforementioned N is equal to 20, the second factor The introduced end-to-end delay variation can be expressed by the following formula (8):

PDV _{e2e_ts} ≤20000/F _rtc (ns) formula (8)

Assuming that F _rtc is equal to 155.52MHz, the error of calculating the timestamp is +/-6.43ns, and the maximum error introduced by a device in calculating the timestamp is 12.86ns. If N is equal to 20, then PDV _{e2e_ts} ≤257.2ns, where 257.2= 12.86*20.

Combining the above two factors, using the packet delay variation introduced by the scheme shown in Figure 3, the theoretical maximum value is

PDV _e2e,max = 2*foffset _max × Delay _e2e +20000/F _rtc (ns)

In one embodiment, PDV _e2e,max =257.2ns+9.2ns=266.4ns.

However, the packet experiment variation eliminated by the method shown in FIG. 3 can generally reach the microsecond level, for example, up to 1 microsecond or more. It can be seen that using the solution of the embodiment of the present application, although an additional packet delay variation is introduced For example, the 266.4ns packet delay variation is introduced, but the eliminated packet delay variation is much larger than the introduced packet delay variation, thereby improving the accuracy of clock synchronization.

Based on the message processing method and clock synchronization method for clock synchronization provided in the above embodiments, the embodiment of the present application also provides a corresponding device, which is described below with reference to the accompanying drawings.

Referring to FIG. 5, FIG. 5 is a schematic structural diagram of a message processing apparatus for clock synchronization provided by an embodiment of the application. The message processing device 500 for clock synchronization shown in FIG. 5 can be used to execute the clock synchronization method shown in FIG. 3. Specifically, the message processing apparatus 500 for clock synchronization may include an acquiring unit 501, a recording unit 502, a determining unit 503, a generating unit 504, and a sending unit 505.

The obtaining unit 501 is used to obtain a first message; the recording unit 502 is used to record a first time stamp indicating the moment when the first message is obtained; and the determining unit 503 is used to determine to forward the first message according to the first message. The port of the message; the recording unit 502 is further configured to record a second time stamp used to indicate the time when the port is determined; the generating unit 504 is configured to generate a second message including a third time stamp according to the first message, The third time stamp is determined according to the difference between the second time stamp and the first time stamp; the sending unit 505 is configured to send the second message to the second device.

In a possible implementation manner, the acquiring unit 501 is specifically configured to generate the first message; the recording unit 502 is specifically configured to record the first time indicating the moment when the first message is generated stamp.

In a possible implementation manner, the acquiring unit 501 is specifically configured to acquire the first message from a third device, and the first message carries a fourth timestamp; the third timestamp is equal to the The sum of the difference and the fourth time stamp.

Since the device 500 is a device corresponding to the message processing method for clock synchronization in FIG. 3 described in the above embodiment, the specific implementation of each unit of the device 500 is based on the same idea as the above method embodiment, so For the specific implementation of each unit of the apparatus 500, reference may be made to the description part of the above method embodiment about the message processing method for clock synchronization corresponding to FIG. 3, which is not repeated here.

Refer to FIG. 6, which is a schematic structural diagram of a clock synchronization device provided by an embodiment of the application. The clock synchronization apparatus 600 shown in FIG. 6 may be used to execute the steps performed by the second device as the sink device. Specifically, the clock synchronization device 600 may include an acquiring unit 601, a recording unit 602, and a synchronization unit 603.

The obtaining unit 601 is used for obtaining a second message from the first device, and the second message includes a third time stamp, which is determined according to the apparatus 500 shown in FIG. 5; the recording unit 602 is used for recording At the fifth time stamp indicating the time when the second message is acquired; the synchronization unit 603 is configured to perform clock synchronization according to the difference between the fifth time stamp and the third time stamp.

Since the device 600 is a device corresponding to the steps performed by the second device as the sink device described in the above embodiment, the specific implementation of each unit of the device 600 is based on the same idea as the above method embodiment, therefore, Regarding the specific implementation of each unit of the apparatus 600, reference may be made to the description part of the steps performed by the second device as the sink device in the above method embodiments, which will not be repeated here.

It should be noted that the aforementioned message processing device 500 and clock synchronization device 600 for clock synchronization may have a hardware structure as shown in FIG. 7. FIG. 7 is a diagram of a device provided by an embodiment of the application. Schematic.

Please refer to FIG. 7, the device 700 includes a processor 710, a communication interface 720, and a memory 730. The number of processors 710 in the device 700 may be one or more. One processor is taken as an example in FIG. 7. In the embodiment of the present application, the processor 710, the communication interface 720, and the memory 730 may be connected through a bus system or other methods. In FIG. 7, the connection through the bus system 740 is taken as an example.

The processor 710 may be a central processing unit (CPU), a network processor (NP), or a combination of a CPU and an NP. The processor 710 may further include a hardware chip. The above-mentioned hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD) or a combination thereof. The above-mentioned PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination thereof.

The memory 730 may include a volatile memory (English: volatile memory), such as random-access memory (RAM); the memory 730 may also include a non-volatile memory (English: non-volatile memory), such as fast Flash memory (English: flash memory), hard disk drive (HDD) or solid-state drive (SSD); the memory 730 may also include a combination of the foregoing types of memory. When the device 700 corresponds to the aforementioned message processing apparatus 500 for clock synchronization, the memory 730 may store, for example, a first time stamp, a second time stamp, and a third time stamp; when the device 700 corresponds to the clock synchronization apparatus 600 shown in FIG. 6 The memory 730 may store the fifth time stamp and the third time stamp, for example.

Optionally, the memory 730 stores an operating system and a program, an executable module or a data structure, or a subset of them, or an extended set of them, where the program may include various operation instructions for implementing various operations. The operating system may include various system programs for implementing various basic services and processing hardware-based tasks. The processor 710 can read the program in the memory 730 to implement the message processing method or the clock synchronization method for clock synchronization provided in the embodiments of the present application.

The bus system 740 may be a peripheral component interconnect standard (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus system 740 can be divided into an address bus, a data bus, a control bus, and so on. For ease of representation, only one thick line is used in FIG. 7, but it does not mean that there is only one bus or one type of bus.

The embodiments of the present application also provide a computer-readable storage medium, including instructions or computer programs, which when run on a computer, cause the computer to execute the message processing method or the clock synchronization method for clock synchronization provided in the above embodiments.

The embodiments of the present application also provide a computer program product containing instructions or computer programs, which when run on a computer, cause the computer to execute the message processing method or the clock synchronization method for clock synchronization provided in the above embodiments.

The device or device mentioned in this application may be a network device, such as a switch, a router, a server, or a part of a network device or server. In some embodiments, the device or device of the present application may also be a functional module deployed in the device or network.

The terms "first", "second", "third", "fourth", etc. (if any) in the description and claims of this application and the above-mentioned drawings are used to distinguish similar objects, without having to use To describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances so that the embodiments described herein can be implemented in a sequence other than the content illustrated or described herein. In addition, the terms "including" and "having" and any variations of them are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those clearly listed. Those steps or units may include other steps or units that are not clearly listed or are inherent to these processes, methods, products, or equipment.

Those skilled in the art can clearly understand that, for the convenience and conciseness of the description, the specific working process of the above-described system, device, and unit can refer to the corresponding process in the foregoing method embodiment, which will not be repeated here.

In the several embodiments provided in this application, it should be understood that the disclosed system, device, and method can be implemented in other ways. For example, the device embodiments described above are merely illustrative, for example, the division of units is only a logical business division, and there may be other divisions in actual implementation, for example, multiple units or components can be combined or integrated. To another system, or some features can be ignored, or not implemented. In addition, the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.

In addition, the business units in the various embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit. The above-mentioned integrated unit can be realized in the form of hardware or software business unit.

If the integrated unit is implemented in the form of a software business unit and sold or used as an independent product, it can be stored in a computer readable storage medium. Based on this understanding, the technical solution of the present application essentially or the part that contributes to the existing technology or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium , Including several instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods in the various embodiments of the present application. The aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disks or optical disks and other media that can store program codes. .

Those skilled in the art should be aware that, in one or more of the foregoing examples, the services described in the present invention can be implemented by hardware, software, firmware, or any combination thereof. When implemented by software, these services can be stored in a computer-readable medium or transmitted as one or more instructions or codes on the computer-readable medium. The computer-readable medium includes a computer storage medium and a communication medium, where the communication medium includes any medium that facilitates the transfer of a computer program from one place to another. The storage medium may be any available medium that can be accessed by a general-purpose or special-purpose computer.

The above specific implementations further describe the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above are only specific implementations of the present invention.

Above, the above embodiments are only used to illustrate the technical solutions of the present application, not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, a person of ordinary skill in the art should understand that it can still implement the foregoing various implementations. The technical solutions described in the examples are modified, or some of the technical features are equivalently replaced; these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

A message processing method for clock synchronization, which is characterized in that it comprises:

The first device obtains the first message, and records a first time stamp used to indicate the moment when the first device obtains the first message;

Determining, by the first device, a port for forwarding the first message according to the first message, and recording a second time stamp used to indicate the moment when the first device determines the port;

The first device generates a second message including a third time stamp according to the first message, and sends the second message to the second device, and the third time stamp is based on the second time stamp and the time stamp. The difference of the first time stamp is determined.
The method according to claim 1, wherein the first device acquiring the first message and recording a first timestamp indicating the moment when the first device acquires the first message comprises:

The first device generates the first message, and records the first timestamp indicating the moment when the first device generates the first message.
The method according to claim 1, wherein the obtaining of the first message by the first device comprises:

Acquiring, by the first device, the first message from a third device, where the first message carries a fourth timestamp;

The third time stamp is equal to the sum of the difference and the fourth time stamp.
The method according to any one of claims 1 to 3, wherein the first device is a source device or an intermediate device that uses a circuit emulation service adaptive clock recovery CESACR method for clock transfer.
The method according to any one of claims 1-3, wherein the first device is a source device that uses a circuit emulation service adaptive clock recovery CESACR method for clock transfer, and the first message is the The message for clock synchronization received by the first device from the device as the clock source; or

The first device is an intermediate device that uses the CESACR method for clock transfer, and the first message is a message for clock synchronization received by the first device from a third device, and the first device is the The next hop device of the third device.
The method according to any one of claims 1-5, wherein the first message includes a field for carrying time stamp data.
The method according to any one of claims 1-6, wherein the first device is a device in an optical transport network (OTN).
The method according to any one of claims 1-7, wherein the first device is a device that processes a constant bit rate CBR service.
8. The method according to any one of claims 1-8, wherein the clock synchronization between the first device and the second device is achieved through an adaptive clock recovery ACR algorithm.
A clock synchronization method is characterized in that it includes:

The second device obtains the second message from the first device, and records a fifth timestamp indicating the moment when the second device obtains the second message, the second message includes the third timestamp, so The third time stamp is determined according to the method according to any one of claims 1-9;

The second device performs clock synchronization according to the difference between the fifth time stamp and the third time stamp.
The method according to claim 10, wherein the second device implements clock synchronization between the first device and the second device through an adaptive clock recovery ACR algorithm.
The method according to claim 11, wherein the input value of the ACR algorithm is the difference between the fifth time stamp and the third time stamp.
The method according to any one of claims 10-12, wherein the second device is a sink device.
A message processing device for clock synchronization, which is characterized in that it comprises:

The obtaining unit is used to obtain the first message;

A recording unit, configured to record a first time stamp used to indicate the moment when the first message is acquired;

A determining unit, configured to determine a port for forwarding the first message according to the first message;

The recording unit is further configured to record a second time stamp used to indicate the time when the port is determined;

A generating unit, configured to generate a second message including a third time stamp according to the first message, the third time stamp being determined according to the difference between the second time stamp and the first time stamp;

The sending unit is configured to send the second message to the second device.
The device according to claim 14, wherein the acquiring unit is specifically configured to: generate the first message;

The recording unit is specifically configured to record the first time stamp used to indicate the moment when the first message is generated.
The device according to claim 14, wherein the acquiring unit is specifically configured to:

Acquiring the first message from a third device, where the first message carries a fourth timestamp;

The third time stamp is equal to the sum of the difference and the fourth time stamp.
The device according to any one of claims 14-16, wherein the device is a source device or an intermediate device that uses a circuit emulation service adaptive clock recovery CESACR method for clock transfer.
The device according to any one of claims 14-17, wherein the device is a source device that uses a circuit emulation service adaptive clock recovery CESACR method for clock transfer, and the first message is the first The message used for clock synchronization received by the device from the device as the clock source; or

The device is an intermediate device that uses the CESACR method for clock transfer, the first message is a message for clock synchronization received by the device from a third device, and the device is the next device of the third device. Jump equipment.
The device according to any one of claims 14-18, wherein the device is a device in an optical transport network (OTN).
The device according to any one of claims 14-19, wherein the device is a device for processing a constant bit rate CBR service.
A clock synchronization device, characterized in that it comprises:

An obtaining unit, configured to obtain a second message from the first device, the second message includes a third time stamp, and the third time stamp is determined according to the apparatus according to any one of claims 14-20;

A recording unit, configured to record a fifth timestamp used to indicate the moment when the second message is acquired;

The synchronization unit is configured to perform clock synchronization according to the difference between the fifth time stamp and the third time stamp.
The device according to claim 21, wherein the device implements clock synchronization between the first device and the device through an adaptive clock recovery ACR algorithm.
The device according to claim 22, wherein the input value of the ACR algorithm is the difference between the fifth time stamp and the third time stamp.
The device according to any one of claims 21-23, wherein the device is a sink device.
A method for processing messages, characterized in that it comprises:

Acquiring a first timestamp used to indicate the moment when the first message is acquired;

Determining a port for forwarding the first message according to the first message, and acquiring a second timestamp indicating the time when the port is determined;

A second message is generated, the second message includes a third timestamp, and the third timestamp is related to the difference between the second timestamp and the first timestamp.
The method according to claim 25, wherein said obtaining said first timestamp comprises: generating said first message, and obtaining said first message indicating the moment when said first message is generated. Timestamp.
The method according to claim 25, wherein said obtaining said first timestamp comprises: receiving said first message, said first message includes a fourth timestamp, and said third timestamp is equal to The sum of the difference and the fourth time stamp.
The method according to any one of claims 25-27, wherein the method is executed by a source device or an intermediate device that uses a circuit emulation service adaptive clock recovery CESACR method for clock transfer.
The method according to any one of claims 25-27, wherein the method is executed by a source device that uses a circuit emulation service adaptive clock recovery CESACR method for clock transfer, and the first message is the source The message used for clock synchronization received by the end device from the device as the clock source; or

The method is executed by an intermediate device that uses the CESACR method for clock transfer, and the first message is a message for clock synchronization received by the intermediate device from a third device, where the intermediate device is the third device The next hop device.
The method according to any one of claims 25-29, wherein the first message includes a field for carrying time stamp data.
The method according to any one of claims 25-29, wherein the method is executed by a device in an optical transport network (OTN).
The method according to any one of claims 25-31, wherein the method is executed by a device that processes a constant bit rate CBR service.
The method according to any one of claims 25-32, characterized in that the clock synchronization between devices is achieved through an adaptive clock recovery ACR algorithm.
A device, characterized by comprising: a processor,

The processor is configured to execute instructions or computer programs, and execute the method described in any one of claims 1-13 and 25-33.
The device according to claim 34, further comprising a memory, and the memory is configured to store the instruction or the computer program.
The device according to claim 34 or 35, wherein the device further comprises a communication interface.
A computer-readable storage medium, characterized by comprising instructions or computer programs, which when run on a computer, causes the computer to execute the method described in any one of claims 1-13 and 25-33.
A computer program product, characterized by comprising instructions or computer programs, which when run on a computer, causes the computer to execute the method described in any one of claims 1-13 and 25-33.