WO2021120026A1 - 视频处理设备 - Google Patents

视频处理设备 Download PDF

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Publication number
WO2021120026A1
WO2021120026A1 PCT/CN2019/126146 CN2019126146W WO2021120026A1 WO 2021120026 A1 WO2021120026 A1 WO 2021120026A1 CN 2019126146 W CN2019126146 W CN 2019126146W WO 2021120026 A1 WO2021120026 A1 WO 2021120026A1
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WIPO (PCT)
Prior art keywords
video
interface
processing
control signal
data
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PCT/CN2019/126146
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English (en)
French (fr)
Inventor
岳耀飞
周晶晶
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西安诺瓦星云科技股份有限公司
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Priority to PCT/CN2019/126146 priority Critical patent/WO2021120026A1/zh
Publication of WO2021120026A1 publication Critical patent/WO2021120026A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/222—Studio circuitry; Studio devices; Studio equipment
    • H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
    • H04N5/268—Signal distribution or switching

Definitions

  • This application relates to the technical field of video processing, and in particular to a video processing device.
  • Video processing equipment is an important basic product widely used in various fields such as the LED image display field, the projection display field, and the DLP (Digital Light Processing) display field.
  • DLP Digital Light Processing
  • the solution is to design multiple products.
  • Each product is equipped with different input interfaces, output interfaces and video processing circuits.
  • the existing This approach brings huge economic and technical challenges to R&D personnel.
  • the embodiments of the application provide a video processing device whose video input interface, video output interface, and video processing card are detachable and replaceable, which meets the needs of users for diversified video input, output interfaces, and video processing, and the hardware design is simple .
  • a video processing device provided by an embodiment of the present application includes: an interconnection board; a video pre-processing card that is detachably plugged into the interconnection board and is provided with a video input interface and a video pre-processing circuit, so The video input interface is connected to the video pre-processing circuit; the video processing card is detachably plugged into the interconnection board and is provided with a video processing circuit, and the video processing circuit is connected to the video pre-processing circuit through the interconnection board.
  • video post-processing card detachably plugged into the interconnection board and provided with a video post-processing circuit and a video output interface, the video output interface is connected to the video post-processing circuit;
  • video post-processing circuit The video processing circuit is connected through the interconnection board;
  • the main control circuit is connected to the video processing circuit; and
  • the power supply module is used to provide the video pre-processing card, the video processing card, and the video post-processing The card and the main control circuit supply power.
  • the above-mentioned technical solutions implement the decoding and pre-processing of the input video and the processing of the video data by adopting the hardware architecture in which three independent circuit boards and interconnecting boards are plugged into independent video pre-processing cards, video processing cards and video post-processing cards. , And video post-processing and encoding functions, and can be detachably plugged into the interconnection board through a connector.
  • the video input interface, video output interface and video processing card can be replaced according to user needs. , In order to meet the user's replacement of diversified input and output interfaces and video processing, and improve the user experience.
  • a second video output interface is provided on the video processing card, where the second video output interface includes multiple types of interfaces, for example, may include HDMI interface, DP interface, DVI interface, SDI interface and optical fiber interface. At least one of.
  • the interconnection board is provided with a first connector, a second connector, and a third connector; the video pre-processing card is provided with a plug-in connection with the first connector.
  • the first connector includes a first video data interface
  • the second connector includes a second video data interface and a third video data interface
  • the third connector includes a fourth video data interface.
  • Video data interface; the first video data interface is connected to the second video data interface, and the third video data interface is connected to the fourth video data interface; wherein, the first video data interface and the second video data interface The interface, the third video data interface, and the fourth video data interface are GTX protocol interfaces;
  • the fourth connector includes a pre-processing data interface, the pre-processing data interface is connected to the video pre-processing circuit, and the pre-processing data interface Connect the first video data interface;
  • the fifth connector includes a first video processing data interface and a second video processing data interface, the first video processing data interface and the second video processing data interface are respectively connected to the In the video processing circuit, the first video processing data interface is also connected to the second video data interface, and the second video processing data interface is also connected to the third video data interface;
  • the sixth connector includes post-processing A data interface,
  • the first connector further includes a first control signal interface
  • the second connector further includes a second control signal interface, a third control signal interface, and a fourth control signal interface
  • the third connector also includes a fifth control signal interface
  • the first control signal interface is connected to the second control signal interface
  • the third control signal interface is connected to the main control circuit
  • the fourth control signal interface Connect the fifth control signal interface
  • the fourth connector also includes a pre-processing control signal interface, the pre-processing control signal interface is connected to the video pre-processing circuit, and the pre-processing control signal interface is connected to the first Control signal interface
  • the fifth connector also includes a video processing control signal interface, a first signal forwarding interface and a second signal forwarding interface, the video processing control signal interface, the first signal forwarding interface and the second The signal forwarding interface is respectively connected to the video processing circuit, the video processing control signal interface is connected to the third control signal interface, the first signal forwarding interface is connected to the second control signal interface, and the second signal forwarding interface is Connected to the
  • the first video data interface of the first connector is connected to the second video of the second connector through a PCB (Printed Circuit Board) wiring
  • a data interface the third video data interface of the second connector is connected to the fourth video data interface of the third connector through a PCB trace;
  • the first control signal of the first connector The interface is connected to the second control signal interface of the second connector through a PCB trace, the third control signal interface of the second connector is connected to the main control circuit through a PCB trace, and the second The fourth control signal interface of the connector is connected to the fifth control signal interface of the third connector through a PCB trace.
  • the video pre-processing circuit includes: a first video processing device, a first controller, and a first non-volatile memory, and the first controller is connected to the first video processing device And the first non-volatile memory, the first video processing device is connected to the video input interface, the video pre-processing output interface, and the pre-processing control signal interface.
  • the video input interface of the first video processing device is used to decode control signals and parameters transmitted through the pre-processing control signal interface to obtain first decoded control signal data;
  • the first video processing device video is further configured to decode the video data obtained from the video input interface according to the first decoded control signal data to obtain decoded image data, and perform color space on the decoded image data
  • the image data after the color space conversion is obtained by conversion, the image data after the color space conversion is deinterlaced to obtain the image data after the deinterlacing, and the image data after the deinterlacing is adjusted to obtain the first image data after the image quality adjustment.
  • the first image quality adjusted image data is encoded and sent to the pre-processing data interface.
  • the number of the video input interfaces is multiple, and the multiple video input interfaces are selected from HDMI interfaces, DVI interfaces, DP interfaces, and SDI interfaces; the number of video output interfaces There are multiple video output interfaces, and the multiple video output interfaces are respectively selected from HDMI interface, DVI interface, DP interface, and SDI interface.
  • the video processing circuit includes: a second video processing device, a second controller, and a second non-volatile memory, and the second controller is connected to the second non-volatile memory. A memory and the second video processing device, the second video processing device is connected to the first video processing data interface, the second video processing data interface, the video processing control signal interface, the first signal forwarding interface, and The second signal forwarding interface.
  • the second video processing device is used to obtain the control signal and parameters transmitted by the main control circuit through the video processing control signal interface and decode to obtain the second decoded control signal data, Non-target control signals and parameters are forwarded to the video pre-processing card and the video post-processing card in a one-to-one correspondence through the first signal forwarding interface and the second signal forwarding interface; the second video processing device also uses After performing scaling processing on the image data obtained from the first video processing data interface according to the second decoded control signal data to obtain scaled image data, and performing image quality enhancement processing on the scaled image data to obtain image quality enhancement After image data, superimposing the image data after image quality enhancement is performed to obtain the superimposed image data, and the superimposed image data is encoded and output through the second video processing data interface.
  • the video post-processing circuit includes: a third video processing device, a third controller, and a third non-volatile memory, and the third controller is connected to the third video processing device And the third non-volatile memory, the third video processing device is connected to the video output interface, the post-processing data interface, and the post-processing control signal interface.
  • the third video processing device is configured to decode control signals and parameters transmitted through the post-processing control signal interface to obtain third decoded control signal data; the third video processing The device is further configured to adjust the image quality of the image data obtained from the post-processing data interface according to the third decoded control signal data to obtain second image quality adjusted image data, and to adjust the second image quality adjusted image
  • the data is encoded to obtain encoded video data, and the encoded video data is output through the video output interface.
  • the interconnection board further includes a seventh connector, the seventh connector includes a sixth control signal interface, and the sixth control signal interface is connected to the third control signal interface;
  • the video processing device further includes: a main control card, detachably plugged into the interconnection board, and the main control circuit is provided on the main control card;
  • the main control card further includes The eighth connector plugged by the seventh connector, the eighth connector includes a control signal output interface, and the main control circuit is connected to the sixth control signal interface through the control signal output interface.
  • the video pre-processing card is at least one, the at least one video pre-processing card is detachably plugged into the interconnection board, and the at least one video pre-processing card
  • the video pre-processing circuit is respectively connected to the video processing circuit through the interconnection board
  • the video post-processing card is at least one, and the at least one video post-processing card is respectively detachably plugged into the interconnection board
  • the video post-processing circuit of the at least one video post-processing card is respectively connected to the video processing circuit through the interconnection board.
  • the video processing device uses three independent circuit boards of independent video pre-processing cards, video processing cards, and video post-processing cards to realize input respectively.
  • Video decoding and pre-processing, video processing, video post-processing and encoding and other functions are detachably plugged into the interconnection board through a connector, and a relatively simple hardware design realizes a video input interface according to user needs ,
  • the replacement of the video output interface and video processing card to meet the user's replacement of diversified input, output interfaces and video processing, and improve the user experience.
  • each board communicates with each other through FPGA's GTX.
  • the video pre-processing card transmits the decoded image to the video processing card through GTX. After the processing is completed, the video is also sent to the video post-processing card through GTX to make it based
  • the encoding specifications of different video interfaces output video images through different video interfaces, realizing that there is no need to use expensive switching chips to complete the selection and switching of input video interfaces and output video interfaces within a certain scale, saving video The cost of processing equipment.
  • FIG. 1 is a schematic structural diagram of a video processing device provided by an embodiment of the application.
  • FIG. 2 is a schematic diagram of another structure of a video processing device provided by an embodiment of the application.
  • Fig. 3a is a schematic diagram of the structure of the video pre-processing card shown in Fig. 2.
  • Fig. 3b is a schematic structural diagram of the video processing device shown in Fig. 3a.
  • Fig. 4a is a schematic diagram of the structure of the video processing card shown in Fig. 2.
  • Fig. 4b is a schematic diagram of the structure of the video processing device shown in Fig. 4a.
  • Fig. 5a is a schematic diagram of the structure of the video post-processing card shown in Fig. 2.
  • Fig. 5b is a schematic structural diagram of the video processing device shown in Fig. 5a.
  • FIG. 6a is another schematic structural diagram of a video processing device provided by an embodiment of this application.
  • Fig. 6b is a schematic structural diagram of the main control circuit shown in Fig. 6a.
  • FIG. 7 is another schematic structural diagram of a video processing device provided by an embodiment of this application.
  • FIG. 8 is a schematic diagram of another structure of the video processing card shown in FIG. 2.
  • the video processing device 100 mainly includes, for example, an interconnection board 110, a main control circuit 111, a video pre-processing card 130, a video processing card 150, a video post-processing card 170, and other circuits such as a power module 180.
  • the main control circuit 111 may be provided on the interconnection board 110. It can be understood here that the main control circuit 111 may be directly located on the interconnection board 110, or may be located on another circuit board different from the interconnection board 100 and connected to the interconnection board 110 through a corresponding interface.
  • the video pre-processing card 130, the video processing card 150, and the video post-processing card 170 are detachably plugged into the interconnection board 110. In this way, the user's need to change the video input interface, video output interface and video processing card at will can be met, and the hardware design cost is relatively low.
  • the main control circuit 111 is mainly used to provide control signals and related parameters to the video pre-processing card 130, the video processing card 150, and the video post-processing card 170.
  • the interconnection board 110 is a PCB circuit board. As shown in FIG. 2, the interconnection board 110 is also provided with multiple connectors, such as connector 113, connector 114, and connector 115, which are used to plug the video pre-processing card 130, the video processing card 150, and the video post-processing card respectively. Processing card 170.
  • the multiple connectors here are, for example, pin header connectors, female header connectors, or high-density connectors.
  • the connector 113 includes a video data interface 1131 and a control signal interface 1132.
  • the connector 114 includes a video data interface 1141, a video data interface 1142, a control signal interface 1143, a control signal interface 1144, and a control signal interface 1145.
  • the connector 115 includes a video data interface 1151 and a control signal interface 1152.
  • the video data interface 1131 is connected to the video data interface 1141, and the video data interface 1142 is connected to the video data interface 1151.
  • the control signal interface 1132 is connected to the control signal interface 1144, the control signal interface 1143 is connected to the main control circuit 111, and the control signal interface 1145 is connected to the control signal interface 1152.
  • the main control circuit 111 mainly includes, for example, an embedded controller 1111, such as an embedded processor based on an ARM core.
  • the video pre-processing card 130 is mainly used for pre-processing the input video source.
  • the video pre-processing card 130 is detachably plugged into the interconnection board 110.
  • the video pre-processing card 130 is provided with, for example, a video input interface 131 and a video pre-processing circuit 132.
  • the video input interface 131 is connected to the video pre-processing circuit 132.
  • the video input interface 131 is used to receive externally input video source signals.
  • the video input interface 131 is, for example, a standard video interface, such as an HDMI interface, a DVI interface, a DP interface, or an SDI interface.
  • the video input interface 131 can also be an optical fiber interface or other interfaces for transmitting video or image data.
  • the number of the video input interface 131 may be multiple, and the multiple video input interfaces 131 are selected from part or all of the HDMI interface, the DVI interface, the DP interface, and the SDI interface, respectively. In this way, the user can set multiple video input interfaces 131 on the video pre-processing card 150 as needed to further meet the user's more diverse video input interface requirements.
  • the video pre-processing card 130 is also provided with a connector 133 that is plugged into the connector 113, so that the video pre-processing card 130 can be detachably plugged to the interconnection board 110.
  • the connector 133 includes, for example, a pre-processing data interface 1331 and a pre-processing control signal interface 1332.
  • the pre-processing data interface 1331 and the pre-processing control signal interface 1332 are respectively connected to the video pre-processing circuit 132.
  • the pre-processing data interface 1331 is connected to the video data interface 1131 of the connector 113, and the pre-processing control signal interface 1332 is connected to the control signal interface 1132 of the connector 113.
  • the video pre-processing circuit 132 is mainly used, for example, to perform processing such as decoding, spatial conversion, de-interlacing, and image quality adjustment on the input video source.
  • the video pre-processing circuit 132 includes, for example, a video processing device 1321, a controller 1322, and a non-volatile memory 1323.
  • the controller 1322 is connected to the video processing device 1321 and the non-volatile memory 1323.
  • the video processing device 1321 is connected to the video input interface 131.
  • the controller 1322 is, for example, a microcontroller (MCU).
  • the non-volatile memory 1323 is, for example, a flash memory (FLASH).
  • the video processing device 1321 includes, for example, a video decoding unit 13211, a color space conversion unit 13212, a de-interlacing unit 13213, an image quality adjustment unit 13214, and a control signal decoding unit 13215 connected in sequence.
  • the control signal decoding unit 13215 is connected to the pre-processing control signal interface 1332, the video decoding unit 13211, the color space conversion unit 13212, the de-interlacing unit 13213, and the image quality adjustment unit 13214.
  • the control signal decoding unit 13215 decodes the control signals and parameters input through the pre-processing control signal interface 1332 to obtain the first decoded control signal data for the video decoding unit 13211, the color space conversion unit 13212, the de-interlacing unit 13213, and the image quality adjustment Unit 13214 is used.
  • the video decoding unit 13211 is connected to the video input interface 131, which decodes the video data obtained from the video input interface 131 according to the first decoded control signal data to obtain decoded image data in RGB format.
  • the color space conversion unit 13212 converts the decoded image data from the RGB color space to the YUV color space according to the first decoded control signal data to obtain the color space converted image data.
  • the color space conversion unit 13212 can also convert the decoded image data from the RGB color space to other color spaces, such as the XYZ color space, according to the actual needs of the user. This is not the case in the present invention. limit.
  • the deinterlacing unit 13213 performs deinterlacing processing on the color space converted image data according to the first decoded control signal data to obtain deinterlaced image data, for example, converting input interlaced image data into progressive output image data.
  • the input image data is progressive image data, it does not need to be de-interlaced.
  • the image quality adjustment unit 13214 is configured to perform image quality adjustment processing on the deinterlaced image data according to the first decoded control signal data to obtain the first image quality adjusted image data, such as adjustment of brightness, contrast, color temperature, etc., and finally The image data after image quality adjustment is encoded and output to the pre-processing data interface 1331 in a 64B/66B encoding format, for example.
  • the video processing device 1321 can also be, for example, a programmable logic device such as FPGA (Field-Programmable Gate Array) or CPLD (Complex Programmable Logic Device, complex video processing device), etc. .
  • the video processing card 150 is mainly used for image data processing.
  • the video processing card 150 includes, for example, a video processing circuit 151 and a connector 153 that is plugged into the connector 113.
  • the video processing circuit 151 performs processing such as scaling, image quality enhancement, and layer aliasing on the image data received from the video pre-processing card 130, for example.
  • the video processing circuit 151 includes, for example, a video processing device 1511, a controller 1512, and a non-volatile memory 1513.
  • the controller 1512 connects the video processing device 1511 and the nonvolatile memory 1513.
  • the controller 1512 is, for example, a microcontroller (MCU).
  • MCU microcontroller
  • the non-volatile memory 1513 is, for example, a flash memory (FLASH).
  • the connector 153 is used for detachably plugging the video processing card 150 to the interconnection board 110.
  • the connector 153 includes, for example, a video processing data interface 1531, a video processing data interface 1532, a video processing control signal interface 1533, a signal forwarding interface 1534, and a signal forwarding interface 1535.
  • the video processing data interface 1531, the video processing data interface 1532, the video processing control signal interface 1533, the signal forwarding interface 1534, and the signal forwarding interface 1535 are respectively connected to the video processing device 1511 of the video processing circuit 151.
  • the video processing data interface 1531 is connected to the video data interface 1141 of the connector 114
  • the video processing data interface 1532 is connected to the video data interface 1142 of the connector 114
  • the video processing control signal interface 1533 is connected to the control signal interface of the connector 114.
  • the signal forwarding interface 1534 is connected to the control signal interface 1144 of the connector 114
  • the signal forwarding interface 1535 is connected to the control signal interface 1145 of the connector 114.
  • the video processing device 1511 includes, for example, an image scaling unit 15111, an image quality enhancement unit 15112, and a layer aliasing unit 15113 connected in sequence, and also includes a control signal decoding unit 15114 and a control signal forwarding unit 15115,
  • the control signal decoding unit 15114 is connected to the video processing control signal interface 1533, the image scaling unit 15111, the image quality enhancement unit 15112, and the layer aliasing unit 15113 to obtain the control signal from the main control circuit 111 through the video processing control signal interface 1533
  • the parameters are decoded to obtain the second decoded control signal data for use by the image scaling unit 15111, the image quality enhancement unit 15112, and the layer aliasing unit 15113.
  • the control signal decoding unit 15114 is further connected to the control signal forwarding unit 15115, and the control signal forwarding unit 15115 is connected to the signal forwarding interface 1534 and the signal forwarding interface 1535.
  • the control signal decoding unit 15114 is configured to forward the video pre-processing card 130 and the video post-processing card 170 through the control signal forwarding unit 15115, the signal forwarding interface 1534, and the signal forwarding interface 1535 in a one-to-one correspondence with control signals and parameters that do not belong to itself.
  • the control signals and parameters of the main control circuit 111 are usually transmitted in the form of data packets, for example.
  • the header part of the data packet includes the identification information of the receiving object of the control signal and the parameter.
  • the receiving object here can be, for example, a video pre-processing card, a video post-processing card, or a video processing card.
  • the identification information here can be, for example, 01, 02, or 03, for example, 01 represents the video pre-processing card, 02 represents the video processing card, and 03 represents the video post-processing card.
  • the video processing card 150 After the video processing card 150 receives the data packet, it will analyze the identification information of the receiving object in the header of the data packet through the control signal decoding unit 15114, and when it recognizes that the data packet belongs to its own control signal and parameters, it will receive The data packet; when it is recognized that the data packet does not belong to its own control signals and parameters, the data packet is sent to the control signal forwarding unit 15115 to output to the video pre-processing card 130 or the video post-processing card 170 through the signal forwarding interface. It is worth mentioning here that the control signals and parameters belonging to the video processing device 1511 may be referred to as target control signals and parameters, and the control signals and parameters not belonging to the video processing device 1511 itself may be referred to as non-target control signals and parameters.
  • the image scaling unit 15111 performs scaling processing on the image data obtained from the video processing data interface 1531 to obtain scaled image data.
  • the image quality enhancement unit 15112 performs image quality enhancement processing on the zoomed image data to obtain image data after image quality enhancement.
  • the image quality enhancement processing may include, for example, converting an SDR (Standard Dynamic Range, standard dynamic range) image into an HDR (High Dynamic Range, high dynamic range) image, and the like.
  • the layer aliasing unit 15113 performs mixing and superposition processing on the image data of at least one layer after the image quality has been enhanced. For example, first superimpose the image data of one of the layers with the background, and then combine the superimposed image data with other layers. The image data of the layers are superimposed one by one to obtain the superimposed image data, and then the superimposed image data is encoded and then output through the video processing data interface 1532 in a 64B/66B encoding format, for example. It is worth mentioning here that the video processing device 1511 may also be, for example, a programmable logic device such as FPGA (Field-Programmable Gate Array) or CPLD (Complex Programmable Logic Device, complex video processing device).
  • FPGA Field-Programmable Gate Array
  • CPLD Complex Programmable Logic Device, complex video processing device
  • the video post-processing card 170 is mainly used for post-processing the processed image data.
  • the video post-processing card 170 is detachably plugged into the interconnection board 110.
  • the video post-processing card 170 is provided with, for example, a video output interface 171 and a video post-processing circuit 172.
  • the video output interface 171 is connected to the video post-processing circuit 172.
  • the video output interface 171 is used to output the processed image data to a back-end device such as an LED display controller.
  • the video output interface 171 is, for example, a standard video interface, such as an HDMI interface, a DVI interface, a DP interface, or an SDI interface.
  • the number of video output interfaces 171 may be multiple, and the multiple video output interfaces 171 are selected from part or all of HDMI interfaces, DVI interfaces, DP interfaces, and SDI interfaces.
  • the video output interfaces 171 may also be optical fiber interfaces. Or other interfaces used to transmit video or image data, this application is not limited to this. In this way, the diversified video output interface needs of users can be further satisfied.
  • the video post-processing card 170 is also provided with a connector 173 that is plugged into the connector 115, so that the video post-processing card 170 can be detachably plugged to the interconnection board 110.
  • the connector 173 includes, for example, a post-processing data interface 1731 and a post-processing control signal interface 1732.
  • the post-processing data interface 1731 and the post-processing control signal interface 1732 are respectively connected to the video post-processing circuit 172.
  • the post-processing data interface 1731 is connected to the video data interface 1151 of the connector 115
  • the post-processing control signal interface 1732 is connected to the control signal interface 1152 of the connector 115.
  • the video post-processing circuit 172 performs post-processing on the image data processed by the video processing circuit 151, such as image quality adjustment, encoding, and the like.
  • the video post-processing circuit 172 includes, for example, a video processing device 1721, a controller 1722, and a non-volatile memory 1723.
  • the controller 1322 is connected to the video processing device 1321 and the non-volatile memory 1323.
  • the video processing device 1721 is connected to the video output interface 171.
  • the controller 1322 is, for example, a microcontroller (MCU).
  • the non-volatile memory 1323 is, for example, FLASH (flash memory).
  • the video processing device 1721 includes, for example, an image quality adjustment unit 17211, an image encoding unit 17212, and a control signal decoding unit 17213.
  • the image quality adjustment unit 17211 is connected between the image encoding unit 17212 and the post-processing data interface 1731.
  • the control signal decoding unit 17213 is connected to the post-processing control signal interface 1732, the image quality adjustment unit 17211, and the image encoding unit 17212.
  • the control signal decoding unit 17213 decodes the control signals and parameters obtained through the post-processing control signal interface 1732 to obtain the third decoded control signal data for use by the image quality adjustment unit 17211 and the image encoding unit 17212.
  • the image quality adjustment unit 17211 adjusts the image quality of the image data obtained from the post-processing data interface 1731 and processed by the video processing circuit 151, such as multi-layer image data after layer aliasing, according to the third decoded control signal data. Adjust brightness, contrast, color temperature, etc. to obtain the image data after the second image quality adjustment.
  • the image encoding unit 17212 encodes the image data after the image quality adjustment according to the third decoded control signal data to obtain the encoded image data in the format required by the user, and outputs the encoded video data through the video output interface 171.
  • the video processing device 1321 may be, for example, a programmable logic device such as FPGA (Field-Programmable Gate Array) or CPLD (Complex Programmable Logic Device, complex video processing device).
  • the video preprocessing card 130 preprocesses the input video source, and then transmits the preprocessed image data to the video processing card 150 through the connector of the interconnection board.
  • Image processing such as scaling, and then transfer the processed image data to the video post-processing card 170 through the connector of the interconnection board for post-processing, and encode the image data into a corresponding format according to the type of the video output interface and output it from the video output interface To complete the entire video processing process.
  • the power supply module 180 is used to supply power to the video pre-processing card 130, the video processing card 150, the video post-processing card 170 and the main control circuit 111.
  • the power supply module 180 may be, for example, a power supply module provided in the video processing device 100, or may be an external power supply module of the video processing device 100.
  • the power module 180 supplies power to the video pre-processing card 130, the video processing card 150, the video post-processing card 170, and the main control circuit 111, which can be understood as the power module 180 connected to the interconnection board 110 and connected to the video pre-processing through the interconnection board 110
  • the card 130, the video processing card 150, the video post-processing card 170 and the main control circuit 111 are used for power supply. It can also be understood that the power module 180 is directly connected to the video pre-processing card 130, the video processing card 150, the video post-processing card 170 and the main control circuit.
  • 111 is used for power supply, of course, other power supply methods are also possible, and this application is not limited to this. For example, as shown in FIG.
  • a power interface 118 is also provided on the interconnection board 110.
  • the power interface 118 is, for example, a pin header connector.
  • the power interface 118 is connected to the video pre-processing card 130, the video processing card 150, the video post-processing card 170, and the main control circuit 111.
  • the power module 180 is connected to the power interface 118 to supply power to the video pre-processing card 130, the video processing card 150, the video post-processing card 170, and the main control circuit 111 through the power interface 118 and multiple connectors on the interconnection board.
  • the connector 113 on the interconnection board 110 and the connector 114, and the connector 114 and the connector 115 are directly connected by PCB (Printed Circuit Board) wiring, that is, the connector There are no active components (or active components) between 113 and the connector 114, and between the connector 114 and the connector 115.
  • the video data interface 1131 is directly connected to the video data interface 1141 through the PCB wiring
  • the video data interface 1142 is directly connected to the video data interface 1151 through the PCB wiring
  • the control signal interface 1132 is directly connected to the control signal interface 1144 through the PCB wiring
  • the control The signal interface 1143 is directly connected to the main control circuit 111 through PCB wiring
  • the control signal interface 1145 is directly connected to the control signal interface 1152 through PCB wiring.
  • the FPGA of the video processing card 150 functions as a switch chip while completing video processing, so that the setting of the interactive chip can be eliminated, which saves expensive switch chips and reduces costs.
  • the video data interface 1131, the video data interface 1141, the video data interface 1142, the video data interface 1151, the pre-processing data interface 1331, the video processing data interface 1531, the video processing data interface 1532, the post-processing data interface 1731 are GTX (Gigabit Transceiver, gigabit transceiver) protocol interface, in this way can realize the fast transmission of video or image data.
  • the processing control signal interface 1732 is an Ethernet protocol interface.
  • the video processing device 100 may also include a main control card 190.
  • the main control card 190 includes a main control circuit 111.
  • the main control card 190 is also provided with a connector 191.
  • the connector 191 includes a control signal output interface 1911.
  • the control signal output interface 1911 is connected to the main control circuit 111.
  • a connector 116 is also provided on the interconnection board 110.
  • the connector 116 includes a control signal interface 1161.
  • the control signal interface 1161 is connected to the control signal interface 1143 and the control signal output interface 1911 of the connector 191.
  • the main control card 190 can also be detachably plugged into the interconnection board 110, and the user can also replace and adjust the main control card 190 according to actual needs, which further meets the diverse needs of users and improves User experience.
  • the main control circuit 111 uses ARM as the main control unit, and eMMC and Flash serve as data storage and program caching functions.
  • the main control circuit 111 also provides interfaces such as RS232, USB, and RJ45 to interconnect the host computer and the ARM of the main control circuit 111, so as to realize the computer-side software control of the video processing device 100.
  • the WIFI module of the main control circuit 111 can connect other mobile devices to the video processing device 100.
  • the ARM's FMC/FSMC, I2C, SPI and other data buses of the main control circuit 111 can also be connected to the interconnection board through FCI interfaces such as high-density connectors, header connectors, etc. 110 is connected to complete the interconnection with the upper computer software and the lower interconnection board 110.
  • the main control circuit 111 also has a U disk drive, and provides a separate USB interface as a U disk to save offline files, offline upgrades and other functions.
  • the RTC module inside the main control circuit 111 provides a real-time clock for the entire control system.
  • the number of the video pre-processing card 130 may be at least one, and the at least one video pre-processing card 130 can be detachably plugged into the interconnection via a connector, for example.
  • the video pre-processing circuit of at least one video pre-processing card 130 is connected to the video processing circuit 151 of the video processing card 150 through the interconnection board 110, respectively.
  • the number of video post-processing cards 170 may also be at least one. At least one video post-processing card 170 is also detachably plugged into the interconnection board 110, for example, through a connector.
  • the video post-processing circuit of the at least one video post-processing card 170 The video processing circuit 151 of the video processing card 150 is connected through the interconnection board 110 respectively. In this way, the diversified needs of users for input and output interfaces are further satisfied, and the user experience is improved.
  • the at least one video pre-processing card may also be a video pre-processing card with different video input interfaces
  • the at least one video post-processing card may also be a video post-processing card with different video output interfaces.
  • a video output interface 155 may also be provided on the video processing card 150.
  • the number of video output interfaces 155 may be one or more.
  • the video output interface 155 may also be, for example, at least one of an HDMI interface, a DP interface, a DVI interface, an SDI interface, and an optical fiber interface. In this way, it can be directly output from the video output interface 155 on the video processing card 150 without post-processing the video or image to meet more needs of users.
  • the video processing device adopts three independent circuit boards of independent video pre-processing cards, video processing cards, and video post-processing cards to implement input video decoding and pre-processing, video processing, and video post-processing, respectively.
  • Functions such as processing and encoding are detachably plugged into the interconnection board through a connector.
  • the relatively simple hardware design realizes the replacement of the video input interface, video output interface and video processing card according to user needs to meet the needs of users.
  • the replacement of diversified input and output interfaces and video processing has improved the user experience. This also promotes the generalization and modularization of video processing equipment products, and saves parts management costs.
  • each board communicates with each other through FPGA's GTX.
  • the video pre-processing card transmits the decoded image to the video processing card through GTX. After the processing is completed, the video is also sent to the video post-processing card through GTX to make it based
  • the encoding specifications of different video interfaces output video images through different video interfaces, realizing that there is no need to use expensive switching chips to complete the selection and switching of input video interfaces and output video interfaces within a certain scale, saving video The cost of processing equipment.
  • the video pre-processing card (or input card), video post-processing card (or output card) and video processing card (or processing card) are all interconnected through GTX, and their connections are all in It is implemented on the interconnection board.
  • the interconnection board is only for direct connection of connectors such as connectors.
  • the number of connections that can be connected is determined by the FPGA model on the processing card. For example, when the FPGA model on the processing card is xcku060, it can provide 28 GTX channels.
  • each video input source needs 2 GTX channels to transmit, then the video processing card can achieve the same with other The interaction of 14 4K ⁇ 2K video images is realized between the input card and the output card.
  • the decoding of various input sources is completed in the input card, including SDI, HDMI, DP, DVI and other video interfaces, and these video interfaces can be customized according to user needs. For example, when the user needs 3 HDMI and 1 SDI, It can be realized only by multiple instantiations in the video decoding unit of the input card. After decoding, it needs to be encoded according to a custom protocol.
  • the input source is output according to the 64B/66B encoding format, and all video sources are follows the agreement.
  • the video processing card there is no need to distinguish the type of input video source, and the limitation of resources on this video processing card depends on the GTX resources. For example, choose the FPGA model of xc7k325t on the input card, which has 16 channels. GTX, you can send up to 8 channels of 4K ⁇ 2K video input sources to the video processing card for processing.
  • the processing card mainly completes the processing of video images, including scaling, image quality adjustment, layer overlay, etc. It decodes the video source sent by the input card from the GTX format and treats it as a common video source for subsequent video processing.
  • the final video data is sent to the output card through GTX.
  • the video data that needs to be output in the output card is output through different video output interfaces under different encoding protocols.
  • the interconnection board only needs to directly connect the GTX transmitter on the input card with the GTX receiver on the processing card according to the requirements of each board, and at the same time directly connect the transmitter on the processing card with the receiver on the output card. Connection, no active components are set in the middle, and the communication between each board is a custom unified protocol.
  • the FPGA of the video processing card acts as a switching chip while completing video processing, saving Expensive switching chips are reduced, and costs are reduced.
  • the disclosed system, device, and method can be implemented in other ways.
  • the device embodiments described above are merely illustrative, for example, the division of units is only a logical function division, and there may be other divisions in actual implementation, for example, multiple units or components can be combined or integrated. To another system, or some features can be ignored, or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.
  • the functional units in the various embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit.
  • the above-mentioned integrated unit may be implemented in the form of hardware, or may be implemented in the form of hardware plus software functional units.

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Abstract

本申请实施例公开的一种视频处理设备包括：互连板；视频前处理卡，可拆卸地插接至所述互连板且设置有视频输入接口、视频前处理电路，所述视频输入接口连接所述视频前处理电路；视频处理卡，可拆卸地插接至所述互连板且设置有视频处理电路，所述视频处理电路通过所述互连板连接所述视频前处理电路；视频后处理卡，可拆卸地插接至所述互连板且设置有视频后处理电路、视频输出接口，所述视频输出接口连接所述视频后处理电路；所述视频后处理电路通过所述互连板连接所述视频处理电路；主控电路，与所述视频处理电路连接；以及电源模块，用于给所述视频前处理卡、所述视频处理卡、所述视频后处理卡以及所述主控电路供电。

Description

视频处理设备 技术领域
本申请涉及视频处理技术领域，尤其涉及一种视频处理设备。
背景技术
视频处理设备是LED图像显示领域、投影显示领域及DLP(Digital Light Processing，数字光处理)显示领域等各个领域广泛应用的重要基础产品。对此，随着用户需求丰富，对视频输入接口、视频输出接口的类型及视频处理功能也提出了更多的要求。
目前，为了满足用户的需求，解决方案是设计多款产品，每款产品配置不同输入接口、输出接口及视频处理电路，然而由于视频处理设备的整机研发成本高且硬件设计复杂，因此现有做法给研发人员带来巨大的经济及技术挑战。
综上所述，在视频处理技术领域的发展方向中，如何提高产品设计灵活性且降低研发成本以满足时下复杂多样的用户需求已成为重要议题之一。
发明内容
本申请的实施例提供了一种视频处理设备，其视频输入接口、视频输出接口及视频处理卡可拆卸更换，满足了用户对多样化视频输入、输出接口以及视频处理的需求，且硬件设计简单。
具体地，本申请实施例提供的一种视频处理设备，包括：互连板；视频前处理卡，可拆卸地插接至所述互连板且设置有视频输入接口、视频前处理电路，所述视频输入接口连接所述视频前处理电路；视频处理卡，可拆卸地插接至所述互连板且设置有视频处理电路，所述视频处理电路通过所述互连板连接所述视频前处理电路；视频后处理卡，可拆卸地插接至所述互连板且设置有视频后处理电路、视频输出接口，所述视 频输出接口连接所述视频后处理电路；所述视频后处理电路通过所述互连板连接所述视频处理电路；主控电路，与所述视频处理电路连接；以及电源模块，用于给所述视频前处理卡、所述视频处理卡、所述视频后处理卡以及所述主控电路供电。
上述技术方案通过采用独立的视频前处理卡、视频处理卡以及视频后处理卡三个独立的电路板与互连板插接的硬件架构，来分别实现输入视频的解码与预处理、视频数据处理、以及视频后处理及编码等功能，且通过接插件可拆卸地插接至互连板上，通过相对简单的硬件设计实现了根据用户需求进行视频输入接口、视频输出接口以及视频处理卡的更换，以满足用户对多样化输入、输出接口以及视频处理的更换，提升了用户体验。
可选地，视频处理卡上设置有第二视频输出接口，其中，所述第二视频输出接口包括多种类型的接口，例如可包括HDMI接口、DP接口、DVI接口、SDI接口和光纤接口中的至少一种。
在本申请的一个实施例中，所述互连板上设置有第一接插件、第二接插件、第三接插件；所述视频前处理卡上设置有与所述第一接插件插接的第四接插件；所述视频处理卡上设置有与所述第二接插件插接的第五接插件；所述视频后处理卡上设置有与所述第三接插件插接的第六接插件。
在本申请的一个实施例中，所述第一接插件包括第一视频数据接口，所述第二接插件包括第二视频数据接口、第三视频数据接口，所述第三接插件包括第四视频数据接口；所述第一视频数据接口连接所述第二视频数据接口，所述第三视频数据接口连接所述第四视频数据接口；其中，所述第一视频数据接口、第二视频数据接口、第三视频数据接口和第四视频数据接口为GTX协议接口；所述第四接插件包括前处理数据接口，所述前处理数据接口连接所述视频前处理电路，所述前处理数据接口连接所述 第一视频数据接口；所述第五接插件包括第一视频处理数据接口和第二视频处理数据接口，所述第一视频处理数据接口和所述第二视频处理数据接口分别连接所述视频处理电路，所述第一视频处理数据接口还连接所述第二视频数据接口，所述第二视频处理数据接口还连接所述第三视频数据接口；所述第六接插件包括后处理数据接口，所述后处理数据接口连接所述视频处理电路，所述后处理数据接口还连接所述第四视频数据接口。
在本申请的一个实施例中，所述第一接插件还包括第一控制信号接口，所述第二接插件还包括第二控制信号接口、第三控制信号接口和第四控制信号接口，所述第三接插件还包括第五控制信号接口；所述第一控制信号接口连接所述第二控制信号接口，所述第三控制信号接口连接所述主控电路，所述第四控制信号接口连接所述第五控制信号接口；所述第四接插件还包括前处理控制信号接口，所述前处理控制信号接口连接所述视频前处理电路，所述前处理控制信号接口连接所述第一控制信号接口；所述第五接插件还包括视频处理控制信号接口、第一信号转发接口和第二信号转发接口，所述视频处理控制信号接口、所述第一信号转发接口和所述第二信号转发接口分别连接所述视频处理电路，所述视频处理控制信号接口连接所述第三控制信号接口，所述第一信号转发接口连接所述第二控制信号接口，所述第二信号转发接口连接所述第四控制信号接口；以及所述第六接插件还包括后处理控制信号接口，所述后处理控制信号接口连接所述视频后处理电路和所述第五控制信号接口；其中，所述第一控制信号接口、所述第二控制信号接口、所述第三控制信号接口、所述第四控制信号接口以及所述第五控制信号接口为以太网协议接口。
在本申请的一个实施例中，所述第一接插件的所述第一视频数据接口通过PCB(Printed Circuit Board，印制电路板)走线连接所述第二接插件的所述第二视频数据接口，所述第二接插件的所述第三视频数据接口通过PCB走线连接所述第三接插件的 所述第四视频数据接口；所述第一接插件的所述第一控制信号接口通过PCB走线连接所述第二接插件的所述第二控制信号接口，所述第二接插件的所述第三控制信号接口通过PCB走线连接所述主控电路，所述第二接插件的所述第四控制信号接口通过PCB走线连接所述第三接插件的所述第五控制信号接口。
在本申请的一个实施例中，所述视频前处理电路包括：第一视频处理器件、第一控制器、第一非易失性存储器，所述第一控制器连接所述第一视频处理器件和所述第一非易失性存储器，所述第一视频处理器件连接所述视频输入接口、所述视频前处理输出接口和所述前处理控制信号接口。
在本申请的一个实施例中，所述第一视频处理器件的所述视频输入接口用于对通过所述前处理控制信号接口传输的控制信号和参数进行解码得到第一解码后控制信号数据；所述第一视频处理器件视频还用于根据所述第一解码后控制信号数据对从所述视频输入接口获取的视频数据进行解码得到解码后图像数据、对所述解码后图像数据进行颜色空间转换得到颜色空间转换后图像数据、对所述颜色空间转换后图像数据进行去隔行处理得到去隔行后图像数据、对所述去隔行后图像数据进行画质调整得到第一画质调整后图像数据以及将所述第一画质调整后图像数据进行编码并发送至所述前处理数据接口。
在本申请的一个实施例中，所述视频输入接口的数量为多个，所述多个视频输入接口分别选自于HDMI接口、DVI接口、DP接口、SDI接口；所述视频输出接口的数量为多个，所述多个视频输出接口分别选自于HDMI接口、DVI接口、DP接口、SDI接口。在本申请的一个实施例中，所述视频处理电路包括：第二视频处理器件、第二控制器、第二非易失性存储器，所述第二控制器连接所述第二非易失性存储器和所述第二视频处理器件，所述第二视频处理器件连接所述第一视频处理数据接口、第二视频处理数据接口、所述视频处理控制信号接口、所述第一信号转发接口和所述第二信 号转发接口。
在本申请的一个实施例中，所述第二视频处理器件用于获取所述主控电路通过所述视频处理控制信号接口传输的控制信号和参数进行解码得到第二解码后控制信号数据、将非目标控制信号和参数通过所述第一信号转发接口和所述第二信号转发接口一一对应转发至所述视频前处理卡和所述视频后处理卡；所述第二视频处理器件还用于根据所述第二解码后控制信号数据对从所述第一视频处理数据接口获得的图像数据进行缩放处理得到缩放后图像数据、对所述缩放后图像数据进行画质增强处理得到画质增强后图像数据、对所述画质增强后图像数据进行叠加处理得到叠加后图像数据以及将所述叠加后图像数据进行编码并通过所述第二视频处理数据接口输出。
在本申请的一个实施例中，所述视频后处理电路包括：第三视频处理器件、第三控制器、第三非易失性存储器，所述第三控制器连接所述第三视频处理器件和所述第三非易失性存储器，所述第三视频处理器件连接所述视频输出接口、所述后处理数据接口和所述后处理控制信号接口。
在本申请的一个实施例中，所述第三视频处理器件用于对通过所述后处理控制信号接口传输的控制信号和参数进行解码得到第三解码后控制信号数据；所述第三视频处理器件还用于根据所述第三解码后控制信号数据对从所述后处理数据接口获取的图像数据进行画质调整得到第二画质调整后图像数据、对所述第二画质调整后图像数据进行编码得到编码后视频数据以及将所述编码后视频数据通过所述视频输出接口输出。
在本申请的一个实施例中，所述互连板还包括第七接插件，所述第七接插件包括第六控制信号接口，所述第六控制信号接口连接所述第三控制信号接口；所述视频处理设备还包括：主控卡，可拆卸地插接在所述互连板上，且所述主控电路设置在所述主控卡上；所述主控卡还包括与所述第七接插件插接的第八接插件，所述第八接插件包括控制信号输出接口，所述主控电路通过所述控制信号输出接口连接所述第六控制 信号接口。
在本申请的一个实施例中，所述视频前处理卡为至少一个，所述至少一个视频前处理卡分别可拆卸地插接至所述互连板上，且所述至少一个视频前处理卡的视频前处理电路分别通过所述互连板连接所述视频处理电路；所述视频后处理卡为至少一个，所述至少一个视频后处理卡分别可拆卸地插接至所述互连板上，且所述至少一个视频后处理卡的视频后处理电路分别通过所述互连板连接所述视频处理电路。
上述技术方案的一个技术方案具有如下优点或有益效果：本申请实施例提供的视频处理设备通过采用独立的视频前处理卡、视频处理卡以及视频后处理卡三个独立的电路板来分别实现输入视频的解码与预处理、视频的处理、以及视频后处理及编码等功能，并通过接插件可拆卸地插接至互连板上，通过相对简单的硬件设计实现了根据用户需求进行视频输入接口、视频输出接口以及视频处理卡的更换，以满足用户对多样化输入、输出接口以及视频处理的更换，提升了用户体验。另外，各个板卡之间通过FPGA的GTX相互通信，视频前处理卡将解码完成的图像通过GTX传给视频处理卡，待处理完成之后将此视频同样通过GTX发送给视频后处理卡使得其根据不同的视频接口的编码规范将视频图像通过不同的视频接口输出，实现了在一定的规模范围内不需要使用价格昂贵的交换芯片来完成输入视频接口和输出视频接口的选择与切换，节约了视频处理设备的成本。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的一种视频处理设备的结构示意图。
图2为本申请实施例提供的一种视频处理设备的另一结构示意图。
图3a为图2所示的视频前处理卡的结构示意图。
图3b为图3a所示的视频处理器件的结构示意图。
图4a为图2所示的视频处理卡的结构示意图。
图4b为图4a所示的视频处理器件的结构示意图。
图5a为图2所示的视频后处理卡的结构示意图。
图5b为图5a所示的视频处理器件的结构示意图。
图6a为本申请实施例提供的一种视频处理设备的再一结构示意图。
图6b为图6a所示的主控电路的一种结构示意图。
图7为本申请实施例提供的一种视频处理设备的又一结构示意图。
图8为图2所示的视频处理卡的又一结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
如图1和图2所示，本申请实施例中提供了一种视频处理装置100。视频处理装置100例如主要包括：互连板110、主控电路111、视频前处理卡130、视频处理卡150、视频后处理卡170，以及电源模块180等其它电路。主控电路111可以设置在互连板110上。此处可以理解的是，主控电路111可直接位于互连板110上，也可以位于与互连板100不同的其它电路板上且通过相应接口连接至互连板110。视频前处理卡130、视频处理卡150以及视频后处理卡170可拆卸地插接至互连板110上。这样一来可以满足用户随意更换视频输入接口、视频输出接口以及视频处理卡的需求，且硬件设计 成本相对较低。
具体地，主控电路111主要用于向视频前处理卡130、视频处理卡150以及视频后处理卡170提供控制信号及相关参数。
互连板110为PCB电路板。如图2所示，互连板110上还设置有多个接插件，例如接插件113、接插件114、接插件115，用于分别插接视频前处理卡130、视频处理卡150以及视频后处理卡170。此处的多个接插件例如为排针接插件、排母接插件或高密接插件等。具体地，如图2所示，接插件113包括视频数据接口1131和控制信号接口1132。接插件114包括视频数据接口1141、视频数据接口1142、控制信号接口1143、控制信号接口1144和控制信号接口1145。接插件115包括视频数据接口1151和控制信号接口1152。视频数据接口1131连接视频数据接口1141，视频数据接口1142连接视频数据接口1151。控制信号接口1132连接控制信号接口1144，控制信号接口1143连接主控电路111，控制信号接口1145连接控制信号接口1152。主控电路111例如主要包括嵌入式控制器1111，比如基于ARM核的嵌入式处理器。
视频前处理卡130主要用于对输入的视频源进行前处理。视频前处理卡130可拆卸地插接至互连板110上。具体地，如图2所示，视频前处理卡130上例如设置有视频输入接口131、视频前处理电路132。视频输入接口131连接视频前处理电路132。视频输入接口131用于接收外部输入的视频源信号。视频输入接口131例如为标准视频接口，比如HDMI接口、DVI接口、DP接口或者SDI接口等，此外，视频输入接口131还可以为光纤接口或其它用于传输视频或图像数据的接口，本申请不以此为限。进一步地，视频输入接口131的数量可为多个，多个视频输入接口131分别选自于HDMI接口、DVI接口、DP接口、SDI接口的部分或全部。这样一来用户可以根据需要在视频前处理卡150上设置多个视频输入接口131，以进一步满足用户更多样化的视频输入接口需求。此外，视频前处理卡130还设置有与接插件113相插接的接插件 133，以便于视频前处理卡130可拆卸地插接至互连板110上。接插件133例如包括前处理数据接口1331和前处理控制信号接口1332。前处理数据接口1331和前处理控制信号接口1332分别连接视频前处理电路132。前处理数据接口1331连接接插件113的视频数据接口1131，前处理控制信号接口1332连接接插件113的控制信号接口1132。
视频前处理电路132例如主要用于对输入的视频源进行解码、空间转换、去隔行、画质调整等处理。具体地，如图3a所示，视频前处理电路132例如包括视频处理器件1321、控制器1322和非易失性存储器1323。控制器1322连接视频处理器件1321和非易失性存储器1323。视频处理器件1321连接视频输入接口131。控制器1322例如为微控制器(MCU)。非易失性存储器1323例如为闪存(FLASH)。
更具体地，如图3b所示，视频处理器件1321例如包括依次连接的视频解码单元13211、颜色空间转换单元13212、去隔行单元13213、画质调整单元13214，还包括控制信号解码单元13215。控制信号解码单元13215连接前处理控制信号接口1332、视频解码单元13211、颜色空间转换单元13212、去隔行单元13213以及画质调整单元13214。控制信号解码单元13215对通过前处理控制信号接口1332输入的控制信号和参数进行解码得到第一解码后控制信号数据以供视频解码单元13211、颜色空间转换单元13212、去隔行单元13213、画质调整单元13214使用。视频解码单元13211连接视频输入接口131，其根据第一解码后控制信号数据对从视频输入接口131获取的视频数据进行解码得到RGB格式的解码后图像数据。颜色空间转换单元13212根据第一解码后控制信号数据将解码后的图像数据从RGB颜色空间转换到YUV颜色空间得到颜色空间转换后图像数据。当然，此处值得一提的是，颜色空间转换单元13212也可根据用户实际需要将解码后的图像数据从RGB颜色空间转换到其它颜色空间例如XYZ颜色空间等，本发明此处不以此为限。去隔行单元13213根据第一解码后控制信号数据将颜色空间转换后图像数据进行去隔行处理得到去隔行后图像数据，例如将输 入的隔行的图像数据转换为逐行输出的图像数据。当然，输入图像数据是逐行的图像数据，则不需要对其进行去隔行操作。画质调整单元13214用于根据第一解码后控制信号数据对去隔行后图像数据进行画质调整处理得到第一画质调整后图像数据，例如对亮度、对比度、色温等的调整，最后将第一画质调整后图像数据进行编码后例如以64B/66B编码格式输出至前处理数据接口1331。此处值得一提的是，视频处理器件1321还可例如为可编程逻辑器件比如FPGA(Field-Programmable Gate Array，即现场可编程门阵列)或CPLD(Complex Programmable Logic Device，复杂视频处理器件)等。
视频处理卡150主要用于图像数据的处理。具体地，视频处理卡150例如包括视频处理电路151和与接插件113插接的接插件153。视频处理电路151例如对从视频前处理卡130接收的图像数据进行缩放、画质增强、图层混叠等处理。具体地，如图4a所示，视频处理电路151例如包括视频处理器件1511、控制器1512和非易失性存储器1513。控制器1512连接视频处理器件1511和非易失性存储器1513。控制器1512例如为微控制器(MCU)。非易失性存储器1513例如为闪存(FLASH)。接插件153用于视频处理卡150可拆卸地插接至互连板110上。接插件153例如包括视频处理数据接口1531、视频处理数据接口1532、视频处理控制信号接口1533、信号转发接口1534和信号转发接口1535。视频处理数据接口1531、视频处理数据接口1532、视频处理控制信号接口1533、信号转发接口1534、信号转发接口1535分别连接视频处理电路151的视频处理器件1511。如图2所示，视频处理数据接口1531连接接插件114的视频数据接口1141，视频处理数据接口1532连接接插件114的视频数据接口1142，视频处理控制信号接口1533连接接插件114的控制信号接口1143，信号转发接口1534连接接插件114的控制信号接口1144，信号转发接口1535连接接插件114的控制信号接口1145。
承上述，如图4b所示，视频处理器件1511例如包括依次连接的图像缩放单元 15111、画质增强单元15112、图层混叠单元15113，还包括控制信号解码单元15114和控制信号转发单元15115，控制信号解码单元15114连接视频处理控制信号接口1533、图像缩放单元15111、画质增强单元15112、图层混叠单元15113，以通过视频处理控制信号接口1533获取的来自于主控电路111的控制信号和参数进行解码得到第二解码后控制信号数据以供图像缩放单元15111、画质增强单元15112、图层混叠单元15113使用。控制信号解码单元15114还连接控制信号转发单元15115，控制信号转发单元15115连接信号转发接口1534和信号转发接口1535。控制信号解码单元15114用于将不属于自身的控制信号和参数通过控制信号转发单元15115、信号转发接口1534和信号转发接口1535一一对应转发视频前处理卡130和视频后处理卡170。具体地，主控电路111的控制信号和参数通常例如以数据包的形式传输。在数据包的包头部分包括控制信号和参数的接收对象的标识信息，此处的接收对象可例如为视频前处理卡、视频后处理卡、或视频处理卡等，此处的标识信息可例如为01、02或03，比如01代表视频前处理卡，02代表视频处理卡，03代表视频后处理卡。当视频处理卡150接收数据包后，其会通过控制信号解码单元15114解析该数据包中的包头里的接收对象的标识信息，当识别出该数据包属于自身的控制信号和参数时，则接收该数据包；当识别出该数据包不属于自身的控制信号和参数时，则将该数据包发送控制信号转发单元15115以通过信号转发接口输出至视频前处理卡130或视频后处理卡170。此处值得一提的是，属于视频处理器件1511的控制信号和参数可称为目标控制信号和参数，不属于视频处理器件1511自身的控制信号和参数可称为非目标控制信号和参数。当然，也可以通过其它方式来进行控制信号和参数的解码和转发，本申请不以此为限。图像缩放单元15111对从视频处理数据接口1531获得的图像数据进行缩放处理得到缩放后图像数据。当然，输入的图像数据的分辨率与显示设备的分辨率一致时，则不需要对图像数据进行缩放处理。画质增强单元15112对缩放后图像数据进行画质增强处理得到 画质增强后图像数据。画质增强处理可例如包括SDR(Standard Dynamic Range，标准动态范围)图像转换成HDR(High Dynamic Range，高动态范围)图像等。图层混叠单元15113将画质增强后的至少一个图层的图像数据进行混合叠加处理，比如首先将其中一个图层的图像数据与背景进行叠加处理，然后将叠加后的图像数据与其它的图层的图像数据进行逐一叠加处理，得到叠加后图像数据，然后将叠加后图像数据进行编码后例如以64B/66B编码格式通过视频处理数据接口1532输出。此处值得一提的是，视频处理器件1511还可例如为可编程逻辑器件比如FPGA(Field-Programmable GateArray，即现场可编程门阵列)或CPLD(Complex Programmable Logic Device，复杂视频处理器件)等。
视频后处理卡170主要用于对经过处理的图像数据进行后处理。视频后处理卡170可拆卸地插接至互连板110上。具体地，如图5a所示，视频后处理卡170上例如设置有视频输出接口171、视频后处理电路172。视频输出接口171连接视频后处理电路172。视频输出接口171用于将经过处理后的图像数据输出至后端的设备例如LED显示屏控制器等。视频输出接口171例如为标准视频接口，比如HDMI接口、DVI接口、DP接口或者SDI接口等。进一步地，视频输出接口171的数量可为多个，多个视频输出接口171选自于HDMI接口、DVI接口、DP接口、SDI接口的部分或全部，此外，视频输出接口171还可以为光纤接口或其它用于传输视频或图像数据的接口，本申请不以此为限。这样一来可以进一步满足用户多样化的视频输出接口需求。视频后处理卡170还设置有与接插件115插接的接插件173，以便于视频后处理卡170可拆卸地插接至互连板110上。接插件173例如包括后处理数据接口1731和后处理控制信号接口1732。后处理数据接口1731和后处理控制信号接口1732分别连接视频后处理电路172。如图2所示，后处理数据接口1731连接接插件115的视频数据接口1151，后处理控制信号接口1732连接接插件115的控制信号接口1152。
视频后处理电路172例如对经过视频处理电路151处理后的图像数据进行后处理，例如画质调整、编码等处理。具体地，如图5a所示，视频后处理电路172例如包括视频处理器件1721、控制器1722和非易失性存储器1723。控制器1322连接视频处理器件1321和非易失性存储器1323。视频处理器件1721连接视频输出接口171。控制器1322例如为微控制器(MCU)。非易失性存储器1323例如为FLASH(闪存)。
更具体地，如图5b所示，视频处理器件1721例如包括画质调整单元17211、图像编码单元17212和控制信号解码单元17213。画质调整单元17211连接在图像编码单元17212和后处理数据接口1731之间。控制信号解码单元17213连接后处理控制信号接口1732、画质调整单元17211、图像编码单元17212。控制信号解码单元17213对通过后处理控制信号接口1732获得的控制信号和参数进行解码得到第三解码后控制信号数据，以供画质调整单元17211、图像编码单元17212使用。画质调整单元17211根据第三解码后控制信号数据对从后处理数据接口1731获取的经过视频处理电路151处理后的图像数据比如图层混叠后的多图层图像数据进行画质调整例如进行亮度、对比度、色温等调整，得到第二画质调整后图像数据。图像编码单元17212根据第三解码后控制信号数据将画质调整后的图像数据进行编码，得到用户需要的格式的编码后图像数据，并将编码后的视频数据通过视频输出接口171并输出。此处值得一提的是，视频处理器件1321可例如为可编程逻辑器件比如FPGA(Field-Programmable Gate Array，即现场可编程门阵列)或CPLD(Complex Programmable Logic Device，复杂视频处理器件)等。
在主控电路111输出的控制信号的控制下，视频前处理卡130对输入的视频源进行预处理，然后通过互连板的接插件将预处理后的图像数据传输至视频处理卡150以进行缩放等图像处理，接着将处理后的图像数据通过互连板的接插件传输至视频后处理卡170上进行后处理并根据视频输出接口的类型将图像数据编码成相应的格式从视 频输出接口输出，以完成整个视频处理过程。
另外，如图1所示，电源模块180用于给视频前处理卡130、视频处理卡150、视频后处理卡170以及主控电路111供电。具体地，电源模块180可例如为设置在视频处理设备100内的供电模块，也可以为视频处理设备100外接的供电模块。电源模块180给视频前处理卡130、视频处理卡150、视频后处理卡170以及主控电路111供电，其可理解为电源模块180连接互连板110、并通过互连板110连接视频前处理卡130、视频处理卡150、视频后处理卡170以及主控电路111以供电，也可以理解为电源模块180直接连接视频前处理卡130、视频处理卡150、视频后处理卡170以及主控电路111以供电，当然还可以有其它的供电方式，本申请不以此为限。举例来说，如图1所示，互连板110上还设置有电源接口118。电源接口118例如为排针接插件。电源接口118连接视频前处理卡130、视频处理卡150、视频后处理卡170以及主控电路111。电源模块180连接电源接口118，以通过电源接口118、以及互连板上的多个接插件，向视频前处理卡130、视频处理卡150、视频后处理卡170以及主控电路111等供电。
具体地，互连板110上的接插件113与接插件114之间、接插件114与接插件115之间分别通过PCB(Printed Circuit Board，印制电路板)走线直接连接，也即接插件113与接插件114之间、接插件114与接插件115之间没有有源元件(或称主动元件)。更具体地，视频数据接口1131通过PCB走线直接连接视频数据接口1141，视频数据接口1142通过PCB走线直接连接视频数据接口1151；控制信号接口1132通过PCB走线直接连接控制信号接口1144，控制信号接口1143通过PCB走线直接连接主控电路111，控制信号接口1145通过PCB走线直接连接控制信号接口1152。这样一来，视频处理卡150的FPGA在完成视频处理的同时充当了交换芯片的作用，从而可以取消交互芯片的设置，节省了昂贵的交换芯片，降低了成本。
进一步地，视频数据接口1131、视频数据接口1141、视频数据接口1142、视频数据接口1151、前处理数据接口1331、视频处理数据接口1531、视频处理数据接口1532、后处理数据接口1731为GTX(Gigabit Transceiver，吉比特收发器)协议接口，这样一来可以实现视频或图像数据的快速传输。控制信号接口1132、控制信号接口1143、控制信号接口1144、控制信号接口1145、控制信号接口1152、前处理控制信号接口1332、视频处理控制信号接口1533、信号转发接口1534、信号转发接口1535、后处理控制信号接口1732为以太网协议接口。
进一步地，如图6a所示，视频处理设备100还可以包括主控卡190。主控卡190包括主控电路111。主控卡190上还设置有接插件191。接插件191包括控制信号输出接口1911。控制信号输出接口1911连接主控电路111。相应地，互连板110上还设置有接插件116。接插件116包括控制信号接口1161。控制信号接口1161连接控制信号接口1143和接插件191的控制信号输出接口1911。这样一来，使得主控卡190也可以可拆卸地插接到互连板110上，用户也可以根据实际需要对主控卡190进行更换和调整，进一步满足了用户的多样化需求，提升了用户体验度。
另外，参见图6b，主控电路111例如采用ARM作为主要控制单元，eMMC和Flash充当数据存储和程序的缓存功能。主控电路111还提供RS232、USB和RJ45等接口将上位机与主控电路111的ARM互连，实现计算机端软件控制视频处理设备100。主控电路111的WIFI模块能够使其他移动设备连接视频处理设备100。再者，作为视频处理设备100的控制单元，主控电路111的ARM的FMC/FSMC、I2C、SPI等各类数据总线还可以通过FCI接口比如高密接插件、排针接插件等与互连板110连接，完成与上位机软件和下端互连板110的互连。另外，主控电路111还具备U盘驱动，提供单独的USB接口作为U盘保存离线文件、离线升级等功能。主控电路111内部的RTC模块则为整个控制系统提供实时时钟。
更进一步地，在本申请其它实施例中，如图7所示，视频前处理卡130的数量可以为至少一个，至少一个视频前处理卡130分别例如通过接插件可拆卸地插接至互连板110上，至少一个视频前处理卡130的视频前处理电路分别通过互连板110连接视频处理卡150的视频处理电路151。视频后处理卡170的数量也可以为至少一个，至少一个视频后处理卡170也分别例如通过接插件可拆卸地插接至互连板110上，至少一个视频后处理卡170的视频后处理电路分别通过互连板110连接视频处理卡150的视频处理电路151。如此一来，更进一步地满足了用户对输入、输出接口的多样化需求，提升了用户体验度。另外，至少一个视频前处理卡也可以为具有不同视频输入接口的视频前处理卡，至少一个视频后处理卡也可以为具有不同视频输出接口的视频后处理卡。
可选地，如图8所示，视频处理卡150上也可以设置有视频输出接口155。视频输出接口155的数量可为一个或多个。视频输出接口155也可例如为HDMI接口、DP接口、DVI接口、SDI接口和光纤接口中的至少一种。这样一来就可以直接从视频处理卡150上的视频输出接口155直接输出，而不再对视频或图像进行后处理，以满足用户更多需求。
本申请实施例提供的视频处理设备通过采用独立的视频前处理卡、视频处理卡以及视频后处理卡三个独立的电路板来分别实现输入视频的解码与预处理、视频的处理、以及视频后处理及编码等功能，并通过接插件可拆卸地插接至互连板上，通过相对简单的硬件设计实现了根据用户需求进行视频输入接口、视频输出接口以及视频处理卡的更换，以满足用户对多样化输入、输出接口以及视频处理的更换，提升了用户体验。这样还提升了视频处理设备产品的通用化和模块化，节约了零部件管理成本。另外，各个板卡之间通过FPGA的GTX相互通信，视频前处理卡将解码完成的图像通过GTX传给视频处理卡，待处理完成之后将此视频同样通过GTX发送给视频后处理卡使得其 根据不同的视频接口的编码规范将视频图像通过不同的视频接口输出，实现了在一定的规模范围内不需要使用价格昂贵的交换芯片来完成输入视频接口和输出视频接口的选择与切换，节约了视频处理设备的成本。
在申请实施例中，视频前处理卡(或称输入卡)，视频后处理卡(或称输出卡)和视频处理卡(或称处理卡)之间都通过GTX互联，且其连接都是在互连板上实现，互连板上仅是设置连接器如接插件直连，可连接的数量由处理卡上的FPGA型号决定，例如处理卡上的FPGA的型号为xcku060时，其可提供28个GTX通道。假设所有的视频输入源为4K×2K-60HZ的数据带宽，每个GTX通道的线速率为10G情况下，每个视频输入源需要2个GTX通道来传输，则视频处理卡最多可以实现与其他输入卡、输出卡之间实现14个4K×2K的视频图像的交互。另外，在输入卡中完成各种输入源的解码，包括SDI、HDMI、DP、DVI等视频接口，且这些视频接口可以根据用户需求进行任意定制，例如用户需要3个HDMI，1个SDI时，仅需要在输入卡的视频解码单元中进行多个实例化即可实现，在解码后需要根据自定义的协议进行编码，例如按照64B/66B编码的格式将输入源输出，并且所有的视频源都遵循该协议。对于视频处理卡来说，其无需区分是输入视频源的类型，而此视频处理卡上资源的限制关键取决于GTX资源，例如在输入卡上选择型号为xc7k325t的FPGA，其有16个通道的GTX，则最多可以将8路4K×2K的视频输入源发送给视频处理卡进行处理。处理卡主要完成视频图像的处理包括缩放、画质调整、图层叠加等，其是将输入卡发送过来的视频源从GTX格式解码出来，当作一路普通的视频源进行后续的视频处理，之后根据后端输出卡的视频输出接口的需求，将最终的视频数据通过GTX发送给输出卡。输出卡中将需要输出的视频数据在在不同的编码协议下将视频数据通过不同的视频输出接口输出。互连板上仅需要根据各个板卡的需求，将输入卡上的GTX的发送端与处理卡上的GTX的接收端直接连接，同时将处理卡上的发送端与输出卡上的接收端直接连 接，中间不设置任何有源元件，各个板卡之间的通信都是自定义的统一协议，在此种硬件架构中视频处理卡的FPGA在完成视频处理的同时充当了交换芯片的作用，节省了昂贵的交换芯片，降低了成本。
此外，本申请不同的实施方式之间的各种元件也可以进行任意组合，只要其不违背本申请的思想，其同样应当视为本申请所公开的内容。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统，装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用硬件加软件功能单元的形式实现。
最后应说明的是：以上实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技 术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围。

Claims (12)

  1. 一种视频处理设备，包括：
    互连板；
    视频前处理卡，可拆卸地插接至所述互连板且设置有视频输入接口、视频前处理电路，所述视频输入接口连接所述视频前处理电路；
    视频处理卡，可拆卸地插接至所述互连板且设置有视频处理电路，所述视频处理电路通过所述互连板连接所述视频前处理电路；
    视频后处理卡，可拆卸地插接至所述互连板且设置有视频后处理电路、视频输出接口，所述视频输出接口连接所述视频后处理电路；所述视频后处理电路通过所述互连板连接所述视频处理电路；
    主控电路，与所述视频处理电路连接；以及
    电源模块，用于给所述视频前处理卡、所述视频处理卡、所述视频后处理卡以及所述主控电路供电。
  2. 如权利要求1所述的视频处理设备，其中，
    所述互连板上设置有第一接插件、第二接插件、第三接插件；所述视频前处理卡上设置有与所述第一接插件插接的第四接插件；所述视频处理卡上设置有与所述第二接插件插接的第五接插件；所述视频后处理卡上设置有与所述第三接插件插接的第六接插件。
  3. 如权利要求2所述的视频处理设备，其中，
    所述第一接插件包括第一视频数据接口，所述第二接插件包括第二视频数据接口、第三视频数据接口，所述第三接插件包括第四视频数据接口；所述第一视频数据接口 连接所述第二视频数据接口，所述第三视频数据接口连接所述第四视频数据接口；
    其中，所述第一视频数据接口、第二视频数据接口、第三视频数据接口和第四视频数据接口为GTX协议接口；所述第四接插件包括前处理数据接口，所述前处理数据接口连接所述视频前处理电路，所述前处理数据接口连接所述第一视频数据接口；
    所述第五接插件包括第一视频处理数据接口和第二视频处理数据接口，所述第一视频处理数据接口和所述第二视频处理数据接口分别连接所述视频处理电路，所述第一视频处理数据接口还连接所述第二视频数据接口，所述第二视频处理数据接口还连接所述第三视频数据接口；
    所述第六接插件包括后处理数据接口，所述后处理数据接口连接所述视频处理电路，所述后处理数据接口还连接所述第四视频数据接口。
  4. 如权利要求3所述的视频处理设备，其中，
    所述第一接插件还包括第一控制信号接口，所述第二接插件还包括第二控制信号接口、第三控制信号接口和第四控制信号接口，所述第三接插件还包括第五控制信号接口；所述第一控制信号接口连接所述第二控制信号接口，所述第三控制信号接口连接所述主控电路，所述第四控制信号接口连接所述第五控制信号接口；所述第四接插件还包括前处理控制信号接口，所述前处理控制信号接口连接所述视频前处理电路，所述前处理控制信号接口连接所述第一控制信号接口；
    所述第五接插件还包括视频处理控制信号接口、第一信号转发接口和第二信号转发接口，所述视频处理控制信号接口、所述第一信号转发接口和所述第二信号转发接口分别连接所述视频处理电路，所述视频处理控制信号接口连接所述第三控制信号接口，所述第一信号转发接口连接所述第二控制信号接口，所述第二信号转发接口连接 所述第四控制信号接口；以及
    所述第六接插件还包括后处理控制信号接口，所述后处理控制信号接口连接所述视频后处理电路和所述第五控制信号接口；
    其中，所述第一控制信号接口、所述第二控制信号接口、所述第三控制信号接口、所述第四控制信号接口以及所述第五控制信号接口为以太网协议接口。
  5. 如权利要求4所述的视频处理设备，其中，所述视频前处理电路包括：第一视频处理器件、第一控制器、第一非易失性存储器，所述第一控制器连接所述第一视频处理器件和所述第一非易失性存储器，所述第一视频处理器件连接所述视频输入接口、所述视频前处理输出接口和所述前处理控制信号接口。
  6. 如权利要求5所述的视频处理设备，其中，所述第一视频处理器件的所述视频输入接口用于对通过所述前处理控制信号接口传输的控制信号和参数进行解码得到第一解码后控制信号数据；所述第一视频处理器件视频还用于根据所述第一解码后控制信号数据对从所述视频输入接口获取的视频数据进行解码得到解码后图像数据、对所述解码后图像数据进行颜色空间转换得到颜色空间转换后图像数据、对所述颜色空间转换后图像数据进行去隔行处理得到去隔行后图像数据、对所述去隔行后图像数据进行画质调整得到第一画质调整后图像数据以及将所述第一画质调整后图像数据进行编码并发送至所述前处理数据接口。
  7. 如权利要求4所述的视频处理设备，其中，所述视频处理电路包括：第二视频处理器件、第二控制器、第二非易失性存储器，所述第二控制器连接所述第二非易失性存储器和所述第二视频处理器件，所述第二视频处理器件连接所述第一视频处理数据接口、第二视频处理数据接口、所述视频处理控制信号接口、所述第一信号转发接口和所述第 二信号转发接口。
  8. 如权利要求7所述的视频处理设备，其中，所述第二视频处理器件用于获取所述主控电路通过所述视频处理控制信号接口传输的控制信号和参数进行解码得到第二解码后控制信号数据、将非目标控制信号和参数通过所述第一信号转发接口和所述第二信号转发接口一一对应转发至所述视频前处理卡和所述视频后处理卡；所述第二视频处理器件还用于根据所述第二解码后控制信号数据对从所述第一视频处理数据接口获得的图像数据进行缩放处理得到缩放后图像数据、对所述缩放后图像数据进行画质增强处理得到画质增强后图像数据、对所述画质增强后图像数据进行叠加处理得到叠加后图像数据以及将所述叠加后图像数据进行编码并通过所述第二视频处理数据接口输出。
  9. 如权利要求4所述的视频处理设备，其中，所述视频后处理电路包括：第三视频处理器件、第三控制器、第三非易失性存储器，所述第三控制器连接所述第三视频处理器件和所述第三非易失性存储器，所述第三视频处理器件连接所述视频输出接口、所述后处理数据接口和所述后处理控制信号接口。
  10. 如权利要求9所述的视频处理设备，其中，所述第三视频处理器件用于对通过所述后处理控制信号接口传输的控制信号和参数进行解码得到第三解码后控制信号数据；所述第三视频处理器件还用于根据所述第三解码后控制信号数据对从所述后处理数据接口获取的图像数据进行画质调整得到第二画质调整后图像数据、对所述第二画质调整后图像数据进行编码得到编码后视频数据以及将所述编码后视频数据通过所述视频输出接口输出。
  11. 如权利要求4所述的视频处理设备，其中，所述互连板还包括第七接插件，所述第七接插件包括第六控制信号接口，所述第六控制信号接口连接所述第三控制信号接口； 所述视频处理设备还包括：
    主控卡，可拆卸地插接在所述互连板上，且所述主控电路设置在所述主控卡上；所述主控卡还包括与所述第七接插件插接的第八接插件，所述第八接插件包括控制信号输出接口，所述主控电路通过所述控制信号输出接口连接所述第六控制信号接口。
  12. 如权利要求1所述的视频处理设备，其中，所述视频前处理卡为至少一个，所述至少一个视频前处理卡分别可拆卸地插接至所述互连板上，且所述至少一个视频前处理卡的视频前处理电路分别通过所述互连板连接所述视频处理电路；所述视频后处理卡为至少一个，所述至少一个视频后处理卡分别可拆卸地插接至所述互连板上，且所述至少一个视频后处理卡的视频后处理电路分别通过所述互连板连接所述视频处理电路。
PCT/CN2019/126146 2019-12-18 2019-12-18 视频处理设备 WO2021120026A1 (zh)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1523474A (zh) * 2003-02-20 2004-08-25 联想(北京)有限公司 用于投影仪和扩展模块间的扩展接口系统及控制方法
US20040252246A1 (en) * 2003-06-12 2004-12-16 Samsung Electronics Co., Ltd. TV signal receiving module and portable computer having the same
CN201332459Y (zh) * 2009-01-03 2009-10-21 海尔集团公司 可实现功能扩展的电视机
CN201699813U (zh) * 2010-05-11 2011-01-05 海尔集团公司 使用pcmcia连接器的信号源
CN202799008U (zh) * 2012-07-13 2013-03-13 深圳市视纬通科技有限公司 基于Android4.0的HDMI热插拔便携式电视机插件
CN209710215U (zh) * 2019-04-19 2019-11-29 西安诺瓦星云科技股份有限公司 具有电视功能的发送卡

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1523474A (zh) * 2003-02-20 2004-08-25 联想(北京)有限公司 用于投影仪和扩展模块间的扩展接口系统及控制方法
US20040252246A1 (en) * 2003-06-12 2004-12-16 Samsung Electronics Co., Ltd. TV signal receiving module and portable computer having the same
CN201332459Y (zh) * 2009-01-03 2009-10-21 海尔集团公司 可实现功能扩展的电视机
CN201699813U (zh) * 2010-05-11 2011-01-05 海尔集团公司 使用pcmcia连接器的信号源
CN202799008U (zh) * 2012-07-13 2013-03-13 深圳市视纬通科技有限公司 基于Android4.0的HDMI热插拔便携式电视机插件
CN209710215U (zh) * 2019-04-19 2019-11-29 西安诺瓦星云科技股份有限公司 具有电视功能的发送卡

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