WO2021117386A1

WO2021117386A1 - Receiving device

Info

Publication number: WO2021117386A1
Application number: PCT/JP2020/041556
Authority: WO
Inventors: 秀行高野
Original assignee: ソニーセミコンダクタソリューションズ株式会社
Priority date: 2019-12-09
Filing date: 2020-11-06
Publication date: 2021-06-17
Also published as: JPWO2021117386A1

Abstract

[Problem] To achieve IMRR improvement with a simple configuration. [Solution] This receiving device is provided with a mixer which includes: a first mixer which converts the phase difference between a first signal and a second signal into a first amplitude on the basis of a logical AND between the first signal and the second signal, and converts the phase difference between a third signal, which forms a differential signal with the first signal, and a fourth signal, which forms a differential signal with the second signal, into a second amplitude on the basis of a logical AND between the third signal and the fourth signal; and a second mixer which converts the phase difference between the first signal and the fourth signal into a third amplitude on the basis of a logical AND between the first signal and the fourth signal, and converts the phase difference between the second signal and the third signal into a fourth amplitude on the basis of a logical AND between the second signal and the third signal.

Description

Receiver

This disclosure relates to a receiving device.

The superheterodyne system is widely used in devices that receive radio waves. In this method, it is desirable to secure a good image rejection ratio (IMRR: Image Response Rejection Ratio). In removing the image signal, it is necessary that the quadrature phase error of the signal (LO signal) oscillated by the local oscillator (LO: Local Oscillator) is sufficiently small. When mounting using an integrated circuit, deterioration of phase accuracy due to element mismatch becomes a problem, but the effect of this mismatch tends to increase with the progress of miniaturization of semiconductor processes in recent years. Therefore, research is being conducted on an image removal mixer that corrects the phase error of the LO signal using a variable phase shifter or the like.

Japanese Unexamined Patent Publication No. 2003-198262

However, since the variable phase shifter is generally composed of a complicated delay circuit, the circuit scale is increased and the power consumption is increased. Therefore, such a configuration is not suitable for applications for high frequency operation or low power consumption.

The present disclosure provides a receiving device that realizes IMRR improvement with a simple configuration.

According to one embodiment, the receiving device converts the phase difference between the first signal and the second signal into the first amplitude based on the logical product of the first signal and the second signal, and constitutes the first signal and the differential signal. A first mixer, a first signal, and a fourth signal that convert the phase difference of these signals into a second amplitude based on the logical product of the third signal, the second signal, and the fourth signal constituting the differential signal. The phase difference of these signals is converted to the third amplitude based on the logical product of, and the phase difference of these signals is converted to the fourth amplitude based on the logical product of the second signal and the third signal. A mixer and a mixer having the mixer may be provided.

The first signal and the second signal may be orthogonal signals.

The mixer may include two switching elements connected in series, each of which receives a signal whose logical product is desired to be acquired as a drive signal.

The switching element may be a MOSFET. In this way, a mixer having a AND circuit may be formed by using a MOSFET.

The mixer may be provided with a logical product gate that acquires the logical product of two signals. In this way, it may be implemented by the AND gate.

The receiving device is connected to the first mixer and amplifies the difference between the first amplitude and the second amplitude. The receiving device is connected to the first amplifier and the second mixer and amplifies the difference between the third amplitude and the fourth amplitude. , A second amplifier may be provided, and between the non-inverting input terminal and the inverting output terminal of the first amplifier and between the inverting input terminal and the non-inverting output terminal of the first amplifier. Connect the resistor having the first resistance value to be connected, between the non-inverting input terminal and the inverting output terminal of the second amplifier, and between the inverting input terminal and the non-inverting output terminal of the second amplifier, respectively. A resistor having a second resistance value to be obtained may be further provided. These resistors can adjust the gain of each amplifier.

The first resistance value and the second resistance value may have a predetermined ratio. IMRR may be improved by adjusting the ratio of the first resistance value to the second resistance value.

The predetermined ratio may be determined based on the amplitude error between the first amplifier output and the second amplifier output, which is converted from the phase error between the first signal and the second signal. That is, the phase error between the first signal and the second signal can also be viewed as an amplitude error at the output of the amplifier by the logical product.

The receiving device may further include an amplitude error detection circuit that detects a quadrature amplitude error based on the output of the amplifier. By providing the detection circuit in this way, the influence of the phase error on the first signal and the second signal peculiar to the receiving device may be suppressed.

The first resistance value and the second resistance value may be controlled based on the output of the amplitude error detection circuit. For example, the first resistance value and the second resistance value may be values that can be controlled by the variable resistance.

In the output from the amplitude error detection circuit, the first resistance value and the second resistance value may be controlled so that the amplitude error between the output from the first amplifier and the output from the second amplifier is 0. ..

The receiving device may further include an AD conversion circuit that converts the output of the amplifier into a digital signal, and the amplitude error detection circuit may detect the quadrature amplitude error based on the output of the AD conversion circuit. As described above, the signal used for improving IMRR may be an analog signal or a digital signal.

The receiving device changes the phase of one of the signals of the output based on the first amplifier and the output based on the second amplifier output from the AD conversion circuit, the phase shifter, the output of the AD conversion circuit, and the phase shift. An adder circuit that adds the output of the device may be further provided. By using a phase shifter, the output may be output with the image removed from the baseband signal.

A gain adjustment circuit that adjusts the gain of the signal output from the AD conversion circuit may be further provided. In this way, instead of adjusting the gain in the amplifier, the gain may be adjusted in the signal output from the amplifier.

The output of the phase shifter, the amplitude error detection circuit, and the output of the phase shifter that change the phase of one of the signals based on the first amplifier and the output based on the second amplifier, which are output from the amplitude error detection circuit. An adder circuit for adding and may be further provided. In this way, the image may be removed in the state of an analog signal.

The phase shifter may change the phase of the signal by 90 degrees. Since the output channels are the I channel and the Q channel, either signal may be changed by 90 degrees to obtain an in-phase signal.

The phase shifter may arbitrarily change the phase of the signal. For example, an angle slightly deviated from 90 degrees may be specified. In this way, the influence of the residual phase error in the circuit can also be taken into consideration.

According to one embodiment, the receiving device is a receiving device that inputs an RF input signal and outputs a baseband signal, the RF input signal is applied to the input terminal, and the first signal is applied to the drive terminal. The first transistor and the input terminal are connected to the output terminal of the first transistor, and the second signal orthogonal to the first signal is applied to the drive terminal. The RF input signal is applied to the second transistor and the input terminal. The third signal and the third signal constituting the differential signal are applied to the drive terminal. The third transistor and the input terminal are connected to the output terminal of the third transistor, and the drive terminal is differential from the second signal. The fourth transistor to which the fourth signal constituting the signal is applied, the non-inverting input terminal is connected to the output terminal of the second transistor, the inverting input terminal is connected to the output terminal of the fourth transistor, and the base of the I channel. A first amplifier that outputs a band signal may be provided.

In the receiving device, the RF input signal is further applied to the input terminal and the fourth signal is applied to the drive terminal. The fifth transistor and the input terminal are connected to the output terminal of the fifth transistor, and the first signal is connected to the drive terminal. Is applied, the RF input signal is applied to the 6th transistor and the input terminal, and the 2nd signal is applied to the drive terminal. The 7th transistor and the input terminal are connected to the output terminal of the 7th transistor to drive. The 8th transistor to which the 3rd signal is applied to the terminal, the non-inverting input terminal is connected to the output terminal of the 6th transistor, the inverting input terminal is connected to the output terminal of the 8th transistor, and the base band signal of the Q channel. A second amplifier, which outputs a signal, may be provided.

The schematic block diagram of the receiving apparatus which concerns on one Embodiment. A circuit diagram of a receiving device according to an embodiment. A configuration example of a switch according to an embodiment. A timing chart showing the relationship between the LO signal and the output of the switch according to the embodiment. A timing chart showing the relationship between the LO signal and the output of the switch according to the embodiment. A timing chart showing the output of the switch according to the embodiment. The graph which shows the relative error of the baseband amplitude which concerns on one Embodiment. The graph which shows the relationship between the LO phase error and the baseband phase error which concerns on one Embodiment. The vector diagram of the LO signal and the baseband signal which concerns on one Embodiment. The vector diagram of the baseband signal when there is no phase shift which concerns on one Embodiment. The figure which shows IMRR in the receiving apparatus which concerns on one Embodiment. The schematic block diagram of the receiving apparatus which concerns on one Embodiment. The figure which shows an example of the circuit connected with the RF input of the receiving apparatus which concerns on one Embodiment. The schematic block diagram of the receiving apparatus which concerns on one Embodiment. The schematic block diagram of the receiving apparatus which concerns on one Embodiment. The schematic block diagram of the receiving apparatus which concerns on one Embodiment. The schematic block diagram of the receiving apparatus which concerns on one Embodiment. The figure which shows the application example of the receiving apparatus which concerns on one Embodiment.

Hereinafter, the receiving device according to some embodiments will be described with reference to the drawings. In the drawings and description, the power supply voltage Vss, Vdd, etc. are not particularly mentioned, but it is assumed that the power supply voltage is appropriately applied to each circuit element, etc.

(First Embodiment)
FIG. 1 is a schematic block diagram of a receiving device according to an embodiment. The receiving device 1 includes a mixer 10 and an amplifier 20. When the receiving device 1 receives the RF (Radio Frequency) input signal, it outputs a baseband signal based on the LO signal output from the local oscillator.

From the local oscillator, there are a first signal LO0 having a reference frequency, a second signal LO90 orthogonal to the first signal LO0, a third signal LO180 which is an inverted signal of the first signal LO0, and an inverted signal of the second signal LO90. The fourth signal LO270 is input to the receiving device 1. As another example, the receiving device 1 may include a local oscillator, and the local oscillator inside the receiver 1 may oscillate these signals. For example, the local oscillator may include a PLL (Phase Locked Loop) or the like.

The mixer 10 is a mixer that mixes the RF input with the first signal LO0, the second signal LO90, the third signal LO180, and the fourth signal LO270 oscillated by the local oscillator. In the mixer 10, the RF input and the LO signal converted based on the AND circuit (logical product circuit) are mixed.

The amplifier 20 is an amplifier that amplifies the mixed signal output from the mixer 10. The amplifier 20 is, for example, an operational amplifier including a non-inverting input terminal, an inverting input terminal, a non-inverting output terminal, and an inverting output terminal. The amplifier 20 amplifies and outputs the signal output from the mixer 10.

FIG. 2 is a circuit diagram showing the overall structure of the receiving device 1 in more detail. The mixer 10 includes a first mixer 10A and a second mixer 10B, and the amplifier 20 includes a first amplifier 20A and a second amplifier 20B.

The first mixer 10A includes a switch 12IP and a switch 12IN, and the second mixer 10B includes a switch 12QP and a switch 12QN. Each switch may be configured by connecting two n-type MOSFETs (Metal-Oxide-Semiconductor Field-Effect-Transistor) in series, for example. An LO signal is applied to the gate (drive terminal) of each MOSFET. The drain (input terminal) of one of the two MOSFETs is connected to the RF input, and the source (output terminal) is connected to the drain of the other MOSFET. The source of the other MOSFET is connected to the appropriate input terminal of the amplifier 20.

Further, the receiving device 1 may include a voltage-current conversion circuit 70. The voltage signal input to the receiving device 1 is converted and gained into a current signal via the voltage-current conversion circuit 70, and is input to the mixer 10.

For example, as shown in FIG. 2, the first signal LO0 is applied to the drive terminal of the first transistor provided in the switch 12IP, and the second signal LO90 is applied to the drive terminal of the second transistor. The third signal LO180 is applied to the drive terminal of the third transistor provided in the switch 12IN, and the fourth signal LO270 is applied to the drive terminal of the fourth transistor. The fourth signal LO270 is applied to the drive terminal of the fifth transistor provided in the switch 12QP, and the first signal LO0 is applied to the drive terminal of the sixth transistor. The second signal LO90 is applied to the drive terminal of the seventh transistor provided in the switch 12QN, and the third signal LO180 is applied to the drive terminal of the eighth transistor.

The signal to be applied may be a transistor provided in the switch as long as it can appropriately acquire the logical product described below. For example, in the switch 12IP, it is sufficient that the logical product of the first signal LO0 and the second signal LO90 can be output. Therefore, the second signal LO90 may be applied to the drive terminal of the first transistor, and the first signal LO0 may be applied to the drive terminal of the second transistor. The same applies to the other switches 12IQ, 12QP, and 12QN provided in the amplifier 20.

FIG. 3 is a configuration example of each switch. As described above, it may be configured to include two MOSFETs or may be configured to include an AND gate. For example, as shown in the above figure, by applying a signal to the gates of two n-type MOSFETs, switching based on the logical product of Sig1 and Sig2 is performed. When both signals are high, it is in an energized state, that is, an on state, and when at least one signal is low, it is in a cutoff state, that is, an off state. Although the n-type MOSFET is used, the present invention is not limited to this, and for example, the signal may be inverted and applied to the gate of the p-type MOSFET. Further, the configuration may include, for example, a bipolar transistor instead of the MOSFET.

Further, as shown in the figure below, the gate of the n-type MOSFET may be provided with an AND gate that outputs the logical product of two signals. Similarly, in this case as well, when both signals are high, it is turned on, and when either signal is low, it is turned off. Although two examples have been given here, the structure shown in FIG. 3 may be replaced by a circuit capable of appropriately acquiring the logical sum of the two signals.

The configuration of the mixer 10 is not limited to these, and may be configured by a circuit that can appropriately acquire a logical product using a PLL or the like.

The receiving device 1 shown in FIG. 2 and the like includes a switch as shown in FIG. 3 in the mixer 10. That is, in the receiving device 1, the synthesis of signals by the mixer 10 is executed by using a switch that acquires the logical sum of the two signals. These switches multiply the RF input with the LO signal and convert it to a baseband signal.

For example, the output of the switch 12IP is connected to the non-inverting input terminal of the first amplifier 20A, and the output of the switch 12IN is connected to the inverting input terminal of the first amplifier 20A. Similarly, the output of the switch 12QP is connected to the non-inverting input terminal of the second amplifier 20B, and the output of the switch 12QN is connected to the inverting input terminal of the second amplifier 20B.

The first amplifier 20A and the second amplifier 20B may be operational amplifiers including a non-inverting input terminal, an inverting input terminal, a non-inverting output terminal, and an inverting output terminal, respectively. The baseband signal output from the mixer 10 is appropriately amplified and output. For example, the I channel baseband signal is output from the first amplifier 20A, and the Q channel baseband signal is output from the second amplifier 20B.

The first amplifier 20A is fed back from the inverting output terminal to the non-inverting input terminal _{via a resistor having a first resistance value R I} , and controls the gain from the non-inverting output terminal to the inverting input terminal. It is fed back through a resistor having a resistance value of R _I. Similarly, the second amplifier 20B is fed back from the inverting output terminal to the non-inverting input terminal _{via a resistor having a second resistance value R Q} , and gains from the non-inverting output terminal to the inverting input terminal. It is fed back through a resistor with a second resistance value R _{Q to control.}

When a phase error occurs in a signal orthogonal to the LO signal, what kind of resistance value is used to suppress the error will be described below.

FIG. 4 is a timing chart showing the LO signal and the output of each switch. In this figure, an ideal state in which no error occurs is shown. From top to bottom, the waveforms of the first signal LO0, the second signal LO90, the third signal LO180, and the fourth signal LO270, the output waveforms of the switches 12QP, 12IP, 12QN, and 12IN shown in FIG. 2, the difference between the switches 12IP and 12IN, and the switches. The waveform of the difference between 12QP and 12QN is shown.

The difference between the switches 12IP and 12IN is the envelope of the difference signal input to the first amplifier 20A, and the difference between the switches 12QP and 12QN is the envelope of the difference signal input to the second amplifier 20B. Here, it can be seen that the phase difference between the signal input to the first amplifier 20A and the signal input to the second amplifier 20B is 90 degrees.

As can be seen from FIG. 4, the duty ratio of the LO signal that drives each MOSFET of the switch is 50%. On the other hand, the duty ratio of the output signal from each switch is 25%. In this way, when there is no phase error in the orthogonal components, switching with a duty ratio of 25% is equivalently performed in all the switches.

On the other hand, FIG. 5 is a timing chart of each signal when an error occurs in the orthogonal component of the LO signal. For example, assume that a phase error of Δθ occurs between the first signal LO0 and the second signal LO90. This phase error is caused by, for example, an element mismatch in a local oscillator. As can be seen from this figure, by switching by logical product, the signals (12IP-12IN, 12QP-12QN) input to each amplifier can be orthogonal even when the LO signal has quadrature phase error. I understand. That is, in the baseband output, the signals of the I channel and the Q channel are orthogonal to each other.

It will be explained in more detail using mathematical formulas. FIG. 6 is a partially extracted difference signal of the output from the switch in FIG. Assuming that the angular frequency of the LO signal is ω _LO , T and ΔT in the figure are defined as follows.

Using these equations (1) and (2), the Fourier series of the waveform shown in FIG. 6 is calculated.

The frequency transform is the first-order component, and the Fourier coefficients a ₁ and b ₁ of the fundamental wave for the switching waveform (10IP-10IN) can be expressed by the following equations.

Based on these, the fundamental wave component can be expressed as follows.

Similarly, the Fourier coefficient for the switching waveform 12QP-12QN can be expressed as follows.

Based on these, the fundamental wave component can be expressed by the following equation.

Next, the equation is expressed with respect to the amplitude and phase of the baseband signal. _{The current I RF of the} RF signal input to the mixer 10 is defined as follows.

Here, g _m is the gain of the voltage-current conversion circuit 70, V _RF is the amplitude of the RF input voltage, and ω _RF is the angular frequency of the RF input signal.

The baseband output voltage on the I channel side is the product of (5) and (9) _{multiplied by the transimpedance gain R I} of the amplifier 20 that operates as a TIA (Trans Impedance Amp), and can be expressed as follows. it can.

Since _{the frequency component of ω RF} + ω _LO is removed by the low-pass characteristic of the baseband amplifier, the final output can be expressed as follows.

Similarly, the baseband output voltage on the Q channel side can be expressed as follows based on (8) and (9) and the transimpedance gain R _{Q of the amplifier 20.}

Now compare (11) and (14). Since cos (ω _BB t + Δθ / 2) and sin (ω _BB t + Δθ / 2) are orthogonal to each other, it can be seen that the phase error Δθ of the LO signal disappears in the baseband. Assuming that the phase error of the baseband signal is Δφ, the following equation holds.

Assuming that Δθ is sufficiently small, (11) and (14) can be approximated as follows.

From these (16) and (17), the relative error ΔA between the I channel and the Q channel of the baseband amplitude can be expressed by the following equation.

FIG. 7 is a graph showing a comparison between the theoretical value and the simulation result when _{R I} / R _{Q = 1 in (18).} As shown in FIG. 7, the simulation results are in good agreement with the theoretical values. More specifically, for a phase error of ± π / 32, an amplitude error of about 10% occurs.

FIG. 8 is a graph showing the relationship between the phase error Δθ of the LO signal and the phase error Δφ of the baseband signal. Also in FIG. 8, the simulation results are almost in agreement with the theoretical values. That is, the value of Δφ is 0 regardless of the value of Δθ.

FIG. 9 is a vector diagram showing the phase difference of the input LO signal and the amplitude difference of the output baseband signal. In both graphs, the horizontal axis represents the real axis and the vertical axis represents the imaginary axis. By calculating the logical product in the mixer 10, a correlation occurs in the switching waveform between the I / Q channels. For example, as shown in FIG. 6, when the signal width in any channel increases by ΔT (= Δθ / ω _LO ), the signal width in the other channel decreases by ΔT. From this relationship, as shown in FIG. 9, the phase shift of the input signal is converted into the amplitude shift of the output signal while maintaining the orthogonal relationship between the I / Q channels. This can also be read from, for example, (16) (17) and (18).

FIG. 10 is a diagram showing a baseband output in which the amplitude deviation is eliminated. The horizontal axis represents the real axis, and the vertical axis represents the imaginary axis. As shown in FIG. 10, by adjusting the gain of the amplifier 20 so as to eliminate the error in the amplitude of the baseband output, the influence of the phase shift of the LO input can be reduced.

The correction of the image rejection ratio (IMMR) adjusts the gain so as to approach the state shown in FIG. When ΔA and Δφ are sufficiently small, IMMR can be approximated by the following equation.

ΔA is the amplitude error of the baseband signal, and Δφ is the phase error of the baseband signal as described above. Here, if Δφ = 0 is set from (15), it can be transformed as follows.

Therefore, if ΔA = 0, then IMRR → -∞. Based on (18), this condition is as follows.

According to (21), each of the ratio of the resistance to adjust the gain in the first amplifier 20A and the second amplifier 20B, be adjusted so R _I / R _Q approaches 1 + [Delta] [theta], close the ΔA 0 be able to. Further, as shown in FIG. 10, the signal amplitude difference between the I channel and the Q channel of the baseband signal may be set to 0. That is, IMRR can be improved by bringing ΔA closer to 0 without actually detecting the value of Δθ in (21).

FIG. 11 is a graph showing an example of IMRR experimented in the receiving device 1 in which the amplitude error according to the present embodiment is measured and the gain of the amplifier 20 is adjusted. A 2.4 GHz sine wave test tone was input as an RF input using an external signal generator, and the 1 MHz signal after down-conversion was measured at the output of the amplifier 20. Before the correction of the amplitude error, all 10 samples did not meet the IMRR specification value, but after the gain adjustment, an improvement of 10 to 15 dB was seen, and the result satisfying the specification value was obtained. ..

As described above, according to the present embodiment, the IMRR of the receiving device 1 can be improved by executing the logical product calculation in the mixer 10 and providing the amplifier 20 whose gain is adjusted. In general, it is difficult to measure and adjust the phase error Δθ of the LO signal. Measuring and adjusting the amplitude error ΔA of the baseband signal is relatively easier than the phase error Δθ of the LO signal because the baseband signal is a signal with a lower frequency than the LO signal. Therefore, according to the receiving device 1 according to the present embodiment, it is possible to easily improve the IMRR without correcting the phase error of the LO signal.

Also, since processing can be performed in the band of the baseband signal, which has a lower frequency than the LO signal, it is possible to reduce power consumption and improve accuracy. Since the logical product is also executed by the switch 12 of the mixer 10, low power consumption can be realized from this point as well. Furthermore, since the limitation on the quadrature phase accuracy of the LO signal can be relaxed, the circuit scale can be reduced and the power consumption can be further reduced.

(Second Embodiment)
FIG. 12 is a block diagram schematically showing the receiving device 1 according to the present embodiment. The receiving device 1 further includes an amplitude error detection circuit 30. The amplitude error detection circuit 30 is connected to the output of the amplifier 20 and detects the amplitude error between the channels of the baseband signal output from the amplifier 20.

The gain adjustment in the amplifier 20 of the receiving device 1 may be performed based on the output of the amplitude error detection circuit 30. For example, the user may adjust _{R I} / R _Q so that the amplitude error ΔA becomes 0 based on the output of the amplitude error detection circuit 30. Further, as another example, the amplitude error detection circuit 30 may be configured to automatically change the gain adjusting resistance of the first amplifier 20A and the second amplifier 20B configured by the variable resistor.

As described above, the test tone may be input from the RF input at the timing of adjusting the gain for improving IMRR. This gain adjustment may be performed, for example, at the time of shipment from the factory, at the time of starting up the equipment, and the like. Further, as another example, it may be executed at a predetermined timing when the receiving device 1 is activated. For example, the resistance value may be adjusted by determining the timing at which signal reception is not continuing. As another example, when the amplitude error detected by the amplitude error detection circuit 30 exceeds a predetermined value, reception may be stopped, the input may be switched to the test tone input, and the IMRR may be improved.

FIG. 13 is a diagram showing an example of a circuit connected to the RF input of FIG. For example, when adjusting the gain for improving IMRR described above, the RF input is connected to the test tone oscillator circuit 40 via the switch shown in FIG. The test tone oscillation circuit 40 oscillates a signal having a waveform whose gain can be adjusted according to the above equation, such as a single tone sine wave or a square wave having a predetermined frequency. _{The first resistance value R I} and the second resistance value R _Q of the receiving device 1 are adjusted based on the signal oscillated from the test tone oscillation circuit 40. The test tone oscillator circuit 40 may include, for example, a PLL or the like.

At the timing when adjustment is not performed, for example, by switching the switch, the RF input terminal is connected to the antenna 42, and the radio wave can be received. Further, the present invention is not limited to this, and when it is desired to suppress power consumption, the switch may be switched so as not to be connected to the antenna 42.

The circuit shown in FIG. 13 may be an external circuit or a circuit built in the receiving device 1.

As described above, according to the receiving device 1 according to the present embodiment, the amplitude error between the I / Q channels of the baseband signal is detected, the resistance value of the gain adjustment is adjusted based on this result, and the IMRR is improved. Can be executed. By making such adjustments, it is possible to configure the receiving device 1 according to the first embodiment described above.

(Third Embodiment)
In the above, the case of adjusting based on the analog signal has been described, but the present invention is not limited to this. For example, the analog signal may be converted into a digital signal, and then the parameters for improving IMRR may be acquired.

FIG. 14 is a diagram schematically showing an example of executing the output of the receiving device 1 with a digital signal. In addition to the configuration shown in FIG. 2, the receiving device 1 includes an analog-to-digital conversion circuit (ADC) 32 and a digital signal processing unit 50.

The ADC 32 is a circuit provided for each amplifier to convert an input analog signal into a digital signal and output it. In this ADC 32, the input is connected to an amplifier for each channel, and the output is connected to the digital signal processing unit 50.

The digital signal processing unit 50 includes an amplitude error detection circuit 52, a phase shifter 54, and an adder circuit 56. The digital signal processing unit 50 outputs a signal from which the image has been removed with respect to the output from the amplifier 20 converted into the input digital signal.

The amplitude error detection circuit 52 executes an operation equivalent to that of the amplitude error detection circuit 30 which was a circuit for processing an analog signal in the above-described embodiment on a digital signal. That is, the amplitude error of these signals is detected with respect to the signals for each input channel. Further, after the detection, the gain adjusting resistance value provided in the amplifier 20 may be updated based on the detected value so that the error approaches zero.

The phase shifter 54 shifts the phase of the signal of any channel, for example, the signal of the I channel by +90 degrees. In this way, the phase shifter 54 is provided for either channel. In FIG. 14, it is provided on the I channel side, but it may be provided on the Q channel side.

The adder circuit 56 adds the output of the phase shifter 54 to one channel and the output of the amplitude error detection circuit 52 to the other channel. When the signals of the I channel and the Q channel are added by shifting one of the channels by 90 degrees, the desired signals are added in the same phase, while the image components are added in the opposite phase. Therefore, it is possible to acquire a signal from which the image component has been removed.

Also in FIG. 14, it is possible to adjust the gain by connecting the circuit shown in FIG. 13 to the RF input terminal. As described above, also in this embodiment, it is possible to appropriately adjust the gain from the amplitude error of the baseband signal without directly acquiring the information on the phase error of the LO signal, and the same operation as in the above-described embodiment. , Can be effective.

(Fourth Embodiment)
FIG. 15 is a block diagram schematically showing the receiving device 1 according to the present embodiment. The image signal level measurement and amplitude error correction circuit 57 in the digital signal processing unit 50 of the receiving device 1 may be connected to the output of the addition circuit 56 to output the image-removed signal. As described above, as shown in FIG. 15, the receiving device 1 measures the level of the image signal in the output stage of the receiving device 1 and adjusts the gain of the amplifier 20 so that the value is minimized. It may be a configuration.

(Fifth Embodiment)
FIG. 16 is a block diagram schematically showing the receiving device 1 according to the present embodiment. The digital signal processing unit 50 of the receiving device 1 may further include a gain adjusting circuit 58. The gain adjustment circuit 58 is provided between the output of the ADC 32 and the amplitude error detection circuit 52 for each channel, for example. The amplitude error detection circuit 52 acquires the gain-adjusted signals of each channel, and adjusts the gain of the gain adjustment circuit 58 by detecting these amplitude errors. By adjusting the gain, it is possible to reduce the amplitude error and improve the image rejection ratio.

For example, if an ADC with a sufficiently large number of bits can be used, such a configuration can be used. In this case, it is not necessary to adjust the gain in the amplifier 20, and the digital signal processing unit 50 can adjust the gain.

(Sixth Embodiment)
FIG. 17 is a block diagram schematically showing the receiving device 1 according to the present embodiment. The receiving device 1 includes an analog signal processing unit 60 instead of the digital signal processing unit 50 in the above-described embodiment. The analog signal processing unit 60 includes an amplitude error detection circuit 30, a phase shifter 62, and an adder circuit 64.

The phase shifter 62 and the adder circuit 64 perform the same operations as those provided in the digital signal processing unit 50. For example, if the ADC cannot be used for some reason, or if it is desired to acquire the output of an analog signal, the signal processing may be executed by an analog circuit as shown in FIG. The configuration of the analog circuit is not particularly limited as long as the same signal processing as in FIG. 14 described above can be executed.

(7th Embodiment)
In FIGS. 14 to 17, the phase shifter 54 or the phase shifter 62 shifts the phase of the signal by 90 degrees, but the present invention is not limited to this. For example, the phase may be shifted by (90 + α) degrees. For example, when the amount of IMRR correction is limited by the phase error of the baseband signal, the phase error of the baseband signal can be corrected by executing such a phase shift. For example, the phase shifter 54 or the phase shifter 62 may be a variable phase shifter. By making α variable, it is possible to perform accurate phase error correction based on the output of the amplitude error detection circuit 52 or the amplitude error detection circuit 30. Also in this embodiment, since the phase error is corrected by signal processing at a low frequency, it can be implemented as a simpler configuration than providing a phase error correction circuit in a local oscillator or the like.

The technology according to the present disclosure can be applied to a technology called IoT (Internet of things), which is a so-called "Internet of Things". IoT is a mechanism in which IoT devices 9100, which are "things", are connected to other IoT devices 9003, the Internet, cloud 9005, etc., and mutually control by exchanging information. IoT can be used in various industries such as agriculture, homes, automobiles, manufacturing, distribution, and energy.

FIG. 18 is a diagram showing an example of a schematic configuration of an IoT system 9000 to which the technique according to the present disclosure can be applied. The IoT device 9001 includes various sensors such as a temperature sensor, a humidity sensor, an illuminance sensor, an acceleration sensor, a distance sensor, an image sensor, a gas sensor, and a human sensor. Further, the IoT device 9001 may include terminals such as smartphones, mobile phones, wearable terminals, and game devices. The IoT device 9001 is powered by an AC power supply, a DC power supply, a battery, a contactless power supply, a so-called energy harvest, or the like. The IoT device 9001 can communicate by wire, wireless, proximity wireless communication, or the like. As the communication method, 3G / LTE (registered trademark), Wi-Fi (registered trademark), IEEE802.5.4, Bluetooth (registered trademark), Zigbee (registered trademark), Z-Wave and the like are preferably used. The IoT device 9001 may switch and communicate with a plurality of these communication means.

The IoT device 9001 may form a one-to-one, star-shaped, tree-shaped, or mesh-shaped network. The IoT device 9001 may connect to the external cloud 9005 directly or through the gateway 9002. An address is assigned to the IoT device 9001 by IPv4, IPv6, 6LoWPAN, or the like. The data collected from the IoT device 9001 is transmitted to another IoT device 9003, the server 9004, the cloud 9005, and the like. The timing and frequency of transmitting data from the IoT device 9001 are appropriately adjusted, and the data may be compressed and transmitted. Such data may be used as it is, or the data may be analyzed by a computer 9008 by various means such as statistical analysis, machine learning, data mining, cluster analysis, discriminant analysis, combination analysis, and time series analysis. By using such data, various services such as control, warning, monitoring, visualization, automation, and optimization can be provided.

The technology related to this disclosure can also be applied to devices and services related to homes. IoT devices 9001 at home include washing machines, dryers, dryers, microwave ovens, dishwashers, refrigerators, ovens, rice cookers, cookware, gas appliances, fire alarms, thermostats, air conditioners, televisions, recorders, audio, Includes lighting equipment, water heaters, water heaters, vacuum cleaners, fans, air purifiers, security cameras, locks, door / shutter opening / closing devices, sprinklers, toilets, thermostats, weight scales, blood pressure monitors, etc. Further, the IoT device 9001 may include a solar cell, a fuel cell, a storage battery, a gas meter, a power meter, and a distribution board.

The communication method of the IoT device 9001 at home is preferably a low power consumption type communication method. Further, the IoT device 9001 may communicate by Wi-Fi indoors and 3G / LTE (registered trademark) outdoors. An external server 9006 for controlling the IoT device may be installed on the cloud 9005 to control the IoT device 9001. The IoT device 9001 transmits data such as the status of household equipment, temperature, humidity, power consumption, and the presence / absence of people / animals inside and outside the house. The data transmitted from the home device is stored in the external server 9006 through the cloud 9005. Based on such data, new services will be provided. Such an IoT device 9001 can be controlled by voice by using voice recognition technology.

Also, by sending information directly from various household devices to the TV, the status of various household devices can be visualized. Furthermore, various sensors determine the presence or absence of residents and send the data to air conditioners, lights, etc., so that their power can be turned on and off. Furthermore, advertisements can be displayed on displays provided in various home appliances via the Internet.

The example of the IoT system 9000 to which the technology according to the present disclosure can be applied has been described above. The technique according to the present disclosure can be suitably applied to a receiving device for communicating between various devices among the configurations described above.

The technique in the present disclosure can be applied not only to the above applications but also to various communications using high frequencies, for example. For example, as described above, it can be used for communication not only in a house but also in an industry such as a factory. Further, for example, it may be mounted on a mobile body and mounted on a device for communication. Not limited to these, it can be implemented in various applications.

The above-described embodiment may be in the following form.

(1)
The receiving device is
Based on the logical product of the first signal and the second signal, the phase difference between these signals is converted into the first amplitude, and the third signal constituting the first signal and the differential signal and the third signal and the second signal are differential. A first mixer that converts the phase difference of these signals into a second amplitude based on the logical product of the fourth signal that constitutes the signal.
The phase difference of these signals is converted into a third amplitude based on the logical product of the first signal and the fourth signal, and the phase difference of these signals is converted based on the logical product of the second signal and the third signal. A second mixer that converts the phase difference to the fourth amplitude,
Has a mixer,
To be equipped.

(2)
The first signal and the second signal are orthogonal signals.
The receiving device according to (1).

(3)
The mixer includes two switching elements connected in series, each of which is a switching element in which a signal whose logical product is desired to be acquired is input as a drive signal.
The receiving device according to (1) or (2).

(4)
The switching element is a MOSFET.
The receiving device according to (3).

(5)
The mixer comprises a AND gate that acquires the AND of two signals.
The receiving device according to (1) or (2).

(6)
A first amplifier that is connected to the first mixer and amplifies the difference between the first amplitude and the second amplitude.
A second amplifier, which is connected to the second mixer and amplifies the difference between the third amplitude and the fourth amplitude,
Equipped with an amplifier that has
A resistor having a first resistance value connected between the non-inverting input terminal and the inverting output terminal of the first amplifier and between the inverting input terminal and the non-inverting output terminal of the first amplifier, respectively.
A resistor having a second resistance value connected between the non-inverting input terminal and the inverting output terminal of the second amplifier and between the inverting input terminal and the non-inverting output terminal of the second amplifier, respectively.
Further prepare,
The receiving device according to any one of (1) to (5).

(7)
The first resistance value and the second resistance value have a predetermined ratio.
The receiving device according to (6).

(8)
The predetermined ratio is determined based on the amplitude error between the first amplifier output and the second amplifier output, which is converted from the phase error between the first signal and the second signal.
The receiving device according to (7).

(9)
An amplitude error detection circuit that detects quadrature amplitude error based on the output of the amplifier.
The receiving device according to any one of (6) to (8).

(10)
The first resistance value and the second resistance value are controlled based on the output of the amplitude error detection circuit.
The receiving device according to (9).

(11)
In the output from the amplitude error detection circuit, the first resistance value and the second resistance value are set so that the amplitude error between the output from the first amplifier and the output from the second amplifier is 0. Controlled,
The receiving device according to (10).

(12)
An AD conversion circuit that converts the output of the amplifier into a digital signal,
With more
The amplitude error detection circuit detects the quadrature amplitude error based on the output of the AD conversion circuit.
The receiving device according to any one of (9) to (11).

(13)
A phase shifter that changes the phase of one of the signals based on the first amplifier and the output based on the second amplifier output from the AD conversion circuit.
An adder circuit that adds the output of the AD conversion circuit and the output of the phase shifter,
The receiving device according to (12).

(14)
A gain adjustment circuit that adjusts the gain of the signal output from the AD conversion circuit,
The receiving device according to (12) or (13), further comprising.

(15)
A phase shifter that changes the phase of one of the signals based on the first amplifier and the output based on the second amplifier output from the amplitude error detection circuit.
An adder circuit that adds the output of the amplitude error detection circuit and the output of the phase shifter,
The receiving device according to any one of (9) to (14).

(16)
The phase shifter changes the phase of the signal by 90 degrees.
The receiving device according to (13) or (15).

(17)
The phase shifter arbitrarily changes the phase of the signal.
The receiving device according to (13) or (15).

(18)
A receiver that inputs RF input signals and outputs baseband signals.
The first transistor, to which the RF input signal is applied to the input terminal and the first signal is applied to the drive terminal,
A second transistor in which an input terminal is connected to an output terminal of the first transistor and a second signal orthogonal to the first signal is applied to a drive terminal.
A third transistor to which the RF input signal is applied to the input terminal and a third signal constituting the first signal and the differential signal is applied to the drive terminal.
A fourth transistor in which an input terminal is connected to an output terminal of the third transistor and a fourth signal constituting the second signal and a differential signal is applied to the drive terminal.
The first amplifier, in which the non-inverting input terminal is connected to the output terminal of the second transistor, the inverting input terminal is connected to the output terminal of the fourth transistor, and the baseband signal of the I channel is output.
A receiver equipped with.

(19)
The fifth transistor, to which the RF input signal is applied to the input terminal and the fourth signal is applied to the drive terminal,
The sixth transistor, in which the input terminal is connected to the output terminal of the fifth transistor and the first signal is applied to the drive terminal,
The seventh transistor, to which the RF input signal is applied to the input terminal and the second signal is applied to the drive terminal,
The eighth transistor, in which the input terminal is connected to the output terminal of the seventh transistor and the third signal is applied to the drive terminal,
A second amplifier that outputs a Q-channel baseband signal by connecting the non-inverting input terminal to the output terminal of the sixth transistor and the inverting input terminal to the output terminal of the eighth transistor.
The receiving device according to (18).

The aspect of the present disclosure is not limited to the above-described embodiment, but also includes various possible modifications, and the effect of the present disclosure is not limited to the above-mentioned contents. The components in each embodiment may be applied in an appropriate combination. That is, various additions, changes and partial deletions are possible without departing from the conceptual idea and purpose of the present disclosure derived from the contents defined in the claims and their equivalents.

1: Receiver,
10: Mixer, 10A: 1st mixer, 10B: 2nd mixer,
12IP, 12IN, 12QP, 12QN: Switch,
20: Amplifier, 20A: 1st amplifier, 20B: 2nd amplifier,
30: Amplitude error detection circuit,
32: ADC,
40: Test tone oscillator circuit,
42: Antenna,
50: Digital signal processing unit,
52: Amplitude error detection circuit,
54: Phaser,
56: Addition circuit,
57: Image signal level measurement and amplitude error correction circuit,
58: Gain adjustment circuit,
60: Analog signal processing unit,
62: Phaser,
64: Addition circuit,
70: Voltage-current conversion circuit

Claims

Based on the logical product of the first signal and the second signal, the phase difference between these signals is converted into the first amplitude, and the third signal constituting the first signal and the differential signal and the third signal and the second signal are differential. A first mixer that converts the phase difference of these signals into a second amplitude based on the logical product of the fourth signal that constitutes the signal.
The phase difference of these signals is converted into a third amplitude based on the logical product of the first signal and the fourth signal, and the phase difference of these signals is converted based on the logical product of the second signal and the third signal. A second mixer that converts the phase difference to the fourth amplitude,
Has a mixer,
A receiver equipped with.
The first signal and the second signal are orthogonal signals.
The receiving device according to claim 1.
The mixer includes two switching elements connected in series, each of which is a switching element in which a signal whose logical product is desired to be acquired is input as a drive signal.
The receiving device according to claim 1.
The switching element is a MOSFET.
The receiving device according to claim 3.
The mixer includes a logical product drive terminal that acquires the logical product of two signals.
The receiving device according to claim 1.
A first amplifier that is connected to the first mixer and amplifies the difference between the first amplitude and the second amplitude.
A second amplifier, which is connected to the second mixer and amplifies the difference between the third amplitude and the fourth amplitude,
Equipped with an amplifier that has
A resistor having a first resistance value connected between the non-inverting input terminal and the inverting output terminal of the first amplifier and between the inverting input terminal and the non-inverting output terminal of the first amplifier, respectively.
A resistor having a second resistance value connected between the non-inverting input terminal and the inverting output terminal of the second amplifier and between the inverting input terminal and the non-inverting output terminal of the second amplifier, respectively.
Further prepare,
The receiving device according to claim 1.
The first resistance value and the second resistance value have a predetermined ratio.
The receiving device according to claim 6.
The predetermined ratio is determined based on the amplitude error between the output of the first amplifier and the output of the second amplifier, which is converted from the phase error between the first signal and the second signal.
The receiving device according to claim 7.
An amplitude error detection circuit that detects quadrature amplitude error based on the output of the amplifier.
6. The receiving device according to claim 6.
The first resistance value and the second resistance value are controlled based on the output of the amplitude error detection circuit.
The receiving device according to claim 9.
In the output from the amplitude error detection circuit, the first resistance value and the second resistance value are set so that the amplitude error between the output from the first amplifier and the output from the second amplifier is 0. Controlled,
The receiving device according to claim 10.
An AD conversion circuit that converts the output of the amplifier into a digital signal,
With more
The amplitude error detection circuit detects the quadrature amplitude error based on the output of the AD conversion circuit.
The receiving device according to claim 9.
A phase shifter that changes the phase of one of the signals based on the first amplifier and the output based on the second amplifier output from the AD conversion circuit.
An adder circuit that adds the output of the AD conversion circuit and the output of the phase shifter,
12. The receiving device according to claim 12.
A gain adjustment circuit that adjusts the gain of the signal output from the AD conversion circuit,
12. The receiving device according to claim 12.
A phase shifter that changes the phase of one of the signals based on the first amplifier and the output based on the second amplifier output from the amplitude error detection circuit.
An adder circuit that adds the output of the amplitude error detection circuit and the output of the phase shifter,
9. The receiving device according to claim 9.
The phase shifter changes the phase of the signal by 90 degrees.
The receiving device according to claim 13.
The phase shifter arbitrarily changes the phase of the signal.
The receiving device according to claim 13.
A receiver that inputs RF input signals and outputs baseband signals.
The first transistor, to which the RF input signal is applied to the input terminal and the first signal is applied to the drive terminal,
A second transistor in which an input terminal is connected to an output terminal of the first transistor and a second signal orthogonal to the first signal is applied to a drive terminal.
A third transistor to which the RF input signal is applied to the input terminal and a third signal constituting the first signal and the differential signal is applied to the drive terminal.
A fourth transistor in which an input terminal is connected to an output terminal of the third transistor and a fourth signal constituting the second signal and a differential signal is applied to the drive terminal.
The first amplifier, in which the non-inverting input terminal is connected to the output terminal of the second transistor, the inverting input terminal is connected to the output terminal of the fourth transistor, and the baseband signal of the I channel is output.
A receiver equipped with.
The fifth transistor, to which the RF input signal is applied to the input terminal and the fourth signal is applied to the drive terminal,
The sixth transistor, in which the input terminal is connected to the output terminal of the fifth transistor and the first signal is applied to the drive terminal,
The seventh transistor, to which the RF input signal is applied to the input terminal and the second signal is applied to the drive terminal,
The eighth transistor, in which the input terminal is connected to the output terminal of the seventh transistor and the third signal is applied to the drive terminal,
A second amplifier that outputs a Q-channel baseband signal by connecting the non-inverting input terminal to the output terminal of the sixth transistor and the inverting input terminal to the output terminal of the eighth transistor.
18. The receiving device according to claim 18.