WO2021109722A1

WO2021109722A1 - Metalized laminate and manufacturing method therefor, and electronic device comprising metalized laminate

Info

Publication number: WO2021109722A1
Application number: PCT/CN2020/121338
Authority: WO
Inventors: 朱慧珑
Original assignee: 中国科学院微电子研究所
Priority date: 2019-12-06
Filing date: 2020-10-16
Publication date: 2021-06-10
Also published as: CN116169118A; CN110993583A; US20230005839A1

Abstract

A metalized laminate and a manufacturing method therefor, and an electronic device comprising the metalized laminate. The metalized laminate can comprise at least one interconnection line layer and at least one via hole layer alternately provided on a substrate. At least one pair of adjacent interconnection line layer and via hole layer in the metalized laminate comprise an interconnection line in the interconnection line layer and a via hole in the via hole layer, wherein the interconnection line layer is closer to the substrate than the via hole layer. At least a portion of the interconnection line is integrated with the via hole on the at least a portion of the interconnection line.

Description

Metallized laminate, manufacturing method thereof, and electronic equipment including metallized laminate

References to related applications

This application claims the priority of the Chinese patent application 201911254541.6 entitled "Metalized Laminate and its Manufacturing Method and Electronic Equipment Including Metalized Laminate" filed on December 6, 2019, the content of which is hereby used as reference.

Technical field

The present disclosure relates to the field of semiconductors, and more specifically, to a metallization stack and a method of manufacturing the same, and an electronic device including such a metallization stack.

Background technique

With the continuous miniaturization of semiconductor devices, it is becoming more and more difficult to manufacture high-density interconnect structures because of the need for extremely thin metal lines (meaning small grain size, excessive barrier thickness and resulting large resistance) and Very small line spacing (meaning misalignment, difficult to fill contact holes). In addition, it is difficult to align the metal lines with the vias, which may cause short-circuit or open-circuit failures in the integrated circuit (IC), and thus increase the manufacturing cost of the IC.

Summary of the invention

In view of this, the purpose of the present disclosure is at least partly to provide a metallized laminate and a manufacturing method thereof, and an electronic device including the metallized laminate.

According to one aspect of the present disclosure, a metallization stack is provided, including at least one interconnection layer and at least one via layer alternately arranged on a substrate. At least a pair of adjacent interconnection layer and via layer in the metallization stack includes interconnections in the interconnection layer and vias in the via layer, wherein the interconnection layer is closer to the liner than the via layer. bottom. At least a part of the interconnection line is integrated with the via on the at least a part of the interconnection line.

According to another aspect of the present disclosure, a method of manufacturing a metalized laminate is provided. The metallization stack includes at least one interconnection layer and at least one via layer alternately arranged. The method includes forming at least a pair of adjacent interconnection line layers and via layers in a metallization stack by the following operations: forming a metal layer on a lower layer; patterning the metal layer into an interconnection pattern; thinning the interconnection pattern The thickness of the first part is to form the interconnection line in the interconnection line layer, wherein the second part outside the first part of the interconnection pattern forms the via hole in the via layer.

According to another aspect of the present disclosure, there is provided an electronic device including the above-mentioned metallization stack.

According to an embodiment of the present disclosure, the interconnection pattern may be formed by photolithography. Thus, the line width and spacing of the interconnection line and the critical dimension (CD) and spacing of the via can be determined by the line width or CD and spacing of the photolithography, so that the line width or CD and spacing can be reduced, and thus the integration can be increased. density. In addition, the problem of metal filling in conventional processes is avoided. Moreover, since no filling process is used, ruthenium (Ru), molybdenum (Mo), rhodium (Rh), platinum (Pt), iridium (Ir), nickel (Ni), cobalt (Co) or chromium (Cr) can be used Metal material, so that it is unnecessary to use a diffusion barrier.

Description of the drawings

Through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, the above and other objectives, features, and advantages of the present disclosure will be more apparent. In the accompanying drawings:

Figures 1 to 16 schematically show some stages in the process of manufacturing a metallized laminate according to an embodiment of the present disclosure,

Among them, Figures 3(a), 7, 8(a), 9, 10(a), 11(a), 14(a) are top views, and Figures 1, 2, 10(b), 11(b), 12 (a), 14(b), 15(a), 15(b), 16 are cross-sectional views along the line AA', Figures 3(b), 4(a), 5(a), 8(b), 10(c), 11(c), 12(b), 13(a), 14(c) are cross-sectional views along the line BB', Figures 3(c), 4(b), 5(b), 8 (c), 10(d), 11(d), 12(c), 13(b), 14(d) are cross-sectional views along the CC' line, and Figures 6(a) to 6(c) are along the BB An enlarged view of the area near the metal wire in the section of the'line or CC' line.

Throughout the drawings, the same or similar reference numerals indicate the same or similar components.

Detailed ways

Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. However, it should be understood that these descriptions are only exemplary, and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily obscuring the concept of the present disclosure.

The drawings show various structural schematic diagrams according to the embodiments of the present disclosure. The figures are not drawn to scale, some details are enlarged and some details may be omitted for clarity of presentation. The shapes of the various regions and layers shown in the figure and the relative size and positional relationship between them are only exemplary. In practice, there may be deviations due to manufacturing tolerances or technical limitations. Areas/layers with different shapes, sizes, and relative positions can be designed as needed.

In the context of the present disclosure, when a layer/element is referred to as being “on” another layer/element, the layer/element may be directly on the other layer/element, or there may be an intermediate layer/element between them. element. In addition, if a layer/element is located "on" another layer/element in one orientation, the layer/element may be located "under" the other layer/element when the orientation is reversed.

The embodiment of the present disclosure proposes a method of manufacturing a metallized laminate. Different from the conventional technique in which an interlayer dielectric layer is formed first, then trenches or holes are formed in the interlayer dielectric layer, and the trenches or holes are filled with a conductive material to form interconnect lines or vias, according to the embodiments of the present disclosure, The metal pattern may be formed on the lower layer (for example, the substrate on which the device is formed or the next layer in the metallization stack) first, and then the gaps of the metal patterns are filled with dielectric material to form an interlayer dielectric layer. The metal pattern can be formed by photolithography. Thus, the line width and spacing of the interconnection line and the critical dimension (CD) and spacing of the via can be determined by the line width or CD and spacing of the photolithography, so that the line width or CD and spacing can be reduced, and thus the integration can be increased. density. In addition, the problem of metal filling in conventional processes is avoided. Moreover, since no filling process is used, ruthenium (Ru), molybdenum (Mo), rhodium (Rh), platinum (Pt), iridium (Ir), nickel (Ni), cobalt (Co) or chromium (Cr) can be used Metal material, so that it is not necessary to use a diffusion barrier layer.

In addition, in a conventional process, the trenches or holes formed by etching have a shape that tapers from top to bottom, so the interconnect lines or vias formed therein have a corresponding shape. In contrast, according to the embodiment of the present disclosure, the interconnection line or the via hole may be directly obtained by photolithography, and thus may have a shape that is tapered from the bottom to the top.

According to an embodiment of the present disclosure, a pair of interconnection layer and via layer adjacent to each other may be formed together. For example, a metal layer may be formed on the lower layer, and the thickness of the metal layer may correspond to the thickness of both the interconnection layer and the via layer. The metal layer may be formed on the entire area where the metallization stack needs to be formed, for example, over substantially the entire surface of the lower layer. The metal layer may be patterned, for example, by photolithography, into an interconnection pattern, and the interconnection pattern may correspond to or be the layout of the interconnection line in the interconnection line layer. The thickness of the first part of the interconnection pattern can be thinned (and possibly cut at certain areas) to form interconnection lines. The second portion (the thickness may not be substantially reduced) other than the first portion in the interconnection pattern may form a via hole in the via layer. Thus, the interconnection lines and the via holes above can be integrated with each other and self-aligned with each other.

The metallization stack may include a plurality of such interconnection line layers and via layers, and at least a part or even all of the interconnection line layers and via layers can be manufactured according to this method.

According to an embodiment of the present disclosure, the interconnection pattern may include a series of metal lines. These metal lines may have the same pattern as the layout of the interconnection lines in the interconnection line layer. That is, the metal layer can be patterned according to the layout of the interconnection lines. Alternatively, the interconnection pattern may have a pattern in which the metal lines extend according to the layout of the interconnection lines, but the metal lines corresponding to the separated interconnection lines opposite to each other may extend continuously. In this case, forming metal wires extending in the same direction is advantageous for patterning. This layout is matched with metal lines extending in another direction that intersects (for example, orthogonal) to the direction in another interconnection line layer, and various interconnection routes can be realized. For example, in a metallization stack, an interconnection line layer in which the interconnection lines extend in a first direction and an interconnection line in which the interconnection lines extend in a second direction orthogonal to the first direction may be alternately arranged in the vertical direction. Floor. After the thickness of the first part of the interconnection pattern is reduced, the metal line can be cut at a predetermined area according to the layout of the interconnection line to achieve separation between different interconnection lines.

In the above manufacturing process, after the metal lines are formed, between the metal lines, after thinning the first part of the metal lines, in the voids caused by the thickness reduction, a dielectric material may be filled to form an interlayer dielectric layer. Since the gap between the metal lines or the above-mentioned gap is small, an air gap or a hole may be formed in the filled dielectric material. Such air gaps or holes can help reduce capacitance. As described below, the position of the air gap or hole can be adjusted by a deposition-etch-deposition method. In addition, the dielectric material of each filling may be the same or different.

According to the above method, a metallization stack according to an embodiment of the present disclosure can be obtained, in which at least a part of the interconnection line in at least one interconnection line layer and the via hole thereon are integrated with each other. In the conventional double damascene process, the interconnection line and the via hole below can be formed together, and they can therefore be integrated. Unlike this, according to the embodiment of the present disclosure, the interconnection line and the via hole thereon can be formed together, and therefore they can be integrated.

As described above, the interconnection line and the via hole above can be obtained by photolithography through the same metal layer, so the sidewall of the via hole may not exceed the sidewall of the interconnection line below.

The present disclosure can be presented in various forms, some examples of which will be described below. In the following description, the selection of various materials is involved. In addition to the selection of materials considering their functions (for example, semiconductor materials are used to form active regions, dielectric materials are used to form electrical isolation, and conductive materials are used to form interconnect lines and vias), etching selectivity is also considered. In the following description, the required etching selectivity may or may not be indicated. It should be clear to those skilled in the art that when etching a certain material layer is mentioned below, if it is not mentioned that other layers are also etched or the figure does not show that other layers are also etched, then this kind of etching It may be selective, and the material layer may have etching selectivity relative to other layers exposed to the same etching recipe.

1 to 16 schematically show some stages in the process of manufacturing metallization according to an embodiment of the present disclosure.

As shown in FIG. 1, a substrate 1001 is provided. The substrate 1001 may be in various forms, including but not limited to bulk semiconductor material substrates such as bulk Si substrates, semiconductor-on-insulator (SOI) substrates, compound semiconductor substrates such as SiGe substrates, and the like. The following description takes the bulk Si substrate as an example.

In the substrate 1001, an active region may be defined by an isolation portion 1003, such as shallow trench isolation (S TI). For example, the isolation part 1003 may surround each active region. On each active area, a semiconductor device T can be formed, such as a metal oxide semiconductor field effect transistor (MOSFET), a fin field effect transistor (FinFET), a nanowire field effect transistor, and the like. The semiconductor device T may have a gate stack including a gate dielectric layer 1005 and a gate electrode layer 1007, and source/drain regions S/D formed on both sides of the gate stack in the active region. On the sidewalls of the gate stack, a gate spacer 1009 may be formed. The semiconductor device T may be a planar device such as a MOSFET or a three-dimensional device such as a FinFET. In the case of FinFET, the active region may be formed in the form of a fin protruding with respect to the surface of the substrate.

An interlayer dielectric layer 1011 such as oxide (for example, silicon oxide) may be formed on the substrate 1001 to cover each semiconductor device T formed on the substrate 1001. In addition, in the interlayer dielectric layer 1011, a contact portion 1013 to each semiconductor device T may be formed. In FIG. 1, only the contact portion to the source/drain region S/D is shown, and the contact portion to the gate electrode layer 1007 may also be included (for example, see FIG. 3(b)).

After that, an interconnection structure or metallization stack can be fabricated on the substrate 1001.

As shown in FIG. 2, a metal layer 1015 can be formed on the interlayer dielectric layer 1011 by, for example, deposition such as physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. For example, the metal layer 1015 may include conductive metals such as ruthenium (Ru), molybdenum (Mo), rhodium (Rh), platinum (Pt), iridium (Ir), nickel (Ni), cobalt (Co), or chromium (Cr), etc. . The metal layer 1015 may have a thickness for both the first interconnect layer and the first via layer in the metallization stack, for example, about 10 nm to 200 nm.

According to an embodiment of the present disclosure, the Ru source can be purified in the following manner to obtain high-purity Ru metal. A gas stream including ozone (O ₃ ) can be introduced into one or more reaction chambers to contact with the Ru source, thereby forming ruthenium tetroxide (RuO ₄ ) that is gaseous under the reaction conditions. Ruthenium tetroxide and unreacted ozone and airflow residues can be sent into the collection chamber, in which the gaseous ruthenium tetroxide can be reduced to a ruthenium dioxide (RuO ₂ ) layer on the semiconductor substrate. Then, the deposited ruthenium dioxide can be reduced by using, for example, hydrogen to produce high-purity Ru metal. In addition, ozone can be used as an etching gas to etch and pattern the deposited Ru metal layer.

As shown in FIGS. 3(a) to 3(c), the metal layer 1015 can be patterned as a series of metal lines. The patterning can be performed by a photolithography process, for example, partition wall pattern transfer photolithography or extreme ultraviolet (EUV) photolithography. In photolithography, reactive ion etching (RIE) can be used, and the RIE can be stopped at the interlayer dielectric layer 1011 (or the contact portion 1013 therein) under the metal layer 1015. The interval between the metal lines may define the interval between the interconnection lines in the first interconnection line layer, and is, for example, about 5 nm-150 nm. In addition, in order to avoid excessive fluctuations in the density of the patterns in the same layer between different regions, dummy metal lines may be formed so that the metal lines are arranged at substantially uniform intervals, for example. The line width of the metal line may define the line width of the interconnection line in the first interconnection line layer, for example, about 5 nm-100 nm. In addition, at least a part of the metal wire may contact and be electrically connected to the contact portion 1013 below.

In this example, the formed metal wire extends substantially in parallel along the first direction (the horizontal direction on the paper in FIG. 3(a)), and may be formed later along the first direction crossing (for example, perpendicular) to the first direction. The metal wires extending in two directions cooperate to realize various interconnection routes. However, the present disclosure is not limited to this. For example, different metal wires can extend in different directions, and the same metal wire can extend zigzag.

As shown in FIGS. 4(a) and 4(b), another interlayer dielectric layer may be formed on the interlayer dielectric layer 1011 to fill the gaps between the metal lines 1015. The other interlayer dielectric layer may include dielectric materials such as silicon oxide, silicon oxycarbide, other low-k dielectric materials, and the like. Here, the other interlayer dielectric layer and the previous interlayer dielectric layer 1011 may include the same material, and thus may be shown as a whole as 1011, and the possible boundary between them is schematically shown with a dashed line. Of course, they can also include different materials.

The other interlayer dielectric layer may be deposited (e.g., CVD or ALD) dielectric material to cover the metal line 1015, and then etch back or planarize (e.g., chemical mechanical polishing (CMP)) the deposited dielectric material and stop at The top surface of the metal wire 1015 is formed. Etching back can use atomic layer etching (ALE) to achieve good process control.

In the examples shown in FIGS. 4(a) and 4(b), the deposited dielectric material completely fills the gaps between the metal lines 1015. However, the present disclosure is not limited to this. As shown in Figures 5(a) and 5(b), since the gap between the metal lines 1015 is small, when the dielectric material is deposited, for example, when a CVD process is used, an air gap or an air gap can be formed between the metal lines 1015. Hole 1017. Such an air gap or hole 1017 helps to reduce the capacitance between the metal lines.

According to an embodiment of the present disclosure, by adjusting the deposition process, the position of the air gap or hole 1017 in the vertical direction can be adjusted.

For example, as shown in FIG. 6(a), a dielectric material may be deposited into the gap between the metal lines 1015 until the dielectric material closes the top of the gap. During the deposition process, multiple films (of the same or different materials) can be used. In this case, the formed air gap or hole 1017a may be located approximately in the middle of the gap in the vertical direction.

Alternatively, as shown in FIG. 6(b), a dielectric material may be deposited into the gap between the metal lines 1015 without closing the top of the gap. Then, the deposited dielectric material can be selectively etched, such as RIE, leaving a part at the bottom of the gap, thereby increasing the opening in the dielectric material. Then, the dielectric material can be deposited continuously until the dielectric material closes the top of the gap. The dielectric material deposited twice can be the same or different. Of course, this deposition-etch-deposition process can be repeated multiple times. In this case, the formed air gap or hole 1017b may be located at the lower part of the gap in the vertical direction.

Alternatively, as shown in FIG. 6(c), a dielectric material may be deposited into the gap between the metal lines 1015 until the dielectric material can completely fill the gap. Then, the deposited dielectric material can be selectively etched such as RIE, leaving a part at the bottom of the gap. Then, the dielectric material can be deposited continuously until the dielectric material closes the top of the gap. The dielectric material deposited twice can be the same or different. Of course, this deposition-etch-deposition process can be repeated multiple times. In this case, the formed air gap or hole 1017c may be located at the upper part of the gap in the vertical direction.

As described above, by alternately performing deposition and etching, the positions of air gaps or holes between metal line gaps can be adjusted up and down.

Currently, in the first via layer, the pattern of the metal layer is the same as the pattern in the first interconnection line layer (ie, the aforementioned metal line pattern). The metal layer (ie, the metal line) may be further patterned in the first via layer to form a via pattern.

As shown in FIG. 7, a photoresist 1019 may be formed on the interlayer dielectric layer 1011 and the metal line 1015, and the photoresist 1019 may be patterned (for example, by exposure and development) to cover the area where the via is to be formed, and expose The rest of the area.

Here, the width W1 of the photoresist 1019 (the width of the via hole in the first via layer defined thereby) (the dimension in the longitudinal extension direction of the metal wire, in this example, the horizontal direction on the paper in FIG. 7 The upper dimension) may be relatively large, so that the interconnection line in the second interconnection line layer formed thereon can better land on the via hole and make better contact with the via hole.

As shown in FIGS. 8(a) to 8(c), the photoresist 1019 can be used as an etching mask to selectively etch the metal line 1015, such as RIE, to form a via. The etching of the metal wire 1015 may be performed to the middle of the metal wire in the vertical direction, for example, a substantially middle position. In this way, the lower part of each metal line 1015 can be kept continuously extending (the interconnection line in the first interconnection line layer can be formed), and at least a part of the upper part of the metal line 1015 can be formed as some separate patterns (the first via hole can be formed). For the vias in the layer, see the top view of Figure 8(a)). There may be some metal lines 1015 (for example, dummy metal lines), the upper part of which is etched away, so there is no corresponding via hole. In FIGS. 8(b) and 8(c), the boundary between the first interconnection layer and the first via layer is schematically shown with a dashed line, but they are physically integrated. After that, the photoresist 1019 may be removed.

Since the via holes are obtained from lines formed by photolithography, the minimum interval between the via holes can be defined by the minimum line interval achievable by the photolithography process (for example, equal). In general, the minimum spacing between vias formed by photolithography is greater than the minimum spacing between lines.

Currently, each metal line 1015 in the first interconnection line layer maintains continuous extension. They can be separated into multiple parts according to the design layout.

As shown in FIG. 9, a photoresist 1021 may be formed on the interlayer dielectric layer 1011 and the metal line 1015, and the photoresist 1021 may be patterned to cover the area where the interconnection lines exist in the pattern of the first interconnection line layer, and A region where there is no interconnection line in the pattern of the first interconnection line layer is exposed.

As shown in FIGS. 10(a) to 10(d), the photoresist 1021 can be used as an etching mask to selectively etch the metal line 1015, such as RIE. Here, the etching of the metal line 1015 can be stopped at the underlying interlayer dielectric layer 1011 to cut the metal line 1015. Therefore, in the first interconnection line layer, the metal lines 1015 can form some separated metal line segments to obtain corresponding interconnection lines. After that, the photoresist 1021 may be removed.

In the above example, first pattern the vias in the first via layer (the etching depth is roughly half the thickness of the metal layer), and then pattern the interconnect lines in the first interconnect layer (the etching depth is also the metal layer Roughly half the thickness). This is advantageous because the etching depth of each etching process is reduced. However, the present disclosure is not limited to this. For example, the order of the two composition processing can be exchanged.

As shown in FIG. 10(b), the lower part of the metal line 1015 extends on the interlayer dielectric layer 1011 to form an interconnection line; the upper part of the metal line 1015 is a localized pattern on the interconnection line to form a via. Since the interconnection line and the via are obtained through the same metal line 1015, they are integrated and self-aligned with each other.

In addition, as shown by the dashed line in the rightmost metal line 1015 in FIG. 10(b), adjacent vias on the same interconnection line will not cause incorrect electrical connection between the upper-level interconnection lines. Next, the thickness of the metal wire between them may not be reduced. That is, the widths of adjacent via holes are increased to be connected to each other as one body. In this way, the connection resistance can be reduced.

In addition, as shown in FIG. 10(b), in the longitudinal extension direction of the metal wire 1015 (the horizontal direction in the paper in FIG. 10(b)), the via hole may be located in a local area of the interconnection line, such as a via hole. The sidewalls are retracted relative to the corresponding sidewalls of the interconnection line. In addition, as shown in FIGS. 10(c) and 10(d), in a cross section perpendicular to the longitudinal extension direction of the metal line 1015, the sidewall of the via hole and the corresponding sidewall of the interconnection line may be substantially coplanar.

Due to the above etching of the metal line 1015, voids are formed in the interlayer dielectric layer 1011. As shown in Figures 11(a) to 11(d), these voids can be filled with dielectric materials. This can be done by deposition and then etch back or planarization as described above. The deposited dielectric material may be the same as or different from the previous interlayer dielectric layer 1011. Here, the deposited dielectric material and the previous interlayer dielectric layer are still integrally shown as 1011, and the possible boundary between them is schematically shown with a dashed line. According to other embodiments, before depositing the dielectric material, a thin layer may be formed by, for example, deposition for the purpose of diffusion barrier, protection, or etch stop.

Similarly, as described above, due to the small gaps to be filled, air gaps or holes 1023 may be formed when the dielectric material is deposited, as shown in FIGS. 12(a) to 12(c). The air gap or hole 1023 may be different according to the shape of the corresponding gap. In addition, as described above, the position of the air gap or hole 1023 in the vertical direction can be adjusted by adjusting the deposition process.

In addition, FIGS. 13(a) and 13(b) show a case where an air gap or a hole is formed when the gap in the interlayer dielectric layer is filled twice. That is, in the example shown in FIGS. 13(a) and 13(b), the above-mentioned air gap or hole 1017 and air gap or hole 1023 are combined.

Through the above process, the first interconnection layer and the first via layer are formed. Next, in the same way, the interconnection layer and the via layer in the upper layer of the metallization stack can be formed continuously.

However, the present disclosure is not limited to this. Hereinafter, in conjunction with the second interconnect layer and the second via layer, a manufacturing method according to another embodiment of the present disclosure will be described. The methods described below can be used alone or in combination with the methods described above.

As shown in FIGS. 14(a) to 14(d), as described above in conjunction with FIG. 2, a metal layer 1025 may be formed. The metal layer 1025 may include the same or different metal material as the metal layer 1015. Similarly, the metal layer 1025 may have a thickness for both the second interconnect line layer and the second via layer in the metallization stack, for example, about 10 nm to 200 nm.

Then, as described above in connection with FIGS. 3(a) to 3(c), the metal layer 1025 can be patterned into a series of metal lines. In this example, instead of patterning the metal layer 1025 into continuously extending metal lines, the metal layer 1025 may be directly patterned according to the pattern of the second interconnection line layer. Thus, the metal layer 1025 can be patterned as a series of metal line segments. That is, here, the metal wire cutting process described above in conjunction with FIGS. 9 and 10(a) to 10(d) is combined to be performed together with the metal layer patterning, so that a separate cutting photolithography process is not required. In addition, due to this patterning manner, the metal line segment may not be limited to a straight line segment, but may include a zigzag line segment.

In addition, when the metal layer 1025 is etched, over-etching of the underlying metal layer 1015 may occur. Thus, as shown in FIG. 14(b), the width of the upper portion of the via hole in the first via layer can be reduced, and is approximately the same as the line width of the metal line segment 1025 formed thereon. In addition, as shown in FIG. 14(b), the line width W2 of the metal line segment 1025 (the scale in the horizontal direction on the paper in FIG. 14(b)) can be relatively small and smaller than the via hole in the first via layer (not Considering the upper part, its width may be reduced due to the above-mentioned over-etching) width W1 (the scale in the horizontal direction on the paper in FIG. 14(b)), so that the metal line segment 1025 (the second interconnection line layer in the second interconnection layer is subsequently formed) is the width W1 The interconnection line can better land on the via hole so as to make better contact with the via hole.

Another interlayer dielectric layer may be formed on the interlayer dielectric layer 1011 to fill the gap between the metal line segments 1025. The other interlayer dielectric layer may include dielectric materials such as silicon oxide, silicon oxycarbide, other low-k dielectric materials, and the like.

This other interlayer dielectric layer is formed as described below.

As shown in FIG. 15(a), a dielectric material may be deposited (for example, CVD or ALD) to cover the metal line segment 1025. Here, the deposited dielectric material and the previous interlayer dielectric layer 1011 may include the same material, and thus may be shown integrally as 1011, and the possible boundary between them is schematically shown with a dashed line. Of course, they can also include different materials.

Alternatively, as described above, as shown in FIG. 15(b), when the dielectric material is deposited, an air gap or hole 1027 may be formed between the metal line segments 1025. In this example, since the metal line segments have the pattern of the second interconnection line layer, the density of the metal line segments in a part of the area may be lower, or the gap between the metal line segments may be larger. In these areas, it is difficult to form air gaps or holes.

Then, as shown in FIG. 16, the dielectric material deposited by CMP can be etched back or planarized and stopped on the top surface of the metal line segment 1025. ALE can be used for etch back to achieve good process control.

After that, the via hole in the second via layer can be formed on the upper portion of the metal line segment 1025 according to the process described above in conjunction with FIGS. 7 and 8(a) to 8(c). Thus, the lower part of the metal line segment 1025 forms an interconnection line in the second interconnection line layer. Then, the gap in the interlayer dielectric layer 1011 can be filled with a dielectric material according to the process described above in conjunction with FIGS. 11(a) to 11(d). In this way, the second interconnect layer and the second via layer are formed.

The metallization stack according to the embodiment of the present disclosure can be applied to various electronic devices. Therefore, the present disclosure also provides an electronic device including the above-mentioned metallization stack. The electronic device may also include components such as a display screen and a wireless transceiver. Such electronic devices are, for example, smart phones, computers, tablet computers (PCs), wearable smart devices, mobile power supplies, and so on.

According to an embodiment of the present disclosure, a manufacturing method of a system on chip (SoC) is also provided. The method may include the method described above. Specifically, a variety of devices can be integrated on the chip, at least some of which are manufactured according to the method of the present disclosure.

In the above description, the technical details such as patterning and etching of each layer have not been described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc., of a desired shape. In addition, in order to form the same structure, those skilled in the art can also design a method that is not completely the same as the method described above. In addition, although the embodiments are separately described above, this does not mean that the measures in the respective embodiments cannot be advantageously used in combination.

The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only, and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, and these substitutions and modifications should fall within the scope of the present disclosure.

Claims

A metallization stack includes at least one interconnection layer and at least one via layer alternately arranged on a substrate, wherein at least a pair of adjacent interconnection layers and via layers in the metallization stack include:

Interconnection lines in the interconnection line layer; and

The vias in the via layer,

Wherein, the interconnect layer is closer to the substrate than the via layer,

Wherein, at least a part of the interconnection line is integrated with a via hole on the at least a part of the interconnection line.
The metallization stack of claim 1, wherein the at least a part of the interconnection line and the via on the at least a part of the interconnection line are formed of the same material.
The metallization stack according to claim 1 or 2, wherein the outer peripheral side wall of the via hole does not exceed the outer peripheral side wall of the at least a part of the interconnection line.
The metallization stack of claim 3, wherein the sidewalls of the at least a portion of the interconnection line along the longitudinal extension direction thereof are substantially coplanar with at least the lower portion of the corresponding sidewall of the via hole.
The metallization stack according to claim 1 or 2, wherein the interconnection line and the via hole comprise metal and are in direct contact with the surrounding dielectric layer.
The metallization stack according to claim 5, wherein the metal includes ruthenium (Ru), molybdenum (Mo), rhodium (Rh), platinum (Pt), iridium (Ir), nickel (Ni), cobalt ( Co) or chromium (Cr).
The metallization stack according to claim 1, further comprising: a dielectric layer surrounding the interconnection line and the via hole, wherein the dielectric layer is between the interconnection lines and/or the There are holes or air gaps between the vias.
The metallization stack according to claim 1 or 2, wherein each interconnection line in the interconnection line layer extends in the same direction.
8. The metallization stack according to claim 8, wherein the interconnection lines in at least a pair of upper and lower interconnection line layers extend in directions orthogonal to each other.
The metallization stack according to claim 1 or 2 or 9, wherein the width of the via hole is greater than the width of the interconnection line on the via hole.
The metallization stack of claim 10, wherein the width of the upper portion of the via hole and the interconnection line on the via hole are substantially the same, and the width of the lower portion of the via hole is greater than the width of the interconnection line on the via hole. The width of the connection.
The metallization stack according to claim 1 or 2, wherein, in a cross section perpendicular to the longitudinal extension direction of the interconnection line, the via hole and the interconnection line are tapered from bottom to top shape.
The metallization stack of claim 1, wherein the minimum spacing between the via holes is defined by the minimum line spacing achievable by the photolithography process.
A method for manufacturing a metallization stack, the metallization stack includes at least one interconnection layer and at least one via layer alternately arranged, the method includes forming at least one of the metallization stacks by the following operations A pair of adjacent interconnect layer and via layer:

Forming a metal layer on the lower layer;

Patterning the metal layer into an interconnection pattern;

Reducing the thickness of the first portion of the interconnection pattern to form interconnection lines in the interconnection line layer,

Wherein, a second part other than the first part of the interconnection pattern forms a via hole in the via hole layer.
The method according to claim 14, wherein each pair of adjacent interconnection layer and via layer in the metallization stack is formed by the operation.
The method according to claim 14, wherein the metal layer comprises ruthenium (Ru), molybdenum (Mo), rhodium (Rh), platinum (Pt), iridium (Ir), nickel (Ni), cobalt (Co) Or chromium (Cr).
The method of claim 14, wherein forming a metal layer on the lower layer comprises:

Through deposition, a metal layer having a thickness corresponding to the sum of the thickness of the interconnection layer and the via layer is formed.
The method of claim 17, wherein the deposited metal layer covers substantially the entire surface of the lower layer.
The method of claim 14, wherein the patterning includes photolithography.
The method of claim 19, wherein the photolithography comprises pattern transfer of partition walls or extreme ultraviolet photolithography.
The method according to claim 14, wherein:

The patterning of the metal layer into an interconnection pattern includes: patterning the metal layer into a series of metal lines,

The method further includes: filling a first dielectric layer between the metal lines.
The method of claim 21, further comprising:

A hole or air gap is formed in the first dielectric layer between the metal lines.
The method of claim 22, wherein forming a hole or an air gap comprises:

The first dielectric layer is filled by depositing a dielectric material into the space between the metal lines to close the top of the space,

Wherein, the hole or air gap is formed substantially in the middle of the space.
The method of claim 23, wherein depositing a dielectric material comprises depositing multiple layers of the same or different dielectric materials.
The method of claim 22, wherein forming a hole or an air gap includes filling the first dielectric layer by:

Depositing a first dielectric material into the space between the metal lines, so that the deposited first dielectric material has an opening at the top of the space;

Selectively etch the deposited first dielectric material to increase the opening; and

A second dielectric material is further deposited into the space between the metal lines to close the top of the space,

Wherein, the hole or air gap is formed in the lower part of the space,

Wherein, the first dielectric material and the second dielectric material are the same or different.
The method of claim 22, wherein forming a hole or an air gap includes filling the first dielectric layer by:

Depositing a first dielectric material into the space between the metal lines to completely fill the space;

Selectively etch the deposited first dielectric material so that it remains at the bottom of the space; and

A second dielectric material is further deposited into the space between the metal lines to close the top of the space,

Wherein, the hole or air gap is formed in the upper part of the space,

Wherein, the first dielectric material and the second dielectric material are the same or different.
The method of claim 21, wherein:

The series of metal wires extend continuously in the same direction,

The method also includes:

Cutting the thinned first portion of at least one of the series of metal wires at a predetermined area; and

In the space formed between the metal wires due to the thinning and the cutting, a second dielectric layer is filled,

Wherein, the first dielectric layer and the second dielectric layer include the same or different materials.
The method of claim 27, further comprising:

A hole or air gap is formed in the second dielectric layer between the metal lines.
The method of claim 21, wherein:

The pattern of the series of metal lines corresponds to the layout of the interconnection lines in the corresponding interconnection line layer.
The method according to claim 15, wherein, for two adjacent pairs of interconnection layer and via layer, in the operation of forming the upper pair of interconnection layer and via layer, the patterning includes over-etching eclipse.
The method of claim 14, wherein the thinning of the thickness of the first portion of the interconnection pattern comprises:

For the area between two adjacent vias on the same interconnection line in the design layout of the metallization stack, the thickness of the interconnection pattern is not reduced, thereby forming a shared via for the two vias.
The method according to any one of claims 14 to 31, wherein a diffusion barrier layer is not formed between the interconnection pattern and the dielectric layer surrounding the interconnection pattern.
The method according to any one of claims 14 to 31, wherein the width of the via hole is greater than the width of the interconnection line on the via hole.
An electronic device comprising the metallized laminate according to any one of claims 1 to 13.
The electronic device according to claim 34, wherein the electronic device comprises a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank.