WO2021109698A1 - Chip and inter-core data transmission method - Google Patents

Abstract

Provided is a chip and an inter-core data transmission method. The chip comprises: a plurality of interconnection structures, wherein each of the interconnection structures is connected to a processing core group, and the processing core group comprises at least two processing cores; data transmission between the processing cores in the processing core group is performed by means of the interconnection structure which is connected to the processing core group; and the plurality of interconnection structures are not directly connected to each other. In the chip, data transmission between cores in the same processing core group is realized by means of the interconnection structure corresponding to the group, and data transmission between cores in different processing core groups can be handled in parallel, such that a total data bandwidth is greatly increased, the efficiency of data transmission between cores is improved, the power consumption is reduced, and the performance of the chip is improved; moreover, since data transmission of different groups can be handled in parallel, the data transmission of different groups will not interfere with each other, thereby preventing the occurrence of a data congestion phenomenon and improving the performance of the chip.

Description

Data transmission method between chip and core Technical field

The present invention relates to the technical field of chips, in particular to a method for transmitting data between chips and cores.

Background technique

With the development of science and technology, human society is rapidly entering the era of intelligence. The important feature of the intelligent age is that people have more and more types of data, the amount of data they can obtain is larger and larger, and the requirements for the speed of data processing are getting higher and higher.

The chip is the cornerstone of data processing, and it fundamentally determines the ability of people to process data. From the perspective of application fields, there are two main routes for chips: one is a general-purpose chip route, such as a central processing unit (CPU), etc. They can provide great flexibility, but they are effective in processing algorithms in specific fields. The power is relatively low; the other is a dedicated chip route, such as Tensor Processing Unit (TPU), etc. They can exert higher effective computing power in some specific fields, but they are more versatile in the face of flexible and changeable In the field, their processing power is relatively poor or even unable to handle.

Due to the wide variety and huge amount of data in the intelligent era, the chip is required to have extremely high flexibility, capable of processing different fields and rapidly changing algorithms, and extremely strong processing capabilities, which can quickly process extremely large and rapidly increasing data. the amount.

Summary of the invention

(1) Purpose of the invention

The purpose of the present invention is to provide a data transmission method between chips and cores. The chip provided by the embodiment of the present invention includes multiple interconnection structures. The processing cores in the same processing core group realize data transmission through the interconnection structure connected to the group, so that the data transmission between different groups of cores can be processed in parallel, greatly Improve the total data bandwidth and improve the performance of the chip.

(2) Technical solution

In order to solve the above-mentioned problems, the first aspect of the present invention provides a chip including: a plurality of interconnection structures, each interconnection structure is connected to a processing core group, and all the processing cores connected by one interconnection structure are one Processing core group; each of the processing cores belonging to the same processing core group performs data transmission through the interconnection structure connected to the processing core group; wherein multiple interconnection structures are not directly connected.

The chip provided by the embodiment of the present invention includes a plurality of interconnection structures. The processing cores in the same processing core group realize data transmission through the interconnection structure connected to the group, so that data transmission between cores in different processing groups can be achieved. Parallel processing greatly improves the total data bandwidth and improves the performance of the chip.

Further, data transmission can be performed between processing cores belonging to different processing core groups.

Further, the amount of data transmitted between any two processing cores belonging to a processing core group is greater than the amount of data transmitted between any two different processing core groups.

Further, the plurality of interconnection structures includes a first interconnection structure and a second interconnection structure; the first interconnection structure is connected to a first processing core; the first processing core is connected to the second interconnection structure.

Further, the first interconnect structure is also connected to a second processing core; the second interconnect structure is connected to a third processing core; the second processing core passes through the first processing core and the third processing core Realize data transmission.

Further, the interconnection structure includes a third interconnection structure; all the processing cores connected by the third interconnection structure are not connected to other interconnection structures.

Further, the processing core connected to each interconnection structure is not connected to other interconnection structures.

Further, each of the processing cores includes at least one transmission unit, and the bandwidth of the interconnection structure meets the bandwidth requirement of the transmission unit.

Further, the bandwidth of the interconnect structure meets the bandwidth requirements of each of the processing cores in the processing core group connected to the interconnect structure.

Further, the bandwidth of the interconnection structure is greater than the bandwidth requirements of each of the processing cores in the processing core group connected to the interconnection structure.

Further, at least two clock frequencies are provided for the plurality of interconnect structures.

Further, at least two bit width values are set for the plurality of interconnect structures.

Furthermore, at least two processing core groups have different bandwidth requirements.

According to a second aspect of the present invention, a card board is provided, which includes one or more chips provided in the first aspect.

According to the third aspect of the present invention, there is also provided an electronic device, including one or more card boards provided in the second aspect.

According to a fourth aspect of the present invention, there is provided an inter-core data transmission method used in the chip provided in the first aspect. The method includes: each of the processing cores belonging to the same processing core group passes through the processing cores. The group-connected interconnection structure realizes data transmission; the two processing cores respectively belonging to two different processing core groups realize data transmission through at least two of the interconnection structures.

Further, the two processing cores respectively belonging to two different processing core groups realize data transmission through at least two interconnection structures, including: the two processing cores respectively belonging to two different processing core groups , Through one processing core belonging to the two different processing core groups at the same time, data transmission is realized through the two interconnection structures.

According to a fifth aspect of the present invention, there is provided a computer storage medium having a computer program stored on the computer storage medium, and when the program is executed by a processor, the steps of the inter-core data transmission method of the fourth aspect are realized.

According to a sixth aspect of the present invention, there is provided an electronic device including a memory, a processor, and a computer program stored in the memory and capable of running on the processor. The processor implements The fourth aspect of the steps of the inter-core data transmission method.

According to a seventh aspect of the present invention, a computer program product is provided, which includes computer instructions, and when the computer instructions are executed by a computing device, the computing device can execute the steps of the fourth aspect of the inter-core data transmission method.

(3) Beneficial effects

The above technical solution of the present invention has the following beneficial technical effects:

(1) The chip provided by the embodiment of the present invention is provided with multiple interconnection structures. The processing cores of the same processing core group realize data transmission through the interconnection structure connected to the group, so that the data transmission of different processing core groups can be processed in parallel. On the one hand, it greatly improves the total data bandwidth, improves the efficiency of data transmission between cores, reduces power consumption, and improves the performance of the chip; on the other hand, because different groups of data transmission can be processed in parallel, different groups The data transmission will not interfere with each other, thereby avoiding data congestion and improving the performance of the chip.

(2) In the chip provided by the embodiment of the present invention, when data is transmitted between cores belonging to the same group, only the data format of the cores in the same group needs to be considered, and there is no need to consider the data format of other cores in other groups of the chip. , Reduce the complexity of the circuit in the chip.

(3) Since a processing core group adopts an interconnection structure to realize data transmission, different interconnection structures can be set with different clock frequencies and different bit widths, and the corresponding bit widths can be set according to the needs of each group of data transmission. All cores in a chip use an interconnection structure for data transmission, which reduces power consumption, improves the performance of the entire chip and increases the flexibility of chip design. The interconnection is determined according to the actual bandwidth requirements of different processing core groups. The appropriate bit width and frequency of the structure can save the area of the chip.

Description of the drawings

Figure 1 is a schematic diagram of the structure of a chip;

FIG. 2 is a structural diagram of a chip according to an embodiment of the present invention;

Fig. 3 is a structural diagram of a chip according to an embodiment of the present invention;

FIG. 4 is a schematic flowchart of a method for transmitting data between cores according to an embodiment of the present invention.

Detailed ways

In order to make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings. It should be understood that these descriptions are only exemplary, and are not intended to limit the scope of the present invention. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily obscuring the concept of the present invention.

In a multi-core chip, all cores may be isomorphic, that is, each core has the same structure, and there may also be heterogeneous cores in all cores, that is, there are at least two different cores. . In a multi-core architecture, multiple cores often participate in the execution of a certain task at the same time. At this time, there will be data transmission between the cores. Therefore, for a multi-core chip, which architecture is adopted, how to perform data transmission, so that homogeneous or heterogeneous cores can form a chip with excellent performance are very important.

Figure 1 is a schematic diagram of the structure of a chip.

In the chip structure shown in Figure 1, the chip has only one network on chip, and all cores are connected to each other through a network on chip (NoC, Network On Chip) to exchange data.

As shown in Figure 1, the chip is equipped with cores of various structures, including K ₁ _C ₁ , K ₂ _C ₁ and K _M _C ₁ , where M indicates that the type of core is M, each The number of cores is multiple. For example, the first type of core K ₁ includes K ₁ _C ₁ , K ₁ _C ₂ and K ₁ _C _NM , where NM means that the number of each type of core is NM. That is, K _M _C _{NM is} represented as the NM-th nucleus of the M-th structure.

Since there are many types of cores in this chip (M types), and different types of cores use the same NoC for data exchange, each core needs to know the data format of all other cores that need to exchange data. (Bit width). Since the same NoC is used between the core and the core, there are higher requirements on the format of the data packet sent or received, that is, the sending core encodes the data format into the data format of the receiving core, or the receiving core is based on The sending core type re-decodes and encodes the data into the data format of the receiving core, resulting in a high complexity of the data packet routing algorithm and a heavy burden on each core.

In addition, because all cores share a NoC, and the amount of data exchanged between cores is different, when there is a pair of cores for data transmission, the other cores cannot use NoC for data transmission. You need to wait for the pair of cores to transmit data. Data transmission, this will cause data transmission delays, resulting in a decrease in the performance of the chip. For example, the data transmission bandwidth between the first core and the second core is very large. During the data transmission between the first core and the second core, the third core generates data that needs to be sent to the fourth core. This part of the data volume is relatively small, but the requirements for real-time performance are very high, and because all cores share a NoC, the third core needs to wait until the data transmission between the first core and the second core is completed before proceeding. Data transmission, such data with high real-time requirements is not transmitted in time, which affects the performance of the chip.

In order to solve the above-mentioned problems, the technical solution of the present invention is proposed.

The chip provided by an embodiment of the present application will be described in detail below. In the description of the present invention, it should be noted that the terms "first", "second", "third", and "fourth" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance. In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

Fig. 2 is a structural diagram of a chip according to an embodiment of the present invention.

As shown in FIG. 2, the chip includes: a plurality of interconnection structures, each interconnection structure is connected to a processing core group, all the processing cores connected by one interconnection structure are a processing core group; the processing core group Each of the processing cores in the processing core performs data transmission through the interconnection structure connected to the processing core group; wherein, a plurality of the interconnection structures are not directly connected.

In the embodiment shown in FIG. 2, the chip includes o interconnection structures, where the interconnection structure may be an inter-core interconnection structure Fabric, a network on chip (Network On Chip, Noc), a bus, or a switch. The interconnection structure of the present invention uses the on-chip network Noc as an example, but is not limited to this. Among them, o interconnected structures are NoC ₁ , NoC ₂ … NoC _o , and each NoC is connected to a processing core group. Each processing core in the processing core group performs data transmission through the NoC connected to the processing core group.

The chip includes a seed cores M, each core number N _M number, respectively. For example, K ₂ _C _N2 represents the N _{2th nucleus of the second type} of nucleus, and K _M _C _{NM represents the N Mth} nucleus of the Mth type of nucleus.

In the embodiment shown in FIG. 2, the first processing core group includes core K ₁ _C ₁ , core K ₁ _C ₂ … core K ₁ _C _N1 , core K ₂ _C ₁ and core K ₂ _C ₂ . The first network on chip NoC _{1 is} connected to the first processing core group, that is, each processing core of the first processing core group is connected to NoC ₁ . Data transmission between the cores of the first processing core group is achieved through the first network on chip NoC _1. For example, when the core K ₁ _C ₁ has data to be transmitted to the core K ₁ _C ₂ , the data is sent to the first on-chip network NoC ₁ , and the first on-chip network NoC ₁ transmits the data to the core K ₁ _C ₂ .

The second processing core group includes: core K ₁ _C ₁ , core K ₁ _C _N1 , core K ₂ _C ₂ , ... core K ₂ _C _N2 , core K _M _C ₁ and core K _M _C ₂ , this second processing core group Each of the processing cores is connected to the second NoC ₂ on-chip network. Data transmission between the cores of the second processing core group is achieved through the second network on chip NoC _2.

The o-th processing core group includes a core K ₁ _C _N1 , a core K ₂ _C ₂ , a core K _M _C ₂ , ... a core K _M _C _NM . Each core of the o-th processing core group is connected to the o-th on-chip network NoC _o . Data transmission is realized between the cores of the o-th processing core group through the o-th interconnect structure NoC _O.

The chip provided by the embodiment of the present invention is provided with a plurality of interconnection structures, and each interconnection structure is connected to a processing core group. Each core of the same processing core group realizes data transmission through the interconnection structure connected to the group. The data transmission between cores can be processed in parallel. On the one hand, when transmitting data between cores belonging to the same group, only the data format of the cores in the same group needs to be considered, and there is no need to consider other groups of the chip. The data format of the core reduces the complexity of the circuit in the chip, improves the data transmission efficiency between the core and the core, reduces the power consumption, and improves the performance of the chip; on the other hand, because the data transmission of different groups can be processed in parallel , The data transmission of different groups will not interfere with each other, thereby avoiding data congestion and improving the performance of the chip.

In one embodiment, data transmission can be performed between processing cores belonging to different processing core groups.

In a preferred embodiment, the plurality of interconnection structures includes a first interconnection structure and a second interconnection structure; the first interconnection structure is connected to a first processing core; and the first processing core is connected to the second interconnection structure.

Specifically, in this embodiment, the same processing core can be set in two different processing core groups at the same time. For example, in the embodiment shown in FIG. 2, the processing cores K ₁ _C ₁ are both set in the first processing core. In the group, it is also set in the second processing core group, that is, the processing core K ₁ _C ₁ is connected to both the first network on chip NoC ₁ and the second network on chip NoC ₂ .

In one embodiment, the amount of data transmitted between any two processing cores belonging to the same processing core group is greater than the amount of data transmitted between any two different groups of processing cores.

Specifically, in this embodiment, if there is a relatively large amount of data transmission between certain two cores, they will be allocated in the same group.

In one embodiment, the first interconnection structure is further connected to a second processing core; the second interconnection structure is connected to a third processing core; the second processing core is connected to the first processing core through the first processing core. Three processing cores realize data transmission.

Specifically, in this embodiment, if there is data to be transmitted between two cores that belong to two groups, generally speaking, the amount of data that needs to be transmitted between the two cores will be relatively small. There is only a small amount of data that needs to be exchanged between them, which can be exchanged through some bridged core transfers, that is, data transmission is realized through cores located in these two groups at the same time. For example, ₁ is connected to the NoC K ₂ _C ₁ to send data to a NoC K _M _C connection _21, since they are not a processing core group, then K ₂ _C ₁ by a both the NoC ₁ is connected also with NoC _{2 The} connected processing core performs transmission, such as K ₁ _C ₁ or K ₂ _C ₂ . I.e., K ₂ _C ₁ transmits data to the K ₁ _C ₁ through NoC _1, K ₁ _C ₁ transmits data to the K _M _C ₁ through NoC _2, in order to achieve data transmission.

For example, in the embodiment shown in FIG. 2, the processing cores K ₁ _C _{2 of the} first processing core group need to send data to the processing cores K _M _C _{2 of the} second processing core group, which can pass through the processing cores K ₁ _C ₁ , K ₁ _C _N1 or K ₂ _C ₂ implementation.

Specifically, the processing core K ₁ _C ₂ sends data to the processing core K ₁ _C ₁ through the first on-chip network NoC ₁ , and the processing core K ₁ _C ₁ sends the data to the processing core K _M _C through the second on-chip network NoC _{2 2} .

In one embodiment, the multiple interconnection structures include a third interconnection structure; all the processing cores connected by the third interconnection structure are not connected to other interconnection structures.

For example, in the embodiment shown in FIG. 2, the chip further includes a third network on chip, the third network on chip is connected to a third processing core group, and the third processing core group includes cores K ₁ _C ₃ and core K ₃ _C ₁ , these two cores are not connected to other interconnect structures.

In an embodiment of the present invention, the processing core connected to each interconnect structure in the chip is not connected to other interconnect structures. In this embodiment, the processing cores connected to each interconnection structure are not connected to other interconnection structures, that is, there is no data transmission between the two processing cores respectively belonging to the two processing core groups.

In an embodiment, each of the processing cores includes at least one transmission unit, and the bandwidth of the interconnect structure meets the bandwidth requirement of the transmission unit. For example, the bandwidth of the interconnect structure is equal to the bandwidth requirement of the transmission unit, so that the processing core can send data to the interconnect structure.

Among them, the bandwidth requirement of the transmission unit may be the bandwidth required by the transmission unit to send a certain amount of data within a certain period of time.

In one embodiment, the bandwidth of the interconnect structure meets the bandwidth requirements of each of the processing cores in the processing core group connected to the interconnect structure.

Wherein, the bandwidth requirement of the processing core may be the bandwidth required by the processing core to send a certain amount of data within a certain period of time.

Preferably, the bandwidth of the interconnect structure is greater than the bandwidth requirements of each of the processing cores in the processing core group connected to the interconnect structure. In this way, each interconnection structure can best match the structure of all the processing cores in the processing core group connected to the interconnection structure. On the one hand, it can save the area to the greatest extent, and on the other hand, it can make the chip have better performance.

In one embodiment, at least two processing core groups in the chip have different bandwidth requirements. For example, the bandwidth requirement of the first group is 1MBps, and the second group is 10MBps. In this way, the corresponding structure can be set based on the different requirements of the processing core groups. The Noc can save the area of Noc to the greatest extent.

FIG. 3 is a schematic diagram of a chip structure provided by an embodiment of the present invention.

As shown in Figure 3, the chip includes 6 cores. These 6 cores include 3 cores with different structures, namely, the first core K ₁ , the second core K ₂ and the third core K ₃ , each There are two types of nuclei.

Among them, the two cores in the first type of core K _{1 are: core K 1} _C ₁ and core K ₁ _C ₂ , and the two cores in the second type of core K _{2 are: core K 2} _C ₁ and core K ₂ _C _2. The two cores in the third type of core K _{2 are: core K 3} _C ₁ and core K ₃ _C ₂ .

The 6 cores in this chip are divided into three groups.

The first processing core group is composed of core K ₁ _C ₁ , core K ₁ _C ₂ , core K ₂ _C ₁ and K ₂ _C ₂ , and each core in the first processing core group is connected to the first interconnection structure NoC ₁ .

The second processing core group is composed of K ₁ _C ₁ , K ₂ _C ₂ , K ₃ _C ₁ , K ₃ _C ₂ , and each core in the second processing core group is connected to the second interconnection structure NoC ₂ .

The third processing core group is composed of K ₁ _C ₂ , K ₂ _C ₂ , and K ₃ _C ₂ , and each core in the third processing core group is connected to the third interconnection structure NoC ₃ .

In a preferred embodiment, each core in the chip includes at least one computing unit.

Among them, the calculation unit may be an execution unit (Execution Unit, EU) or a processing unit (Processing Unit, PU).

The chip includes multiple interconnected structures. Each interconnected structure is connected to a processing core group. The same group of processing cores are connected to the processing core group to achieve data transmission. The interconnected structure will be based on the corresponding group of cores. The required bandwidth, the data bit width used by the core, and the data packet and corresponding protocol dedicated to this group of cores are designed.

In an embodiment, at least two clock frequencies are set in the plurality of interconnect structures in the chip. Since multiple interconnect structures are provided in the chip, each interconnect structure is connected to a group of processing cores, and data transmission between the groups of processing cores can be processed in parallel, so multiple interconnect structures in the chip can be set with multiple different clock frequencies.

Optionally, multiple interconnect structures in the chip can also be set to the same clock frequency.

In one embodiment, at least two bit width values are set in the plurality of interconnect structures. Since multiple interconnection structures are provided in the chip, each interconnection structure is connected to a group of processing cores, and the data transmission between each group of processing cores can be processed in parallel, so multiple bit width values can be set in the interconnection structure.

Optionally, multiple interconnect structures in the chip may also be set to the same bit width value.

It should be noted that bandwidth = bit width * clock frequency. If a higher bandwidth is required for data transmission between processing cores of a certain processing core group, the bandwidth of the NoC can be determined according to the bandwidth requirements of the processing core group (for example, determine Appropriate clock frequency and bit width), so that the bandwidth of the NoC meets the bandwidth requirements of each processing core in the processing core group. For example, set a higher NoC bit width. In addition, since the data transmission between each processing core group is independent of each other, if other processing core groups do not require a higher bandwidth, you can set a suitable NoC bit width according to their needs, which can save the area of the chip, thereby Save power consumption.

Moreover, in the chip of the embodiment of the present invention, since one NoC is used for data transmission between a processing core group, different NoCs can be set with different clock frequencies and different bit widths, and corresponding bits can be set according to the needs of each group of data transmission. Compared with all cores in a chip using an interconnect structure for transmission, it reduces power consumption, improves the performance of the entire chip, increases the flexibility of chip design, and saves area.

The above technical solution of the present invention has the following beneficial technical effects:

(1) The chip provided by the embodiment of the present invention is provided with a plurality of interconnection structures, and data transmission between the same processing core group is realized through the interconnection structure connected to the processing core group, so that the cores of different processing core groups can communicate with each other. Data transmission can be processed in parallel. On the one hand, it greatly increases the total data bandwidth, improves the efficiency of data transmission between cores, reduces power consumption, and improves the performance of the chip; on the other hand, due to the data transmission of different groups It can be processed in parallel, and the data transmission of different groups will not interfere with each other, thereby avoiding data congestion and improving the performance of the chip.

(2) In the chip provided by the embodiment of the present invention, when data is transmitted between cores belonging to the same group, only the data format of the cores in the same group needs to be considered, and there is no need to consider the data format of other cores in other groups of the chip. , Reduce the complexity of the circuit in the chip.

An embodiment of the present invention also provides a card board, which includes one or more chips provided in the foregoing embodiments.

An embodiment of the present invention also provides an electronic device, including one or more card boards provided in the foregoing embodiments.

FIG. 4 is a schematic flowchart of a method for transmitting data between cores according to an embodiment of the present invention.

As shown in Figure 4, the method includes steps S101 to S102:

Step S101, each of the processing cores belonging to the same processing core group realizes data transmission through the interconnection structure connected to the processing core group.

In step S102, the two processing cores respectively belonging to two different processing core groups implement data transmission through at least two interconnection structures.

In one embodiment, the step of implementing data transmission for the two processing cores respectively belonging to two different processing core groups through at least two interconnection structures includes:

The two processing cores respectively belonging to two different processing core groups realize data transmission through the two interconnection structures via one processing core belonging to the two different processing core groups at the same time.

For example, in the embodiment shown in FIG. 3, NoC ₁ K ₂ _C ₁ of the data to be transmitted in the NoC ₂ K ₃ _C _1, since they are not in a group, then K ₂ _C ₁ either by a In NoC ₁ and in NoC ₂ , the core transmits, for example, K ₁ _C ₁ or K ₂ _C ₂ . I.e., K ₂ _C ₁ transmits data to the K ₁ _C ₁ through NoC _1, K ₁ _C ₁ transmits the data through the NoC ₂ to K ₃ _C _1, in order to achieve data transmission.

It should be noted that two processing cores belonging to two different processing core groups can also realize data transmission through multiple interconnection structures.

For example, in the embodiment shown in FIG. 3, the processing core K ₂ _C ₁ can send data to the processing core K ₃ _C ₁ through NoC ₁ , NoC ₂ and NoC ₃ . Specifically, the processing core K ₂ _C ₁ sends data to the processing core K ₁ _C ₂ through NoC ₁ , the processing core K ₁ _C ₂ sends the data to the processing core K ₃ _C ₂ through NoC ₃ , and the processing core K ₃ _C ₂ will The data is sent to the processing core K ₃ _C _{1 through NoC 2} .

In the inter-core data transmission method provided by the embodiment of the present invention, each processing core belonging to the same processing core group realizes data transmission through an interconnect structure connected to the processing core group, so that data transmission between different groups of cores can be processed in parallel. , Which greatly improves the total data bandwidth, improves the efficiency of data transmission between cores, reduces power consumption, and improves the performance of the chip; on the other hand, because the data transmission of different groups can be processed in parallel, the data of different groups can be processed in parallel. The transmission will not interfere with each other, thereby avoiding data congestion and improving the performance of the chip.

According to an embodiment of the present invention, a computer storage medium is provided, and a computer program is stored on the computer storage medium. When the program is executed by a processor, the steps of the inter-core data transmission method provided in the foregoing embodiment are implemented.

According to an embodiment of the present invention, there is provided an electronic device including a memory, a processor, and a computer program stored on the memory and running on the processor, and the processor implements The steps of the inter-core data transmission method provided in the foregoing implementation manners.

According to an embodiment of the present invention, there is provided a computer program product, which includes computer instructions, and when the computer instructions are executed by a computing device, the computing device can execute the steps of the inter-core data transmission method provided in the above embodiments .

The flowcharts and block diagrams in the drawings of the present disclosure illustrate the possible implementation architecture, functions, and operations of the system, method, and computer program product according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagram may represent a module, program segment, or part of code, and the module, program segment, or part of code contains one or more for realizing the specified logical function Executable instructions. It should also be noted that, in some alternative implementations, the functions marked in the block may also occur in a different order from the order marked in the drawings. For example, two blocks shown in succession can actually be executed substantially in parallel, or they can sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and/or flowchart, and the combination of the blocks in the block diagram and/or flowchart, can be implemented by a dedicated hardware-based system that performs the specified functions or operations Or it can be realized by a combination of dedicated hardware and computer instructions.

The units involved in the embodiments described in the present disclosure can be implemented in software or hardware. Among them, the name of the unit does not constitute a limitation on the unit itself under certain circumstances.

The functions described above in this document may be performed at least in part by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that can be used include: Field Programmable Gate Array (FPGA), Application Specific Integrated Circuit (ASIC), Application Specific Standard Product (ASSP), System on Chip (SOC), Complex Programmable Logical device (CPLD) and so on.

In the context of the present disclosure, a machine-readable medium may be a tangible medium, which may contain or store a program for use by the instruction execution system, apparatus, or device or in combination with the instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. The machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or device, or any suitable combination of the foregoing. More specific examples of machine-readable storage media would include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination of the foregoing.

It should be understood that the above-mentioned specific embodiments of the present invention are only used to exemplarily illustrate or explain the principle of the present invention, and do not constitute a limitation to the present invention. Therefore, any modifications, equivalent substitutions, improvements, etc. made without departing from the spirit and scope of the present invention should be included in the protection scope of the present invention. In addition, the appended claims of the present invention are intended to cover all changes and modifications that fall within the scope and boundary of the appended claims, or equivalent forms of such scope and boundary.

The present invention has been described above with reference to the embodiments of the present invention. However, these examples are for illustrative purposes only, and are not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims and their equivalents. Without departing from the scope of the present invention, those skilled in the art can make many substitutions and modifications, and these substitutions and modifications should fall within the scope of the present invention.

Obviously, the above-mentioned embodiments are merely examples for clear description, and are not intended to limit the implementation manners. For those of ordinary skill in the art, other changes or modifications in different forms can be made on the basis of the above description. It is unnecessary and impossible to list all the implementation methods here. The obvious changes or changes derived from this are still within the protection scope created by the present invention.

Claims (16)

1. A chip, characterized by comprising: a plurality of interconnection structures, each interconnection structure is connected to at least two processing cores, and all the processing cores connected by one interconnection structure are a processing core group;

   Each of the processing cores belonging to the same processing core group performs data transmission through the interconnection structure connected to the processing core group;

   Wherein, the multiple interconnection structures are not directly connected.
2. 8. The chip of claim 1, wherein data transmission can be performed between processing cores belonging to different processing core groups.
3. The chip of claim 2, wherein:

   The amount of data transmitted between any two processing cores belonging to one processing core group is greater than the amount of data transmitted between any two different processing core groups.
4. The chip according to any one of claims 1-3, wherein:

   The plurality of interconnection structures includes a first interconnection structure and a second interconnection structure;

   The first interconnection structure is connected with a first processing core;

   The first processing core is connected to the second interconnect structure.
5. The chip of claim 4, wherein:

   The first interconnect structure is also connected with a second processing core; the second interconnect structure is connected with a third processing core;

   The second processing core implements data transmission through the first processing core and the third processing core.
6. The chip according to claim 4 or 5, wherein:

   The interconnection structure includes a third interconnection structure;

   All the processing cores connected by the third interconnect structure are not connected with other interconnect structures.
7. The chip according to any one of claims 1 to 6, wherein the bandwidth of the interconnect structure meets the bandwidth requirements of each of the processing cores in the processing core group connected to the interconnect structure.
8. 8. The chip according to claim 7, wherein each of the processing cores includes at least one transmission unit, and the bandwidth of the interconnection structure meets the bandwidth requirements of the transmission units of each processing core connected to the interconnection structure .
9. 8. The chip according to any one of claims 1-8, wherein the plurality of interconnect structures are provided with at least two clock frequencies; and/or

   At least two bit width values are set for the plurality of interconnect structures.
10. A card board, characterized by comprising one or more chips according to any one of claims 1-9.
11. An electronic device, characterized by comprising one or more card boards according to claim 10.
12. An inter-core data transmission method, used in the chip according to any one of claims 1-9, characterized in that it comprises:

    Each of the processing cores belonging to the same processing core group realizes data transmission through an interconnect structure connected to the processing core group;

    The two processing cores respectively belonging to two different processing core groups realize data transmission through at least two interconnection structures.
13. The method according to claim 12, wherein the two processing cores respectively belonging to two different processing core groups realize data transmission through at least two interconnection structures, comprising:

    The two processing cores respectively belonging to two different processing core groups realize data transmission through the two interconnection structures via one processing core belonging to the two different processing core groups at the same time.
14. A computer storage medium, characterized in that a computer program is stored on the computer storage medium, and when the program is executed by a processor, the steps of the inter-core data transmission method according to claim 12 or 13 are realized.
15. An electronic device, comprising a memory, a processor, and a computer program stored on the memory and capable of running on the processor. The processor executes the program as claimed in claim 12 or 13. The steps of the inter-core data transmission method.
16. A computer program product, characterized by comprising computer instructions, when the computer instructions are executed by a computing device, the computing device can execute the steps of the inter-core data transmission method according to claim 12 or 13.

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