WO2021108965A1

WO2021108965A1 - Encapsulation substrate integrated with inductor, and electronic device

Info

Publication number: WO2021108965A1
Application number: PCT/CN2019/122479
Authority: WO
Inventors: 刘宁; 刘铁军; 路鹏; 朱靖华
Original assignee: 华为技术有限公司
Priority date: 2019-12-02
Filing date: 2019-12-02
Publication date: 2021-06-10
Also published as: CN114730740A

Abstract

Provided are an encapsulation substrate integrated with an inductor, and an electronic device, wherein same relate to the technical field of electronics and are used to reduce the number of chip power pins. The encapsulation substrate comprises a core layer and an inductor. The core layer has a cavity. The cavity passes through the upper surface and the lower surface of the core layer. The inductor is located in the cavity. The inductor comprises a magnetic core and a coil. The magnetic core is filled in the cavity. In addition, the coil comprises at least one conductor segment. The at least one conductor segment comprises a first metal trace, and a first via hole and a second via hole which pass through the magnetic core. The first metal trace is arranged on the lower surface of the core layer. A first end of the first metal trace is coupled to the end of the first via hole located on the lower surface of the core layer. A second end of the first metal trace is coupled to the end of the second via hole located on the lower surface of the core layer.

Description

Package substrate and electronic equipment integrated with inductance

Technical field

This application relates to the field of electronic technology, and in particular to a package substrate and electronic equipment integrated with an inductor.

Background technique

The electronic product is provided with a power conversion module (voltage regulator module, VRM) for supplying power to the chip in the electronic device. VRM includes a direct current (DC) to direct current circuit, that is, a DC-DC step-down circuit. The DC-DC step-down circuit includes a switch tube and an inductor. By controlling the on and off states of the switch tube, the inductor can be charged and discharged, so that the voltage provided by the battery can be converted into the power supply voltage of the chip.

In the above-mentioned DC-DC step-down circuit, when the switching frequency of the switch tube is low, for example, tens of KHz to hundreds of KHz, the inductor needs to have a very large inductance, such as tens of μH to hundreds of nH, to reduce The ripple of the output current of the small step-down circuit. In this way, as the power consumption of the above-mentioned chip is getting higher and higher, the current required by the chip is gradually increasing, for example, it can be as high as 600-1000A. Due to the limited flow capacity of the power supply pins of the chip, the number of power supply pins required by the chip will increase sharply, resulting in a further increase in the area of the chip, which is not conducive to the miniaturization of electronic products.

Summary of the invention

The embodiments of the present application provide a package substrate and electronic device integrated with an inductor, which are used to reduce the number of chip power pins.

In order to achieve the above objectives, this application adopts the following technical solutions:

The first aspect of the present application provides a package substrate integrated with inductors. The package substrate includes a core layer and an inductor. Among them, the core layer has a cavity. The cavity penetrates the upper surface and the lower surface of the core layer. The inductor is located in the cavity. The inductor includes a magnetic core and a coil. The magnetic core is filled in the cavity. In addition, the coil includes at least one wire segment. The at least one wire segment includes a first metal trace, and a first via hole and a second via hole penetrating the magnetic core. The first metal trace is arranged on the lower surface of the core layer. The first end of the first metal trace is coupled to an end of the first through hole located on the lower surface of the core layer. The second end of the first metal trace is coupled to an end of the second through hole located on the lower surface of the core layer.

In this way, on the one hand, through the cavity formed in the core layer of the package substrate. The magnetic material constituting the magnetic core of the inductor is filled in the cavity. In addition, a first through hole and a second through hole are provided in the magnetic core. The coil in the inductor includes a first via hole, a second via hole, and a first metal wire for coupling the first via hole and the second via hole. So as to achieve the purpose of integrating the inductor into the package substrate. In this case, when the fully integrated voltage regulation technology is used to integrate electronic components in the voltage conversion circuit other than inductors, such as switch tubes, diodes, etc., on the chip, the higher power supply voltage provided by the power supply can be directly transmitted to the chip. The supply voltage is generated by stepping down the power supply voltage through the above-mentioned voltage conversion circuit. Therefore, the voltage received by the chip is relatively large and the current is relatively small. When the pin flow capacity of the chip is constant, the number of pins used for coupling with the package substrate in the chip can be reduced.

On the other hand, when the inductor is integrated into the package substrate, the inductor can be placed close to the power supply pin of the chip. Therefore, the power supply path through which the battery provides the power supply voltage to the chip can be reduced, the influence of parasitic resistance on the power supply path can be reduced, the current loss on the above-mentioned power supply path can be reduced, and the power supply efficiency can be improved.

Optionally, the coil includes a first wire segment, a second wire segment, and a second metal trace. Any one of the first wire segment and the second wire segment is the same as described above, including the first via hole and the second via hole penetrating the magnetic core, and is used to connect the first via hole and the second via hole. The first metal trace for coupling. In addition, the second metal trace is arranged on the upper surface of the core layer. The first end of the second metal trace is coupled to an end of the second via hole of the first wire segment located on the upper surface of the core layer. The second end of the second metal trace is coupled to an end of the first via hole of the second wire segment located on the upper surface of the core layer. In this way, the number of coil turns can be increased by increasing the number of wire segments in the coil. Thereby increasing the inductance of the inductor.

Optionally, the magnetic core has at least one side surface perpendicular to the upper surface or the lower surface of the core layer. The magnetic core includes a recessed portion recessed toward the inside of the magnetic core provided on at least one side surface of the magnetic core. The recess is located between two adjacent via holes. Because, relative to the magnetic field around each via hole, the magnetic field between two adjacent via holes is relatively small. Therefore, the above-mentioned recess can be made on the side surface of the magnetic core and between any two adjacent through holes, so as to reduce the magnetic material constituting the magnetic core and achieve the purpose of reducing the manufacturing cost.

Optionally, the magnetic core has a first side surface and a second side surface. The first side surface is parallel to a plane where the axes of the first and second conductive holes of the first wire segment are located. The second side surface is parallel to the plane where the first via hole of the first wire segment and the first via hole of the second wire segment are located. A first recessed portion is provided on the first side surface, and a second recessed portion is provided on the second side surface. The area of the cross section of the first depressed portion is smaller than the area of the cross section of the second depressed portion. The cross section is parallel to the upper or lower surface of the core layer. In this case, since the magnetic field strength between the first via hole of the first wire segment and the first via hole of the second wire segment is smaller than that between the first via hole of the first wire segment and the first wire segment The intensity of the magnetic field between the second via holes, therefore, a second recess with a larger cross-section can be provided at a position where the intensity of the magnetic field is relatively small. At locations where the magnetic field strength is greater, a first recess with a smaller cross-section may be provided. Therefore, on the basis of ensuring that the inductance of the inductor will not be greatly reduced, the magnetic material at the positions of the first recessed portion and the second recessed portion can be removed as required.

Optionally, the vertical projection of the first metal trace on the core layer is located within the range where the magnetic core is located. In this way, the length of the first metal trace is reduced to achieve the purpose of reducing the DC resistance of the inductor.

Optionally, the vertical projection of the second metal trace on the core layer is located within the range where the magnetic core is located. In this way, the length of the second metal trace is reduced to achieve the purpose of reducing the DC resistance of the inductor.

Optionally, the material constituting the magnetic core includes a soft magnetic composite material. The soft magnetic composite material includes magnetic particles and a resin material. The material constituting the magnetic particles includes at least one of iron-silicon-chromium alloy, carbonyl iron, or iron-based amorphous material.

Optionally, the inductor further includes a first terminal electrode and a second terminal electrode. One end of the first via hole located on the upper surface of the core layer is coupled to the first terminal electrode. One end of the second via hole located on the upper surface of the core layer is coupled to the second terminal electrode. The first terminal electrode of the above-mentioned inductor can be coupled with other electronic components in the voltage conversion circuit, such as a switch tube and a diode. The second terminal electrode of the inductor can be used as the output terminal of the voltage conversion circuit. As a result, other electronic components in the voltage conversion circuit, such as switch tubes and diodes, can be coupled with the inductor integrated in the package substrate.

Optionally, the inductor further includes a first terminal electrode and a second terminal electrode. One end of the first via hole of the first wire segment located on the upper surface of the core layer is coupled to the first terminal electrode. One end of the second via hole of the second wire segment located on the upper surface of the core layer is coupled to the second terminal electrode. When the number of turns of the coil in the inductor is increased, that is, when the coil includes a first wire segment and a second wire segment, the end of the first via hole of the first wire segment located on the upper surface of the core layer is connected to the first terminal electrode. The coupling enables the first end of the coil to be coupled to other electronic components in the voltage conversion circuit, such as switch tubes and diodes, through the first end electrode and the first end electrode of the inductor. In addition, by coupling one end of the second via hole of the second wire segment located on the upper surface of the core layer to the second terminal electrode, the other end of the coil can be used as the output terminal of the voltage conversion circuit through the second terminal electrode.

Optionally, the packaging substrate further includes a first build-up layer. The first build-up layer is located on the upper surface of the core layer; the first build-up layer includes a first interconnection structure, a second interconnection structure, a first pad and a second pad. The end of the first interconnect structure close to the core layer is coupled to the end of the first via hole located on the upper surface of the core layer, and the end of the first interconnect structure away from the core layer is coupled to the first pad. The disc serves as the first terminal electrode of the inductor. The end of the second interconnect structure close to the core layer is coupled to the end of the second via hole located on the upper surface of the core layer, and the end of the second interconnect structure far away from the core layer is coupled to the second pad. The disk serves as the second terminal electrode of the inductor. In this way, the first terminal electrode of the inductor can be coupled to one end of the coil through the first interconnect structure in the first build-up layer, and the second end of the inductor can be connected through the second interconnect structure in the first build-up layer. The electrode is coupled to the other end of the coil.

Optionally, the packaging substrate further includes a second build-up layer and a third interconnection structure. The second build-up layer is located on the lower surface of the core layer. The second build-up layer includes a third pad on the side away from the core layer. Wherein, the third interconnection structure penetrates the core layer, the first build-up layer and the second build-up layer. The first build-up layer further includes a fourth pad on a side away from the core layer, the first end of the third interconnect structure is coupled to the third pad, and the second end is coupled to the fourth pad. The third pad serves as a power input terminal of the package substrate, and the fourth pad serves as a power output terminal of the package substrate. In this way, the power supply voltage provided by the battery can be transmitted to the chip through the fourth pad, the third interconnection structure, and the third pad.

In a second aspect of the present application, there is provided an electronic device, including a chip, and at least one of the above-mentioned package substrates integrated with inductors. The chip is on the package substrate. The chip includes a voltage regulation module and a processing module. The package substrate has power output terminals. Among them, the package substrate includes an inductor. The power output terminal of the package substrate is coupled with the voltage adjustment module, the voltage adjustment module is also coupled with the first terminal electrode of the inductor, and the second terminal electrode of the inductor is also coupled with the processing module. The voltage regulation module and the inductor form a voltage conversion circuit, which is used to provide a supply voltage to the processing module. The above-mentioned electronic device has the same technical effect as the packaging substrate provided in the foregoing embodiment, and will not be repeated here.

Description of the drawings

FIG. 1 is a schematic structural diagram of an electronic device provided by an embodiment of this application;

2 is a schematic diagram of the structure of a package substrate and a chip coupled to the PCB shown in FIG. 1;

3 is a schematic structural diagram of a voltage conversion circuit provided by an embodiment of the application;

FIG. 4a is a schematic structural diagram of coupling a package substrate and a chip according to an embodiment of the application;

4b is a schematic diagram of the connection structure of some components in the electronic equipment provided by the embodiments of the application;

FIG. 5 is a schematic structural diagram of a package substrate provided by an embodiment of the application;

FIG. 6a is a schematic diagram of a part of the structure of a core layer in a package substrate provided by an embodiment of the application; FIG.

FIG. 6b is a schematic diagram of the structure of the integrated inductor part in the cavity of the core layer shown in FIG. 6a;

FIG. 7a is a schematic structural diagram of an inductor provided by an embodiment of this application;

FIG. 7b is a schematic diagram of the structure of integrating the inductor shown in FIG. 7a with the package substrate;

Figure 7c is a cross-sectional view taken along the dashed line O-O in Figure 7a;

FIG. 8 is a schematic diagram of another structure of coupling a package substrate and a chip according to an embodiment of the application;

FIG. 9a is a schematic structural diagram of another inductor provided by an embodiment of the application;

FIG. 9b is a schematic structural diagram of another inductor provided by an embodiment of the application;

Figure 10 is a plan view taken along the direction C shown in Figure 9a;

FIG. 11 is an electric field distribution diagram of an inductor provided by an embodiment of the application;

FIG. 12 is a schematic structural diagram of an inductive magnetic core provided by an embodiment of the application;

FIG. 13 is a schematic structural diagram of another inductive magnetic core provided by an embodiment of the application;

FIG. 14 is a schematic structural diagram of another inductor provided by an embodiment of the application.

Reference signs:

01-Electronic equipment; 10-display module; 11-middle frame; 12-shell; 100-package substrate; 101-chip; 111-pin; 102-voltage conversion circuit; 20-inductance; 120-voltage adjustment module 121-processing module; 13-power input terminal; 14-power output terminal; 15-first terminal electrode; 16-second terminal electrode; 30-core layer; 31-first build-up layer; 32-second build-up layer 301-metal trace; 302-insulating layer; 303-cavity; 230-magnetic core; 231-coil; 41-first metal trace; 51-first via hole; 52-second via hole; 40-conductive layer; 311-first interconnection structure; 312-second interconnection structure; 313-first pad; 314-second pad; 315-third pad; 316-fourth pad; 317 -The third interconnection structure; 300a- the first wire segment; 300b- the second wire segment; 42- the second metal trace; 400- the recessed portion; 400a- the first recessed portion; 400b- the second recessed portion; 300c- The third wire segment; 43-the third metal trace.

Detailed ways

The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments.

Hereinafter, the terms "first", "second", etc. are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined with "first", "second", etc. may explicitly or implicitly include one or more of these features.

In addition, in this application, the azimuthal terms such as "upper" and "lower" are defined relative to the schematic placement of the components in the drawings. It should be understood that these directional terms are relative concepts, and they are used for relative For the description and clarification, it can be changed correspondingly according to the changes in the orientation of the components in the drawings.

In this application, unless expressly stipulated and limited otherwise, the term "connected" should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or a whole; it can be a direct connection, or Can be indirectly connected through an intermediary. In addition, the term "coupling" can be a way of electrical connection for signal transmission, and "coupling" can be a direct electrical connection or an indirect electrical connection through an intermediate medium.

The embodiments of the present application provide an electronic device. The electronic device includes, for example, a mobile phone, a tablet computer, a vehicle-mounted computer, and a smart wearable product. The embodiments of the present application do not impose special restrictions on the specific form of the above-mentioned electronic device. For the convenience of description, the following description takes the electronic device as a mobile phone as an example. As shown in FIG. 1, the electronic device 01 includes a display module 10, a middle frame 11 and a casing 12.

The display module 10 is used for displaying images. In some embodiments of the present application, the display module 10 includes a liquid crystal display (LCD) module and a backlight unit (BLU). Alternatively, in other embodiments of the present application, the display module 10 may be an organic light emitting diode (OLED) display screen.

The middle frame 11 is located between the display module 10 and the casing 12, and the side of the middle frame 11 facing the display module 10 is used to carry the display module 10. In addition, the aforementioned electronic device 01 also includes a printed circuit board (PCB). The side surface of the middle frame 11 facing the housing 12 is used to carry electronic devices such as PCB, camera, and battery. Among them, the camera and battery are not shown in the figure. The housing 12 is connected with the middle frame 11 to form a accommodating cavity for accommodating the above-mentioned PCB, camera, battery and other electronic devices. Therefore, it is possible to prevent external water vapor and dust from intruding into the accommodating cavity and affecting the performance of the above-mentioned electronic device.

In addition, the above-mentioned electronic device 01 further includes a packaging substrate 100 and a chip 101 as shown in FIG. 2. The chip 101 is flip-chip mounted on the package substrate 100 through a plurality of pins 111, such as micro bumps or Cu-pillars. The bottom of the package substrate 100 may be coupled to the aforementioned PCB through a ball grid array (BGA). In this way, the chip 101 can realize signal transmission through the packaging substrate 100 and the PCB.

It should be noted that the above is an example of flip-chip mounting the chip 101 above the packaging substrate 100 to illustrate the manner in which the chip 101 and the packaging substrate 100 are coupled. In other embodiments of the present application, the aforementioned chip 101 may also be coupled to the package substrate 100 through a wire bonding process.

In some embodiments of the present application, the aforementioned chip 101 may be a system-on-chip (SoC), a central processing unit (CPU), a graphics processing unit (GPU), or a power supply. Management chip (power management integrated circuits, PMIC), etc.

In order to supply power to the aforementioned chip 101, the electronic device 01 may include a voltage conversion circuit 102 as shown in FIG. 3. The voltage conversion circuit 102 includes an inductor 20, a switch Q, a diode D, and a capacitor Co. The inductor 20 has the functions of energy storage and filtering. The switch Q can be a transistor.

The first pole of the switch Q, such as the source (source, s), is coupled to the input terminal Ui of the voltage conversion circuit 102, and the input terminal Ui of the voltage conversion circuit 102 may be coupled to a power source, such as the positive electrode of a battery, Used to receive power, such as a power supply voltage (for example, 1.8V) provided by a battery. The second electrode of the switch Q, such as the drain (drain, d), is coupled to the first end of the inductor 20 (ie, the first end electrode 15 as shown in FIG. 4a). The second terminal of the inductor 20 (ie, the second terminal electrode 16 as shown in FIG. 4a) is coupled to the output terminal Uo of the voltage conversion circuit 102. The gate (gate, g) of the switching tube Q is used to receive a control signal, which can control the switching tube Q to be turned on and off.

In addition, the cathode (cathode, c) of the diode D is coupled to the first end of the inductor 20, and the anode (anode, a) is coupled to the power source, such as the negative electrode of the aforementioned battery. The first terminal of the capacitor Co is coupled to the output terminal Uo of the voltage conversion circuit 102, and the second terminal is coupled to the power source, such as the negative electrode of the aforementioned battery. When the switch Q is turned on, the inductor 20 is charged. When the switch Q is turned off, the inductor 20 discharges and continuously provides a stable power supply voltage to each chip through the capacitor Co.

It should be noted that FIG. 3 is an example in which the voltage conversion circuit 102 includes an inductor 20. In some other embodiments of the present application, the aforementioned voltage conversion circuit 102 may include at least two inductors 20.

Based on this, the switching frequency of the switch tube Q can be increased, for example, to about 100 MHz, so as to reduce the size of the inductor 20. At this time, only a few nH of the inductor 20 in the voltage conversion circuit 102 can output a current with a small ripple. In this way, the size of the inductor 20 can be reduced to less than 1 square millimeter.

In this case, as shown in FIG. 4a, the inductor 20 may be integrated in a packaging substrate 100, which is a packaging substrate integrated with the inductor 20. At this time, a fully integrated voltage regulator (FIVR) technology can be used, and a voltage regulator module 120 as shown in FIG. 4a is provided inside the chip 101. Wherein, the switch tube Q and the diode D in the voltage conversion circuit 102 can be integrated in the voltage adjustment module 120. In addition, the aforementioned chip 101 also includes a processing module 121 for realizing the main functions of the chip 101.

In this way, as shown in FIG. 4 a, the package substrate 100 has a power input terminal 13 and a power output terminal 14. The power input terminal 13 can be coupled to the PCB shown in FIG. 2 through the pin VDD formed by using solder balls, so that the power supply voltage (for example, 1.8V) provided by the battery can be received through the PCB. The above-mentioned power supply voltage (for example, 1.8V) is transmitted to the voltage regulation module 120 after passing through the power input terminal 13 of the package substrate 100 and the pin Vdd (which can be formed by using solder pads or copper pillars) coupled with the power output terminal 14 Inside.

Since the voltage adjustment module 120 is coupled to the first terminal electrode 15 of the inductor 20 through the pin Lx, the voltage conversion circuit 102 composed of the voltage adjustment module 120 and the inductor 20 can perform voltage conversion on the above-mentioned power supply voltage (for example, 1.8V) , For example, a step-down process to reduce the power supply voltage (for example, 1.8V) to the power supply voltage of the chip 101 (for example, 0.9V). In addition, since the second terminal electrode 16 of the inductor 20 is coupled to the processing module 121 in the chip 101 through the power pin Ot (the pins 111 of the chip 101 used to provide the power supply voltage to the chip 101) Therefore, when the processing module 121 receives the power supply voltage (for example, 0.9V) provided by the power pin Ot, the processing module 121 of the chip 101 can start to work and perform the main functions of the chip 101.

For example, in some embodiments of the present application, when the above-mentioned chip 101 is the above-mentioned SoC, CPU or CPU, as shown in FIG. 4b, when the processing module 121 of the chip 101 starts to work, the processing module 121 can pass data The data bus provides information to the remaining components in the electronic device 01, such as radio frequency module, memory, hard disk, camera and imaging processing module, input/output (I/O) interface, human-computer interaction device (human interactive device), etc. provide data.

For another example, in some other embodiments of the present application, when the above-mentioned chip 101 is the above-mentioned PMIC, as shown in FIG. 4b, when the processing module 121 of the chip 101 starts to work, the processing module 121 can pass through the power bus ( The power supply bus) or power supply network provides power supply voltage to the remaining components in the electronic device 01, such as the above-mentioned radio frequency transceiver, memory, hard disk, camera and image processor, input/output interface, and human-computer interaction equipment.

In this way, on the one hand, it can be known from the above that the voltage provided by the package substrate 100 to the voltage regulation module 120 of the chip 101 through the pin Vdd is the power supply voltage (for example, 1.8V). At this time, assuming that the current required by the chip 101 is 50A, and the flow capacity of each pin Vdd is 1A, for example, 50 pins Vdd are required between the chip 101 and the packaging substrate 100. Next, after the step-down effect of the voltage conversion circuit 102 (including the voltage adjustment module 120 and the inductor 20 integrated in the package substrate 100), a power supply voltage (for example, 0.9V) for providing to the processing module 121 of the chip 101 is generated .

Compared with the electronic device 01 provided in the embodiment of the present application, if the voltage conversion circuit is provided externally, the power supply voltage (for example, 1.8V) needs to be stepped down by the external voltage conversion circuit before the generated power supply voltage ( For example, 0.9V) is provided to the chip 101 through the pin Vdd. At this time, the voltage received by the chip 101 is reduced by half compared with the present application, so the current is doubled (for example, 100A), and the number of pins Vdd is also doubled (for example, 100). In the electronic device provided by the embodiment of the present application, the chip 101 has fewer pins Vdd (for example, 50), so the area of the chip 101 can be effectively reduced, which is beneficial to reducing the size of the electronic device 01.

On the other hand, as shown in FIG. 4a, when the inductor 20 is integrated in the package substrate 100, the inductor 20 can be disposed at a position close to the power pin Ot of the chip 101. Therefore, after the voltage conversion circuit 102 steps down the power supply voltage (for example, 1.8V) to the power supply voltage (for example, 0.9V), the second terminal electrode 16 of the inductor 20 can transmit the power supply voltage (for example, 0.9V) to the above-mentioned inductor. 20 is a very close power pin Ot, so as to supply power to the processing module 121 of the chip 101. In this way, the power supply path of the power supply voltage (for example, 0.9V) provided by the battery to the chip 101 can be reduced, thereby reducing the influence of the parasitic resistance on the power supply path, the current loss on the power supply path, and the power supply efficiency.

The structure of the package substrate 100 integrated with the inductor 20 will be described in detail below.

In some embodiments of the present application, the aforementioned packaging substrate 100 may include a core 30, a first build-up 31, and a second build-up 32 as shown in FIG. 5. Wherein, the material constituting the core layer 30 may be a resin material. The thickness of the core layer 30 is relatively large, so as to provide sufficient strength for the package substrate 100. Wherein, the above-mentioned core layer 30 has an upper surface A and a lower surface B. The upper surface A is close to the chip 101 shown in FIG. 2, and the lower surface B is close to the PCB shown in FIG. 2.

In addition, the first build-up layer 31 is located on the upper surface A of the core layer 30, and the second build-up layer 32 is located on the lower surface B of the core layer 30. Any one of the first build-up layer 31 and the second build-up layer 32 may include a multilayer metal wiring 301 and an insulating layer 302 located between two adjacent layers of the metal wiring 301. A plating through hole (PTH) can be provided on the insulating layer 302, so that metal traces 301 of different layers can be electrically connected to form an interconnection structure for signal transmission.

On this basis, as shown in FIG. 6 a, the core layer 30 is provided with a cavity 303 penetrating the upper surface A and the lower surface B of the core layer 30. As shown in FIG. 6b, the inductor 20 integrated in the package substrate 100 may be disposed in the cavity 303. The inductor 20 includes a magnetic core 230 and a coil 231. The magnetic core 230 is filled in the cavity 303 described above.

In some embodiments of the present application, the material constituting the magnetic core 230 may include a soft magnetic composite (SMC) material. The SMC material includes magnetic particles and resin materials. The SMC material can be formed by combining the above-mentioned magnetic particles and the resin material. Wherein, the above-mentioned magnetic particles may be iron-silicon-chromium alloy particles, carbonyl iron particles, or iron-based amorphous particles. The relative permeability of the aforementioned SMC material can usually be 5-10.

In addition, as shown in FIG. 7a, the aforementioned coil 231 includes at least one wire segment. The aforementioned at least one wire segment includes a first metal trace 41, and a first through hole 51 and a second through hole 52 penetrating the magnetic core 230. As shown in FIG. 7b, the first metal trace 41 is disposed on the lower surface B of the core layer 30.

The longitudinal cross-sectional view of the core layer 30 is shown in FIG. 7c (a cross-sectional view cut along the dashed line OO in FIG. 7a), and any one of the first via 51 and the second via 52 is vias. The upper surface A and the lower surface B of the core layer 30 may be penetrated. The walls of the first via 51 and the second via 52 are covered with a conductive layer 40 made of metal. In some embodiments of the present application, the first via 51 and the second via 52 covered with a conductive layer on the wall of the hole may also be filled with resin material.

In addition, the first end of the first metal trace 41 is coupled to the end of the first via 51 located on the lower surface B of the core layer 30. The second end of the first metal trace 41 is coupled to the end of the second via 52 located on the lower surface B of the core layer 30 to form the aforementioned coil 231.

To sum up, in order to integrate the inductor 20 into the package substrate 100, the core layer 30 of the package substrate 100 can be fabricated as shown in FIG. 6a, which penetrates the upper surface A and the lower surface B of the core layer 30. Cavity 303. Next, a magnetic core material is embedded in the cavity 303 to form a magnetic core 230 filled in the cavity 303 (as shown in FIG. 6b). Then, a hole through the magnetic core 230 is formed on the magnetic core 230 by a drilling process, and the inner wall of the hole is metalized by an electroplating process to form a conductive layer 40 as shown in FIG. 7c, thereby completing the first conductive layer. Preparation of the through hole 51 and the second via hole 52. Next, on the lower surface B of the core layer 30, a first metal wiring 41 is made to couple the first via 51 and the second via 52.

In this case, it can be seen from the above that in order to couple the inductor 20 with the voltage regulating module 120 in the chip 101 and the processing module 121 in the chip 101, the inductor 20 may include the first terminal electrode 15 as shown in FIG. 4a. And the second terminal electrode 16.

In order to form the first terminal electrode 15 and the second terminal electrode 16 of the above-mentioned inductor 20, as shown in FIG. 8, the first build-up layer 31 on the upper surface A of the core layer 30 includes a first interconnect structure 311 and a second interconnect structure 312. , The first pad 313 and the second pad 314. Either the first interconnection structure 311 or the second interconnection structure 312 is mainly composed of the PTH in the first build-up layer 31 and the multilayer metal wiring 301 (as shown in FIG. 5).

Based on this, the first interconnect structure 311 is close to an end of the core layer 30 and is coupled to an end of the first via 51 located on the upper surface A of the core layer 30. An end of the first interconnect structure 311 away from the core layer 30 is coupled to the first pad 313. In this case, the above-mentioned first pad 313 can be used as the first terminal electrode 15 of the inductor 20 (as shown in FIG. 4a). The first terminal electrode 15 can be coupled to the voltage adjustment module 120 in the chip 101 through the pin Lx. The voltage regulation module 120 integrates other elements (for example, the light emitting diode D shown in FIG. 3) in the voltage conversion circuit 102 except for the inductor 20.

In addition, the second interconnect structure 312 is close to an end of the core layer 30 and is coupled to an end of the second via 52 located on the upper surface A of the core layer 30. An end of the second interconnect structure 312 away from the core layer 30 is coupled to the second pad 314. In this case, the above-mentioned second pad 314 can be used as the second terminal electrode 16 of the inductor 20 (as shown in FIG. 4a). The second terminal electrode 16 can be coupled to the processing module 121 in the chip 101 through the power pin Ot. In this case, the above-mentioned second terminal electrode 16 may be the output terminal Uo of the voltage conversion circuit 102 in FIG. 3 or FIG. 6b.

On this basis, it can be seen from the above that the power supply voltage (for example, 1.8V) provided by the battery in the electronic device 01 can pass through the power input terminal 13 of the package substrate 100 (as shown in FIG. 4a) and be coupled to the power output terminal 14. After the connected pin Vdd, it is transmitted to the voltage regulation module 120.

In order to form the power input terminal 13 and the power output terminal 14 described above, as shown in FIG. 8, the second build-up layer 32 on the lower surface B of the core layer 30 includes a third pad 315 away from the core layer 30. The first build-up layer 31 on the upper surface A of the core layer 30 further includes a fourth pad 316 on the side away from the core layer 30. In addition, the above-mentioned package substrate 100 further includes a third interconnect structure 317 penetrating through the core layer 30, the first build-up layer 31 and the second build-up layer 32.

Based on this, the first end of the third interconnect structure 317 is coupled to the third pad 315, and the second end is coupled to the fourth pad 316. In this case, the third pad 315 can be used as the power input terminal 13 of the packaging substrate 100 (as shown in FIG. 4a), and the third pad 315 is coupled to the pin VDD under the packaging substrate 100. In addition, the fourth pad 316 can be used as the power output terminal 14 of the package substrate 100 (as shown in FIG. 4a). The fourth pad 316 is coupled to the pin Vdd under the chip 101.

In this way, the PCB can transmit the power supply voltage (for example, 1.8V) provided by the battery to the third interconnection structure 317 through the pin VDD and the power input terminal 13 under the packaging substrate 100. The third interconnect structure 317 transmits the above-mentioned power supply voltage (for example, 1.8V) to the voltage regulation module 120 in the chip 101 through the power output terminal 14 and the pin Vdd. Next, since the voltage regulation module 120 is coupled to the first terminal electrode 15 of the inductor 20 through the pin Lx, the voltage conversion circuit 102 composed of the voltage regulation module 120 and the inductor 20 can perform the above-mentioned power supply voltage (for example, 1.8V) A voltage conversion, such as a step-down process, is performed to reduce the power supply voltage (for example, 1.8V) to the power supply voltage of the chip 101 (for example, 0.9V). The second terminal electrode 16 of the inductor 20 is used as the output terminal Uo of the voltage conversion circuit 102 to provide a supply voltage to the processing module 121 in the chip 101, and the processing module 121 starts to work.

It can be seen from the above that, in order to integrate the inductor 20 into the packaging substrate 100, the cavity 303 formed in the core layer 30 of the packaging substrate 100 is filled with a magnetic core 230 made of a magnetic material, and the magnetic core 230 is provided with a first conduction Hole 51 and second via hole 52. The coil 231 in the inductor 20 includes a first via 51, a second via 52, and a first metal wire 41 for coupling the first via 51 and the second via 52. Therefore, most of the coil 231 is wrapped by the magnetic core 230. In this way, when the coil 231 in the inductor 20 passes current, the magnetic material around the first through hole 51 and the second through hole 52 can strengthen the magnetic material around the first through hole 51 and the second through hole 52. The magnetic field can increase the inductance of the inductor 20.

On this basis, in order to further increase the inductance of the aforementioned inductor 20, the number of turns of the coil 231 can be increased. For example, the above-mentioned coil 231 includes a first wire segment 300a and a second wire segment 300b as shown in FIG. 9a. The structure of any one of the first wire segment 300a and the second wire segment 300b is the same as that described above, and may include a first via 51, a second via 52, and for connecting the first via 51 and the second via 51. The first metal trace 41 coupled to the two vias 52.

Based on this, in order to reduce the DC resistance of the inductor, as shown in FIG. 10 (a view taken from the direction C in FIG. 9a), the first metal trace of any one of the first wire segment 300a and the second wire segment 300b is The vertical projection of the line 41 on the core layer 30 is located within the range where the magnetic core 230 is located. Thus, the length of the first metal wiring 41 can be reduced.

In addition, as shown in FIG. 9a, the aforementioned coil 231 further includes a second metal trace 42. After the structure of FIG. 9a is turned over, as shown in FIG. 9b, the second metal trace 42 is disposed on the upper surface A of the core layer 30. The first end of the second metal trace 42 is coupled to the end A of the second via 52 of the first wire segment 300 a located on the upper surface of the core layer 30. The second end of the second metal trace 42 is coupled to an end of the first through hole 51 of the second wire segment 300 b located on the upper surface A of the core layer 30.

In the same way, in order to reduce the DC resistance of the inductor, as shown in FIG. 10 (a view taken from the direction C in FIG. 9a), the vertical projection of the second metal trace 42 on the core layer 30 may be located where the magnetic core 230 is located. In the range. Therefore, the length of the second metal trace 42 can be reduced.

Based on this, in order to couple the inductor 20 shown in FIG. 9b with the voltage regulating module 120 in the chip 101 and the processing module 121 in the chip 101, the same principle can be obtained, the first in the first build-up layer 31 in FIG. The pad 313 may be coupled with the first via 51 of the first wire segment 300a shown in FIG. 9b. When the first pad 313 is used as the first terminal electrode 15 of the inductor 20, the electrical signal (such as voltage and current) output by the voltage regulation module 120 can be transmitted to the first conductor of the first wire segment 300a through the first terminal electrode 15. The through hole 51 faces one end of the upper surface A (not shown in FIG. 10) of the core layer 30. Thus, the inductor 20 can store energy and filter.

Based on this, when the current output by the voltage regulation module 120 flows into the first wire segment shown in FIG. 10 (in FIG. 10, "×" indicates that the current is perpendicular to the paper surface inward; "·" indicates that the current is perpendicular to the paper surface outward). When the first through hole 51 of 300a faces one end of the upper surface A (not shown in FIG. 10) of the core layer 30, the above-mentioned current flows from the first through hole 51 of the first wire segment 300a toward the lower surface of the core layer 30 One end of B flows out, passes through the first metal trace 41 of the first wire segment 300a (located on the lower surface B of the core layer 30), flows into the second via hole 52 of the first wire segment 300a, and faces the lower surface of the core layer 30 One end of B. Next, the second conductive hole 52 of the first wire segment 300a flows toward the end of the upper surface A of the core layer 30 to the second metal trace 42 located on the upper surface A of the core layer 30.

Next, the above-mentioned current flows into the first via hole 51 of the second wire segment 300 b through the second metal trace 42, and faces one end of the upper surface A of the core layer 30. Then, the first via 51 of the second wire segment 300b flows out toward one end of the lower surface B of the core layer 30, and flows into the first metal trace 41 of the second wire segment 300b (located on the lower surface B of the core layer 30) , The first metal trace 41 flowing from the second wire segment 300b to the second via hole 52 of the second wire segment 300b faces one end of the lower surface B of the core layer 30. Next, the above-mentioned current passes through the second via hole 52 of the second wire segment 300 b, flows to the second via hole 52 of the second wire segment 300 b, and faces one end of the upper surface A of the core layer 30.

In addition, the second pad 314 in the first build-up layer 31 in FIG. 8 may be coupled to the end of the second via hole 52 of the second wire segment 300b shown in FIG. 9b facing the upper surface A of the core layer 30. When the second pad 314 is used as the second terminal electrode 16 of the inductor 20, the electrical signal filtered by the inductor 20 can be transmitted to the processing module 121 in the chip 101 through the second terminal electrode 16 for processing The module 121 provides the above-mentioned power supply voltage.

To sum up, the coil 231 in the inductor 20, as shown in FIG. 9b, includes a first wire segment 300a and a second wire segment 300b that are coupled by the second metal trace 42. Therefore, by increasing the number of wire segments of the coil 231, the purpose of increasing the inductance of the inductor 20 can be achieved.

For example, when the electronic device 01 provided in the embodiment of the present application uses the inductor 20 as shown in FIG. 9b, when the voltage conversion circuit 102 of the electronic device 01, the switching frequency of the switch Q (as shown in FIG. 3) is When it reaches 100MHz, the inductance of the inductor 20 can reach about 7.58nH. Compared with the existing integrated and substrate air inductance (inductance 2.1nH), and the inductance (inductance 5.69nH) formed by embedding magnetic materials in the through holes of the substrate, the inductor 20 provided by the embodiment of the present application The inductance has been greatly improved.

Hereinafter, the structure of the magnetic core 230 in the above-mentioned inductor 20 will be described. In some embodiments of the present application, as shown in FIG. 10, the cross section of the above-mentioned magnetic core 230 may be rectangular or approximately rectangular. In this case, the cross section of the cavity 303 made in the core layer 30 may be rectangular or a regular shape approximately rectangular. In this way, the process of making the cavity 303 can be simplified. The cross section of the magnetic core 230 may be parallel to the upper surface A or the lower surface B of the core layer 30.

In addition, it can be seen from the above that current flows through the first via 51 and the second via 52 in any one of the first wire segment 300a and the second wire segment 300b. Therefore, as shown in FIG. 11 It is shown that the periphery of the first through hole 51 and the second through hole 52 in any of the above-mentioned wire segments has a relatively strong magnetic field. In Fig. 11, the area where the magnetic field is located is represented by a dashed circle ① located around any one of the above-mentioned via holes.

On this basis, the farther the area of the magnetic core 230 from any one of the above-mentioned via holes is, the smaller the magnetic field intensity in this area is. For example, in Fig. 11, the magnetic field strength in the range of the dashed circle ② is greater than the magnetic field strength in the range of the dashed circle ③.

In addition, as shown in FIG. 10, the directions of current transmission on the first via 51 of the first wire segment 300a and the second via 52 of the first wire segment 300a are opposite. According to the right-hand rule, the magnetic induction line around the first via hole 51 of the first wire segment 300a is counterclockwise, and the magnetic induction line around the second via hole 52 of the first wire segment 300a is clockwise. In this way, the portion between the first via 51 of the first wire segment 300a and the second via 52 of the first wire segment 300a is formed by the first via 51 and the second via 52. The directions of the generated magnetic induction lines are the same.

Therefore, the intensity of the magnetic field between the first via 51 of the first wire segment 300a and the second via 52 of the first wire segment 300a is smaller than that of the peripheral portion of the first via 51 or the second via 52. magnetic field. In the same way, the magnetic field strength between the first via 51 of the second wire segment 300b and the second via 52 of the second wire segment 300b is smaller than the peripheral portion of the first via 51 or the second via 52 Magnetic field.

In addition, since the first via 51 of the first wire segment 300a and the first via 51 of the second wire segment 300b have the same direction of current transmission. According to the right-hand rule, the magnetic induction lines around the first via 51 of the first wire segment 300a and the first via 51 of the second wire segment 300b are all counterclockwise. Therefore, the portion between the first via 51 of the first wire segment 300a and the first via 51 of the second wire segment 300b is defined by the first via 51 of the first wire segment 300a and the second wire segment. The direction of the magnetic induction line generated by the first via hole 51 of 300b is opposite.

Therefore, the intensity of the magnetic field between the first via 51 of the first wire segment 300a and the first via 51 of the second wire segment 300b is smaller than that of the first via 51 and the first wire of the first wire segment 300a. The intensity of the magnetic field between the second via holes 52 of the segment 300a. As shown in FIG. 11, the dashed circle ② and the dashed circle ③ are recessed inwardly at a position between the first via 51 of the first wire segment 300a and the first via 51 of the second wire segment 300b, which is larger than the circle ② and the dotted circle ③ are inwardly recessed at the position between the first via 51 of the first wire segment 300a and the second via 52 of the first wire segment 300a.

In the same way, the magnetic field strength between the second via 52 of the first wire segment 300a and the second via 52 of the second wire segment 300b is also smaller than that of the first via 51 and the second via 51 of the first wire segment 300a. The intensity of the magnetic field between the second via holes 52 of a wire segment 300a. As shown in FIG. 11, the dashed circle ② and the dashed circle ③ are recessed inwardly in the position between the second via 52 of the first wire segment 300a and the second via 52 of the second wire segment 300b, which is larger than the circle ② and the dotted circle ③ are inwardly recessed at the position between the first via 51 of the first wire segment 300a and the second via 52 of the first wire segment 300a.

Based on this, in order to save the material constituting the magnetic core 230, in some other embodiments of the present application, no magnetic material is provided at a position where the magnetic field intensity is less than the magnetic field around any one of the above-mentioned via holes. For example, the portion between the first via 51 of the first wire segment 300a and the second via 52 of the first wire segment 300a in FIG. 11. For another example, the portion between the first via 51 of the second wire segment 300b and the second via 52 of the second wire segment 300b. For another example, the portion between the first via 51 of the first wire segment 300a and the first via 51 of the second wire segment 300b. Or, for another example, the portion between the second through hole 52 of the first wire segment 300a and the second through hole 52 of the second wire segment 300b is no longer provided with magnetic material.

In this case, the structure of the magnetic core 230 is as shown in FIG. 12, and the magnetic core 230 has at least one side surface S perpendicular to the upper surface A or the lower surface B of the core layer 30. The above-mentioned magnetic core 230 includes a recess 400 that is provided on at least one side surface S of the magnetic core 230 and recessed toward the inside of the magnetic core 230. The recess 400 is located between any two adjacent via holes. In this way, by providing the above-mentioned recess 400 on the magnetic core 230, it is possible to reduce the material used to make the magnetic core 230 while ensuring that the inductance of the inductor 20 will not be greatly reduced, so as to achieve the purpose of reducing the manufacturing cost.

In other embodiments of the present application, as shown in FIG. 13, the magnetic core 230 may have a first side surface S1 and a second side surface S2. The first side surface S1 is parallel to the plane where the axes of the first through hole 51 and the second through hole 52 of the first wire segment 300a are located (that is, the plane where the connection line of E1-E2 is located). The second side surface S2 is parallel to the plane where the axes of the first via 51 of the first wire segment 300a and the first via 51 of the second wire segment 300b are located (that is, the plane where the connection line of E1-E3 is located).

Based on this, as shown in FIG. 13, the first side surface S1 is provided with a first recessed portion 400 a, and the second side surface S2 is provided with a second recessed portion 400 b. It can be seen from the above that, as shown in FIG. 11, the dashed circle ② and the dashed circle ③ are located inwardly between the first via 51 of the first wire segment 300a and the first via 51 of the second wire segment 300b. The degree of depression is greater than the degree of inward depression of the circle ② and the dotted circle ③ between the first via 51 of the first wire segment 300a and the second via 52 of the first wire segment 300a. Therefore, the cross-sectional area of the second recessed portion 400b provided on the second side surface S2 may be larger than the cross-sectional area of the first recessed portion 400a provided on the first side surface. Therefore, on the basis of ensuring that the inductance of the inductor 20 will not be greatly reduced, the magnetic material at the positions of the first recessed portion 400a and the second recessed portion 400b can be removed as needed.

Wherein, the cross-sections of the first recessed portion 400a and the second recessed portion 400b may be parallel to the upper surface A or the lower surface B of the core layer 30.

It should be noted that, in order to further increase the inductance of the above-mentioned inductor 20, the above is based on the example that the coil 231 may include the first wire segment 300a and the second wire segment 300b as shown in FIG. 9a, and the number of turns of the coil 231 is increased. For example. In other embodiments of the present application, as shown in FIG. 14, in order to increase the number of turns of the coil 231, the coil 231 may include a first wire segment 300a, a second wire segment 300b, and a third wire segment 300c. The structure of any one of the first wire segment 300a, the second wire segment 300b, and the third wire segment 300c is the same as that described above, and may include a first via 51, a second via 52, and for connecting the first via The first metal trace 41 is coupled to the through hole 51 and the second via hole 52.

In addition, the aforementioned coil 231 further includes a second metal wire 42 and a third metal wire 43. The arrangement of the second metal wiring 42 is the same as that described above, and will not be repeated here. The third metal wiring 43 and the second metal wiring 42 are both disposed on the upper surface A of the core layer 30. The first end of the third metal trace 43 is coupled to the end A of the second via hole 52 of the second wire segment 300 b located on the upper surface of the core layer 30. The second end of the third metal trace 43 is coupled to an end of the first through hole 51 of the third wire segment 300 c located on the upper surface A of the core layer 30. When the coil 231 includes more than three wire segments, the arrangement of each via hole and the metal wiring in the coil 231 is the same as described above, and will not be repeated here.

The above are only specific implementations of this application, but the protection scope of this application is not limited to this. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in this application. Should be covered within the scope of protection of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims

A package substrate integrated with an inductor, which is characterized in that it comprises:

The core layer has a cavity; the cavity penetrates the upper surface and the lower surface of the core layer;

The inductor is located in the cavity; the inductor includes a magnetic core and a coil; the magnetic core is filled in the cavity;

Wherein, the coil includes at least one wire segment; the at least one wire segment includes a first metal trace, and a first via hole and a second via hole penetrating the magnetic core;

The first metal trace is disposed on the lower surface of the core layer; the first end of the first metal trace is coupled to the end of the first via hole located on the lower surface of the core layer; The second end of the first metal trace is coupled to an end of the second through hole located on the lower surface of the core layer.
The package substrate integrated with inductors according to claim 1, wherein the coil includes a first wire segment, a second wire segment, and a second metal trace;

The second metal trace is disposed on the upper surface of the core layer; the first end of the second metal trace and the second via hole of the first wire segment are located at one end of the upper surface of the core layer Phase coupling; the second end of the second metal trace is coupled to one end of the first via hole of the second wire segment located on the upper surface of the core layer.
The package substrate integrated with inductors according to claim 1 or 2, wherein the magnetic core has at least one side surface perpendicular to the upper surface or the lower surface of the core layer; the magnetic core is included in the At least one side surface of the magnetic core is provided with a recessed portion recessed toward the inside of the magnetic core; the recessed portion is located between any two adjacent conductive holes.
The package substrate integrated with inductors according to claim 3, characterized in that:

The magnetic core has a first side surface and a second side surface; the first side surface is parallel to the plane on which the axes of the first conductive hole and the second conductive hole of the first wire segment are located; the second side surface is parallel to the The planes on which the first via hole of the first wire segment and the first via hole of the second wire segment are located are parallel;

The first side surface is provided with a first recessed portion, and the second side surface is provided with a second recessed portion; the cross-sectional area of the first recessed portion is smaller than the cross-sectional area of the second recessed portion; The cross section is parallel to the upper surface or the lower surface of the core layer.
The package substrate integrated with the inductor according to any one of claims 1 to 4, wherein the vertical projection of the first metal trace on the core layer is located within a range where the magnetic core is located.
The package substrate integrated with inductors according to claim 2, wherein the vertical projection of the second metal trace on the core layer is located within the range where the magnetic core is located.
The package substrate integrated with inductance according to any one of claims 1 to 6, wherein the material constituting the magnetic core includes a soft magnetic composite material; the soft magnetic composite material includes magnetic particles and a resin material; The material of the magnetic particles includes at least one of iron-silicon-chromium alloy, carbonyl iron, or iron-based amorphous material.
The package substrate integrated with an inductor according to claim 1, wherein the inductor further comprises a first terminal electrode and a second terminal electrode;

One end of the first via hole located on the upper surface of the core layer is coupled to the first terminal electrode; one end of the second via hole located on the upper surface of the core layer is coupled to the second terminal electrode Phase coupling.
The package substrate integrated with an inductor according to claim 2, wherein the inductor further comprises a first terminal electrode and a second terminal electrode;

One end of the first via hole of the first wire segment located on the upper surface of the core layer is coupled to the first terminal electrode; the second via hole of the second wire segment is located on the core layer One end of the surface is coupled with the second terminal electrode.
The package substrate integrated with inductors according to claim 8 or 9, wherein the package substrate further comprises:

The first build-up layer is located on the upper surface of the core layer; the first build-up layer includes a first interconnection structure, a second interconnection structure, a first pad, and a second pad;

An end of the first interconnect structure close to the core layer is coupled to an end of the first via hole located on the upper surface of the core layer, and an end of the first interconnect structure away from the core layer is coupled to The first pad is coupled; the first pad serves as the first terminal electrode of the inductor;

An end of the second interconnect structure close to the core layer is coupled to an end of the second via hole located on the upper surface of the core layer, and an end of the second interconnect structure away from the core layer is coupled to The second pad is coupled; the second pad serves as a second terminal electrode of the inductor.
The package substrate integrated with inductors according to claim 10, wherein the package substrate further comprises:

The second build-up layer is located on the lower surface of the core layer; the second build-up layer includes a third pad on a side away from the core layer;

A third interconnection structure that penetrates the core layer, the first build-up layer, and the second build-up layer;

The first build-up layer further includes a fourth pad on a side away from the core layer, a first end of the third interconnection structure is coupled to the third pad, and a second end is connected to the fourth pad. The pad is coupled; the third pad is used as a power input terminal of the packaging substrate, and the fourth pad is used as a power output terminal of the packaging substrate.
An electronic device, comprising a chip, and at least one package substrate integrated with an inductor according to any one of claims 1-11; the chip is on the package substrate; the chip includes a voltage regulator A module and a processing module; the package substrate has a power output terminal;

The package substrate includes an inductor; the power output terminal of the package substrate is coupled to the voltage adjustment module, and the voltage adjustment module is also coupled to the first terminal electrode of the inductor; the second end of the inductor The electrode is also coupled to the processing module;

The voltage regulation module and the inductor form a voltage conversion circuit for providing a supply voltage to the processing module.