WO2021105839A1

WO2021105839A1 - Microelectronic sensors for inter-chip networks capable of recording and processing neural signals and action potentials

Info

Publication number: WO2021105839A1
Application number: PCT/IB2020/061000
Authority: WO
Inventors: Ayal RAM; Nikhil KARUNAKARAN PONON; Walid-Madhat Munief
Original assignee: Epitronic Holdings Pte. Ltd.
Priority date: 2019-11-26
Filing date: 2020-11-22
Publication date: 2021-06-03

Abstract

A microelectronic sensor based on an open-gate, pseudo-conductive, high-electron mobilitytransistor (PC-HEMT) is used in a non-invasive method for receiving and processing neural signalsfrom brain of a patient, compound muscle action potentials (CMAPs), sensory nerve actionpotentials (SNAPs) or signals associated with an encephalogram or electromyogram. Beingextremely sensitive, this sensor allows omitting any invasive procedures in introducing neuralelectrodes into the brain. Moreover, due to its extremely high sensitivity, this sensor is capable ofsensing neural signals and signals associated with encephalogram or electromyogram not only frombrain, but from any single point on the patient's body, such as a limb, an arm, an elbow, a forearm, awrist, a palm or a finger, and even remotely from the patient's body, being positioned in a spaceagainst the patient's body.

Description

MICROELECTRONIC SENSORS FOR INTER-CHIP NETWORKS CAPABLE OF RECORDING AND PROCESSING NEURAL SIGNALS AND ACTION POTENTIALS

TECHNICAL FIELD

[0001] The present application relates to the field of microelectronic sensors based on open-gate pseudo-conductive high-electron-mobility transistors (PC-HEMT) and their use in systems-on-chip and inter-chip networks for receiving and processing neural signals from brain, compound muscle action potentials, sensory nerve action potentials or signals associated with an encephalogram or electromyogram.

BACKGROUND

High-Electron Mobility Transistors

[0002] The polarisation doped high-electron-mobility transistor (HEMT) is a field effect transistor (FET) in which two layers of different bandgap and polarisation field are grown upon each other forming a hetero-junction structure. As a consequence of the discontinuity in the polarisation field, surface charges are created at the interface between the layers of the hetero-junction structure. If the induced surface charge is positive, electrons will tend to compensate the induced charge resulting in the formation of the channel. Since in the HEMT, the channel electrons are confined in a quantum well in an infinitely narrow spatial region at the interface between the layers, these electrons are referred to as a two-dimensional electron gas (2DEG). This special confinement of the channel electrons in the quantum well actually grants them two-dimensional features, which strongly enhance their mobility surpassing the bulk mobility of the material in which the electrons are flowing.

[0003] The HEMTs based on the layers of III-V semiconductor materials, such as gallium nitride (GaN) and aluminium gallium nitride (AlGaN), have recently been developed with a view to high-voltage and high-power switching applications. The high voltages and high switching speeds allow smaller, more efficient devices, such as home appliances, communications and automobiles to be manufactured. To control the density of electrons in the 2DEG channel and to switch the HEMT on and off, the voltage at the gate of the transistor should be regulated.

[0004] Figs, la-lc schematically shows the quantum well at three different biasing conditions starting from the positive gate potential (V_G), much higher than the threshold voltage (V_T), and going down to the 0V gate potential and further to the negative values below the threshold voltage. The VT is defined as a voltage required to populate electrons at the interface between the GaN and AlGaN layers, thereby creating conductivity of the 2DEG channel. Since the 2DEG channel electrons occupy energy levels below the Fermi level, the Fermi level in a quantum well is located above several energy levels when V_G >> VT (Fig. la). This enables high population of the 2DEG channel electrons and hence, high conductivity. The HEMT is turned on in this case. However, when V_G decreases to 0V (Fig. lb), the Fermi level also drops with respect to the quantum well. As a result, much fewer electron energy levels are populated and the amount of the 2DEG channel electrons significantly decreases. When V_G << VT (Fig. lc), all electron energy levels are above the Fermi level, and there is no 2DEG electrons below the gate. This situation is called "channel depletion", and the HEMT is turned off.

[0005] Many commercially available AlGaN/GaN -based HEMT structures have a negative VT, resulting in a "normally-on" operation mode at 0V gate potential. They are called "depletion-mode transistors" and used in various power switching applications when the negative voltage must be applied on the gate in order to block the current. However, for safe operation at high voltage or high-power density, in order to reduce the circuit complexity and eliminate standby power consumption, HEMTs with "normally-off" characteristics are preferred.

[0006] Several techniques to manufacture the normally-off HEMTs have been reported. Burnham et al in " Gate-recessed normally-off GaN-on-Si HEMT using a new O2-BCI3 digital etching technique" , Phys. Status Solidi C, Vol. 7, 2010, No. 7-8, pp. 2010-2012, proposed normally- off structures of the recessed gate type. In this structure, the AlGaN barrier layer is etched and the gate is brought closer to the interface between the AlGaN barrier layer and the GaN buffer layer. As the gate approaches the interface between the layers, the VT increases. The normally-off operation of the transistor is achieved once the depletion region reaches the interface and depletes the 2DEG channel at zero gate voltage. The major advantages of these HEMTs are lower power consumption, lower noise and simpler drive circuits. These HEMTs are currently used, for example, in microwave and millimetre wave communications, imaging and radars.

[0007] Chang et al in " Development of enhancement mode AlN/GaN high electron mobility transistors" , Appl. Phys. Lett., Vol. 94, 2009, No. 26, p. 263505, proposed using a very thin AlGaN barrier instead of etching the relatively thick barrier layer to approach the AlGaN/GaN interface. This structure also achieves the normally-off operation by approaching the transistor gate towards the AlGaN/GaN interface. Chen et al (2010) in "Self-aligned enhancement-mode AlGaN/GaN HEMTs using 25 keV fluorine ion implantation", in Device Research Conference (DRC), 2010, pp. 137-138, proposed to use the fluorine-based plasma treatment method. Although many publications have adopted various methods to achieve normally-off devices with minimum impact on the drain current, they unfortunately sacrificed device turn-on performance.

Nerve Conduction Studies

[0008] An electrically evoked compound action potential is a measure of the electrical response from the tissue to stimulation providing direct insight into the electrophysiology of the stimulation. A nerve conduction study (NCS) is a medical diagnostic test commonly used to evaluate this action potential, especially the ability of electrical conduction of the motor and sensory nerves of the human body. Early nerve conduction studies (NCS) were conducted by Luigi Galvani on frogs in the end of the 18^th century. He discovered that the muscles of dead frogs' legs twitched when struck by an electrical stimulation. In the early 19th century, Francois Magendie differentiated the anterior and posterior spinal nerve roots in dogs and then noticed that electrical stimulation of the former caused movement, while stimulation of the latter resulted in pain. In 1852, Herman von Helmholz measured nerve conduction velocities in human subjects. In the subsequent years, the technical progress and the better understanding of anatomy and the disease processes led to increased use of the electrical testing. Today, the electrodiagnostic tests are a valuable tool in the hands of physicians in the process of diagnosis and management of neuromuscular disorders.

[0009] The routine NCS includes testing of the motor and sensory fibres of the median, ulnar and radial nerves, the motor fibres of the peroneal and tibial, and the sensory fibres of the superficial peroneal and sural nerves. Less frequently, the facial and the accessory nerves are tested. While the typical NCS tests the distal nerve, the late responses, H-reflexes and F-wave latencies, provide information about the proximal segment. Most of the NCS tests and electromyography (EMG) are performed using needles. Nerve conduction velocity (NCV) is a common measurement made during the tests.

[0010] Motor NCS are performed by electrical stimulation of a peripheral nerve and recording from a muscle supplied by this nerve. In motor NCS, the nerve is stimulated at least at two points along its course. The active surface electrode is placed on the muscle belly innervated by the nerve while the reference electrode is positioned distally on the tendon, and the stimulus is delivered at increasing distances from the muscle. The time it takes for the electrical impulse (signal) to travel from the stimulation to the onset of the negative response (recording site) is measured. This value measured in milliseconds (ms) is called the latency. The intensity of the response signal from the baseline to the negative peak is called the amplitude and is also measured. The motor amplitudes are measured in millivolts (mV). By such supramaximal stimulating in two or more different locations along the same nerve, the activation of all axons is achieved and the NCV can be determined across different segments. Calculations are performed using the distance between the different stimulating electrodes and the difference in latencies. The obtained waveform is called compound muscle action potential (CMAP).

[0011] Sensory NCS are performed by electrical stimulation of a peripheral nerve and recording from a purely sensory portion of the nerve, such as on a finger. The electrodes in sensory NCS are attached over a sensory or a mixed nerve. The stimulation can be proximal (antidromic) or distal (orthodromic) to the recording electrode. Like the motor studies, sensory latencies are on the scale of milliseconds. Sensory amplitudes are much smaller than the motor amplitudes, usually in the microvolt (pV) range. It is therefore much more challenging to obtain the sensory nerve action potential (SNAP). The sensory NCV is calculated based upon the latency and the distance between the stimulating and recording electrodes. Stimulation at different sites along the nerve results in change of the waveform and temporal dispersion that is important to recognise.

[0012] As mentioned above, most of the NCS tests including electromyography (EMG) are performed by inserting a needle containing a recording electrode into the muscle of interest. The muscle is then evaluated at rest. Abnormal spontaneous activity includes fibrillation potentials and positive waves, fasciculations, complex repetitive discharges, myotonic and myokimic discharges, and neuromyotonia. The recruitment pattern, the motor unit potential (MUP) duration, shape and amplitude are evaluated with minimal and maximal activation. The number of nerves and muscles tested depends on the suspected underlying condition and is decided on a case -by-case basis. More information on the NCS techniques is available in A. Mallik and A. I. Weir, "Nerve conduction studies: essentials and pitfalls in practice", Journal of Neurology, Neurosurgery & Psychiatry 76, (2005), pp. 23-31 ( http : // d .doi. 2005.069138).

Neural Lace Technology and Brain-Machine Interface

[0013] A "neural lace" technology has been announced by Elon Mask in 2017 along with the establishment of Neuralink Corporation developing a first brain-machine interface (BMI). The idea behind the technology is to create inter-chip networks in a form of a lace of very tiny electrodes and then to implant them into brain for registering neural signals from the brain. This neural lace was defined by Elon Mask as a "brain-machine" interface and claimed to be capable of treating serious brain diseases in the short-term, with the eventual goal of human enhancement. In several interviews in public, Elon Musk defined the neural lace as a "digital layer above the cortex" that would not necessarily imply extensive surgical insertion but ideally an implant through a vein or artery. He explained that the long-term goal is actually to achieve some kind of "symbiosis with artificial intelligence".

[0014] Elon Mask et al in " An integrated brain-machine interface platform with thousands of channels' ', BioRxiv, posted on August 02, 2019, DOI: h tips ;//doi.or g/ 10.1101 i! 03801 , described a brain-machine interface (BMI) with the high-channel count and single-spike resolution, based on flexible polymer probes, a robotic insertion system and custom low-power electronics. At the present time, some neuroprosthetics can interpret brain signals and allow disabled people to control their prosthetic arms and legs. Musk suggested to link the neural lace technology with implants that, instead of actuating movement, can interface at broadband speed with other types of external software and gadgets.

[0015] The neural lace suggested by Mask et al (2019) comprises flexible "threads", which are less likely to damage the brain than the materials currently used in brain-machine interfaces. These threads also create the possibility of transferring a higher volume of data. The entire neural lace may comprise as many as 3,072 electrodes per array distributed across 96 threads, which are 4 to 6 pm in width, that makes them considerably thinner than a human hair. In addition, described is a machine that automatically embeds them into brain.

[0016] US 20190286592 Al by Neuralink Corporation describes electronic chips and systems- on-chip used to receive and process neurological events in brain, captured by electrodes. Such chips and systems include an array of amplifiers and electrodes to receive neurological voltage signals, a circuitry in communication with the array of amplifiers, and a controller. The circuitry is configured to receive program instructions and instruct the amplifiers of a voltage threshold and instruct the controller to pass on signals from only specific rows and columns of the amplifiers in the array. The controller, which is in communication with the array of the amplifiers is configured to packetize the neurological voltage signals into data packets.

[0017] The exemplary electronic chips mentioned in US 20190286592 Al are based on metal- oxide semiconductor field-effect transistors (MOSFETs). To avoid using invasive "threads" which are surgically inserted into a brain, significantly improve sensitivity of the neural lace and BMIs and their responsiveness (response time), the present inventors suggested to incorporate their proprietary pseudo-conducting high-electron-mobility transistors into the inter-chip networks for receiving and processing neural signals from brain. As a result, the present technology developed by the inventors can omit any invasive procedures suggested by Neuralink. The sensors of the present invention are capable of non-invasively measuring neural signals from brain, compound muscle action potentials, sensory nerve action potentials or signals associated with an encephalogram or electromyogram. Moreover, due to their extremely high sensitivity, the sensors of the present invention are capable of sensing neural signals and signals associated with encephalogram (ECC) from any single point on the patient's body, such as a limb, an arm, an elbow, a forearm, a wrist, a palm or a finger.

SUMMARY

[0018] The present invention describes embodiments of a non-invasive method for receiving and processing neural signals from brain of a patient, compound muscle action potentials (CMAPs), sensory nerve action potentials (SNAPs) or signals associated with an encephalogram or electromyogram, comprising:

I. providing a microelectronic sensor comprising an open-gate, pseudo-conductive, high-electron mobility transistor (PC-HEMT) or an array thereof, wherein said transistor comprises: a) a multilayer hetero-junction structure made of gallium nitride (GaN) and aluminium gallium nitride (AlGaN) single-crystalline or polycrystalline semiconductor materials and deposited on a substrate layer (10) or placed on a free-standing membrane (21), said structure comprising at least one buffer layer (11) and at least one barrier layer (12), said layers being stacked alternately; b) a conducting channel (13) comprising a two-dimensional electron gas (2DEG) or a two- dimensional hole gas (2DHG), formed at the interface between said buffer layer (12) and said barrier layer (11) and upon applying a bias to said transistor, becoming capable of providing electron or hole current, respectively, in said transistor between source and drain contacts (15); c) the source and drain contacts (15) connected to said 2DEG or 2DHG conducting channel (13) and to electrical metallisations (14) for connecting said transistor to an electric circuit; and d) an open gate area (17) between said source and drain contacts (15); said transistor is characterised in that the thickness of a top (barrier or buffer) layer (11 or 12) of said heterojunction structure in the open gate area (17) is 5-9 nanometres (nm) and the surface of said top layer (11 or 12) has a roughness of 0.2 nm or less, wherein the combination of said thickness and said roughness of the top layer (11 or 12) creates a quantum electronic effect of operating said 2DEG or 2DHG channel (13) simultaneously in both normally-on and normally-off operation modes of the channel (13), thereby making said transistor to conduct electric current through said channel (13) in a quantum well between normally-on and normally-off operation modes of the transistor;

II. contacting a single sensing point on the patient's body with, or remotely positioning in a space against the patient's body, said microelectronic sensor;

III. recording neural signals or action potentials received from the patient's body in a form of a source-drain electric potential of said transistor over time (defined as V_DS dynamics) with said microelectronic sensor;

IV. transmitting the recorded signals from said microelectronic sensor to an external memory for further processing; and

V. processing the transmitted signals in the external memory, correlating said V_DS dynamics with electrophysiological parameters and extracting said electrophysiological parameters from said transmitted signals in a form of medical data; and

VI. displaying said medical data in a form of a visual, graphical or mathematical representation of the VDS dynamics or any other readable format, thereby processing said neural signals from brain, said compound muscle action potentials (CMAPs), said sensory nerve action potentials (SNAPs) or signals associated with an encephalogram or electromyogram.

[0019] In a further embodiment, the PC-HEMT of the embodiments comprises a metamaterial antenna electrode placed on the top layer between said source and drain contact in the open gate area of the transistor and capable of detecting and transmitting electrical signals in the frequency range of 30 GHz to 300 THz.

[0020] In a further embodiment, the multilayer hetero-junction structure of the PC-HEMT of the invention comprises either:

(i) one AlGaN barrier layer at the top of the structure recessed in the open gate area to the thickness of 5-9 nm with the surface roughness of 0.2 nm or less, and one GaN buffer layer at the bottom of the structure; said layers having Ga-face polarity, thus forming the two- dimensional electron gas (2DEG) conducting channel in said GaN layer, close to the interface with said AlGaN layer; or

(ii) one GaN layer at the top of the structure recessed in the open gate area to the thickness of 5-9 nm with the surface roughness of 0.2 nm or less, one GaN buffer layer at the bottom of the structure, and one AlGaN barrier layer in between; said layers having the Ga-face polarity, thus forming the two-dimensional hole gas (2DHG) conducting channel in the top GaN layer, close to the interface with said AlGaN barrier layer; or

(iii) one GaN layer at the top of the structure recessed in the open gate area to the thickness of 5-9 nm with the surface roughness of 0.2 nm or less, one GaN buffer layer at the bottom of the structure, and one AlGaN barrier layer in between; said layers having the N-face polarity, thus forming the two-dimensional electron gas (2DEG) conducting channel in the top GaN layer, close to the interface with said AlGaN barrier layer; or

(iv) one AlGaN barrier layer at the top of the structure recessed in the open gate area to the thickness of 5-9 nm with the surface roughness of 0.2 nm or less, and one GaN buffer layer at the bottom of the structure; said layers having N-face polarity, thus forming the two- dimensional hole gas (2DHG) conducting channel in said GaN layer, close to the interface with said AlGaN layer.

[0021] The PC-HEMT source and drain contacts may be ohmic or non-ohmic. When the source and drain contacts are non-ohmic, the electrical metallisations of the transistor are capacitively- coupled to the 2DEG or 2DHG conducting channel for inducing displacement currents, thereby creating said non-ohmic source and drain contacts. In a particular embodiment, the transistor further comprises a dielectric layer deposited on top of said multilayer hetero-junction structure. In a specific embodiment, the thickness of the PC-HEMT top (barrier or buffer) layer in the open gate area is 6 to 7 nm, or 6.2 nm to 6.4 nm; and the surface of said top layer has a roughness of 0.2 nm or less, or 0.1 nm or less, or 0.05 nm or less. In another embodiment, the multilayer heterojunction structure further comprises a piezoelectric electro-optical crystal (EOC) transducer adapted to be brought into a contact with a medium to be sensed and adapted to be illuminated with a polarised light.

[0022] The single sensing point on the patient's body may be a patient's head or any patient's limb, an arm, an elbow, a forearm, a wrist, a palm or a finger. In some embodiments, provided is an inter-chip network for non-invasively receiving and processing of neural signals from brain, compound muscle action potentials (CMAPs), sensory nerve action potentials (SNAPs) or signals associated with an encephalogram or electromyogram, said inter-chip network comprising:

(A) A plurality of microelectronic sensors (1) of the present embodiemnts configured to non- invasively receive and process neural signals from brain, compound muscle action potentials (CMAPs), sensory nerve action potentials (SNAPs) or signals associated with an encephalogram or electromyogram, said microelectronic sensors (1) integrated inside said inter-chip network in rows and in columns, thereby forming a spatial array (900), wherein each of said microelectronic sensors (1) is connected to its dedicated electrical contact in a contact array (2);

(B) A row multiplexer (901) connected to said contact array (2) for addressing each and every microelectronic sensor (1) arranged in rows, selecting one of several analogue or digital input signals and forwarding the selected input into a single line;

(C) A column multiplexer (902) connected to said contact array (2) for addressing each and every microelectronic sensor (1) arranged in columns, selecting one of several analogue or digital input signals and forwarding the selected input into a single line; and

(D) An integrated circuit (903) for storing and processing said neural signals from brain, compound muscle action potentials (CMAPs), sensory nerve action potentials (SNAPs) or signals associated with an encephalogram or electromyogram.

[0023] Various embodiments may allow various benefits and may be used in conjunction with various applications. The details of one or more embodiments are set forth in the accompanying figures and the description below. Other features, objects and advantages of the described techniques will be apparent from the description and drawings and from the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Disclosed embodiments will be understood and appreciated more fully from the following detailed description taken in conjunction with the appended figures. The drawings included and described herein are schematic and are not limiting the scope of the disclosure. It is also noted that in the drawings, the size of some elements may be exaggerated and, therefore, not drawn to scale for illustrative purposes. The dimensions and the relative dimensions do not necessarily correspond to actual reductions to practice of the disclosure.

[0025] Fig. 1 schematically shows the quantum well at three different biasing conditions:

Fig. la: positive gate potential (+VG) is much higher than threshold voltage (VT),

Fig. lb: 0V gate potential, and

Fig. lc: negative gate potential (-VG) is below threshold voltage (VT).

[0026] Fig. 2 schematically shows a mixed analogue/digital amplifier circuit comprising an array of the microelectronic sensors or systems-on-chip of the present invention.

[0027] Figs. 3a-3b schematically shows a cross-sectional view (XZ) (a) and a top view (XY) (b) of the PC-HEMT of the present invention without a dielectric layer. [0028] Fig. 3c schematically shows a cross-sectional view of the PC-HEMT of the present invention having non-ohmic (capacitively-coupled) contacts and no dielectric layer.

[0029] Fig. 3d schematically shows a cross-sectional view of the PC-HEMT of the present invention with highly-doped source and drain areas.

[0030] Fig. 3e schematically shows a cross-sectional view of the PC-HEMT of the present invention with a dielectric layer.

[0031] Fig. 3f schematically shows a cross-sectional view of the PC-HEMT of the present invention having non-ohmic (capacitively-coupled) contacts and a dielectric layer.

[0032] Fig. 3g schematically shows a cross-sectional view of the PC-HEMT of the present invention with free-standing membranes.

[0033] Fig. 3h illustrates a situation when the external pressure (mass effect) is applied on the sensor incorporating the PC-HEMT of Fig. 3g and transferred into a changed internal strain caused by bending.

[0034] Fig. 3i schematically shows a cross-sectional view of the PC-HEMT of the present invention with free-standing membranes and having non-ohmic (capacitively-coupled) contacts. [0035] Fig. 4 schematically shows the dependence of the source-drain current (a charge carrier density) induced inside the 2DEG channel of a GaN/AlGaN HEMT on the thickness of the AlGaN layer recessed in the open gate area.

[0036] Fig. 5 illustrates a theory behind the 2DEG formation (charge neutrality combined with the lowest energy level) at the conduction band discontinuity.

[0037] Fig. 6a schematically shows the 2DEG area created in the step of the 2DEG-pattering via ion implantation during the manufacturing process. AZ 4533 is a positive thick resist.

[0038] Fig. 6b shows the lithographic mask of the sensor layout of the present invention.

[0039] Fig. 6c shows the lithographic image of the 2DEG channel formed with AZ 4533 thick resist lithography over the mask shown in Fig. 5b.

[0040] Figs. 6d-6e show the mask and the corresponding lithographic image, respectively, of the sensor layout of the present invention.

[0041] Fig. 6f shows the ±2-pm alignment precision on 25 x 25 mm2 samples in the lithography of the sensor layout of the present invention.

[0042] Fig. 6g shows the lithographic images of the multichannel samples.

[0043] Fig. 6h shows the fixed sample on the Si-GaN/AlGaN wafer prepared for ion implantation and containing around 30-32 sensors with 4-8 channels on each sample. [0044] Fig. 6i shows the lithographic image of the sensor layout with the AZ4533 resist after development, prepared for ion implantation.

[0045] Fig. 6j shows the 2DEG channels (dark) patterned by ion-implantation after the resist removal.

[0046] Fig. 6k shows the visible non-implanted area containing the conductive 2DEG channel.

[0047] Fig. 7a shows the AFM surface image of the top recessed layer of the PC-HEMT made by the manufacturing process of the present invention. The measured RMS value of the surface roughness is 0.674 nm in this case.

[0048] Fig. 7b shows the AFM surface image of the top recessed layer of the HEMT made by a conventional manufacturing process. The measured RMS value of the surface roughness is 1.211 nm in this case.

[0049] Fig. 7c shows the time-dependent plot of the drain-source electric current IDS of the nitrogen oxide sensor of the present invention measuring 100 ppb of the NO2 gas in humid air, where the sensor is based on the PC-HEMT made by the manufacturing process of the present invention.

[0050] Fig. 7d shows the time-dependent plot of the drain-source electric current IDS of the nitrogen oxide sensor measuring 100 ppb of the NO2 gas in humid air, where the sensor is based on the HEMT made by a conventional manufacturing process.

[0051] Fig. 8a schematically shows the formation of the 2DEG and 2DHG channels in the Ga- face three-layer Ga/AlGaN/GaN PC-HEMT structure.

[0052] Fig. 8b schematically shows the formation of the 2DEG and 2DHG channels in the N- face three-layer Ga/AlGaN/GaN PC-HEMT structure.

[0053] Fig. 8c schematically shows the formation of the 2DEG channel in the N-face three-layer GaN/AlGaN/GaN PC-HEMT structure with an ultrathin Al(GaN)N layer for improved confinement. [0054] Fig. 9a schematically shows an inter-chip network of the present invention for receiving and processing neural signals from brain or signals associated with encephalogram.

[0055] Fig. 9b schematically shows the inter-chip network of the present invention with the integrated circuit (903) for receiving and processing the neural signals from brain or signals associated with encephalogram.

[0056] Fig. 9c schematically shows another configuration of the inter-chip network of the present invention with the integrated circuit (903) for receiving and processing neural signals from brain or signals associated with encephalogram. DETAILED DESCRIPTION

[0057] In the following description, various aspects of the present application will be described. For purposes of explanation, specific configurations and details are set forth in order to provide a thorough understanding of the present application. However, it will also be apparent to one skilled in the art that the present application may be practiced without the specific details presented herein. Furthermore, well-known features may be omitted or simplified in order not to obscure the present application.

[0058] The term "comprising", used in the claims, is "open ended" and means the elements recited, or their equivalent in structure or function, plus any other element or elements which are not recited. It should not be interpreted as being restricted to the means listed thereafter; it does not exclude other elements or steps. It needs to be interpreted as specifying the presence of the stated features, integers, steps or components as referred to, but does not preclude the presence or addition of one or more other features, integers, steps or components, or groups thereof. Thus, the scope of the expression "a device comprising x and z" should not be limited to devices consisting only of components x and z. Also, the scope of the expression "a method comprising the steps x and z" should not be limited to methods consisting only of these steps.

[0059] Unless specifically stated, as used herein, the term "about" is understood as within a range of normal tolerance in the art, for example within two standard deviations of the mean. In one embodiment, the term "about" means within 10% of the reported numerical value of the number with which it is being used, preferably within 5% of the reported numerical value. For example, the term "about" can be immediately understood as within 10%, 9%, 8%, 7%, 6%, 5%, 4%, 3%, 2%, 1%, 0.5%, 0.1%, 0.05%, or 0.01% of the stated value. In other embodiments, the term "about" can mean a higher tolerance of variation depending on for instance the experimental technique used. Said variations of a specified value are understood by the skilled person and are within the context of the present invention. As an illustration, a numerical range of "about 1 to about 5" should be interpreted to include not only the explicitly recited values of about 1 to about 5, but also include individual values and sub-ranges within the indicated range. Thus, included in this numerical range are individual values such as 2, 3, and 4 and sub-ranges, for example from 1-3, from 2-4, and from 3-5, as well as 1, 2, 3, 4, 5, or 6, individually. This same principle applies to ranges reciting only one numerical value as a minimum or a maximum. Unless otherwise clear from context, all numerical values provided herein are modified by the term "about". Other similar terms, such as "substantially", "generally", "up to" and the like are to be construed as modifying a term or value such that it is not an absolute. Such terms will be defined by the circumstances and the terms that they modify as those terms are understood by those of skilled in the art. This includes, at very least, the degree of expected experimental error, technical error and instrumental error for a given experiment, technique or an instrument used to measure a value.

[0060] As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein. Well-known functions or constructions may not be described in detail for brevity and/or clarity.

[0061] It will be understood that when an element is referred to as being "on", "attached to", "connected to", "coupled with", "contacting", etc., another element, it can be directly on, attached to, connected to, coupled with or contacting the other element or intervening elements may also be present. In contrast, when an element is referred to as being, for example, "directly on", "directly attached to", "directly connected to", "directly coupled" with or "directly contacting" another element, there are no intervening elements present. It will also be appreciated by those of skill in the art that references to a structure or feature that is disposed "adjacent" another feature may have portions that overlap or underlie the adjacent feature.

[0062] As used herein, the term "system on chip" includes any integrated circuit that integrates all components of a computer or other electronic system. These components typically include a central processing unit, memory, input/output ports and secondary storage, all on a single substrate or microchip. As used herein, the term "inter-chip network" includes any network that is capable of transmitting and receiving signals between microelectronic sensors or systems-on-chip containing source and destination nodes.

[0063] As shown in Fig. 2, each microelectronic sensor or system-on-chip (1) connects to at least two neighbouring chips in the plane and to an array of contacts (2). This inter-chip connection spatially forms an exemplary "hemisphere" topology, which bears similarity to a lace or a knit cap. While the physical architecture of the inter-chip network is not symmetric in the vertical and horizontal dimensions, the non-limiting example of the spatial geometry and topology implemented by the network of the present invention is isotropic. More details on a similar inter-chip network can be found in US 20190286592 Al. As mentioned in the background section of the present disclosure, the exemplary microelectronic chips described in US 20190286592 Al are based on MOSFETs that have much lower sensitivity that the transistors of the present invention and, as a result, do not allow to implement the non-invasive approach.

[0064] In order to significantly improve sensitivity of the neural lace and similar brain-machine interfaces (BMIs) to neural signals and sensory nerve action potentials, as well as their response time, the present inventions suggests replacing the electronic chips of US 20190286592 Al with the pseudo-conducting high-electron-mobility transistors (PC-HEMTs). The extremely high sensitivity of the PC-HEMT-based sensors of the present invention makes it possible to use the inter-chip network non-invasively for measuring neural signals received from brain, compound muscle action potentials (CMAPs), sensory nerve action potentials (SNAPs) or neural signals associated with an encephalogram or electromyogram. The thin "needle-like" electrodes suggested by Neuralink can therefore be entirely omitted. As a result, the overall design of the inter-chip network, which is described in US 20190286592 Al, becomes essentially simplified, not mentioning the fact that the invasive procedure of inserting the electrodes in brain is now completely avoided.

[0065] Therefore, in one aspect of the present invention, provided is a non-invasive method for receiving and processing neural signals from brain of a patient, compound muscle action potentials (CMAPs), sensory nerve action potentials (SNAPs) or signals associated with an encephalogram or electromyogram, comprising:

I. providing a microelectronic sensor comprising an open-gate, pseudo-conductive, high-electron mobility transistor (PC-HEMT) or an array thereof, wherein said transistor comprises: a) a multilayer hetero-junction structure made of gallium nitride (GaN) and aluminium gallium nitride (AlGaN) single-crystalline or polycrystalline semiconductor materials and deposited on a substrate layer (10) or placed on a free-standing membrane (21), said structure comprising at least one buffer layer (11) and at least one barrier layer (12), said layers being stacked alternately; b) a conducting channel (13) comprising a two-dimensional electron gas (2DEG) or a two- dimensional hole gas (2DHG), formed at the interface between said buffer layer (12) and said barrier layer (11) and upon applying a bias to said transistor, becoming capable of providing electron or hole current, respectively, in said transistor between source and drain contacts (15); c) the source and drain contacts (15) connected to said 2DEG or 2DHG conducting channel (13) and to electrical metallisations (14) for connecting said transistor to an electric circuit; and d) an open gate area (17) between said source and drain contacts (15); said transistor is characterised in that the thickness of a top (barrier or buffer) layer ( 11 or 12) of said heterojunction structure in the open gate area (17) is 5-9 nanometres (nm) and the surface of said top layer (11 or 12) has a roughness of 0.2 nm or less, wherein the combination of said thickness and said roughness of the top layer (11 or 12) creates a quantum electronic effect of operating said 2DEG or 2DHG channel (13) simultaneously in both normally-on and normally-off operation modes of the channel (13), thereby making said transistor to conduct electric current through said channel (13) in a quantum well between normally-on and normally-off operation modes of the transistor;

III. recording neural signals or action potentials received from the patient's body in a form of a source -drain electric potential of said transistor over time (defined as V_DS dynamics) with said microelectronic sensor;

[0066] In general, motor nerve conducting studies are performed by electrical stimulation of a nerve and recording the compound muscle action potential (CMAP) from surface electrodes overlying a muscle supplied by that nerve. The recording electrodes are performed using adhesive conductive pads placed onto the skin overlying the target muscle. The active electrode is placed over the muscle belly and the reference over an electrically inactive site (usually the muscle tendon). A ground electrode is also placed somewhere between the stimulating and recording electrodes providing a zero-voltage reference point. The median motor study might involve stimulation at the wrist, the elbow, and less frequently the axilla and the brachial plexus.

[0067] The CMAP is actually a sum of electrophysiological potentials across the measured organ, which is a sum mated voltage response from the individual muscle fibre action potentials. The shortest latency of the CMAP is the time from stimulus artefact to onset of the response and is a biphasic response with an initial upward deflection followed by a smaller downward deflection. Thus, the CMAP amplitude is measured from baseline to negative peak (the neurophysiological convention is that negative voltage is demonstrated by an upward deflection) and measured in millivolts (mV).

[0068] To record the CMAP, the stimulating current or voltage is gradually increased until a point is reached where an increase in stimulus produces no increment in CMAP amplitude. It is only at this (supramaximal) point that reproducible values for CMAP amplitude and the latency between the stimulus and the onset of the CMAP can be recorded accurately. The nerve is then stimulated at a more proximal site, i.e. in the median nerve this will be the antecubital fossa, close to the biceps tendon. In the normal state, stimulating the median nerve for example at the wrist and the elbow results in two CMAPs of similar shape and amplitude because the same motor axons innervate the muscle fibres making up the response. However, the latency will be greater for elbow stimulation compared with wrist stimulation because of the longer distance between the stimulating and recording electrodes. The difference in latency represents the time taken for the fastest nerve fibres to conduct between the two stimulation points as all other factors involving neuromuscular transmission and muscle activation are common to both stimulation sites. If one measures the distance between the two sites, then the fastest motor nerve conduction velocity can be calculated as the distance (mm) between the two stimulation sites to divide by the difference of their latencies (ms).

[0069] The SNAP is obtained by electrically stimulating sensory fibres and then recording the sensory nerve action potential at a point further along that nerve. As above, the stimulus must be supramaximal. Recording the SNAP orthodromically refers to distal nerve stimulation and recording more proximally (the direction in which physiological sensory conduction occurs), while antidromic testing is the reverse. Different laboratories prefer antidromic or orthodromic methods for testing different nerves. The sensory latency and the peak to peak amplitude of the SNAP are measured. The velocity correlates directly with the sensory latency and therefore either the result may be expressed as a latency over a standard distance or a velocity. [0070] Each microelectronic sensor or each system-on-chip (1) schematically shown in Fig. 2 as a dot comprises at least one PC-HEMT (at least one sensing channel) exposed to sensing neural signals, CMAPs, SNAPs or signals associated with an encephalogram or electromyogram, having electrical metallisations (14) (see Figs. 3a-3i) for connecting said transistor to an electric circuit and one common metal electrode (not shown here) for feeding the AC sinusoidal stimulation and for conducting sensing or testing operations. This reference electrode is also used to set the DC bias voltage. All the sensors or systems-on-chip (1) in the array operate synchronously having the same transfer characteristics. Therefore, it is essential to set all the gate contacts at a common ground potential (which is the reference electrode potential) in order to operate all the sensors or systems- on-chip (1) in the array at the same time.

[0071] Reference is now made to Figs. 3a-3i schematically showing the structure and topology of the PC-HEMT of the present invention, having different configurations. In one aspect, the sensors or systems-on-chip of the present invention are based on the open-gate pseudo-conductive high- electron mobility transistor (PC-HEMT), comprising:

(1) a multilayer heterojunction structure composed of III-V single-crystalline or poly -crystalline semiconductor materials, said structure comprising at least one buffer layer (11) and at least one barrier layer (12), said layers being stacked alternately, and said structure being deposited on a substrate layer (10) or placed on free-standing membranes (21);

(2) a conducting channel (13) comprising a two-dimensional electron gas (2DEG) or a two- dimensional hole gas (2DHG), formed at the interface between said buffer layer (11) and said barrier layer (12), and upon applying a bias to said transistor, capable of providing electron or hole current, respectively, in said transistor between source and drain contacts;

(3) the source and drain contacts connected to said 2D EG or 2DHG channel (13) and to electrical metallisations (14) for connecting said transistor to an electric circuit; and

(4) an open gate area (17) between said source and drain contacts; characterised in that the thickness (d) of a top layer of said structure in said open gate area is 5-9 nm which corresponds to the pseudo-conducting current range between normally-on and normally-off operation mode of the transistor, and the surface of said top layer has a roughness of about 0.2 nm or less.

[0072] The term "2DEG" mentioned in the present description and claims should not be understood or interpreted as being restricted to the two-dimensional electron gas. As stated above and will be explained later in this application, the two-dimensional hole gas may also be a possible current carrier in a specific heterojunction structure. Therefore, the term "2DEG" may be equally replaced with the term "2DHG" without reference to any particular PC-HEMT configuration.

[0073] The source and drain contacts connecting the PC-HEMT to the electric circuit may be ohmic or non-ohmic (capacitively-coupled, as will be described below). Figs. 3a-3b show a cross- sectional view (XZ) and a top view (XY) of the transistor of the present application, comprising:

(1) a multilayer heterojunction structure composed of III-V single-crystalline or poly -crystalline semiconductor materials, said structure comprising at least one buffer layer (11) and at least one barrier layer (12), said layers being stacked alternately, and said structure being deposited on a substrate layer (10);

(3) source and drain ohmic contacts (15) connected to said 2DEG conducting channel (13) and to electrical metallisations (14) for connecting said transistor to an electric circuit; and

(4) an open gate area (17) between said source and drain ohmic contacts (15); characterised in that the thickness (d) of a top layer of said structure in said open gate area is 5-9 nm which corresponds to the pseudo-conducting current range between normally-on and normally-off operation mode of the transistor, and the surface of said top layer has a roughness of about 0.2 nm or less.

[0074] Further, Fig. 3c shows a cross-sectional view of the PC-HEMT of another embodiment comprising:

(2) a conducting channel (13) comprising a two-dimensional electron gas (2DEG) or a two- dimensional hole gas (2DHG), formed at the interface between said buffer layer (11) and said barrier layer (12), and upon applying a bias to said transistor, capable of providing electron or hole current, respectively, in said transistor between non-ohmic source and drain contacts; (3) electrical metallisations (14) capacitively -coupled to said 2DEG channel (13) for inducing displacement currents (19), thereby creating non-ohmic source and drain contacts connecting said transistor to an electric circuit; and

(4) an open gate area (17) between said source and drain non-ohmic contacts; characterised in that the thickness (d) of a top layer of said structure in said open gate area is 5-9 nm which corresponds to the pseudo-conducting current range between normally-on and normally-off operation mode of the transistor, and the surface of said top layer has a roughness of about 0.2 nm or less.

[0075] "Capacitive coupling" is defined as an energy transfer within the same electric circuit or between different electric circuits by means of displacement currents induced by existing electric fields between circuit/s nodes. In general, ohmic contacts are the contacts that follow Ohm's law, meaning that the current flowing through them is directly proportional to the voltage. Non-ohmic contacts however do not follow the same linear relationship of the Ohm's law. In other words, electric current passing through non-ohmic contacts is not linearly proportional to voltage. Instead, it gives a steep curve with an increasing gradient, since the resistance in that case increases as the electric current increases, resulting in increase of the voltage across non-ohmic contacts. This is because electrons carry more energy, and when they collide with atoms in the conducting channel, they transfer more energy creating new high-energy vibrational states, thereby increasing resistance and temperature.

[0076] When electrical metallisations are placed over single-crystalline or polycrystalline semiconductor material, the "Schottky contact" or "Schottky barrier contact" between the metal and the semiconductor occurs. Energy of this contact is covered by the Schottky-Mott rule, which predicts the energy barrier between a metal and a semiconductor to be proportional to the difference of the metal-vacuum work function and the semiconductor-vacuum electron affinity. However, this is an ideal theoretical behaviour, while in reality most interfaces between a metal and a semiconductor follow this rule only to some degree. The boundary of a semiconductor crystal abrupt by a metal creates new electron states within its band gap. These new electron states induced by a metal and their occupation push the centre of the band gap to the Fermi level. This phenomenon of shifting the centre of the band gap to the Fermi level as a result of a metal- semiconductor contact is defined as "Fermi level pinning", which differs from one semiconductor to another. If the Fermi level is energetically far from the band edge, the Schottky contact would preferably be formed. However, if the Fermi level is close to the band edge, an ohmic contact would preferably be formed. The Schottky barrier contact is a rectifying non-ohmic contact, which in reality is almost independent of the semi-conductor or metal work functions.

[0077] Thus, a non-ohmic contact allows electric current to flow only in one direction with a non-linear current-voltage curve that looks like that of a diode. On the contrary, an ohmic contact allows electric current to flow in both directions roughly equally within normal device operation range, with an almost linear current-voltage relationship that comes close to that of a resistor (hence, "ohmic").

[0078] Reference is now made to Fig. 3c illustrating the situation when an electrical connection of the transistor to the 2DEG channel is realised via capacitive coupling to electrical metallisations through a Schottky barrier contact. This coupling becomes possible only if sufficiently high AC frequency, higher than 30 kHz, is applied to the metallisations. The electrical metallisations capacitively coupled to the 2DEG channel utilise the known phenomenon of energy transfer by displacement currents. These displacement currents are induced by existing electrical fields between the electrical metallisations and the 2DEG conducting channel operated in the AC frequency mode through the Schottky contact as explained above.

[0079] Fig. 3d schematically shows a cross-sectional view of the PC-HEMT of an embodiment of the present application with highly-doped source and drain areas (18). In that case, the strong doping of the source and drain areas may result in a band-edge mismatch. However, if the semiconductor is doped strongly enough, it will form a certain potential barrier, low enough for conducting electrons to have a high probability of tunnelling through this barrier, and therefore conducting an electric current through the 2DEG channel.

[0080] An electrical connection to the 2DEG channel shown in Fig. 3d is realised with highly doped semiconductor areas (18) overlapping the 2DEG channel and having a very low electrical resistance. Dopant ions such as boron (B⁺), phosphorus (P⁺) or arsenic (As⁺) are generally created from a gas source, so that the purity of the source can be very high. When implanted in a semiconductor, each dopant atom creates a charge carrier in the semiconductor material after annealing. Holes are created for a p-type dopant, and electrons are created for an n-type dopant, modifying conductivity of the semiconductor in its vicinity. As⁺ can be used for n-type doping, while B⁺ and P⁺ ions can be used for p-type doping. For example, in case of the AlGaN/GaN structure, the source and drain areas of the silicon structure are heavily doped with either B⁺ or P⁺ to create an electrical connection to the 2DEG channel. The silicon layers have a very low electrical junction resistance between each other in that case, and in order to induce an electrical current in the 2DEG channel, the metallisations are placed on top of the source and drain areas and connected to a circuit.

[0081] The third option would be the use of the photo effect that may also induce an electric current in the 2DEG channel. In order to couple the light excitation with the electronic effects in the conductive 2DEG channel, a photo effect in a silicon layer should be created. Regarding the direct photo effect, it is well known that light can only be absorbed when the energy of the absorbed photon (E = hv) is large enough for an electron to be excited into the valence band. In that case, E is the photon energy, h is Planck’s constant and v is the frequency of the photon. The frequency is coupled to the wavelength l of light by the constant speed of light c = ln. Typically, the bandgap of silicon at room temperature is 1.12 eV, which means that silicon becomes transparent for wavelength larger than 1240 nm, which is the near infrared range.

[0082] For smaller wavelength (i.e. larger energy of the photons), electron/hole pairs are generated leading to a photocurrent. In the fully-depleted, intrinsically doped silicon structures, this results in a higher charge carrier density and consequently, higher sensitivity. For these structures, light is adsorbed in the whole visible range making such devices ideal photodetectors. The mechanism that allows the silicon semiconductor to become photosensitive to irradiation with light has already been described in literature. In the direct photo effect, it can be tuned by the size, crystalline direction and surface termination. These effects actually originate from two-dimensional quantum confinement of electrons in the nano-sized 2DEG structure.

[0083] Although irradiation of the silicon structure with light of larger wavelengths with photon energies below the bandgap does not have enough energy to excite carriers from the valence to the conduction band in bulk silicon, the electron/hole pairs can also be generated between the valence band and surface states, and the donor-like surface trap states can still be formed (see the definition and explanation of the surface trap states below). The electrons actually deplete these holes trapped at the surface and hence, modulate the gate field. The photogenerated holes are confined to the centre of the silicon structure by the gate field, where they increase the conduction of the 2DEG channel, because of the band bending. The holes increase the channel conductivity for a certain lifetime until they are trapped (recaptured) at the surface. The gain of the transistor can be extremely huge if this re-trapping lifetime is much longer than the holes transit time.

[0084] If the source and drain contacts are non-ohmic (capacitively-coupled), in order to electrically contact the 2DEG channel underneath, which is about 7-20 nm bellow metallisations (14), the AC frequency regime is used. The capacitive coupling of the non-ohmic metal contacts with the 2DEG channel is normally induced at the frequency higher than 30 kHz. In the case of the non-ohmic contacts, the DC readout cannot be performed. Instead, the AC readout or impedance measurements of the electric current flowing through the 2DEG channel are carried out.

[0085] Thus, the significant features of the PC-HEMT stmcture are that:

(a) the thickness of the top barrier layer in the open gate area is 5-9 nm, preferably 6-7 nm, more preferably 6.3 nm, which corresponds to the pseudo-conducting current range between normally-on and normally-off operation mode of the transistor, and

(b) the surface of the top barrier layer has a roughness of 0.2 nm or less, preferably 0.1 nm or less, more preferably 0.05 nm.

[0086] The same transistors of the embodiments shown in Figs. 3a-3c, but further comprising an optional dielectric layer (16), which is deposited on top of the barrier layer (12) of the transistors, are schematically shown in Figs. 3e and 3f, respectively. The optional dielectric layer (16), which is used for device passivation, is made for example of SiO-SiN-SiO ("ONO") stack having thickness of 100-100-100 nm or SiN-SiO-SiN ("NON") stack having the same thicknesses. This dielectric layer (16) is deposited on top of the barrier layer by a method of plasma-enhanced chemical vapour deposition (PECVD), which is a stress-free deposition technique.

[0087] Fig. 3g shows a cross-sectional view of the PC-HEMT configuration of an embodiment with free-standing membranes, comprising:

1) a multilayer heterojunction structure composed of III-V single-crystalline or poly -crystalline semiconductor materials, said structure comprising at least one buffer layer (11) and at least one barrier layer (12), said layers being stacked alternately, and said structure being placed on free standing membranes (21);

2) a conducting channel (13) comprising a two-dimensional electron gas (2DEG) or a two- dimensional hole gas (2DHG), formed at the interface between said buffer layer (11) and said barrier layer (12), and upon applying a bias to said transistor, capable of providing electron or hole current, respectively, in said transistor between source and drain contacts;

3) source and drain ohmic contacts (15) connected to said 2DEG conducting channel (13) and to electrical metallisations (14) for connecting said transistor to an electric circuit; and

4) an open gate area (17) between said source and drain ohmic contacts (15); characterised in that the thickness (d) of a top layer of said structure in said open gate area is 5-9 nm which corresponds to the pseudo-conducting current range between normally-on and normally-off operation mode of the transistor, and the surface of said top layer has a roughness of about 0.2 nm or less.

[0088] The PC-HEMT shown in Fig. 3g and placed on free standing membranes may be used in "pressure-sensitive" sensors of an embodiment, which are capable of measuring very small pressures. These sensors use the free-standing membranes for creating a mass-loading effect which makes it possible to increase selectivity of the sensors via adding mechanical stress (mass-loading effect) as an additional parameter of the PC-HEMT-based sensor. The free-standing membranes (21) are very flexible free-standing columns of substrate composed of sapphire, silicon, silicon carbide, gallium nitride or aluminium nitride, preferably gallium nitride, having thickness of 0.5-2 pm. The free-standing substrate membranes are very sensitive to any tensile, compressive or mechanical stress changes on the surface of the multilayer hetero-junction structure. This results in a mass loading effect, which will be discussed below.

[0089] In general, mechanical sensors, much like pressure sensors, are based on the measurement of the externally induced strain in the heterostructures. The pyroelectric properties of group-III-nitrides, such as gallium nitride (GaN), allow two mechanisms for strain transduction: piezoelectric and piezoresistive. The direct piezoelectric effect is used for dynamical pressure sensing. For measurements of static pressure, such sensors are not suitable due to some leakage of electric charges under the constant conditions. For static operation, the piezoresistive transduction is more preferable.

[0090] Piezoresistive sensors using wide band gap materials have been previously employed using hexagonal silicon carbide bulk materials for high temperature operation. The piezoresistivity of GaN and AlGaN structures was found to be comparable to silicon carbide. However, piezoresistivity can be further amplified by HEMT structure, as taught by Martin Eickhoff et al in "Piezoresistivity of Al_xGai xN layers and Al_xGai _xN/GaN heterostructures" , Journal of Applied Physics 90, 2001, 3383.

[0091] For piezoresistive strain sensing at relatively lower pressures (or pressure differences), diaphragm or membranes should be used, where the external pressure is transferred into a changed internal strain caused by bending, as shown in Fig. 3h. The resulting change in polarization alters the 2DEG channel current which is measured.

[0092] Eickhoff et al (2001) conducted the first experiments on AlGaN/GaN hetero-structures where the 2DEG channel confined between the upper GaN and AlGaN barrier layer and demonstrated the linear dependence of the 2DEG channel resistivity on the applied strain. Moreover, a direct comparison to cubic SiC and a single AlGaN layer clearly demonstrated the superior piezoresistive properties of the latter. From these results, it is clear that the interaction of piezoelectric and piezoresistive properties improves the sensitivity of pressure sensors by using GaN/AlGaN heterostructures confined with the 2DEG channel.

[0093] The sensor configuration shown in Figs. 3g and 3i involves piezoelectrically coupled, charge and mass sensitive, free-standing GaN membranes, which are prepared, for example, according to U.S. Patent No. 8,313,968, and offer an elegant and effective solution to achieve both downscaling and an integrated all-electrical low-power sensing-actuation. As mentioned above, GaN exhibits both, piezo- and pyro-electrical properties, which can be functionally combined. Whereas the piezoelectricity enables realisation of an integrated coupling mechanism, the 2DEG additionally delivers a pronounced sensitivity to mechanical stress and charge, which allows the sensor to use the pyroelectric effects. The dynamic change in 2DEG conductivity is also caused by a change in piezoelectric polarisation.

[0094] The electrical metallisations (14) connect the PC-HEMT to an electric circuit and allow electric current to flow between the source and drain contacts. The electrical metallisations (14) are made of metal stacks, such as Cr/Au, Ti/Au, Ti/W, Cr/Al and Ti/Al. The Cr or Ti layers of the metal stack is, for example, of 5-10 nm thickness, while the second metal layer, such as Au, W and Al, is of 100-400 nm thickness. The actual metallisations (14) are chosen according to the established technology and assembly line at a particular clean room fabrication facility. The source and drain ohmic contacts are usually made of metal stacks, such as Ti/Al/Mo/Au, Ti/Al/Ni/Au, Ti/Au and Ti/W having the thickness of 15-50 nm. The non-ohmic contacts on the other hand are capacitively coupled to the conducting 2DEG channel (13) via displacement currents (19).

[0095] In yet further embodiment, substrate layer (10) comprises a suitable material for forming the barrier layer and is composed, for example, of sapphire, silicon, silicon carbide, gallium nitride or aluminium nitride. The hetero-junction structure (11, 12) is deposited on the substrate layer (10), for example, by a method of metalorganic chemical vapour deposition (MOCVD), and it forms a two-dimensional electron gas (2DEG) channel (13) in the close proximity to the interface between the buffer layer (11) and the top barrier layer (12). The top barrier layer (12) then may be either recessed or grown as a thin layer between the source and drain contacts, thereby forming an open gate area.

[0096] The 2DEG/2DHG channel (13) formed near the interface between the buffer layer (11) and the barrier layer (12) serves as a main sensitive element of the transistor reacting to a surface charge and potential. The 2DEG/2DHG channel (13) is configured to interact with very small variations in surface or proximal charge or changes of electrical field on the barrier layer/liquid-air or barrier layer/metal/liquid-air interfaces interacting with the donor-like surface trap states of the barrier layer. This will be defined and discussed below in detail.

[0097] "Open gate area" of the PC-HEMT is defined as an area between the source and drain contacts of the transistor which is directly exposed to a conductive medium, such as liquid or gas capable of conducting current. An example of the conductive liquid is an electrolyte saline solution. In this case, instead of the fixed gate voltage, which is normally applied to a gate electrode, a reference potential is applied to the electrolyte-semiconductor system, via an optional reference electrode that is dipped into the electrolyte. As a result, in the absence of the physical gate, the electrolyte itself becomes an open gate of the transistor. This will be explained in more detail below. [0098] The specific thickness of the top barrier layer (12) in the open gate area is achieved by either dry etching the semiconductor material of the barrier layer (12), i.e. recessing the layer in the open gate area with the etching rate of 1 nm per 1-2 min in a controllable process, or coating the buffer layer ( 11 ) in the open gate area with an ultrathin layer of the III-V semiconductor material. In order to increase the charge sensitivity of the transistor, the surface of the recessed ultrathin barrier layer is post-treated with plasma (chloride) epi-etch process. Consequently, the natively passivated surface is activated by the plasma etch to create an uncompensated (ionised) surface energy bonds or states, which are neutralized after MOCVD growing.

[0099] Fig. 4 shows the dependence of the source-drain current (a charge carrier density) on the barrier layer thickness recessed in the open gate area. As seen from the plot, the HEMTs that have a thickness of the barrier layer in the open gate area larger than about 9 nm are normally-on devices. In such devices, due to the inherent polarisation effects present in the III-V materials, a thin sheet of charges is induced at the top and bottom of the interfaces of the barrier layer. As a result, a high electric field is induced in the barrier layer, and surface donor states at the top interface start donating electrons to form the 2DEG channel at the proximity of the hetero-junction interface without the application of a gate bias. These HEMTs are therefore normally-on devices. On the other hand, the HEMTs that have a thickness of the barrier layer in the open gate area lower than about 5 nm act as normally-off devices.

[0100] The top barrier layer recessed or grown in the open gate area to 5-9 nm is optimised by minimising the roughness of the top semiconductor layer to 0.2 nm and less. The resulted structure was surprisingly found to significantly enhance sensitivity of the sensor. This specific thickness of 5-9 nm of the top barrier layer in the open gate area with the roughness of 0.2 nm or less corresponds to the "pseudo -conducting" current range between normally-on and normally-off operation modes of the transistor and requires further explanation.

[0101] "Pseudo-conducting" current range of the HEMT is defined as an operation range of the HEMT between its normally-on and normally-off operation modes. "Trap states" are states in the band-gap of a semiconductor which trap a carrier until it recombines. "Surface states" are states caused by surface reconstruction of the local crystal due to surface tension caused by some crystal defects, dislocations, or the presence of impurities. Such surface reconstruction often creates "surface trap states" corresponding to a surface recombination velocity. Classification of the surface trap states depends on the relative position of their energy level inside the band gap. The surface trap states with energy above the Fermi level are acceptor-like, attaining negative charge when occupied. However, the surface trap states with energy below the Fermi level are donor-like, positively charged when empty and neutral when occupied. These donor-like surface trap states are considered to be the source of electrons in the formation of the 2DEG channel. They may possess a wide distribution of ionization energies within the band gap and are caused by redox reactions, dangling bonds and vacancies in the surface layer. A balance always exists between the 2DEG channel density and the number of ionised surface donors which is governed by charge neutrality and continuity of the electric field at the interfaces.

[0102] Thus, the donor-like surface traps formed at the surface of the barrier layer of the HEMT are one of the most important sources of the 2DEG in the channel. However, this only applies for a specific barrier layer thickness. In a relatively thin top barrier layer, the surface trap state is below the Fermi level. However, as the top barrier layer thickness increases, the energy of the surface trap state approaches the Fermi energy until it coincides with it. The thickness of the top barrier layer corresponding to such situation is defined as "critical". At this point, electrons filling the surface trap state become pulled to the channel by the strong polarisation-induced electric field found in the barrier to form the 2DEG instantly.

[0103] If the surface trap states are completely depleted, further increase in the barrier layer thickness will not increase the 2DEG density. Actually, if the 2DEG channel layer fails to stretch the barrier layer, the later will simply relax. Upon relaxation of the barrier layer, crystal defects are created at the interface between the buffer layer and the barrier layer, and the piezoelectric polarisation instantly disappears causing deterioration in the 2DEG density. [0104] In order to illustrate the above phenomenon of pseudo-conducting current, reference is now made to the following figures. As mentioned above, Fig. 4 shows the dependence of the source -drain current (a charge carrier density) on the recessed AlGaN barrier layer thickness. An energy equilibrium between the donor surface trap states and the AlGaN tunnel barrier leads to formation of the 2DEG (charge neutrality combined with the lowest energy level) at the conduction band discontinuity. As explained above, decrease in the thickness of the top barrier layer results in increase of the energy barrier. As a result, the ionisable donor-like surface trap states, which are responsible for electron tunnelling from the surface to 2DEG, drift bellow the Fermi level, thereby minimizing the electron supply to the 2DEG channel. This theoretical situation is schematically illustrated in Fig. 5. Therefore, the recess of the top AlGaN layer from 9 nm to 5 nm leads to extremely huge drop in the 2DEG conductivity for six orders of magnitude.

[0105] In view of the above, it is clear that the mechanism of the 2DEG depletion based on recessing the top barrier layer is strongly dependent on the donor-like surface trap states (or total surface charge). As the thickness of the barrier layer decreases, less additional external charge is needed to apply to the barrier layer surface in order to deplete the 2DEG channel. There is a critical (smallest) barrier thickness, when the 2DEG channel is mostly depleted but still highly conductive due to a combination of the energy barrier and the donor surface trap states energy. At this critical thickness, even the smallest energy shift at the surface via any external influence, such as surface reaction, charging etc., leads immediately to very strong 2DEG depletion. As a result, the surface of the top barrier layer at this critical thickness is extremely sensitive to any smallest change in the electrical field of the surroundings.

[0106] Thus, it has been found that the recess of the top layer in the open gate area from 9 nm down to 5 nm drastically reduces the 2DEG density, brings the transistor to the "near threshold" operation and results in highly increased surface charge sensitivity. The specific 5-9 nm thickness of the transistor's top layer responsible for its surprising pseudo-conducting behaviour gives the transistor the incredible sensitivity. So, when it comes into a contact with an ionic fluid or body skin, it opens up the gate to be able to do the ultrasensitive sensing. This thickness must be optimised for significantly enhancing sensitivity of the sensor. This specific thickness of the top layer was surprisingly found to correspond to the "pseudo-conducting" current range between normally-on and normally-off operation modes of the 2DEG channel and requires further explanation. [0107] The top layer is recessed to this specific thickness after subjecting to short plasma activation by an ultra-low damage reactive-ion etching technique using inductively-coupled plasma (ICP) with a narrow plasma-ion energy distribution. Such short plasma treatment allows much lower roughness of the surface, which is a function of the semiconductor vertical damage depth during the plasma etching process. Such low surface roughness (about 0.2 nm and less) can be achieved only via this ICP-RIE ultra low damage etching process with a narrow plasma-ion energy distribution, and this inherently results in a very low vertical damage depth to the top layer, which allows the minimal surface scattering and minimal surface states-2DEG channel interaction with the maximum signal-to-noise ratio of the sensor. Thus, the depth effect of the vertical sub-nanometre damage to the top recessed layer, due to an ultra-low damage ICP-RIE etching process with a very narrow plasma-ion energy distribution, is the only way to optimally achieve the required sub-nanometre roughness of the semiconductor surface. This inherently results in an adjustable pseudo-conductive working point with the highest charge sensitivity ever possible. This depth effect is always inherent to the sub-nanometre roughness of the semiconductor surface, which was measured using AFM (atomic force microscope).

[0108] Thus, in addition to the recessed top layer thickness, roughness of the top layer surface is another very important parameter that has not been previously disclosed. It has been surprisingly found that the roughness of the top layer surface (in the open gate sensitive area) bellow 0.2 nm prevents scattering of the donor-like surface trap states. Thus, combination of these two features: 5-9 nm thickness of the top layer in the open gate area and strongly reduced roughness of its surface (bellow 0.2 nm) make the sensor incredibly sensitive.

[0109] In a certain aspect, the method for manufacturing of the PC-HEMTs of the present invention comprises the following steps:

Step 1: Plasma-enhanced atomic layer deposition (ALD) of alumina (AI2O3) on a pre-aligned masked Si-GaN/AlGaN wafer with nitrogen-plasma de-trapping for the thickness of the AI2O3 layer being 3-10 nm. The AI2O3 layer thickness was measured with an X-ray reflectometer.

Step 2: Plasma-enhanced atomic layer deposition (ALD) pattering of the wafer coated with the thin AI2O3 layer in Step 1, with hydrogen fluoride (HF) or using the aforementioned reactive-ion etching (RIE) technique.

Step 3: Optionally creating the source and drain ohmic contacts (in case ohmic contacts are required) on the coated wafer obtained in Step 2 from metal stacks, for example Ti/Al/Mo/Au, Ti/Al/Ni/Au, Ti/Au and Ti/W, having 15-50 nm thickness, using spin coating technique or e-beam physical vapour deposition (VPD) of the stack metals. The deposition rates using the e-VPD technique were determined for the ohmic-stack metals using the Dektak Profilometer with dummy lift-off samples.

Step 4: Two-dimensional electron gas (2DEG) channel-pattering of the wafer obtained in Step 3 with argon- or nitrogen-ion implantation. Step 5: Plasma-enhanced chemical vapour deposition (CVD) of the ONO stack over the wafer obtained in Step 4. This is the stress-free technique to deposit the layer of the SiO-SiN- SiO stack having an exemplary thickness of about 200-300 nm and structured by the ICP- RIE dry etching, which is the CF4-based etching method. In this step, the pseudo conducting channel areas and ohmic electrical contact pads of the transistor become available.

Step 6: Optional lift-off deposition of an Au or Ti/W-CMOS-gate electrode (in case a gate electrode is to be deposited on the top layer of the heterojunction structure for an integrated MMIC-HEMT-based amplifier manufacturing).

Step 7 : Optional plasma-enhanced ALD pattering with RIE or HF above sensing area (in case the plasma-enhanced ALD layer deposited in Step 1 is removed separately to ONO stack). Step 8: Atomic layer etching (ALE) of the wafer obtained in Steps 5-7. This sophisticated technique carried out in the clean manufacturing cluster of the applicant is the only technique allowing the removal of individual atomic layers (the top atomic layers of the wafer). ALE is a way better-controlled technique than RIE, though it has not been commercially used until now because very sophisticated gas handling is required, and removal rates of one atomic layer per second are the real state of the art. This step is the step of creating the pseudo-conducting working point of the transistor, because ALE allows achieving the specific thickness of 5-9 nm thickness of the top layer in the open gate area with the extremely low surface roughness of the top layer below 0.2 nm.

Step 9: Optional plasma-enhanced CVD or ALD of the dielectric layer used for device passivation and in some gas sensors. Step 10: Optional deep reactive-ion etching (DRIE or Bosch process) of the Si-substrate under sensing areas (in case the substrate is on the free-standing membranes - used, for example, in RF-HEMTs, FBAR and SAW sensors). [0110] Reference is now made to Figs. 6a-6c showing the sensor, which is obtained in Step 4 of the 2DEG-channel pattering. The lithography of the sensor was performed with AZ 4533, which is a positive thick resist having optimised adhesion for common wet etching. The lithographic resist film thickness obtained at 7000-rpm spin speed and at 100° C for 1 min was 3 pm. Thus, as seen in the lithographic image of Fig. 6c, the formed 2DEG channel (13) is approximately 2-3 pm wide. The overall exposure time was 9 sec, followed by 5-min development in MIF726 developer.

[0111] Fig. 6d-6e show the mask and corresponding lithographic image, respectively, of the sensor layout of the present invention. Fig. 6f demonstrates the high alignment precision of ± 2-pm on 25 x 25 mm² samples in the lithography of the sensor layout of the present invention. Fig. 6g shows the lithographic images of the multichannel samples. Fig. 6h shows the fixed sensor chip sample on the Si-GaN/AlGaN wafer, which contains approximately 30-32 sensors with 4-8 channels on each sample and prepared for ion implantation. Fig. 6i shows the obtained lithographic image of the present sensor layout with the AZ4533 resist after development, prepared for ion implantation. Fig. 6j shows the 2DEG channels (dark) patterned by ion-implantation after the resist removal. The argon-ion implantation was conducted with 20 keV and 30 keV energies and with an exemplary dose of 2.5e¹³/cm² and a 7° tilt angle. AZ4533 was removed with oxygen plasma at 220 W for 10 min. Fig. 6k shows the visible non-implanted area containing the conductive 2DEG channel.

[0112] The atomic layer etching (ALE) performed in Step 8 of the manufacturing process is the most important stage in the process. As mentioned above, it allows the controlled recess of a top layer, removing a single atomic layer-by-layer, where the etch thickness is in the order of magnitude of a single atomic monolayer. As explained above, such ultra-low damage to the top layer of the heterogeneous structure, when the actual surface roughness is controlled by a single atomic monolayer, allows to achieve the sub-nanometre roughness (about 0.2 nm and less) of the top layer when its thickness is only few nanometres (5-9 nm). There are no known ways in the semiconductor technology which would allow to achieve such low roughness at this particular thickness of the semiconductor layer. Therefore, the manufacturing method developed by the present inventors is unique and made it possible to unexpectedly arrive to the pseudo-conducting structures of the present invention.

[0113] The ALE process sequence consists of repeated cycling of process conditions. The total amount of material removed is determined by the number of repeated cycles. Each cycle is typically comprised of four steps: adsorption, first purge, desorption and second purge. During the adsorption step of the cycle, reactive species are generated in the reactor (for example, upon plasma excitation), adsorbed by, and react with material on the wafer. Due to the self-limiting process, and with the proper choice of reactants and process conditions, reaction takes place with only a thin layer of material, and the reaction by-products are formed. This step is followed by purging of the reactor to remove all traces of the reactant. Then the by-product desorption takes place due to bombardment of the wafer surface by noble gas ions with a tightly controlled energy. Again, by-products are purged from the reactor, and the wafer is ready for the last two (optional) steps of the manufacturing process.

[0114] Reference is now made to Fig. 7a showing the AFM image of the top recessed layer surface of the PC-HEMT produced by the manufacturing process of the present invention. The measured RMS value of the surface roughness is 0.674 nm in this case. Fig. 7b shows the AFM surface image of the top recessed layer of the HEMT made by a conventional manufacturing process. In this conventional process, the HEMT initially had a top ultrathin-grown AlGaN layer of the 6-7 nm thickness. This layer was recessed with inductively-coupled plasma (ICP) for 60 sec using a conventional reactive-ion etching (RIE) technique. The measured RMS value of the surface roughness is 1.211 nm in this case. Figs. 7c show the time -dependent plot of the drain-source electric current IDS of the nitrogen oxide sensor measuring 100 ppb of the NO2 gas in 80%-humid air, where the sensor incorporates the PC-HEMT made by the manufacturing process of the present invention. Figs. 7d show the time-dependent plot of the IDS of the nitrogen oxide sensor measuring 100 ppb of the NO2 gas in 80%-humid air, where the sensor incorporates and based on the HEMT made by the conventional manufacturing process. It is clear from these comparative examples that the manufacturing process of the present invention based on the ultra-low damaging RIE with a narrow plasma-ion energy distribution leads to much lower roughness of the semiconductor surface, which in turn leads to incredibly high sensitivity of the sensor.

[0115] In a further aspect, the hetero-junction structure may be a three-layer structure consisting of two GaN layers and one AlGaN layer squeezed between said buffer layers like in a sandwich, wherein the top layer is a buffer layer. This may lead to formation of the two-dimensional hole gas (2DHG) in the top GaN layer above the AlGaN layer which results in reversing polarity of the transistor compared to the two-layer structure discussed above.

[0116] In general, polarity of III-V nitride semiconductor materials strongly affects performance of the transistors based on these semiconductors. The quality of the wurtzite GaN materials can be varied by their polarity, because both the incorporation of impurities and the formation of defects are related to the growth mechanism, which in turn depends on surface polarity. The occurrence of the 2DEG/2DHG and the optical properties of the hetero-junction structures of nitride -based materials are influenced by the internal field effects caused by spontaneous and piezo-electric polarizations. Devices in all of the III-V nitride materials are fabricated on polar {0001 } surfaces. Consequently, their characteristics depend on whether the GaN layers exhibit Ga-face positive polarity or N-face negative polarity. In other words, as a result of the wurtzite GaN materials polarity, any GaN layer has two surfaces with different polarities, a Ga-polar surface and an N-polar surface. A Ga-polar surface is defined herein as a surface terminating on a layer of Ga atoms, each of which has one unoccupied bond normal to the surface. Each surface Ga atom is bonded to three N atoms in the direction away from the surface. In contrast, an N-polar surface is defined as a surface terminating on a layer of N atoms, each of which has one unoccupied bond normal to the surface. Each surface N atom is also bonded to three Ga atoms in the direction away from the surface. Thus, the N-face polarity structures have the reverse polarity to the Ga-face polarity structures.

[0117] As described above for the two-layer heterojunction structure, the barrier layer is always placed on top of the buffer layer. The layer which is therefore recessed in the two-layer heterojunction structure is the barrier layer, specifically the AlGaN layer. As a result, since the 2DEG is used as the conducting channel and this conducting channel is located slightly below the barrier layer (in a thicker region of the GaN buffer layer), the hetero-junction structure is grown along the {0001} -direction or, in other words, with the Ga-face polarity. However, as explained above, the physical mechanism that leads to the formation of the 2DEG is a polarisation discontinuity at the AlGaN/GaN interface, reflected by the formation of the polarisation-induced fixed interface charges that attract free carriers to form a two-dimensional carrier gas. It is a positive polarisation charge at the AlGaN/GaN interface that attracts electrons to form 2DEG in the GaN layer slightly below this interface.

[0118] As noted above, polarity of the interface charges depends on the crystal lattice orientation of the hetero-junction structure, i.e. Ga-face versus N-face polarity, and the position of the respective AlGaN/GaN interface in the hetero-junction structure (above or below the interface). Therefore, different types of the accumulated carriers can be present in the hetero-junction structure of the embodiments.

[0119] In case of the three-layer hetero-junction structure, there are four possible configurations: Ga-face polarity

1) The Ga-face polarity is characterised by the 2DEG formation in the GaN layer below the AlGaN barrier layer. This is actually the same two-layer configuration as described above, but with addition of the top GaN layer. In this configuration, the AlGaN barrier layer and two GaN layers must be nominally undoped or n-type doped.

2) In another Ga-face configuration shown in Fig. 8a, in order to form the conducting channel comprising a two-dimensional hole gas (2DHG) in the top GaN layer above the AlGaN barrier layer in the configuration, the AlGaN barrier layer should be p-type doped (for example, with Mg or Be as an acceptor) and the GaN buffer layer should be also p-type doped with Mg, Be or intrinsic.

N-face polarity

3) The N-face polarity is characterised by the 2DEG formation in the top GaN layer above the AlGaN barrier layer, as shown in Fig. 8b. In this case, the AlGaN barrier layer and two GaN buffer layers must be nominally undoped or n-type doped.

4) The last configuration assumes that the 2DHG conducting channel is formed in the buffer GaN layer below the AlGaN barrier layer. The top GaN layer may be present (three-layer structure) or not (two-layer structure) in this case. The AlGaN barrier layer must be p-type doped (for example, with Mg or Be as an acceptor) and the bottom GaN layer should be also p-type doped with Mg, Be or intrinsic.

[0120] Thus, there are four hetero-junction three-layer structures implemented in the transistor of the embodiments, based on the above configurations:

A. Ga-Face GaN/AlGaN/GaN heterostructure with the 2DEG formed in the GaN buffer layer below the AlGaN barrier layer. In this case, the top GaN layer may be omitted to obtain the two-layer structure. For the three-layer structure, the top GaN layer must be recessed to 1-9 nm thickness in the open gate area or grown with this low thickness, with the roughness below 0.2 nm, and the thickness of the AlGaN barrier can be adjusted properly during growth

B. Ga-Face GaN/AlGaN/GaN heterostructure with the 2DHG conducting channel formed in the top GaN layer above the AlGaN barrier layer. The top GaN layer must be recessed to 5-9 nm thickness in the open gate area with the roughness below 0.2 nm, and the thickness of the AlGaN barrier layer can be adjusted properly. P-type doping concentrations of the GaN layer and AlGaN barrier have to be adjusted; the 2DHG has to be contacted (in the ideal case by ohmic contacts).

C. N-Face GaN/AlGaN/GaN heterostructure with the 2DEG in the top GaN layer above the AlGaN barrier layer. The top GaN layer must be recessed to 5-9 nm thickness in the open gate area with the roughness below 0.2 nm. Thickness of the AlGaN barrier can be adjusted during growth. N-type doping levels of the GaN buffer layer and the AlGaN barrier layer must be adjusted; the 2DEG has to be contacted (in the ideal case by ohmic contacts).

D. N-Face GaN/AlGaN/GaN heterostructure with the 2DHG in the GaN buffer layer below the AlGaN barrier layer. In this case, the top GaN layer may be omitted to obtain the two-layer structure. In both, the two-layer and three-layer configurations, the top GaN layer must be recessed to 1-9 nm thickness in the open gate area with the roughness below 0.2 nm, and the thickness of the AlGaN barrier can be adjusted properly.

[0121] In all the above structures, the deposition of a dielectric layer on top might be beneficial or even necessary to obtain a better confinement (as in case of the N-face structures). As shown, for example, in Fig. 8c, for the above "C" structure, it may be even more beneficial to include an ultrathin (about 1 nm) AIN or AlGaN barrier layer with high Al-content on top of the 2DEG channel to improve the confinement.

[0122] The preferable structures of the embodiments are structures "B", "C" and "D". In the structure "B", the 2DHG conducting channel formed in the top GaN layer, which has a higher chemical stability (particularly towards surface oxidation) than the AlGaN layer. Concerning the structure "C", the 2DEG conducting channel might be closer to the surface. Therefore, the electron mobility might be lower than in the 2DEG structure with the Ga-face polarity. The structure "D" has also the N-face polarity and the 2DHG channel close to the surface. In general, the polarity of the heterostructure can be adjusted by the choice of the substrate (e.g. C-face SiC) or by the growth conditions.

[0123] Based on the above, one of the aspects of the present invention is an open-gate pseudo- conductive high-electron mobility transistor (PC-HEMT) for non-invasively receiving and processing neural signals from brain, compound muscle action potentials (CMAPs), sensory nerve action potentials (SNAPs) or signals associated with an encephalogram or electromyogram, comprising either:

1) one AlGaN barrier layer at the top of the structure recessed in the open gate area to the thickness of 5-9 nm with the surface roughness of 0.2 nm or less, and one GaN buffer layer at the bottom of the structure; said layers having Ga-face polarity, thus forming the two- dimensional electron gas (2DEG) conducting channel in said GaN layer, close to the interface with said AlGaN layer; or

2) one GaN layer at the top of the structure recessed in the open gate area to the thickness of 5-9 nm with the surface roughness of 0.2 nm or less, one GaN buffer layer at the bottom of the structure, and one AlGaN barrier layer in between; said layers having the Ga-face polarity, thus forming the two-dimensional hole gas (2DHG) conducting channel in the top GaN layer, close to the interface with said AlGaN barrier layer; or

3) one GaN layer at the top of the structure recessed in the open gate area to the thickness of 5-9 nm with the surface roughness of 0.2 nm or less, one GaN buffer layer at the bottom of the structure, and one AlGaN barrier layer in between; said layers having the N-face polarity, thus forming the two-dimensional electron gas (2DEG) conducting channel in the top GaN layer, close to the interface with said AlGaN barrier layer; or

4) one AlGaN barrier layer at the top of the structure recessed in the open gate area to the thickness of 5-9 nm with the surface roughness of 0.2 nm or less, and one GaN buffer layer at the bottom of the structure; said layers having N-face polarity, thus forming the two- dimensional hole gas (2DHG) conducting channel in said GaN layer, close to the interface with said AlGaN layer.

[0124] In another aspect of the present disclosure, Fig. 9a schematically illustrates an inter-chip network for non-invasively receiving and processing neural signals from brain, compound muscle action potentials (CMAPs), sensory nerve action potentials (SNAPs) or signals associated with an encephalogram or electromyogram, said inter-chip network comprising:

(A) A plurality of microelectronic sensors or systems-on-chip (1) configured to receive and process neural signals from brain or signals associated with encephalogram, said sensors or systems-on-chip (1) are integrated inside said inter-chip network in rows and in columns, thereby forming a spatial array (900), wherein each of said sensors or systems-on-chip (1) is connected to its dedicated electrical contact in a contact array (2) (see Fig. 2; it is not visible in the present figure);

(B) A row multiplexer (901) connected to said contact array (2) for addressing each and every sensor or system-on-chip (1) arranged in rows, selecting one of several analogue or digital input signals and forwarding the selected input into a single line;

(C) A column multiplexer (902) connected to said contact array (2) for addressing each and every sensor or system-on-chip arranged in columns, selecting one of several analogue or digital input signals and forwarding the selected input into a single line; and

(D) An integrated circuit (903) for storing and processing said neural signals from brain or signals associated with encephalogram; characterised in that each of said microelectronic sensors or systems-on-chip (1) comprises an open-gate pseudo-conductive high-electron mobility transistor, said transistor comprising:

1) A multilayer hetero-junction structure being made of III-V single- or poly crystalline semi conductor materials and deposited on a substrate layer (10) or placed on a free-standing membrane (21), said structure comprising at least one buffer layer (11) and at least one barrier layer (12), said layers being stacked alternately, wherein the thickness of a top (barrier or buffer) layer in an open gate area (17) of said transistor is 5-9 nanometre (nm), which corresponds to the pseudo-conducting current range between normally-on and normally-off operation mode of the transistor, and the surface of said top layer has a roughness of about 0.2 nm or less;

2) A conducting channel (13) comprising a two-dimensional electron gas (2DEG) or a two- dimensional hole gas (2DHG), formed at the interface between said buffer layer (12) and said barrier layer (11) and providing electron or hole current in said transistor between source and drain contacts (15);

3) The source and drain contacts (15) connected to said 2DEG or 2DHG conducting channel (13) and to electrical metallisations (14) for connecting said transistor to an electric circuit; and

4) The open gate area (17) between said source and drain contacts (15).

[0125] The PC-HEMT of the invention may further comprise a metamaterial antenna electrode placed on the top layer between said source and drain contacts (15) in the open gate area (17) of the transistor in order to enable detection of electrical signals in the THz or sub-THz frequency range of approximately 30 GHz to 300 THz. For example, the PC-HEMT of the present invention comprises an Aharonov-Bohm metamaterial antenna electrode developed by the present inventors, described in detail in WO 2020188389 Al, and incorporated herein by reference. This electrode is placed on the top layer between said source and drain contacts (15) in the open gate area (17) of the transistor in order to enable detection of electrical signals in the frequency range of 30 GHz to 300 THz.

[0126] As mentioned above, an electrical connection of the multilayer heterojunction structure to the 2DEG or 2DHG channel can be realised via capacitive coupling to the electrical metallisations through a Schottky barrier contact. In that case, since the source and drain contacts are non-ohmic (i.e. capacitively-coupled), the DC readout cannot be carried out. Therefore, in order to electrically contact the 2DEG/2DHG channel underneath, about 5-20 nm bellow the electrical metallisations, the AC-frequency regime must be used. In other words, the AC readout or impedance measurements of the electric current flowing through the 2DEG/2DHG-channel should be performed in this particular case. The capacitive coupling of the non-ohmic metal contacts with the 2DEG/2DHG channel becomes possible only if sufficiently high AC frequency, higher than 30 kHz, is applied to the metallisations. To sum up, the electrical metallisations, which are capacitively coupled to the 2DEG/2DHG channel utilise the known phenomenon of energy transfer by displacement currents. These displacement currents are induced by existing electrical fields between the electrical metallisations and the 2DEG/2DHG conducting channel operated in the AC frequency mode through the Schottky contact as explained above.

[0127] Reference is now made to Fig. 9b schematically showing the inter-chip network of the present invention with the integrated circuit (903) for receiving and processing neural signals from brain or signals associated with encephalogram, said integrated circuit (903) comprising:

1) A voltage source (904) connected to an electric circuit for supplying electric power to the network;

2) An integrated or CMOS current amplifier (905) connected to said array (900) for amplification of an electric current obtained from the sensors or systems-on-chip (1);

3) An integrated waveform generator (906) for generating frequency of a sinusoidal electric stimulation;

4) An analogue-to-digital converter (907) with in-built digital input/output connected to said current amplifier (905) for outputting the converted signal to a user interface or external memory (908); and

5) (i) A connection module (909) for wired connection of the inter-chip network to said user interface or external memory (908); or

(ii) A wireless connection module (910) for wireless connection of the inter-chip network to said user interface or external memory (908).

[0128] In a further aspect of the present disclosure, Fig. 9c illustrates the inter-chip network of the present invention with the integrated circuit (903) for receiving and processing neural signals from brain or signals associated with encephalogram, said integrated circuit (903) comprising:

1) an ASIC (Application-Specific Integrated Circuit) chip (911) customised for a particular use of the inter-chip network;

2) a battery or power receiver (912) connected to an electric circuit for supplying electric current to the network; and 3) a wireless connection module (913) for wireless connection of the inter-chip network to a user interface or external memory (908).

[0129] The ASIC chip (911) may include an amplifier for amplification of an electric current obtained from the sensors or systems-on-chip (1), an additional voltage source, such as a battery, for powering the sensors or systems-on-chip (1), a waveform function generator for generating frequency of a sinusoidal electric stimulation, and decoders.

[0130] In a specific embodiment, the wireless connection module (910 or 913) may be a short- range Bluetooth^® or NFC providing wireless communication between the sensor and the readout module for up to 20 m. If the connection module is Wi-Fi, the connection can be established with a network for up to 200 nm, while GSM allows the worldwide communication to a cloud. The external memory can be a mobile device (such as a smartphone), desktop computer, server, remote storage, internet storage or cloud.

[0131] In a further aspect of the present invention, the combined transducer principle defined herein as a "multiparametric readout" includes: DC electronic readout of the sensor, AC electronic readout of the sensor and temperature sensing. The PC-HEMT -based sensor of the present invention therefore further comprises a reference or counter electrode and characterised with respect to its electronic properties and the measurement configuration for neural sensing. The main features of the sensors or systems-on-chip of the present invention are determined by the transfer characteristics and the output characteristics at room temperature. The transfer characteristics shows the drain current of the PC-HEMTs as a function of their source voltage at constant drain-source voltages. [0132] In a specific embodiment, the microelectronic sensor or system-on-chip (1) of the present invention for receiving and processing neural signals from brain or signals associated with an encephalogram comprises the following components:

(a) the PC-HEMT of the present invention, or an array thereof, wherein each of said transistors is connected to its dedicated electrical contact line (thereby constituting a sensing channel);

(b) a voltage source connected to said electrical contact lines via an electric circuit for supplying electric current to said transistors;

(c) an integrated or CMOS current amplifier connected to said voltage source for amplification of an electric current obtained from said transistor/s;

(d) an analogue-to-digital converter (ADC) with in-built digital input/output card connected to said current amplifier for converting the received analogue signal to a digital signal and outputting said digital signal to a microcontroller unit; (e) the microcontroller unit (MCU) for processing and converting the received digital signal into data readable in a user interface or external memory; and

(f) a wireless connection module for wireless connection of said microelectronic sensor to said user interface or external memory.

[0133] The ADC card may be any suitable analogue-to-digital converter data logger card that can be purchased, for example, from National Instruments^® or LabJack^®. Optionally, the current amplifier can be operated directly with current flowing via the conducting 2DEG channel into the amplifier with small input resistance of 1MW at gain higher than 10⁴ and only 1W at gains lower than 200. This setup may directly amplify the electric current modulation in the 2DEG channel originated from external body charges.

[0134] Alternatively, the PC-HEMT of the invention may be based on a piezoelectric electro- optical crystal (EOC) transducer. The PC-HEMT based on the EOC piezoelectric substrate exhibits the highest coupling between electrical and mechanical energy compared to all other varieties of substrates. Additionally, such a substrate also has the advantages of having a high velocity-shift coefficient and a very high electromechanical coupling coefficient, K2, which yields a greater mass sensitivity in comparison with the same regular SAW device on any other piezoelectric substrates. The EOC may be any suitable electro-optical crystalline material such as LiNbOs, which is brought into a contact with medium to be sensed. The EOC is then illuminated with a polarised light.

[0135] In case of the LiNbOs crystalline material, the wavelength of the polarised light is about 400-600 nm. Modulated light from the light source illuminates the substrate with the EOC, and then falls on the 2DEG structure. The 2DEG structure is ultrasensitive to an incident light creating the p- n- pairs in the top recessed layer and as a result, strongly affecting the 2DEG conductivity. In general, irradiation of the 2DEG structure with light switches the 2DEG channel from normally-off to a pseudo-conducting or normally-on state. Therefore, being in a close proximity to the ionic cloud, the EOC is capable of changing its light absorbance strongly affecting electrical current in the 2DEG channel, thereby resolving any smallest light intensity changes coming from the EOC transducer. Depending on the excitation light wavelength, the position of the sensor relative to the incident light beam can be changed. For instance, in case of IR light (700-1500 nm), the sensor should be placed perpendicularly to the light beam for achieving the highest sensitivity. The parasitic charging of the EOC is compensated via the electrodes attached to the crystal. Additionally, a variety of light filters in front of the sensor can be utilised. Thus, the use of the EOC configuration of the PC-HEMT of the invention makes it possible to drastically increase sensitivity of the sensor to an electrical charge.

[0136] In a further specific embodiment, the microelectronic sensor or system-on-chip (1) of the present invention for non-invasively receiving and processing neural signals from brain, compound muscle action potentials (CMAPs), sensory nerve action potentials (SNAPs) or signals associated with an encephalogram or electromyogram comprises the following components:

(b) a modulated light source, such as a surface -mounted-device light-emitting diode (SMD LED) or UV-VIS-IR laser diode, for irradiating the top layer surface of said transistors;

(c) a voltage source connected to said electrical contact lines via an electric circuit for supplying electric current to said transistors;

(d) a lock-in amplifier connected to said voltage source for amplification of a signal with a known carrier wave obtained from said transistors and increasing the signal-to-noise ratio;

(e) an analogue-to-digital converter (ADC) with in-built digital input/output card connected to said lock-in amplifier for outputting the converted signal to a user interface;

(f) a feedback control microcontroller unit (MCU) for energy level adjustment and de-trapping via an external or integrated gate electrode; and

(g) a wireless connection module for wireless connection of the sensor to a readout module; wherein said readout module comprises another wireless connection module connecting the sensor to said user interface via a digital-to-analogue converter (DAC).

[0137] In some embodiments, the sensors or systems-on-chip of the present application can be used for portable long-time-operation solution within the external memory, which is a remote cloud- based service. The portable sensor or system-on-chip of an embodiment should have a very small power consumption saving the battery life for a prolong usage. In this case, the non-ohmic high- resistive contacts capacitively connecting the sensor to an electric circuit are preferable. The non- ohmic contacts actually limit an electric current flowing through the 2DEG/2DHG channel by having an electrical resistance 3-4 times higher than the resistance of the 2DEG/2DHG-channel, thereby reducing electrical power consumption without sacrificing sensitivity and functionality of the sensor. Thus, the use of non-ohmic contacts in some embodiments of the sensor of the present application is a hardware solution allowing minimising the power consumption of the device. In another embodiment, the power consumption of the device can be minimised using a software algorithm managing the necessary recording time of the sensor and a battery saver mode, which limits the background data and switches the wireless connection only when it is needed.

[0138] While certain features of the present application have been illustrated and described herein, many modifications, substitutions, changes, and equivalents will be apparent to those of ordinary skill in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the present application.

Claims

1. A non-invasive method for receiving and processing neural signals from brain of a patient, compound muscle action potentials (CMAPs), sensory nerve action potentials (SNAPs) or signals associated with an encephalogram or electromyogram, comprising:

I. providing a microelectronic sensor comprising an open-gate, pseudo-conductive, high- electron mobility transistor (PC-HEMT) or an array thereof, wherein said transistor comprises: a) a multilayer hetero-junction structure made of gallium nitride (GaN) and aluminium gallium nitride (AlGaN) single-crystalline or polycrystalline semiconductor materials and deposited on a substrate layer (10) or placed on a free-standing membrane (21), said structure comprising at least one buffer layer (11) and at least one barrier layer (12), said layers being stacked alternately; b) a conducting channel (13) comprising a two-dimensional electron gas (2DEG) or a two-dimensional hole gas (2DHG), formed at the interface between said buffer layer

(12) and said barrier layer (11) and upon applying a bias to said transistor, becoming capable of providing electron or hole current, respectively, in said transistor between source and drain contacts (15); c) the source and drain contacts (15) connected to said 2DEG or 2DHG conducting channel (13) and to electrical metallisations (14) for connecting said transistor to an electric circuit; and d) an open gate area (17) between said source and drain contacts (15); said transistor is characterised in that the thickness of a top (barrier or buffer) layer ( 11 or 12) of said heterojunction structure in the open gate area (17) is 5-9 nanometres (nm) and the surface of said top layer (11 or 12) has a roughness of 0.2 nm or less, wherein the combination of said thickness and said roughness of the top layer (11 or 12) creates a quantum electronic effect of operating said 2DEG or 2DHG channel (13) simultaneously in both normally-on and normally-off operation modes of the channel

(13), thereby making said transistor to conduct electric current through said channel (13) in a quantum well between normally-on and normally-off operation modes of the transistor;

II. contacting a single sensing point on the patient's body with, or remotely positioning in a space against the patient's body, said microelectronic sensor; III. recording neural signals or action potentials received from the patient's body in a form of a source-drain electric potential of said transistor over time (defined as V_DS dynamics) with said microelectronic sensor;

VI. displaying said medical data in a form of a visual, graphical or mathematical representation of the V_DS dynamics or any other readable format, thereby processing said neural signals from brain, said compound muscle action potentials (CMAPs), said sensory nerve action potentials (SNAPs) or signals associated with an encephalogram or electromyogram.

2. The method of claim 1, wherein said single sensing point on the patient's body is any point on a patient's head, or any patient's limb, an arm, an elbow, a forearm, a wrist, a palm or a finger.

3. The method of claim 1, wherein said microelectronic sensor is contactless and used remotely from a patient's body, being positioned in a space against the patient's body.

4. The method of claim 1, wherein said PC-HEMT further comprises a metamaterial antenna electrode placed on the top layer (11 or 12) between said source and drain contacts (15) in the open gate area (17) of the transistor and capable of detecting electrical signals in the frequency range of 30 GHz to 300 THz.

5. The method of claim 1, wherein the source and drain contacts (15) of said PC-HEMT are either ohmic or non-ohmic, and when said source and drain contacts (15) are non-ohmic, the electrical metallisations (14) of the PC-HEMT are capacitively coupled to 2DEG or 2DHG conducting channel (13) for inducing displacement currents, thereby creating said non-ohmic source and drain contacts.

6. The method of claim 1 , wherein the PC-HEMT further comprises a dielectric layer deposited on top of the multilayer hetero-junction structure.

7. The method of claim 1 , wherein the thickness of the top layer of the PC-HEMT in the open gate area (17) is 6 to 7 nm, or 6.2 nm to 6.4 nm; and the surface of said top layer has a roughness of 0.2 nm or less, or 0.1 nm or less, or 0.05 nm or less.

8. The method of claim 1, wherein said multilayer hetero-junction structure comprises:

A. (i) one top AlGaN layer (12) recessed in the open gate area (17) of the PC-HEMT to the thickness of 5-9 nm and having the surface roughness of 0.2 nm or less, and (ii) one bottom GaN buffer layer (11); said layers have Ga-face polarity, thus forming the two-dimensional electron gas (2DEG) conducting channel (13) in said GaN layer, close to the interface with said AlGaN layer; or

B. (i) one top GaN layer (11) recessed in the open gate area (17) of the PC-HEMT to the thickness of 5-9 nm and having the surface roughness of 0.2 nm or less, (ii) one bottom GaN buffer layer (11), and (iii) one AlGaN barrier layer (12) in between; said layers have Ga- face polarity, thus forming a two-dimensional hole gas (2DHG) conducting channel (13) in the top GaN layer, close to the interface with said AlGaN barrier layer; or

C. (i) one top GaN layer (11) recessed in an open gate area (17) of the PC-HEMT to the thickness of 5-9 nm and having the surface roughness of 0.2 nm or less, (ii) one bottom GaN buffer layer (11), and (iii) one AlGaN barrier layer (12) in between; said layers have N-face polarity, thus forming a two-dimensional electron gas (2DEG) conducting channel (13) in the top GaN layer, close to the interface with said AlGaN barrier layer; or

D. (i) one top AlGaN layer (12) recessed in an open gate area (17) of the PC-HEMT to the thickness of 5-9 nm and having the surface roughness of 0.2 nm or less, and (ii) one bottom GaN buffer layer (11); said layers have N-face polarity, thus forming a two-dimensional hole gas (2DHG) conducting channel (13) in the GaN buffer layer, close to the interface with said AlGaN barrier layer.

9. The method of claim 1, wherein the multilayer heterojunction structure further comprises a piezoelectric electro-optical crystal (EOC) transducer adapted to be illuminated with a polarised light.

10. The method of claim 1, wherein the microelectronic sensor further comprises:

(a) a voltage source connected to said PC-HEMT or the array thereof via an electric circuit for supplying electric current to said PC-HEMT/s; (b) an integrated or CMOS current amplifier connected to said voltage source for amplification of an electric current obtained from said PC-HEMT/s;

(c) an analogue-to-digital converter (ADC) with in-built digital input/output card connected to said current amplifier for converting the received analogue signal to a digital signal and outputting said digital signal to a microcontroller unit;

(d) the microcontroller unit (MCU) for processing and converting the received digital signal into data readable in a user interface or external memory; and

(e) a wired or wireless connection module for connecting said microelectronic sensor to said user interface, external memory or readout module.

11. The method of claim 1, wherein each PC-HEMT further comprises an excitation light source for irradiating the multilayer hetero-junction structure, thereby inducing a photoelectric current in the 2DEG or 2DHG conducting channel (13).

12. The method of claim 11, wherein said excitation light source is a laser diode or LED.

13. The method of any one of claims 10 to 12, wherein the microelectronic sensor further comprises:

(a) a modulated light source for irradiating said PC-HEMT or the array thereof;

(b) a lock-in amplifier connected to the voltage source for amplification of a signal with a known carrier wave obtained from said PC-HEMT/s and increasing the signal-to-noise ratio;

(c) an analogue-to-digital converter with in-built digital input/output card connected to said lock-in amplifier for outputting the converted signal to a user interface, external memory or readout module; and

(d) a feedback control microcontroller unit (MCU) for energy level adjustment and de -trapping via an external or integrated gate electrode.

14. The method of any one of claims 10 to 13, wherein the microelectronic sensor further comprises:

1) a reference electrode for remote potentiometric body charge detection, or

2) a gate electrode for discharging parasitic electric current.

15. The method of any one of claims 10 to 14, wherein said external memory is a personal gadget, mobile device, desktop computer, server, remote storage, internet storage or telemedicine cloud.

16. An inter-chip network for non-invasively receiving and processing of neural signals from brain, compound muscle action potentials (CMAPs), sensory nerve action potentials (SNAPs) or signals associated with an encephalogram or electromyogram, said inter-chip network comprising:

(A) A plurality of microelectronic sensors (1) of any one of claims 1 to 15 configured to non- invasively receive and process neural signals from brain, compound muscle action potentials (CMAPs), sensory nerve action potentials (SNAPs) or signals associated with an encephalogram or electromyogram, said microelectronic sensors (1) integrated inside said inter-chip network in rows and in columns, thereby forming a spatial array (900), wherein each of said microelectronic sensors (1) is connected to its dedicated electrical contact in a contact array (2);

17. The inter-chip network of claim 16, wherein said integrated circuit (903) comprising:

3) An integrated waveform generator (906) for generating frequency of a sinusoidal electric stimulation; 4) An analogue-to-digital converter (907) with in-built digital input/output connected to said current amplifier (905) for outputting the converted signal to a user interface or external memory (908); and

18. The inter-chip network of claim 16, wherein said integrated circuit (903) comprising:

2) A battery or power receiver (912) connected to an electric circuit for supplying electric current to the network; and

3) A wireless connection module (913) for wireless connection of the inter-chip network to a user interface or external memory (908).

19. The inter-chip network of claim 18, wherein said ASIC chip (911) comprises an amplifier for amplification of an electric current obtained from the sensors or systems-on-chip (1), an additional voltage source, such as a battery, for powering the sensors or systems-on-chip (1), a waveform function generator for generating frequency of a sinusoidal electric stimulation, and decoders.

20. The inter-chip network of any one of claims 16 to 19, wherein said inter-chip network is designed to be placed on the head of a patient or positioned over the head of the patient.