WO2021104516A1 - Method and apparatus for clock data recovery, phase detector and storage medium - Google Patents

Abstract

Disclosed by the present application are a method and apparatus for clock data recovery, a phase detector and a storage medium. The method comprises: acquiring a sampling signal and processing the sampling signal to obtain a reference symbol and an error component corresponding to the sampling signal, wherein when the sampling signal is a first sampling signal, the reference symbol and error component corresponding to the first sampling signal are a first reference symbol and a first error component respectively, when the sampling signal is a second sampling signal, the reference symbol and error component corresponding to the second sampling signal are a second reference symbol and a second error component respectively, and the first sampling signal and the second sampling signal are continuous in a time sequence; generating a logic relationship according to the first reference symbol, the first error component, the second reference symbol, and the second error component; and confirming the phase state of a sampling point according to a calculation result of the logic relationship.

Description

Method and device for clock data recovery, phase detector and storage medium

This application claims the priority of a Chinese patent application filed with the Chinese Patent Office with application number 201911205457.5 on November 29, 2019. The entire content of this application is incorporated into this application by reference.

Technical field

This application relates to the field of communications, such as a clock data recovery method, device, phase detector and storage medium.

Background technique

Clock Data Recovery (CDR) is an important part of the communication system receiver. The CDR is set to process the sampled data signal and recover the correct sampling clock phase to ensure the correctness of the received data signal. At present, most data signals are modulated in N-level Pulse Amplitude Modulation-N (PAM-N) mode. However, as the transmission rate of data signals continues to increase, the phase detector does not provide training sequences. , The phase discrimination interval will gradually decrease as the value of N increases.

Summary of the invention

The present application provides a clock data recovery method, device, phase detector and storage medium, which can ensure the size of the phase discrimination interval, broaden the lock capture range, reduce the phase capture time, and improve the performance of the clock data recovery circuit.

An embodiment of the present application provides a clock data recovery method, including:

Obtain the sampled signal and process the sampled signal to obtain the reference symbol and error component corresponding to the sampled signal. In the case where the sampled signal is the first sampled signal, the reference symbol corresponding to the first sampled signal is the first reference symbol, The error component corresponding to the first sampling signal is the first error component; when the sampling signal is the second sampling signal, the reference symbol corresponding to the second sampling signal is the second reference symbol, and the error component corresponding to the second sampling signal is the first Two error components, the first sampling signal and the second sampling signal are continuous in time sequence;

Generate a logical relationship according to the first reference symbol, the first error component, the second reference symbol, and the second error component;

According to the calculation result of the logical relationship, confirm the phase state of the sampling point.

The embodiment of the application provides a clock data recovery device, including: a signal sampling module, a signal processing module, a logic generation module, and a phase judgment module;

The signal sampling module is set to obtain the sampling signal;

The signal processing module is configured to process the sampled signal to obtain the reference symbol and error component corresponding to the sampled signal. In the case where the sampled signal is the first sampled signal, the reference symbol corresponding to the first sampled signal is the first reference symbol , The error component corresponding to the first sampling signal is the first error component; when the sampling signal is the second sampling signal, the reference symbol corresponding to the second sampling signal is the second reference symbol, and the error component corresponding to the second sampling signal is The second error component, the first sampling signal and the second sampling signal are continuous in time sequence;

A logic generation module, configured to generate a logic relationship based on the first reference symbol, the first error component, the second reference symbol, and the second error component;

The phase judgment module is set to confirm the phase state of the sampling point according to the calculation result of the logical relationship.

The embodiment of the present application provides a phase detector, including a processor, and the processor is configured to implement the method of any of the foregoing embodiments when a computer program is executed.

The embodiments of the present application also provide a computer-readable storage medium that stores a computer program, and when the computer program is executed by a processor, the method of any of the foregoing embodiments is implemented.

Description of the drawings

FIG. 1 is a schematic flowchart of a clock data recovery method provided by an embodiment;

FIG. 2 is a micro-architecture diagram of a logical relationship provided by an embodiment;

FIG. 3 is a simulation result of the phase detector corresponding to FIG. 2 provided by an embodiment;

4 is a schematic flowchart of another method for clock data recovery provided by an embodiment;

FIG. 5 is a diagram of another logical relationship micro-architecture provided by an embodiment;

FIG. 6 is a simulation result of the phase detector corresponding to FIG. 5 provided by an embodiment;

FIG. 7 is a schematic structural diagram of a clock data recovery device provided by an embodiment;

Fig. 8 is a schematic structural diagram of a phase detector provided by an embodiment.

Detailed ways

Hereinafter, the embodiments of the present application will be described in detail with reference to the accompanying drawings.

In communication systems (such as high-speed serial (optical) communication serializers and deserializers (SERializer/DESerializer, SerDes) system (hereinafter referred to as SerDes system)), CDR is a very important module, and CDR is set to The data signal sampled by the analog-to-digital converter (ADC) of the receiver is processed and the correct sampling clock phase is recovered to ensure the correctness of the received data signal. Therefore, the performance of CDR is very important to the link quality of the SerDes system. The core of the CDR is the phase detector. The performance of the phase detector is mainly affected by the sampling rate of the ADC, the size of the phase detector interval, the linearity of the phase detector and the magnitude of the phase detector gain.

At present, most of the data signals sampled by the ADC of the SerDes receiver are modulated in the PAM-N (N=2 ⁿ , n is a positive integer) mode. With the continuous improvement of the data signal transmission rate, on the one hand, for the 2 times baud rate phase detector (such as Bang-Bang phase detector), the demand for the sampling clock rate will become higher; on the other hand, for working in wave The phase detector under special rate (such as the Mueller-Muller phase detector), without providing a training sequence (ie, reference symbols, which are determined and generated from the data obtained by sampling), the phase detection interval will increase with the value of N Constantly increase and gradually decrease.

The embodiments of the present application provide a clock data recovery method, device, phase detector, and storage medium, which can ensure the size of the phase detection interval, broaden the lock capture range, reduce the phase capture time, and improve the performance of the clock data recovery circuit. performance.

The terms "system" and "network" in this application are often used interchangeably in this application. The terms "first", "second", etc. in the specification, claims, and drawings of this application are used to distinguish different objects, rather than to limit a specific order. The following embodiments of the present application can be executed individually, and the various embodiments can also be implemented in combination with each other, which is not limited by the embodiments of the present application.

In the following, the method and device for clock data recovery and its technical effects will be described.

FIG. 1 shows a schematic flow chart of a clock data recovery method provided by an embodiment. As shown in FIG. 1, the method provided in this embodiment is suitable for a phase detector (such as a Mueller-Muller phase detector), and the method includes Steps S110 to S130.

S110. Obtain a sampled signal, and process the sampled signal to obtain a reference symbol and an error component corresponding to the sampled signal.

The phase detector is a device that can identify the phase difference of the input signal (ie, the sampling signal), and is a circuit that makes the output voltage and the phase difference between the two input signals have a definite relationship. Therefore, when acquiring the sampling signal, at least two sampling signals can be acquired, and the at least two sampling signals can be processed to obtain the reference symbols and error components corresponding to the two sampling signals.

In one embodiment, the sampled signal is expressed in the form of twos complement code to ensure that the 0 or 1 obtained by the following symbol decision is the correct value that needs to be used for logic calculation.

In an embodiment, the method of processing the sampled signal to obtain the reference symbol and the error component corresponding to the sampled signal may include two steps of step 1 and step 2.

Step 1: Perform symbol decision on the sampled signal Sig(n) to obtain the reference symbol S[n] corresponding to the sampled signal Sig(n).

Optionally, the value of the reference symbol S[n] is 0 or 1. When S[n]=0, it means that the sampling signal Sig(n) is not a negative value; or, when S[n]=1, the sampling signal Sig(n) is a negative value. In this way, regardless of the value of N of PAM-N, the reference symbol has only two possible values, which greatly reduces the probability of misjudgment of the reference symbol.

Step 2: Obtain the error component corresponding to the sampling signal Sig(n) according to the sampling signal Sig(n) and the reference symbol S[n] corresponding to the sampling signal Sig(n).

Wherein, the method for obtaining the error component corresponding to the sampled signal in step 2 may include the following two steps of cyclically executing n times:

Step a): Eliminate the symbolic components of Sig(i) to obtain Sig(i-1), where Sig(i-1)=Sig(i)+(2*S[i]-1)*A/2 ^{( ni)} ;

Step b): Perform symbol judgment on Sig(i-1) to obtain S[i-1];

Let i take an integer from n to 1, repeat steps a) and b) n times, and use the obtained {S[n-1],S[n-2],...,S[0]} as the sampling signal Corresponding error components; it can be seen that the error components include n bit values, and the accuracy of the error signal has been qualitatively improved.

Among them, n is the smallest integer greater than or equal to log ₂ N, N is the number of PAM levels, and A is the average value of the absolute value of the sampled signal amplitude.

n is the smallest integer greater than or equal to log ₂ N: when log ₂ N is an integer, n=log ₂ N; when log ₂ N is not an integer, n is equal to the value of log ₂ N rounded up.

This application takes the acquisition of two sampling signals as an example. The two sampling signals are the first sampling signal and the second sampling signal. Then, when the sampling signal is the first sampling signal, the reference symbol corresponding to the first sampling signal is the first sampling signal. Reference symbol, the error component corresponding to the first sampling signal is the first error component; when the sampling signal is the second sampling signal, the reference symbol corresponding to the second sampling signal is the second reference symbol, and the error component corresponding to the second sampling signal is The second error component, the first sampling signal and the second sampling signal are continuous in time sequence. It can be understood that the first sampling signal may be located before the second sampling signal in time sequence, or may be located after the second sampling signal. The following embodiments are performed based on the first sampling signal being located before the second sampling signal in time sequence. Described (that is, the sequence number of the first sampled signal is k-1, and the sequence number of the second sampled signal is k). If the first sampling signal is behind the second sampling signal in time sequence, the sequence number of the second sampling signal should be k-1, and the sequence number of the first sampling signal should be k.

Take N=8 as an example, that is, the sampling signal is modulated in PAM-8 mode, n=log ₂ 8=3, then the first sampling signal is processed to obtain the first reference symbol and the first sampling signal corresponding to the first sampling signal. The error component process includes:

1) for the first sampling signal Sig (3) _k-1 symbol decisions, to obtain a first sampling signal Sig (3) _k-1 corresponding to the first reference symbol S [3] _k-1.

2) Eliminate the symbolic components of Sig(3) _k-1 to obtain Sig(2) _k-1 , where Sig(2) _k-1 = Sig(3) _k-1 +(2*S[3] _{k- 1} -1)*A.

3) Perform symbol judgment on Sig(2) _k-1 to obtain S[2] _k-1 .

4) Eliminate the symbolic components of Sig(2) _k-1 to obtain Sig(1) _k-1 , where Sig(1) _k-1 = Sig(2) _k-1 +(2*S[2] _{k- 1} -1)*A/2.

5) Perform symbol judgment on Sig(1) _k-1 to obtain S[1] _k-1 .

6) Eliminate the symbolic components of Sig(1) _k-1 to obtain Sig(0) _k-1 , where Sig(0) _k-1 = Sig(1) _k-1 +(2*S[1] _{k- 1} -1)*A/4.

7) Perform symbol judgment on Sig(0) _k-1 to obtain S[0] _k-1 .

8) Use the obtained {S[2] _k-1 , S[1] _k-1 , S[0] _k-1 } as the first error component corresponding to the first sampling signal.

Similarly, the process of processing the second sampling signal to obtain the second reference symbol and the second error component corresponding to the second sampling signal includes:

1) of the second sampling signal Sig (3) _k for symbol decision, to obtain a second sampling signal Sig (3) _k corresponding to the second reference symbol S [3] _k.

2) Eliminate the symbolic components of Sig(3) _k to obtain Sig(2) _k , where Sig(2) _k = Sig(3) _k + (2*S[3] _k -1)*A.

3) Perform symbol judgment on Sig(2) _k to obtain S[2] _k .

4) Eliminate the symbol components of Sig(2) _k to obtain Sig(1) _k , where Sig(1) _k = Sig(2) _k + (2*S[2] _k -1)*A/2.

5) Perform symbol judgment on Sig(1) _k to obtain S[1] _k .

6) Eliminate the symbol components of Sig(1) _k to obtain Sig(0) _k , where Sig(0) _k = Sig(1) _k + (2*S[1] _k -1)*A/4.

7) Perform symbol judgment on Sig(0) _k to obtain S[0] _k .

8) Use the obtained {S[2] _k , S[1] _k , S[0] _k } as the second error component corresponding to the second sampling signal.

S120: Generate a logical relationship according to the first reference symbol, the first error component, the second reference symbol, and the second error component.

Among them, according to the first reference symbol, the first error component, the second reference symbol, and the second error component, the generated logical relationship is as shown in formula (1):

among them,

Is the "exclusive OR" logic operation, ⊙ is the "exclusive OR" logic operation, & is the "AND" logic operation, ∪() _| is the continuous OR operation; k-1 is the serial number of the first sampled signal, and k is The sequence number of the second sampling signal, where n is _{the smallest integer greater than or equal to log 2} N, N is the number of PAM levels, and i is an integer from n-1 to 0 respectively.

The logic relationship is realized by logic operation, which reduces the realization sequence to approximately

That is, the time complexity is log ₂ (log ₂ N). among them

t _⊙ , t _& , t _| are the hardware realization time of an XOR gate, XOR gate, AND gate, or gate respectively,

It is round up operation.

S130: Confirm the phase state of the sampling point according to the calculation result of the logical relationship.

Exemplarily, if early=1 in formula (1), the phase of the sampling point is too early, and the sampling point needs to be shifted to the right; or,

If late=1 in formula (1), the phase of the sampling point is late, and the sampling point needs to be shifted to the left; or,

If early=0 in formula (1) and late=0, the phase of the sampling point remains unchanged.

Some exemplary implementation manners are listed below to illustrate the clock data recovery method provided in FIG. 1 in the embodiments of the present application. In the following embodiments, N=4 is taken as an example, that is, the sampling signal is modulated in the PAM-4 mode, and n=log ₂ 4=2.

It is defined that the amplitude distribution of the sampled PAM-N signal is symmetrical about 0 (that is, the statistical average of the amplitude is 0). Assuming that the four reference level amplitudes corresponding to the sampled signal are {-1, -1/3, +1/3, +1}, that is, the average value of the absolute value of the sampled signal amplitude is 2/3, and the sampled signal adopts Represented in two's complement form.

Step 1: Process the first sampled signal.

First sampling signal (2) _k-1 is represented by Sig, the first sampling signal Sig (2) _k-1 symbol decision performed to obtain a first sampling signal Sig (2) _k-1 corresponding to the first reference symbol S [ 2] _k-1 . Among them, when S[2] _k-1 =0, it means Sig(2) _{k-1 is} not negative; when S[2] _k-1 =1, it means Sig(2) _k-1 is negative .

Eliminate the symbolic components of Sig(2) _k-1 to obtain Sig(1) _k-1 , where Sig(1) _k-1 = Sig(2) _k-1 +(2*S[2] _k-1- 1)*2/3. And perform symbol judgment on Sig(1) _k-1 to obtain S[1] _k-1 . Among them, when S[1] _k-1 =0, it means that Sig(1) _{k-1 is} not negative; when S[1] _k-1 =1, it means Sig(1) _k-1 is negative .

Eliminate the symbolic components of Sig(1) _k-1 to obtain Sig(0) _k-1 , where Sig(0) _k-1 = Sig(1) _k-1 +(2*S[1] _k-1- 1)*1/3. And perform symbol judgment on Sig(0) _k-1 to obtain S[0] _k-1 . Among them, when S[0] _k-1 =0, it means that Sig(0) _{k-1 is} not negative; when S[0] _k-1 =1, it means Sig(0) _k-1 is negative .

It can be seen that the first reference symbol of the first sampling signal is S[2] _k-1 , and the first error component of the first sampling signal is {S[1] _k-1 , S[0] _k-1 }.

Step 2: Process the second sampled signal.

Second sampling signal (2) _k is represented by Sig, a second sampling signal Sig (2) _k for symbol decision, the second reference symbol to obtain a second sampling signal Sig (2) _k corresponding to S [2] _k. Among them, when S[2] _k =0, it means that Sig(2) _{k is} not a negative value; when S[2] _k =1, it means that Sig(2) _k is a negative value.

Eliminate the symbolic components of Sig(2) _k to obtain Sig(1) _k , where Sig(1) _k = Sig(2) _k + (2*S[2] _k -1)*2/3. And perform symbol judgment on Sig(1) _k to obtain S[1] _k . Among them, when S[1] _k =0, it means that Sig(1) _{k is} not a negative value; when S[1] _k =1, it means that Sig(1) _k is a negative value.

Eliminate the symbol components of Sig(1) _k to obtain Sig(0) _k , where Sig(0) _k = Sig(1) _k + (2*S[1] _k-1 -1)*1/3. And perform symbol judgment on Sig(0) _k to obtain S[0] _k . Among them, when S[0] _k =0, it means that the sampling signal Sig(0) _{k is} not a negative value; when S[0] _k =1, it means that the sampling signal Sig(0) _k is a negative value.

It can be seen that the second reference symbol of the second sampling signal is S[2] _k , and the second error component of the second sampling signal is {S[1] _k , S[0] _k }.

Step 3: Generate logical relationships.

From the first and second steps, the first reference symbol of the first sampled signal is S[2] _k-1 , and the first error component of the first sampled signal is {S[1] _k-1 , S[0 ] _k-1 }, the second reference symbol of the second sampling signal is S[2] _k , and the second error component of the second sampling signal is {S[1] _k ,S[0] _k }, referring to equation (1 )Available:

Among them, FIG. 2 shows a logical relationship micro-architecture diagram provided by an embodiment.

Step 4: Confirm the phase status of the sampling point.

According to the logical relationship obtained in the third step, the result of the logical relationship is calculated. If early=1, it means that the phase of the sampling point is too early, and the sampling point needs to be shifted to the right; or, if late=1, it means that the phase of the sampling point is late, and the sampling point needs to be shifted to the left; or, if early=0 , And late=0, it means that there is no clear signal sooner or later, and the phase of the sampling point remains unchanged.

Fig. 3 shows a simulation result of the phase detector corresponding to Fig. 2 provided by an embodiment. It is a comparison chart of phase discrimination curves obtained through numerical simulation in the presence of phase noise with the same standard deviation. It can be seen from Figure 3 that the dotted line is the phase detection curve of the traditional Mueller-Muller (MM) phase detector, and the solid line is the phase detection curve of the phase detector corresponding to Figure 2; the horizontal axis represents the phase difference, and the unit is send/ The unit interval (Unit Interval, UI) of receiving the sampled signal, the vertical axis represents the relative value of the average output value of the phase detector under the corresponding phase difference, where the slope of the line between the point on the curve and the origin is the phase detector gain Relative value, the relative value of the phase discrimination gain is used to compare the relative magnitude of different phase discrimination gains.

The implementation of the clock data recovery method provided by the embodiment of the application has nothing to do with the circuit process, and does not require sampling at 2 times the baud rate, and the value of N changes, and the phase discrimination interval can be maintained between -π～+π. The phase point starts to capture. The phase detection gain changes more smoothly in the effective phase detection interval, which broadens the lock capture range, reduces the phase capture time, and significantly improves the performance of the clock data recovery circuit. At the same time, the traditional numerical calculation method is improved and simplified into a digital logic method, which reduces the complexity and power consumption of the hardware.

Figure 4 shows a schematic flowchart of another clock data recovery method provided by an embodiment. As shown in Figure 4, the method provided by this embodiment is suitable for a phase detector (such as a Mueller-Muller phase detector). Compared with the clock data recovery method shown in 1, when the average value of the absolute value of the sampled signal amplitude is 2 ^j (j is an integer), the process of processing the sampled signal can be simplified, and the symbol decision of the sampled signal is no longer necessary. And the operation of eliminating symbolic components. The method includes steps S210 to S230.

S210. Obtain a sampled signal, use the highest bit of the sampled signal as the reference symbol S[n] corresponding to the sampled signal, and after logically invert the n bits starting from the bit ^{representing the real signal with an amplitude of 2 j,} As the error component corresponding to the sampling signal {S[n-1],S[n-2],...,S[0]}; where n is _{the smallest integer greater than or equal to log 2} N, and N is the level of PAM number.

The phase detector is a device that can identify the phase difference of the input signal (ie, the sampling signal), and is a circuit that makes the output voltage and the phase difference between the two input signals have a definite relationship. Therefore, when acquiring the sampling signal, at least two sampling signals can be acquired, and the at least two sampling signals can be processed to obtain the reference symbols and error components corresponding to the two sampling signals.

In one embodiment, the sampled signal is expressed in the form of twos complement to ensure that the expression form 0 or 1 is the correct value that needs to be used for logic calculation.

It should be noted that the sampling signal needs to meet the following requirements: the sampling signal starts from ^{the bit representing the real signal with an amplitude of 2 j} , and the number of bits included after the bit with the amplitude of 2 ^{j is greater than or equal to n-1.} Otherwise, the n bits cannot be taken out for logical inversion as the error component corresponding to the sampling signal.

This application takes the acquisition of two sampling signals as an example. The two sampling signals are the first sampling signal and the second sampling signal. Then, when the sampling signal is the first sampling signal, the reference symbol corresponding to the first sampling signal is the first sampling signal. Reference symbol, the error component corresponding to the first sampling signal is the first error component; when the sampling signal is the second sampling signal, the reference symbol corresponding to the second sampling signal is the second reference symbol, and the error component corresponding to the second sampling signal is The second error component, the first sampling signal and the second sampling signal are continuous in time sequence. It can be understood that the first sampling signal may be located before the second sampling signal in time sequence, or may be located after the second sampling signal.

Take N=16 as an example, that is, the sampling signal is modulated in PAM-16 mode, n=log ₂ 16=4, then, suppose the highest 5 bits of the twos complement of the first sampling signal are 11100, and the second from the left One bit 1 indicates that the amplitude of the real signal is 2 ^j . The most significant bit of the first sampling signal as a first sampling signal corresponding to the first reference symbol S [4] _k-1, and represents the magnitude of the real signal is 2 ^j bits 4 bits starting with 1 (1100 ) Respectively logically inverted as the first error component corresponding to the first sampling signal {S[3] _k-1 ,S[2] _k-1 ,S[1] _k-1 ,S[0] _k-1 } .

In the same way, it is assumed that the highest five bits of the two's complement code of the second sampled signal are 11010, and the second bit from the left 1 indicates that the amplitude of the real signal is 2 ^j . Take the most significant bit 1 of the second sampling signal as the second reference symbol S[4] _k corresponding to the second sampling signal, and indicate that the real signal's amplitude is 2 ^j and the 4 bits (1010) starting from bit 1 are logically respectively After being inverted, it is used as the second error component {S[3] _k , S[2] _k , S[1] _k , S[0] _k } corresponding to the second sampling signal.

S220: Generate a logical relationship according to the first reference symbol, the first error component, the second reference symbol, and the second error component.

Among them, according to the first reference symbol, the first error component, the second reference symbol, and the second error component, the generated logical relationship is as shown in formula (2):

among them,

Is the "exclusive OR" logic operation, ⊙ is the "exclusive OR" logic operation, & is the "AND" logic operation, ∪() _| is the continuous OR operation; k-1 is the serial number of the first sampled signal, and k is The sequence number of the second sampling signal, where n is _{the smallest integer greater than or equal to log 2} N, N is the number of PAM levels, and i is an integer from n-1 to 0 respectively.

The logic relationship is realized by logic operation, which reduces the realization sequence to approximately

That is, the time complexity is log ₂ (log ₂ N). among them

t _⊙ , t _& , t _| are the hardware realization time of an XOR gate, XOR gate, AND gate, or gate respectively,

It is round up operation.

S230: Confirm the phase state of the sampling point according to the calculation result of the logical relationship.

Exemplarily, if early=1 in formula (2), the phase of the sampling point is too early, and the sampling point needs to be shifted to the right; or,

If late=1 in formula (2), the phase of the sampling point is late, and the sampling point needs to be shifted to the left; or,

If early=0 in formula (2) and late=0, the phase of the sampling point remains unchanged.

Some exemplary implementation manners are listed below to illustrate the clock data recovery method provided in FIG. 4 in the embodiment of the present application. In the following embodiments, N=8 is taken as an example, that is, the sampling signal is modulated in the PAM-8 mode, and n=log ₂ 8=3.

It is defined that the amplitude distribution of the sampled PAM-N signal is symmetrical about 0 (that is, the statistical average of the amplitude is 0). Assume that the eight reference level amplitudes corresponding to the sampled signal are (-7/8, -5/8, -3/8, -1/8, +1/8, +3/8, +5/8, +7/8}, that is, the average value of the absolute value of the sampled signal amplitude is 1/2 (ie j=-1), the sampled signal is expressed in the form of twos complement, and the second bit from the left represents the real signal The amplitude is 1/2.

Step 1: Process the first sampled signal.

Suppose that the twos complement form of the received first sampled signal has m bits, where m should be at least 4, and the form is a _{k-1, m-1} a _{k-1, m-2} ... a _{k-1, 1} a _k-1,0 , which can represent the range of values from -1 to 1-2 ^(1-m) , that is: the first reference symbol S[3] _k-1 = a _{k-1, m-1} .

a _{k-1, m-2} indicates that the amplitude of the real signal is 1/2, that is _{, count 3 bits backward from a k-1, m-2} , and respectively compare a _{k-1, m-2} , a _{K-1, m-3} and a _{k-1, m-4 are} logically inverted to obtain S[2] _k-1 , S[1] _k-1 and S[0] _k-1 .

It can be seen that the first reference symbol of the first sampling signal is a _{k-1, m-1} , and the first error component of the first sampling signal is {a _{k-1, m-2} , a _{k-1, m- 3} ,a _k-1,m-4 }.

Step 2: Process the second sampled signal.

Suppose that the twos complement form of the received second sampling signal has m bits, where m should be at least 4, and the form is a _k,m-1 a _k,m-2 ...a _k,1 a _k,0 , The range of values that can be expressed is -1～1-2 ^(1-m) , that is, there is: the second reference symbol S[3] _k = a _{k, m-1} .

a _{k, m-2} indicates that the amplitude of the real signal is 1/2, that is, 3 bits count backward _{from a k, m-2 , and a k, m-2} , a _{k, m-3} and The _{logic of a k, m-4 is} inverted, and S[2] _k , S[1] _k and S[0] _{k are obtained} .

It can be seen that the second reference symbol of the second sampling signal is a _{k, m-1} , and the second error component of the second sampling signal is {a _{k, m-2} , a _{k, m-3} , a _{k, m -4} }.

Step 3: Generate logical relationships.

From the first and second steps, the first reference symbol of the first sampled signal is a _{k-1, m-1} , and the first error component of the first sampled signal is {a _{k-1, m-2} , a _k-1,m-3 , _ak-1,m-4 }, the second reference symbol of the second sampled signal is _ak,m-1 , and the second error component of the second sampled signal is { _{ak,m -2} , a _{k, m-3} , a _{k, m-4} } Refer to formula (2) to obtain:

Among them, FIG. 5 shows another logical relationship micro-architecture diagram provided by an embodiment.

Step 4: Confirm the phase status of the sampling point.

According to the logical relationship obtained in the third step, the result of the logical relationship is calculated. If early=1, it means that the phase of the sampling point is too early, and the sampling point needs to be shifted to the right; or, if late=1, it means that the phase of the sampling point is late, and the sampling point needs to be shifted to the left; or, if early=0 , And late=0, it means that there is no clear signal sooner or later, and the phase of the sampling point remains unchanged.

Fig. 6 shows a simulation result of the phase detector corresponding to Fig. 5 provided by an embodiment. It is a comparison chart of phase discrimination curves obtained through numerical simulation in the presence of phase noise with the same standard deviation. It can be seen from Figure 6 that the dotted line is the phase detection curve of the traditional MM phase detector, and the solid line is the phase detection curve of the phase detector corresponding to Figure 5; the horizontal axis represents the phase difference, and the unit is the unit of sending/receiving sampled signals. Unit Interval (UI). The vertical axis represents the relative value of the average output value of the phase detector under the corresponding phase difference. The slope of the line between the point on the curve and the origin is the relative value of the phase detector gain. The relative value of phase gain is used to compare the relative magnitude of different phase discrimination gains.

The implementation of the clock data recovery method provided by the embodiment of the application has nothing to do with the circuit process, and does not require sampling at 2 times the baud rate, and the value of N changes, and the phase discrimination interval can be maintained between -π～+π. The phase point starts to capture. The phase detection gain changes more smoothly in the effective phase detection interval, which broadens the lock capture range, reduces the phase capture time, and significantly improves the performance of the clock data recovery circuit. At the same time, the traditional numerical calculation method is improved and simplified into a digital logic method, which reduces the complexity and power consumption of the hardware. In addition, compared with the clock data recovery method shown in FIG. 1, the process of processing the sampled signal can be simplified, and it is no longer necessary to perform symbol judgment and remove symbol components of the sampled signal.

FIG. 7 is a schematic structural diagram of a clock data recovery device provided by an embodiment. The clock data recovery device can be configured in a phase detector, as shown in FIG. 7, comprising: a signal sampling module 10, a signal processing module 11, and logic The generation module 12 and the phase judgment module 13.

The signal sampling module 10 is set as a sampling signal.

The signal processing module 11 is configured to process the sampled signal to obtain the reference symbol and error component corresponding to the sampled signal, where, when the sampled signal is the first sampled signal, the reference symbol corresponding to the first sampled signal is the first reference symbol, The error component corresponding to the first sampling signal is the first error component; when the sampling signal is the second sampling signal, the reference symbol corresponding to the second sampling signal is the second reference symbol, and the error component corresponding to the second sampling signal is the second error Component, the first sampling signal and the second sampling signal are continuous in time sequence.

The logic generating module 12 is configured to generate a logic relationship according to the first reference symbol, the first error component, the second reference symbol, and the second error component.

The phase judgment module 13 is configured to confirm the phase state of the sampling point according to the calculation result of the logical relationship.

The clock data recovery device provided in this embodiment implements the clock data recovery method of the foregoing embodiment, and the implementation principle of the clock data recovery device provided in this embodiment is similar, and will not be repeated here.

In one embodiment, the signal processing module 11 is configured to perform symbol decision on the sampled signal Sig(n) to obtain the reference symbol S[n] corresponding to the sampled signal Sig(n); according to the sampled signal Sig(n) and the sample The reference symbol S[n] corresponding to the signal is used to obtain the error component corresponding to the sampled signal.

In one embodiment, the signal processing module 11 is set to let i take an integer from n to 1, and repeat steps a) and b) to obtain {S[n-1], S[n-2 ],...,S[0]} as the error component corresponding to the sampled signal; among them, step a) eliminates the symbol component of Sig(i) to obtain Sig(i-1), where Sig(i-1)=Sig( i)+(2*S[i]-1)*A/2 ⁽ⁿⁱ⁾ ; Step b) Perform symbol judgment on Sig(i-1) to obtain S[i-1]; n is greater than or equal to log ₂ The smallest integer of N, N is the level number of the pulse amplitude modulation PAM, and A is the average value of the absolute value of the amplitude of the sampled signal.

In one embodiment, when the average value of the absolute value of the sampled signal amplitude is 2 ^j ; the signal processing module 11 is set to use the highest bit of the sampled signal as the reference symbol S[n] corresponding to the sampled signal, It means that the n bits starting from the bit whose amplitude of the real signal is 2 ^j are logically inverted and used as the error component corresponding to the sampled signal {S[n-1],S[n-2],...,S[0]} ; Among them, n is _{the smallest integer greater than or equal to log 2} N, N is the number of PAM levels, and j is an integer.

In an embodiment, the logical relationship is:

among them,

Is the "exclusive OR" logic operation, ⊙ is the "exclusive OR" logic operation, & is the "AND" logic operation, ∪() _| is the continuous OR operation; k-1 is the serial number of the first sampled signal, and k is The sequence number of the second sampling signal, where n is _{the smallest integer greater than or equal to log 2} N, N is the number of PAM levels, and i is an integer from n-1 to 0 respectively.

In an embodiment, the logic generation module 12 is set to if early=1, the phase of the sampling point is early; or, if late=1, the phase of the sampling point is late; or, if early=0, and late =0, the phase of the sampling point remains unchanged.

In an embodiment, the sampled signal is represented in the form of twos complement.

The embodiment of the present application further provides a phase detector, including a processor, which is configured to implement the method provided in any embodiment of the present application when the computer program is executed. FIG. 8 is a schematic structural diagram of a phase detector provided by an embodiment. As shown in FIG. 8, the phase detector includes a processor 60, a memory 61, and a communication interface 62; the number of processors 60 in the phase detector may be At least one, one processor 60 is taken as an example in FIG. 8; the processor 60, the memory 61, and the communication interface 62 in the phase detector may be connected by a bus or other methods. In FIG. 8, the connection by a bus is taken as an example. The bus represents one or more of several types of bus structures, including a memory bus or a memory controller, a peripheral bus, a graphics acceleration port, a processor, or a local bus using any bus structure among multiple bus structures.

As a computer-readable storage medium, the memory 61 can be configured to store software programs, computer-executable programs, and modules, such as program instructions/modules corresponding to the methods in the embodiments of the present application. The processor 60 executes at least one functional application and data processing of the phase detector by running the software programs, instructions, and modules stored in the memory 61, that is, realizes the above-mentioned clock data recovery method.

The memory 61 may include a storage program area and a storage data area. The storage program area may store an operating system and an application program required by at least one function; the storage data area may store data created according to the use of the phase detector, and the like. In addition, the memory 61 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one magnetic disk storage device, a flash memory device, or other non-volatile solid-state storage devices. In some examples, the memory 61 may include a memory remotely provided with respect to the processor 60, and these remote memories may be connected to the phase detector through a network. Examples of the aforementioned networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The communication interface 62 can be configured to receive and send data.

The embodiment of the present application also provides a computer-readable storage medium, and a computer program is stored on the computer-readable storage medium. When the computer program is executed by a processor, the method as provided in any embodiment of the present application is implemented.

The computer storage medium of the embodiment of the present application may adopt any combination of at least one computer-readable medium. The computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or device, or a combination of any of the above. Computer-readable storage media include (non-exhaustive list): electrical connections with at least one wire, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM) ), electrically erasable programmable read-only memory (Electrically Erasable Programmable Read-Only Memory, EEPROM), flash memory, optical fiber, portable compact disk read-only memory (Compact Disc Read-Only Memory, CD-ROM), optical storage devices, Magnetic storage device, or any suitable combination of the above. In this application, the computer-readable storage medium may be any tangible medium that contains or stores a program, and the program may be used by or in combination with an instruction execution system, apparatus, or device.

The computer-readable signal medium may include a data signal propagated in baseband or as a part of a carrier wave, and the computer-readable program code is carried in the data signal. This propagated data signal can take many forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the foregoing. The computer-readable signal medium may also be any computer-readable medium other than the computer-readable storage medium, and the computer-readable medium may send, propagate, or transmit the program for use by or in combination with the instruction execution system, apparatus, or device .

The program code contained on the computer-readable medium can be transmitted by any suitable medium, including but not limited to wireless, wire, optical cable, radio frequency (RF), etc., or any suitable combination of the foregoing.

The computer program code used to perform the operations of the present disclosure can be written in one or more programming languages or a combination of multiple programming languages. The programming languages include object-oriented programming languages-such as Java, Smalltalk, C++, Ruby, Go also includes conventional procedural programming languages-such as "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partly on the user's computer, executed as an independent software package, partly on the user's computer and partly executed on a remote computer, or entirely executed on the remote computer or server. In the case of a remote computer, the remote computer can be connected to the user's computer through any kind of network-including Local Area Network (LAN) or Wide Area Network (WAN)-or it can be connected to an external computer ( For example, use an Internet service provider to connect via the Internet).

Those skilled in the art should understand that the term user terminal encompasses any suitable type of wireless user equipment, such as a mobile phone, a portable data processing device, a portable web browser, or a vehicle-mounted mobile station.

In general, the various embodiments of the present application can be implemented in hardware or dedicated circuits, software, logic or any combination thereof. For example, some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software that may be executed by a controller, microprocessor, or other computing device, although the present application is not limited thereto.

The embodiments of the present application may be implemented by executing computer program instructions by a data processor of a mobile device, for example, in a processor entity, or by hardware, or by a combination of software and hardware. Computer program instructions can be assembly instructions, Instruction Set Architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, or written in any combination of one or more programming languages Source code or object code.

The block diagram of any logic flow in the drawings of the present application may represent program steps, or may represent interconnected logic circuits, modules, and functions, or may represent a combination of program steps and logic circuits, modules, and functions. The computer program can be stored on the memory. The memory can be of any type suitable for the local technical environment and can be implemented using any suitable data storage technology, such as but not limited to read-only memory (ROM), random access memory (RAM), optical storage devices and systems (digital multi-function optical discs) (Digital Versatile Disc, DVD) or CD disc) etc. Computer-readable media may include non-transitory storage media. The data processor can be any type suitable for the local technical environment, such as but not limited to general-purpose computers, special-purpose computers, microprocessors, digital signal processors (Digital Signal Processing, DSP), application specific integrated circuits (ASICs) ), programmable logic devices (Field-Programmable Gate Array, FGPA), and processors based on multi-core processor architecture.

Claims (10)

1. A method for clock data recovery, including:

   Obtain the sampled signal and process the sampled signal to obtain the reference symbol and error component corresponding to the sampled signal. In the case where the sampled signal is the first sampled signal, the reference symbol corresponding to the first sampled signal is the first reference Symbol, the error component corresponding to the first sampling signal is the first error component; when the sampling signal is the second sampling signal, the reference symbol corresponding to the second sampling signal is the second reference symbol, and the error component corresponding to the second sampling signal Is the second error component, the first sampling signal and the second sampling signal are continuous in time sequence;

   Generate a logical relationship according to the first reference symbol, the first error component, the second reference symbol, and the second error component;

   According to the calculation result of the logical relationship, the phase state of the sampling point is confirmed.
2. The method according to claim 1, wherein processing the sampled signal to obtain a reference symbol and an error component corresponding to the sampled signal comprises:

   Perform a symbol decision on the sample signal Sig(n) to obtain a reference symbol S[n] corresponding to the sample signal Sig(n);

   According to the sampling signal Sig(n) and the reference symbol S[n] corresponding to the sampling signal Sig(n), the error component corresponding to the sampling signal Sig(n) is obtained.
3. The method according to claim 2, wherein obtaining the error component corresponding to the sampling signal Sig(n) comprises:

   Eliminate the symbolic components of Sig(i) to obtain Sig(i-1), where Sig(i-1)=Sig(i)+(2*S[i]-1)*A/2 ⁽ⁿⁱ⁾ ;

   Perform symbol judgment on Sig(i-1) to obtain S[i-1];

   Let i take an integer from n to 1 respectively, repeat the above steps, and use the obtained {S[n-1], S[n-2],...,S[0]} as the error component corresponding to the sampling signal;

   Among them, n is the smallest integer greater than or equal to log ₂ N, N is the number of levels of the pulse amplitude modulation PAM, and A is the average value of the absolute value of the sampled signal amplitude.
4. The method according to claim 1, wherein when the average value of the absolute value of the amplitude of the sampled signal is 2 ^j ;

   Processing the sampled signal to obtain the reference symbol and error component corresponding to the sampled signal includes:

   The highest bit of the sampled signal as said reference symbol corresponding to the sampling signal S [n], and represents the magnitude of the real signal is 2 ^j bits starting n bits after each logical negation, as the The error component corresponding to the sampled signal {S[n-1],S[n-2],...,S[0]}; where n is _{the smallest integer greater than or equal to log 2} N, and N is the level of PAM Number, j is an integer.
5. The method according to claim 3 or 4, wherein the logical relationship is:

   

   among them,

   

   Is the "exclusive OR" logical operation, ⊙ is the "exclusive OR" logical operation, & is the "AND" logical operation, ∪() _| is the continuous "OR"operation; k-1 is the serial number of the first sampled signal, k is the sequence number of the second sampling signal, where n is _{the smallest integer greater than or equal to log 2} N, N is the number of PAM levels, and i is an integer from n-1 to 0, respectively.
6. The method according to claim 5, wherein, according to the calculation result of the logical relationship, confirming the phase state of the sampling point comprises:

   In response to the calculation result of the logical relationship being early=1, it is determined that the phase of the sampling point is too early; or,

   In response to the calculation result of the logical relationship being late=1, it is determined that the phase of the sampling point is late; or,

   In response to the calculation result of the logical relationship being early=0 and late=0, it is determined that the phase of the sampling point remains unchanged.
7. The method according to claim 1, wherein the sampling signal is represented in the form of twos complement.
8. A clock data recovery device, including: a signal sampling module, a signal processing module, a logic generation module and a phase judgment module;

   The signal sampling module is configured to obtain a sampling signal;

   The signal processing module is configured to process the sampling signal to obtain a reference symbol and an error component corresponding to the sampling signal. In the case where the sampling signal is the first sampling signal, the reference symbol corresponding to the first sampling signal is The first reference symbol, the error component corresponding to the first sampling signal is the first error component; when the sampling signal is the second sampling signal, the reference symbol corresponding to the second sampling signal is the second reference symbol, and the second sampling signal corresponds to The error component of is a second error component, and the first sampling signal and the second sampling signal are continuous in time sequence;

   The logic generation module is configured to generate a logic relationship according to the first reference symbol, the first error component, the second reference symbol, and the second error component;

   The phase judgment module is configured to confirm the phase state of the sampling point according to the calculation result of the logical relationship.
9. A phase detector, comprising: a processor configured to implement the clock data recovery method according to any one of claims 1-7 when a computer program is executed.
10. A computer-readable storage medium storing a computer program, and when the computer program is executed by a processor, the clock data recovery method according to any one of claims 1-7 is realized.

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