WO2021097962A1 - 一种异构芯片的任务处理方法、任务处理装置及电子设备 - Google Patents

一种异构芯片的任务处理方法、任务处理装置及电子设备 Download PDF

Info

Publication number
WO2021097962A1
WO2021097962A1 PCT/CN2019/124350 CN2019124350W WO2021097962A1 WO 2021097962 A1 WO2021097962 A1 WO 2021097962A1 CN 2019124350 W CN2019124350 W CN 2019124350W WO 2021097962 A1 WO2021097962 A1 WO 2021097962A1
Authority
WO
WIPO (PCT)
Prior art keywords
subtasks
task
subtask
pipeline
single task
Prior art date
Application number
PCT/CN2019/124350
Other languages
English (en)
French (fr)
Inventor
邵翠萍
李慧云
梁浩天
羌浩南
Original Assignee
深圳先进技术研究院
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳先进技术研究院 filed Critical 深圳先进技术研究院
Publication of WO2021097962A1 publication Critical patent/WO2021097962A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G06F9/3869—Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • This application belongs to the technical field of high-performance computing, and in particular relates to a task processing method, a task processing device, electronic equipment, and a computer-readable storage medium for heterogeneous chips.
  • a multi-board heterogeneous many-core includes a host device and multiple accelerator devices, and each device is interconnected through a bus.
  • hardware resources are allocated according to the scale of the computing task, and each device executes a single-cycle task, so that most of the processing resources are in the waiting stage when the device is running, which reduces the operating efficiency of the computing device to a certain extent.
  • this application provides a heterogeneous chip data processing method, data processing device, electronic equipment, and computer-readable storage medium, which can greatly reduce the waiting time of processing resources when processing tasks and improve hardware resources The processing efficiency.
  • this application provides a task processing method for heterogeneous chips, including:
  • this application provides a task processing device for heterogeneous chips, including:
  • the receiving module is used to receive the execution instruction of a single task
  • the dividing module is used to divide the above single task into at least two subtasks in sequence;
  • a distribution module for distributing each subtask to different computing chips in the heterogeneous chip
  • the processing module is used to control the above-mentioned different computing chips to sequentially process the above-mentioned subtasks in the first pipeline mode, wherein the first pipeline stage corresponding to the first pipeline mode is the same as the number of subtasks, and the number of the above-mentioned first pipeline
  • the first-level computing time includes the execution time of a subtask and the time for transmitting the data corresponding to the subtask between two adjacent computing chips.
  • the present application provides an electronic device, including a memory, a processor, and a computer program stored in the foregoing memory and capable of running on the foregoing processor.
  • the foregoing processor executes the foregoing computer program, the foregoing first aspect is implemented. The method provided.
  • the present application provides a computer-readable storage medium.
  • the above-mentioned computer-readable storage medium stores a computer program, and when the above-mentioned computer program is executed by a processor, the method provided in the first aspect is implemented.
  • the present application provides a computer program product, which when the computer program product runs on an electronic device, causes the electronic device to execute the method provided in the above-mentioned first aspect.
  • the execution instruction of a single task is first received; then the single task is divided into at least two subtasks in sequence, and each subtask is distributed to different computing chips in the heterogeneous chip. ; Finally, the different computing chips are controlled to sequentially process the subtasks in the first pipeline mode, wherein the number of first pipeline stages corresponding to the first pipeline mode is the same as the number of subtasks, and the first-stage operation of the first pipeline
  • the time includes the execution time of a subtask and the time for transmitting the data corresponding to the aforementioned subtask between two adjacent computing chips.
  • the computing chip can immediately start processing the subtasks of the next task after processing the subtasks of one task, which greatly reduces the waiting time of processing resources when processing tasks and improves the processing efficiency of hardware resources.
  • FIG. 1 is a schematic flowchart of a task processing method for a heterogeneous chip provided by an embodiment of the present application
  • FIG. 2 is a schematic diagram of task processing of a pipeline provided by an embodiment of the present application
  • FIG. 3 is an example diagram of data interaction between an electronic device and a heterogeneous chip provided by an embodiment of the present application
  • FIG. 4 is a schematic structural diagram of a task processing device for a heterogeneous chip provided by an embodiment of the present application
  • Fig. 5 is a schematic structural diagram of an electronic device provided by an embodiment of the present application.
  • the term “if” can be construed as “when” or “once” or “in response to determination” or “in response to detecting “.
  • the phrase “if determined” or “if detected [described condition or event]” can be interpreted as meaning “once determined” or “in response to determination” or “once detected [described condition or event]” depending on the context ]” or “in response to detection of [condition or event described]”.
  • FIG. 1 shows a flowchart of a task processing method for a heterogeneous chip provided by an embodiment of the present application, and the details are as follows:
  • Step 101 Receive an execution instruction of a single task
  • the task processing method of the heterogeneous chip is applied to an electronic device, which has a general-purpose processor function.
  • the general-purpose processor executes the steps of the above task processing method, it controls the processing tasks of each computing chip in the above heterogeneous chips.
  • the above tasks include data to be processed (such as images, texts, videos) and programs for processing the data.
  • the task execution instruction is issued or triggered by the user. When the user sends the execution instruction to the electronic device, the electronic device starts to execute the steps of the task processing method described above.
  • Step 102 Divide the foregoing single task into at least two subtasks in a sequential order
  • each subtask includes a part of the foregoing program, and the execution of each subtask has a sequence, and the foregoing sequence is the execution sequence of the foregoing program.
  • Each subtask is executed in sequence to complete the processing of the data to be processed.
  • the convolutional neural network includes a first convolutional layer, a first pooling layer, a second convolutional layer, and a second pooling that are sequentially connected. Layer and three-layer fully connected layer. After dividing the convolutional neural network, three subtasks are obtained.
  • the first subtask includes processing the data to be processed through the first convolutional layer and the first pooling layer
  • the second subtask includes processing the data to be processed through the second convolutional layer and the second convolutional layer.
  • the second pooling layer processes the data to be processed
  • the third subtask includes processing the data to be processed through the three-layer fully connected layer, and sequentially executes the first, second, and third subtasks above to complete the input To the processing of the data of the convolutional neural network.
  • the execution time of each subtask obtained after task division is equal. If the execution time of each subtask is not equal in the process of task division, a delay should be added after the execution of each subtask, so that the execution time of each subtask after the delay is added is equal. Further, the way to add a delay after the execution of each subtask may be: find the subtask with the longest execution time from the subtasks with unequal execution time, and do not add the delay after the execution of the subtask with the longest execution time. When the delay is added to other subtasks, the execution time becomes equal to the execution time of the subtask with the longest execution time.
  • step 102 specifically includes:
  • the single task is divided into at least two subtasks in sequence.
  • the hardware resource information of the aforementioned heterogeneous chips includes the number of computing chips.
  • CNN network convolutional neural network
  • the number of determined subtasks is N, and m basic units need to be divided into N parts.
  • the number of subtasks can be determined in the following way: Take the above CNN network as an example, first divide the above CNN network into multiple units, each unit is a layer in the CNN network, which is the CNN network The smallest indivisible unit in the middle. From multiple units, select the unit with the longest execution time. Calculate the ratio of the total execution time of the CNN network to the execution time of the unit with the largest execution time. Compare the number of computing chips in the above heterogeneous chips with the ratio. If the number of computing chips is greater than the ratio, the number of subtasks after division is the ratio rounded up. If the number of computing chips is less than With this ratio, the number of divided subtasks is the number of computing chips.
  • the number of subtasks obtained cannot be greater than the number of computing chips to ensure that each subtask is executed by one computing chip.
  • the output obtained from the execution of the previous subtask is sent to the next subtask as the input of the next subtask, and the input of the first subtask is the data to be processed included in the task.
  • the output of the last subtask is the execution result of the last task.
  • step A1 specifically includes:
  • multiple division schemes are determined according to the execution time of the aforementioned single task and the number of computing chips in the aforementioned heterogeneous chip.
  • the number of division schemes depends on the number of computing chips, and the subdivisions to be divided by the division scheme can be determined first.
  • the tasks are divided correspondingly according to the task division method in step A1.
  • the above heterogeneous chip includes four computing chips, then the number of the above division schemes is three, and the three division schemes are respectively the first scheme: divide the task into 4 subtasks, and the second scheme: divide the task into 3 subtasks, the third scheme: divide the task into 2 subtasks.
  • the resource conversion efficiency corresponding to each division scheme is calculated respectively.
  • the electronic device can calculate the resource conversion efficiency based on the task's floating point calculation amount, throughput rate, and hardware resources occupied by the task.
  • the resource conversion efficiency indicates the processing capability of the unit hardware resource in the task processing process of the heterogeneous chip, and reflects the degree of optimization of the hardware resource by the corresponding partitioning scheme. The greater the resource conversion efficiency, the stronger the processing capability of the unit hardware resource of the heterogeneous chip. Conversely, the lower the resource conversion efficiency, the weaker the processing capability of the unit hardware resource of the heterogeneous chip. Therefore, after calculating the resource conversion efficiency corresponding to each division scheme, compare the numerical value of the resource conversion efficiency corresponding to each division scheme, and use the division scheme with the highest resource conversion efficiency in each division scheme as the final division scheme.
  • the resource conversion efficiency corresponding to the first scheme is 0.5
  • the resource conversion efficiency corresponding to the second scheme is 0.6
  • the resource conversion corresponding to the third scheme The efficiency is 0.7
  • the third scheme is selected as the final division scheme by comparing the size of resource conversion efficiency.
  • step B2 specifically includes:
  • ⁇ is the resource conversion efficiency
  • P is the calculation amount of a single task
  • ⁇ is the throughput rate during the execution of a single task by the heterogeneous chip
  • N is the number of calculation chips.
  • the above-mentioned throughput rate can be calculated according to the number of subtasks corresponding to the division scheme and the running time of the subtasks, and the number of calculation chips mentioned above is the number of calculation chips actually used according to the number of subtasks.
  • step A1 specifically includes:
  • multiple division schemes are determined according to the execution time of the aforementioned single task and the number of computing chips in the aforementioned heterogeneous chip.
  • the number of division schemes depends on the number of computing chips, and the subdivisions to be divided by the division scheme can be determined first.
  • the tasks are divided correspondingly according to the task division method in step A1.
  • the above heterogeneous chip includes four computing chips, then the number of the above division schemes is three, and the three division schemes are respectively the first scheme: divide the task into 4 subtasks, and the second scheme: divide the task into 3 subtasks, the third scheme: divide the task into 2 subtasks.
  • the resource utilization rate corresponding to each division scheme is calculated respectively, and the above resource utilization rate indicates the hardware resource size occupied when the subtask runs on the corresponding single computing chip.
  • the above filtering condition is that the resource utilization rate corresponding to the division scheme is greater than the preset resource utilization rate. Threshold, when the division scheme meets the screening conditions, the performance of the computing chip can be fully utilized.
  • the primary partitioning scheme with the largest number of subtasks is selected as the final partitioning scheme.
  • the above-mentioned tasks are divided into at least two sub-tasks in sequence.
  • the resource utilization rate corresponding to the above-mentioned first scheme is 50%
  • the resource utilization rate corresponding to the second scheme is 70%
  • the resource utilization rate corresponding to the third scheme is 80%.
  • the filter condition is the resource utilization rate corresponding to the division scheme. If it is greater than 60%, then the primary division plan selected according to the screening condition includes the second plan and the third plan. If the number of subtasks corresponding to the second scheme is 2, and the number of subtasks corresponding to the third scheme is 1, the second scheme is selected as the final division scheme. According to the final division plan, the task is divided into 2 subtasks.
  • Step 103 Distribute each subtask to different computing chips in the heterogeneous chip
  • each divided subtask needs to be sent to different computing chips for execution, and one computing chip executes one subtask.
  • the above heterogeneous chip includes 5 computing chips, and the number of subtasks is 3, then the subtasks are sent to 3 of the 5 computing chips for execution, and the remaining 2 computing chips do not perform subtasks. deal with.
  • the computing chips in the heterogeneous chips are connected in sequence through a bus. Taking the computing chip as an FPGA as an example, before distributing each subtask to different FPGAs, each subtask needs to be converted into a bitstream file, and then the bitstream file corresponding to each subtask is programmed to the corresponding FPGA.
  • Step 104 Control the above-mentioned different computing chips to sequentially process the above-mentioned subtasks in the first pipeline mode.
  • the number of stages of the first pipeline corresponding to the first pipeline mode is the same as the number of the subtasks
  • the first stage operation time of the first pipeline includes the execution time of one subtask and the execution time of two adjacent subtasks. Calculate the time for transmitting the data corresponding to the above subtasks between chips.
  • the operation time of each pipeline stage of the first pipeline is equal. It should be noted that the execution time of each subtask on the computing chip is equal, and the time for transmitting the data corresponding to the subtask between adjacent computing chips is also the same. The execution time of the subtask on the computing chip is greater than the corresponding time. The time for the data corresponding to the above subtasks to be transmitted between adjacent computing chips.
  • the first stage of the first pipeline includes the computing chip executing the corresponding subtask and transmitting the processing result of the subtask to the next computing chip.
  • the time of the data corresponding to the task, the operation time of the first stage of the first pipeline is equal to t m + t l .
  • the first task, the second task, and the third task are all convolutional neural networks, and the convolutional neural network includes a 2-layer convolutional layer, a 2-layer pooling layer, and a 1-layer fully connected layer.
  • Conv+Pool represents a subtask that includes a convolutional layer and a pooling layer
  • Fullyconn represents a subtask that includes a fully connected layer.
  • step 104 specifically includes:
  • the above-mentioned task processing method further includes:
  • the execution of a subtask and the transmission of data corresponding to the subtask between two adjacent computing chips are respectively used as the first stage of the second pipeline corresponding to the second pipeline mode, and the first stage calculation of the second pipeline Time is equal to the execution time of a subtask.
  • the execution of a subtask and the transmission of data corresponding to the subtask between two adjacent computing chips are used as the first stage of the first pipeline, and the second pipeline is to combine a subtask.
  • the execution of the task and the transmission of the data corresponding to the subtask between two adjacent computing chips are respectively used as the first stage of the second pipeline corresponding to the second pipeline mode.
  • the first stage of the above-mentioned second pipeline may be the execution of a subtask, or it may be the transmission of data corresponding to a subtask between two adjacent computing chips. It should be noted that, in order to make the calculation time of each stage of the second pipeline equal, a delay is added after the data corresponding to the subtask is transmitted between adjacent computing chips, so that the execution time of a subtask is equal to the aforementioned The time for the data corresponding to the subtask to be transmitted between two adjacent computing chips.
  • each stage of the second pipeline the operation time of each stage of the second pipeline is equal, and each stage of the subtask processing pipeline stage of the second pipeline processes one subtask, when there are multiple tasks to be processed, the first The two pipelines can process the above-mentioned multiple tasks in parallel. That is, when the second stage of the second pipeline (the data transmission pipeline stage) starts data transmission of the first task, the first stage of the second pipeline starts to process the second task, and the third stage of the second pipeline When the first task is processed, the first stage of the second pipeline starts to process the third task, and so on.
  • Figure 2 is drawn for explanation.
  • Part (b) in Figure 2 is the process of the second pipeline processing three tasks in parallel, where t m is the execution time of the subtasks, and the operation time of the first stage of the second pipeline is equal to t m .
  • the first task, the second task, and the third task are all convolutional neural networks, and the convolutional neural network includes a 2-layer convolutional layer, a 2-layer pooling layer, and a 1-layer fully connected layer.
  • Conv+Pool represents a subtask that includes a convolutional layer and a pooling layer
  • Fullyconn represents a subtask that includes a fully connected layer
  • Latency is a data transmission pipeline stage.
  • the electronic device can be a ZYNQ 7035 series development board launched by Xilinx, and the computing chip can be a Field Programmable Gate Array (FPGA), which is not limited here.
  • the ZYNQ 7035 series development board communicates with the host computer through the Ethernet port on the PS (Processing System) side.
  • the RapidIO protocol is used, and the high-speed serial transceiver communicates with each FPGA.
  • the user can communicate to the ZYNQ 7035 series development board through the host computer.
  • Send task execution instructions The ZYNQ 7035 series development board receives the execution instructions and controls each FPGA to perform the above tasks. When each FPGA finishes executing the above tasks and obtains the processing result, the ZYNQ 7035 series development board receives the processing result and sends the processing result. Send to the host computer through the Ethernet port.
  • the execution instruction of a single task is first received; then the single task is divided into at least two subtasks in sequence, and each subtask is distributed to different computing chips in the heterogeneous chip. ; Finally, the different computing chips are controlled to sequentially process the subtasks in the first pipeline mode, wherein the number of first pipeline stages corresponding to the first pipeline mode is the same as the number of subtasks, and the first-stage operation of the first pipeline
  • the time includes the execution time of a subtask and the time for transmitting the data corresponding to the aforementioned subtask between two adjacent computing chips.
  • the computing chip can immediately start processing the subtasks of the next task after processing the subtasks of one task, which greatly reduces the waiting time of processing resources when processing tasks and improves the processing efficiency of hardware resources.
  • FIG. 4 shows a schematic structural diagram of a task processing device for a heterogeneous chip provided by an embodiment of the present application.
  • the task processing device for a heterogeneous chip can be applied to electronic equipment.
  • electronic equipment For ease of description, only the implementation of the present application is shown. Examples of related parts.
  • the task processing device 400 of the heterogeneous chip includes:
  • the receiving module 401 is used to receive the execution instruction of a single task
  • the dividing module 402 is used to divide the above single task into at least two subtasks in a sequential order;
  • a distribution module 403, configured to distribute each subtask to different computing chips in the heterogeneous chip
  • the processing module 404 is configured to control the above-mentioned different computing chips to sequentially process the above-mentioned subtasks in the first pipeline mode, wherein the first pipeline stage corresponding to the first pipeline mode is the same as the number of subtasks, and the above-mentioned first pipeline mode
  • the first-level computing time includes the execution time of a subtask and the time for transmitting the data corresponding to the subtask between two adjacent computing chips.
  • the above-mentioned processing module 404 further includes:
  • the mode threshold calculation unit is configured to calculate the mode threshold according to the number of subtasks of a single task, the operation time of the subtasks, and the time for transmitting the data corresponding to the subtasks between two adjacent computing chips;
  • the first control unit is configured to control the different computing chips to sequentially process the subtasks in the first pipeline mode if the number of the same single tasks is less than or equal to the mode threshold.
  • the task processing device 400 of the heterogeneous chip further includes:
  • the second control unit is used to control the above-mentioned different computing chips to sequentially process the above-mentioned subtasks in a second pipeline mode, wherein the execution of one subtask and the transmission of data corresponding to the above-mentioned subtasks between two adjacent computing chips They are respectively used as the first stage of the second pipeline corresponding to the second pipeline mode, and the first stage operation time of the second pipeline is equal to the execution time of one subtask.
  • the above-mentioned dividing module 402 further includes:
  • the execution time dividing unit is configured to divide the single task into at least two sequential subtasks according to the execution time of the single task and the hardware resource information of the heterogeneous chip, wherein the output of the previous subtask is regarded as adjacent to it. The input of the next subtask.
  • the foregoing execution time dividing unit further includes:
  • the first scheme determining subunit is configured to determine at least one division scheme according to the execution time of the aforementioned single task and the hardware resource information of the aforementioned heterogeneous chip, and the aforementioned division scheme is a scheme of dividing a single task into at least two subtasks;
  • the efficiency calculation subunit is used to calculate the resource conversion efficiency corresponding to each division scheme, where the above resource conversion efficiency indicates the data processing capability of the unit hardware resource of the heterogeneous chip;
  • the first final plan determination subunit is used to select a corresponding division plan with the greatest resource conversion efficiency from the above at least one division plan as the final division plan;
  • the first final division subunit is configured to divide the single task into at least two subtasks in sequence according to the final division scheme.
  • the foregoing efficiency calculation subunit further includes:
  • the efficiency formula calculation subunit is used to calculate the resource conversion efficiency corresponding to each division scheme according to the preset resource conversion efficiency formula.
  • the foregoing execution time dividing unit further includes:
  • the second scheme determining subunit is configured to determine at least one division scheme according to the execution time of the aforementioned single task and the hardware resource information of the aforementioned heterogeneous chip, and the aforementioned division scheme is a scheme of dividing a single task into at least two subtasks;
  • the screening subunit is used to screen out at least one primary division plan that meets a preset screening condition from the above at least one division plan, where the screening condition is that the resource utilization rate corresponding to the division scheme is greater than the preset resource utilization threshold. ;
  • the second final plan determination subunit is used to select the primary division plan with the largest number of subtasks from the at least one primary division plan as the final division plan;
  • the second final division subunit is configured to divide the single task into at least two subtasks in sequence according to the final division scheme.
  • the execution instruction of a single task is first received; then the single task is divided into at least two subtasks in sequence, and each subtask is distributed to different computing chips in the heterogeneous chip. ; Finally, control the above-mentioned different computing chips to sequentially process the above-mentioned subtasks in the first pipeline mode, wherein the first pipeline stage corresponding to the first pipeline mode is the same as the number of subtasks, and the first-stage operation of the first pipeline
  • the time includes the execution time of a subtask and the time for transmitting the data corresponding to the aforementioned subtask between two adjacent computing chips.
  • the computing chip can immediately start processing the subtasks of the next task after processing the subtasks of one task, which greatly reduces the waiting time of processing resources when processing tasks and improves the processing efficiency of hardware resources.
  • FIG. 5 is a schematic structural diagram of an electronic device provided by an embodiment of the application.
  • the electronic device 5 of this embodiment includes: at least one processor 50 (only one is shown in FIG. 5), a processor, a memory 51, and a memory 51 that is stored in the memory 51 and can be stored in the at least one processor 50.
  • the processor 50 executes the computer program 52, the following steps are implemented:
  • the foregoing Controlling the aforementioned different computing chips to sequentially process the aforementioned subtasks in the first pipeline mode includes:
  • the different computing chips are controlled to sequentially process the subtasks in the first pipeline mode.
  • the foregoing task processing method further includes:
  • the foregoing division of the foregoing single task into at least two sequential subtasks includes:
  • the single task is divided into at least two subtasks in sequence, where the output of the previous subtask is used as the input of the next subtask adjacent to it. .
  • the foregoing single task is divided into sequential order based on the execution time of the foregoing single task and the hardware resource information of the foregoing heterogeneous chip. At least two subtasks, including:
  • the above-mentioned single task is divided into at least two sub-tasks in sequence.
  • the foregoing calculation of the resource conversion efficiency corresponding to each division scheme includes:
  • the foregoing single task is divided into sequential order based on the execution time of the foregoing single task and the hardware resource information of the foregoing heterogeneous chip. At least two subtasks, including:
  • the above-mentioned single task is divided into at least two sub-tasks in sequence.
  • the electronic device may include, but is not limited to, a processor 50 and a memory 51.
  • FIG. 5 is only an example of the electronic device 5, and does not constitute a limitation on the electronic device 5. It may include more or less components than shown in the figure, or a combination of certain components, or different components , For example, can also include input and output devices, network access devices, and so on.
  • the so-called processor 50 may be a central processing unit (Central Processing Unit, CPU), and the processor 50 may also be other general-purpose processors, digital signal processors (Digital Signal Processors, DSPs), and application specific integrated circuits (Application Specific Integrated Circuits). , ASIC), ready-made programmable gate array (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc.
  • the general-purpose processor may be a microprocessor or the processor may also be any conventional processor or the like.
  • the above-mentioned memory 51 may be an internal storage unit of the above-mentioned electronic device 5 in some embodiments, for example, a hard disk or a memory of the electronic device 5.
  • the above-mentioned memory 51 may also be an external storage device of the above-mentioned electronic device 5, such as a plug-in hard disk equipped on the above-mentioned electronic device 5, a smart memory card (Smart Media Card, SMC), and a secure digital (Secure Digital). , SD) card, flash card (Flash Card), etc.
  • the aforementioned memory 51 may also include both an internal storage unit of the aforementioned electronic device 5 and an external storage device.
  • the above-mentioned memory 51 is used to store an operating system, an application program, a boot loader (BootLoader), data, and other programs, such as the program code of the above-mentioned computer program.
  • the aforementioned memory 51 can also be used to temporarily store data that has been output or will be output.
  • the execution instruction of a single task is first received; then the single task is divided into at least two subtasks in sequence, and each subtask is distributed to different computing chips in the heterogeneous chip. ; Finally, the different computing chips are controlled to sequentially process the subtasks in the first pipeline mode, wherein the number of first pipeline stages corresponding to the first pipeline mode is the same as the number of subtasks, and the first-stage operation of the first pipeline
  • the time includes the execution time of a subtask and the time for transmitting the data corresponding to the aforementioned subtask between two adjacent computing chips.
  • the computing chip can immediately start processing the subtasks of the next task after processing the subtasks of one task, which greatly reduces the waiting time of processing resources when processing tasks and improves the processing efficiency of hardware resources.
  • the embodiments of the present application also provide a computer-readable storage medium.
  • the above-mentioned computer-readable storage medium stores a computer program.
  • the steps in the above-mentioned method embodiments can be realized.
  • the embodiments of the present application provide a computer program product.
  • the computer program product runs on an electronic device, the electronic device can realize the steps in the foregoing method embodiments when the electronic device is executed.
  • the above integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable storage medium.
  • this application implements all or part of the processes in the above-mentioned embodiments and methods, which can be completed by instructing relevant hardware through a computer program.
  • the above-mentioned computer program can be stored in a computer-readable storage medium, and the computer program can be stored in a computer-readable storage medium. When executed by the processor, the steps of the foregoing method embodiments can be implemented.
  • the above-mentioned computer program includes computer program code, and the above-mentioned computer program code may be in the form of source code, object code, executable file, or some intermediate forms.
  • the above-mentioned computer-readable medium may at least include: any entity or device capable of carrying computer program code to a task processing device/electronic device of a heterogeneous chip, a recording medium, a computer memory, a read-only memory (ROM, Read-Only Memory), Random Access Memory (RAM, Random Access Memory), electrical carrier signal, telecommunications signal, and software distribution medium.
  • ROM Read-Only Memory
  • RAM Random Access Memory
  • electrical carrier signal telecommunications signal
  • software distribution medium for example, U disk, mobile hard disk, floppy disk or CD-ROM, etc.
  • computer-readable media cannot be electrical carrier signals and telecommunication signals.
  • the disclosed apparatus/network equipment and method may be implemented in other ways.
  • the device/network device embodiments described above are merely illustrative.
  • the division of the above-mentioned modules or units is only a logical function division, and there may be other divisions in actual implementation, such as multiple units or Components can be combined or integrated into another system, or some features can be omitted or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, mechanical or other forms.
  • the units described above as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
  • Multi Processors (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

适用于高性能计算技术领域，提供了一种异构芯片的任务处理方法、任务处理装置、电子设备及计算机可读存储介质，所述方法包括：接收单个任务的执行指令（101）；将所述单个任务划分为有先后顺序的至少二个子任务（102）；将各个子任务分发到所述异构芯片中的不同的计算芯片上（103）；控制所述不同的计算芯片以第一流水线模式依次处理所述各个子任务，其中，第一流水线模式对应的第一流水线级数与子任务的个数相同，且所述第一流水线的一级运算时间包括一个子任务的执行时间和在相邻两个计算芯片之间传输所述子任务对应的数据的时间（104）。通过上述方法，可以极大程度地降低处理资源在处理任务时的等待时间，提升硬件资源的处理效率。

Description

一种异构芯片的任务处理方法、任务处理装置及电子设备 技术领域
本申请属于高性能计算技术领域，尤其涉及一种异构芯片的任务处理方法、任务处理装置、电子设备及计算机可读存储介质。
背景技术
由于物联网，人工智能等领域的兴起，计算规模和数据体量持续增长，相比于有限的单核计算能力，多板异构众核成为一种新的解决方案。
在现有技术中，多板异构众核包括一个主机设备和多个加速器设备，各设备通过总线互联。在接收到计算任务时，根据计算任务的规模分摊硬件资源，各个设备执行单周期任务，使得设备运行时大部分处理资源处于等待阶段，在一定程度上降低了计算设备的运行效率。
因此，现有技术有待进一步改进。
技术问题
有鉴于此，本申请提供了一种异构芯片的数据处理方法、数据处理装置、电子设备及计算机可读存储介质，可以极大程度地降低处理资源在处理任务时的等待时间，提升硬件资源的处理效率。
技术解决方案
第一方面，本申请提供了一种异构芯片的任务处理方法，包括：
接收单个任务的执行指令；
将上述单个任务划分为有先后顺序的至少二个子任务；
将各个子任务分发到所述异构芯片中的不同的计算芯片上；
控制上述不同的计算芯片以第一流水线模式依次处理上述各个子任务，其中，第一流水线模式对应的第一流水线级数与子任务的个数相同，且上述第一流水线的一级运算时间包括一个子任务的执行时间和在相邻两个计算芯片之间传输上述子任务对应的数据的时间。
第二方面，本申请提供了一种异构芯片的任务处理装置，包括：
接收模块，用于接收单个任务的执行指令；
划分模块，用于将上述单个任务划分为有先后顺序的至少二个子任务；
分发模块，用于将各个子任务分发到所述异构芯片中的不同的计算芯片上；
处理模块，用于控制上述不同的计算芯片以第一流水线模式依次处理上述各个子任 务，其中，第一流水线模式对应的第一流水线级数与子任务的个数相同，且上述第一流水线的一级运算时间包括一个子任务的执行时间和在相邻两个计算芯片之间传输上述子任务对应的数据的时间。
第三方面，本申请提供了一种电子设备，包括存储器、处理器以及存储在上述存储器中并可在上述处理器上运行的计算机程序，上述处理器执行上述计算机程序时实现如上述第一方面所提供的方法。
第四方面，本申请提供了一种计算机可读存储介质，上述计算机可读存储介质存储有计算机程序，上述计算机程序被处理器执行时实现如第一方面所提供的方法。
第五方面，本申请提供了一种计算机程序产品，当计算机程序产品在电子设备上运行时，使得电子设备执行上述第一方面所提供的方法。
有益效果
由上可见，本申请方案中首先接收单个任务的执行指令；然后将上述单个任务划分为有先后顺序的至少二个子任务并将各个子任务分发到所述异构芯片中的不同的计算芯片上；最后控制上述不同的计算芯片以第一流水线模式依次处理上述各个子任务，其中，第一流水线模式对应的第一流水线级数与子任务的个数相同，且上述第一流水线的一级运算时间包括一个子任务的执行时间和在相邻两个计算芯片之间传输上述子任务对应的数据的时间。采用上述方法可以使计算芯片在处理完一个任务的子任务后，立即开始处理下一个任务的子任务，极大程度地降低处理资源在处理任务时的等待时间，提升硬件资源的处理效率。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的异构芯片的任务处理方法的流程示意图；
图2是本申请实施例提供的流水线的任务处理示意图；
图3是本申请实施例提供的电子设备与异构芯片之间的数据交互示例图；
图4是本申请实施例提供的异构芯片的任务处理装置的结构示意图；
图5是本申请实施例提供的电子设备的结构示意图。
本发明的实施方式
以下描述中，为了说明而不是为了限定，提出了诸如特定系统结构、技术之类的具体 细节，以便透彻理解本申请实施例。然而，本领域的技术人员应当清楚，在没有这些具体细节的其它实施例中也可以实现本申请。在其它情况中，省略对众所周知的系统、装置、电路以及方法的详细说明，以免不必要的细节妨碍本申请的描述。
应当理解，当在本申请说明书和所附权利要求书中使用时，术语“包括”指示所描述特征、整体、步骤、操作、元素和/或组件的存在，但并不排除一个或多个其它特征、整体、步骤、操作、元素、组件和/或其集合的存在或添加。
还应当理解，在本申请说明书和所附权利要求书中使用的术语“和/或”是指相关联列出的项中的一个或多个的任何组合以及所有可能组合，并且包括这些组合。
如在本申请说明书和所附权利要求书中所使用的那样，术语“如果”可以依据上下文被解释为“当...时”或“一旦”或“响应于确定”或“响应于检测到”。类似地，短语“如果确定”或“如果检测到[所描述条件或事件]”可以依据上下文被解释为意指“一旦确定”或“响应于确定”或“一旦检测到[所描述条件或事件]”或“响应于检测到[所描述条件或事件]”。
另外，在本申请说明书和所附权利要求书的描述中，术语“第一”、“第二”、“第三”等仅用于区分描述，而不能理解为指示或暗示相对重要性。
在本申请说明书中描述的参考“一个实施例”或“一些实施例”等意味着在本申请的一个或多个实施例中包括结合该实施例描述的特定特征、结构或特点。由此，在本说明书中的不同之处出现的语句“在一个实施例中”、“在一些实施例中”、“在其他一些实施例中”、“在另外一些实施例中”等不是必然都参考相同的实施例，而是意味着“一个或多个但不是所有的实施例”，除非是以其他方式另外特别强调。术语“包括”、“包含”、“具有”及它们的变形都意味着“包括但不限于”，除非是以其他方式另外特别强调。
图1示出了本申请实施例提供的一种异构芯片的任务处理方法的流程图，详述如下：
步骤101，接收单个任务的执行指令；
在本申请实施例中，异构芯片的任务处理方法应用于电子设备，该电子设备具有通用处理器功能。当通用处理器执行上述任务处理方法的步骤时，控制上述异构芯片中的各个计算芯片处理任务，上述任务包括待处理的数据(如图像、文本、视频)和处理该数据的程序。任务的执行指令由用户发出或触发，当用户向电子设备发出执行指令后，该电子设备即开始执行上述任务处理方法的步骤。
步骤102，将上述单个任务划分为有先后顺序的至少二个子任务；
在本申请实施例中，每个子任务包括上述程序的一部分，且每个子任务的执行具有先后顺序，上述先后顺序即上述程序的执行顺序。每个子任务按照先后顺序依次执行，即可 完成对待处理数据的处理。例如，当上述任务为通过一个卷积神经网络对待处理数据进行处理时，该卷积神经网络包括依次连接的第一卷积层、第一池化层、第二卷积层、第二池化层以及三层全连接层。将该卷积神经网络划分后，得到三个子任务，第一子任务包括通过第一卷积层和第一池化层对待处理数据进行处理，第二子任务包括通过第二卷积层和第二池化层对待处理数据进行处理，第三子任务包括通过三层全连接层对待处理数据进行处理，依次执行上述第一子任务、第二子任务以及第三子任务，即可完成对输入到该卷积神经网络的数据的处理。
需要说明的是，任务划分后得到的各个子任务的执行时间相等。如果在任务划分的过程中各个子任务的执行时间不相等，则应在各个子任务执行后添加延时，使得添加延时后的各个子任务的执行时间相等。进一步地，在各个子任务执行后添加延时的方式可以是：从各个执行时间不相等的子任务中找出执行时间最长的子任务，该执行时间最长的子任务执行后不添加延时，而其它的子任务添加延时后，执行时间变成与该执行时间最长的子任务的执行时间相等。
可选地，上述步骤102具体包括：
A1、根据上述单个任务的执行时间和上述异构芯片的硬件资源信息将上述单个任务划分为有先后顺序的至少二个子任务。
其中，上述异构芯片的硬件资源信息包括计算芯片的个数。以上述任务为通过卷积神经网络(CNN网络)对待处理数据进行处理为例进行说明，首先确定子任务的数目，再对子任务的执行时间进行优化，使子任务的执行时间尽量小。例如，将CNN网络划分为m个不可再分割的基本单元M 1，M 2，...M m，其中每个基本单元对应的执行时间为L(M i)，1≤i≤m，且i为整数。确定的子任务的数目为N，需要将m个基本单元分为N个部分。利用二分法完成：首先将各个基本单元对应的执行时间按顺序二分为
Figure PCTCN2019124350-appb-000001
与
Figure PCTCN2019124350-appb-000002
部分，1≤j≤m，且j为整数，在满足
Figure PCTCN2019124350-appb-000003
的情况下取j的最大值，将基本单元M 1、M 2……M j一起组成一个子任务，其中L(Max)为各个基本单元对应的执行时间中最长的执行时间。下一步将
Figure PCTCN2019124350-appb-000004
划分为
Figure PCTCN2019124350-appb-000005
和
Figure PCTCN2019124350-appb-000006
两部分，其中，j+1≤k≤m，且k为整数，在满足
Figure PCTCN2019124350-appb-000007
的 情况下取k的最大值，将基本单元M j+1、M j+2……M k一起组成一个子任务，依次迭代划分。
作为一种可能的实现方式，确定子任务的数目可以采用以下方式：以上述CNN网络为例，先将上述CNN网络划分为多个单元，每个单元为CNN网络中的一层，为CNN网络中不可分割的最小单元。从多个单元中，选取执行时间最大的单元。计算上述CNN网络总执行时间与该执行时间最大的单元的执行时间的比值。将上述异构芯片中计算芯片的个数与该比值进行比较，若计算芯片的个数大于该比值，则划分后的子任务数目为该比值向上取整的数值，若计算芯片的个数小于该比值，则划分后的子任务数目为计算芯片的个数。
单个任务划分后，得到的子任务数目不能够大于计算芯片的数目，以保证每个子任务被一个计算芯片执行。在有先后顺序的多个子任务中，前一个子任务执行完毕得到的输出发送到后一个子任务，作为后一个子任务的输入，首个子任务的输入则为任务中包括的待处理的数据，最后一个子任务的输出则为最后的任务执行结果。划分后各个子任务对应的执行时间一致。
可选地，上述步骤A1具体包括：
B1、根据上述单个任务的执行时间和上述异构芯片的硬件资源信息确定至少一个划分方案，上述划分方案为将任务划分为至少二个子任务的方案；
B2、计算每个划分方案对应的资源转换效率；
B3、从上述至少一个划分方案中选取对应的资源转换效率最大的划分方案作为最终划分方案；
B4、根据上述最终划分方案将上述单个任务划分为有先后顺序的至少二个子任务。
具体地，首先根据上述单个任务的执行时间和上述异构芯片中计算芯片的个数确定多个划分方案，划分方案的个数取决于计算芯片的个数，可以先确定划分方案所要划分的子任务的数目，再根据步骤A1中的任务划分方法将任务对应划分。例如，上述异构芯片包括四个计算芯片，那么上述划分方案的个数就为三个，三个划分方案分别为第一方案：将任务划分为4个子任务，第二方案：将任务划分为3个子任务，第三方案：将任务划分为2个子任务。得到多个划分方案后，分别计算各个划分方案对应的资源转换效率。
电子设备可以基于任务的浮点运算量、吞吐率以及任务占用的硬件资源计算资源转换效率。该资源转换效率指示了在异构芯片在任务处理过程中，单位硬件资源的处理能力，反映了对应划分方案对硬件资源的优化程度。资源转换效率越大，则表示异构芯片的单位硬件资源的处理能力越强，反之，资源转换效率越小，则表示异构芯片的单位硬件资源的处理能力越弱。因此，在计算得到各个划分方案对应的资源转换效率后，比较各个划分方案对应的资源转换效率的数值大小，将各个划分方案中对应的资源转换效率最大的划分方 案作为最终划分方案。还是以上述第一方案、第二方案以及第三方案为例，通过计算，得到第一方案对应的资源转换效率为0.5，第二方案对应的资源转换效率为0.6，第三方案对应的资源转换效率为0.7，则通过比较资源转换效率的大小，选取第三方案作为最终划分方案。
可选地，上述步骤B2具体包括：
根据预设的资源转换效率公式计算每个划分方案对应的资源转换效率。
其中，上述资源转换效率公式为γ＝Pβ/N，γ为资源转换效率，P为单个任务的计算量，β为异构芯片执行单个任务过程中的吞吐率，N为计算芯片的个数。上述吞吐率可以根据划分方案对应的子任务的个数和子任务的运行时间计算得到，上述计算芯片的个数为根据子任务的个数实际使用的计算芯片个数。
可选地，上述步骤A1具体包括：
C1、根据上述单个任务的执行时间和上述异构芯片的硬件资源信息确定至少一个划分方案，上述划分方案为将单个任务划分为至少二个子任务的方案；
C2、从上述至少一个划分方案中筛选出至少一个满足预设的筛选条件的初选划分方案；
C3、从至少一个初选划分方案中选取子任务数目最大的初选划分方案作为最终划分方案；
C4、根据上述最终划分方案将上述单个任务划分为有先后顺序的至少二个子任务。
具体地，首先根据上述单个任务的执行时间和上述异构芯片中计算芯片的个数确定多个划分方案，划分方案的个数取决于计算芯片的个数，可以先确定划分方案所要划分的子任务的数目，再根据步骤A1中的任务划分方法将任务对应划分。例如，上述异构芯片包括四个计算芯片，那么上述划分方案的个数就为三个，三个划分方案分别为第一方案：将任务划分为4个子任务，第二方案：将任务划分为3个子任务，第三方案：将任务划分为2个子任务。得到多个划分方案后，分别计算各个划分方案对应的资源利用率，上述资源利用率指示了子任务在对应的单个计算芯片上运行时占用的硬件资源大小。得到各个划分方案对应的资源利用率后，从各个划分方案中筛选出满足预设的筛选条件的初选划分方案，上述筛选条件即为划分方案对应的资源利用率要大于预设的资源利用率阈值，当划分方案满足该筛选条件时，可以充分发挥计算芯片的性能。在多个初选划分方案中，选择子任务数目最大的初选划分方案作为最终划分方案，子任务的数目越大，任务处理时的并行程度就越高，异构芯片的吞吐率也就越大。根据上述最终划分方案将上述任务划分为有先后顺 序的至少二个子任务。例如，上述第一方案对应的资源利用率为50％，第二方案对应的资源利用率为70％，第三方案对应的资源利用率为80％，筛选条件为划分方案对应的资源利用率要大于60％，那么根据该筛选条件筛选出的初选划分方案就包括第二方案和第三方案。而第二方案对应的子任务数目为2，第三方案对应的子任务数目为1，则选取第二方案作为最终划分方案。根据该最终划分方案，将任务划分为2个子任务。
步骤103，将各个子任务分发到所述异构芯片中的不同的计算芯片上；
在本申请实施例中，划分后的各个子任务需发送到不同的计算芯片上执行，一个计算芯片执行一个子任务。例如，上述异构芯片中包括5个计算芯片，子任务数目为3个，则将子任务分别发送到5个计算芯片中的3个计算芯片上执行，剩余2个计算芯片不进行子任务的处理。其中，异构芯片中的计算芯片通过总线依次连接。以计算芯片为FPGA为例，在将各个子任务分发到不同的FPGA之前，需要将各个子任务转换为比特流文件，然后将各个子任务对应的比特流文件烧写到相应的FPGA。
步骤104，控制上述不同的计算芯片以第一流水线模式依次处理上述各个子任务。
在本申请实施例中，上述第一流水线模式对应的第一流水线的级数与上述子任务的个数相同，上述第一流水线的一级运算时间包括一个子任务的执行时间与相邻两个计算芯片之间传输上述子任务对应的数据的时间。且上述第一流水线的各个流水线级的运算时间相等。需要说明的是，各个子任务在计算芯片上的执行时间是相等的，各相邻计算芯片之间传输子任务对应的数据的时间也是相等的，子任务在计算芯片上的执行时间要大于相邻计算芯片之间传输上述子任务对应的数据的时间。上述第一流水线的一级包括计算芯片执行对应的子任务和将上述子任务的处理结果传输至下一个计算芯片。
进一步地，由于上述第一流水线的每一级的运算时间均相等，且上述第一流水线的每一级都处理一个子任务，在需要处理的相同的单个任务有多个时，上述第一流水线可以并行处理上述多个任务。即上述第一流水线的第二级开始处理第一个任务时，上述第一流水线的第一级开始处理第二个任务，上述第一流水线的第二级开始处理第二个任务时，上述第一流水线的第一级开始处理第三个任务，以此类推。引出图2以作解释，图2中的(a)部分为第一流水线处理并行三个任务的过程，其中，t m为子任务的执行时间，t l为各相邻计算芯片之间传输子任务对应的数据的时间，第一流水线的一级的运算时间等于t m+t l。第一任务、第二任务以及第三任务均为卷积神经网络，且该卷积神经网络包括2层卷积层、2层池化层、1层全连接层。Conv+Pool表示一个包含一层卷积层和一层池化层的子任务，Fullyconn表示一个包含一层全连接层的子任务。当第一任务的第一个Conv+Pool执行结束并经过一个t l的时长后，第一流水线开始处理第二任务的第一个Conv+Pool。
可选地，若接收到至少二个相同的单个任务的执行指令，则上述步骤104具体包括：
D1、根据单个任务的子任务的个数、子任务的运算时间以及在相邻两个计算芯片之间传输上述子任务对应的数据的时间，计算模式阈值；
D2、若上述相同的单个任务的个数小于或等于上述模式阈值，则控制上述不同的计算芯片以第一流水线模式依次处理上述各个子任务。
具体地，根据预设的公式计算L＝M(t m+t l)/t l+1计算上述模式阈值，其中，L为模式阈值，M为流水线的级数，t m为子任务的执行时间，t l为在相邻两个计算芯片之间传输上述子任务对应的数据的时间。当需要处理的任务的个数小于或等于上述模式阈值时，则控制上述不同的计算芯片以第一流水线模式依次处理上述各个子任务。
可选地，若上述相同的单个任务的个数大于上述模式阈值，则上述任务处理方法还包括：
控制上述不同的计算芯片以第二流水线模式依次处理上述各个子任务；
其中，一个子任务的执行和上述子任务对应的数据在相邻两个计算芯片之间的传输分别作为上述第二流水线模式对应的第二流水线的一级，且上述第二流水线的一级运算时间等于一个子任务的执行时间。与上述第一流水线模式是将一个子任务的执行和所述子任务对应的数据在相邻两个计算芯片之间的传输一起作为上述第一流水线的一级，上述第二流水线是将一个子任务的执行和将所述子任务对应的数据在相邻两个计算芯片之间的传输分别作为所述第二流水线模式对应的第二流水线的一级。也即是说，上述第二流水线的一级可能为一个子任务的执行，也可能为一个子任务对应的数据在相邻两个计算芯片之间的传输。需要说明的是，为了使上述第二流水线的每一级的运算时间相等，在各相邻计算芯片之间传输子任务对应的数据后添加了延时，使得一个子任务的执行时间等于所述子任务对应的数据在相邻两个计算芯片之间传输的时间。
进一步地，由于上述第二流水线的每一级的运算时间均相等，且上述第二流水线的每一级子任务处理流水线级都处理一个子任务，在需要处理的任务有多个时，上述第二流水线可以并行处理上述多个任务。即上述第二流水线的第二级(为数据传输流水线级)开始进行第一个任务的数据传输时，上述第二流水线的第一级开始处理第二个任务，上述第二流水线的第三级开始进行处理第一个任务时，上述第二流水线的第一级开始处理第三个任务，以此类推。引出图2以作解释，图2中的(b)部分为第二流水线处理并行三个任务的过程，其中，t m为子任务的执行时间，第二流水线的一级的运算时间等于t m。第一任务、第二任务以及第三任务均为卷积神经网络，且该卷积神经网络包括2层卷积层、2层池化层、1层全连接层。Conv+Pool表示一个包含一层卷积层和一层池化层的子任务，Fullyconn 表示一个包含一层全连接层的子任务，Latency为数据传输流水线级。当第一任务的第一个Conv+Pool执行结束，第二流水线开始处理第二任务的第一个Conv+Pool。
如图3所示，电子设备可以为赛灵思公司推出的ZYNQ 7035系列开发板，计算芯片可以为现场可编程逻辑门阵列(Field Programmable Gate Array，FPGA)，此处不作限定。ZYNQ 7035系列开发板通过PS(Processing System，处理系统)端的以太网口与上位机进行通信，同时使用RapidIO协议，高速串行收发器与各个FPGA通信，用户可通过上位机向ZYNQ 7035系列开发板发送任务的执行指令，该ZYNQ 7035系列开发板接收到执行指令，控制各个FPGA执行上述任务，当各个FPGA执行完上述任务得到处理结果时，ZYNQ 7035系列开发板接收该处理结果并将该处理结果通过以太网口发送给上位机。
由上可见，本申请方案中首先接收单个任务的执行指令；然后将上述单个任务划分为有先后顺序的至少二个子任务并将各个子任务分发到所述异构芯片中的不同的计算芯片上；最后控制上述不同的计算芯片以第一流水线模式依次处理上述各个子任务，其中，第一流水线模式对应的第一流水线级数与子任务的个数相同，且上述第一流水线的一级运算时间包括一个子任务的执行时间和在相邻两个计算芯片之间传输上述子任务对应的数据的时间。采用上述方法可以使计算芯片在处理完一个任务的子任务后，立即开始处理下一个任务的子任务，极大程度地降低处理资源在处理任务时的等待时间，提升硬件资源的处理效率。
应理解，上述实施例中各步骤的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
图4示出了本申请实施例提供的一种异构芯片的任务处理装置的结构示意图，该异构芯片的任务处理装置可应用于电子设备，为了便于说明，仅示出了与本申请实施例相关的部分。
该异构芯片的任务处理装置400包括：
接收模块401，用于接收单个任务的执行指令；
划分模块402，用于将上述单个任务划分为有先后顺序的至少二个子任务；
分发模块403，用于将各个子任务分发到所述异构芯片中的不同的计算芯片上；
处理模块404，用于控制上述不同的计算芯片以第一流水线模式依次处理上述各个子任务，其中，第一流水线模式对应的第一流水线级数与子任务的个数相同，且上述第一流水线的一级运算时间包括一个子任务的执行时间和在相邻两个计算芯片之间传输上述子任 务对应的数据的时间。
可选地，若接收到至少二个相同的单个任务的执行指令，则上述处理模块404还包括：
模式阈值计算单元，用于根据单个任务的子任务的个数、子任务的运算时间以及在相邻两个计算芯片之间传输上述子任务对应的数据的时间，计算模式阈值；
第一控制单元，用于若上述相同的单个任务的个数小于或等于上述模式阈值，则控制上述不同的计算芯片以第一流水线模式依次处理上述各个子任务。
可选地，若上述相同的单个任务的个数大于上述模式阈值，则上述异构芯片的任务处理装置400还包括：
第二控制单元，用于控制上述不同的计算芯片以第二流水线模式依次处理上述各个子任务，其中，一个子任务的执行和上述子任务对应的数据在相邻两个计算芯片之间的传输分别作为上述第二流水线模式对应的第二流水线的一级，且上述第二流水线的一级运算时间等于一个子任务的执行时间。
可选地，上述划分模块402还包括：
执行时间划分单元，用于根据上述单个任务的执行时间和上述异构芯片的硬件资源信息将上述单个任务划分为有先后顺序的至少二个子任务，其中，前一个子任务的输出作为与其相邻的后一个子任务的输入。
可选地，上述执行时间划分单元还包括：
第一方案确定子单元，用于根据上述单个任务的执行时间和上述异构芯片的硬件资源信息确定至少一个划分方案，上述划分方案为将单个任务划分为至少二个子任务的方案；
效率计算子单元，用于计算每个划分方案对应的资源转换效率，其中，上述资源转换效率指示了异构芯片的单位硬件资源的数据处理能力；
第一最终方案确定子单元，用于从上述至少一个划分方案中选取对应的资源转换效率最大的划分方案作为最终划分方案；
第一最终划分子单元，用于根据上述最终划分方案将上述单个任务划分为有先后顺序的至少二个子任务。
可选地，上述效率计算子单元还包括：
效率公式计算子单元，用于根据预设的资源转换效率公式计算每个划分方案对应的资源转换效率，上述资源转换效率公式为γ＝Pβ/N，其中，γ为资源转换效率，P为单个任务的计算量，β为异构芯片执行单个任务过程中的吞吐率，N为计算芯片的个数。
可选地，上述执行时间划分单元还包括：
第二方案确定子单元，用于根据上述单个任务的执行时间和上述异构芯片的硬件资源信息确定至少一个划分方案，上述划分方案为将单个任务划分为至少二个子任务的方案；
筛选子单元，用于从上述至少一个划分方案中筛选出至少一个满足预设的筛选条件的初选划分方案，其中，上述筛选条件为划分方案对应的资源利用率大于预设的资源利用率阈值；
第二最终方案确定子单元，用于从至少一个初选划分方案中选取子任务数目最大的初选划分方案作为最终划分方案；
第二最终划分子单元，用于根据上述最终划分方案将上述单个任务划分为有先后顺序的至少二个子任务。
由上可见，本申请方案中首先接收单个任务的执行指令；然后将上述单个任务划分为有先后顺序的至少二个子任务并将各个子任务分发到所述异构芯片中的不同的计算芯片上；最后控制上述不同的计算芯片以第一流水线模式依次处理上述各个子任务，其中，第一流水线模式对应的第一流水线级数与子任务的个数相同，且上述第一流水线的一级运算时间包括一个子任务的执行时间和在相邻两个计算芯片之间传输上述子任务对应的数据的时间。采用上述方法可以使计算芯片在处理完一个任务的子任务后，立即开始处理下一个任务的子任务，极大程度地降低处理资源在处理任务时的等待时间，提升硬件资源的处理效率。
图5为本申请实施例提供的电子设备的结构示意图。如图5所示，该实施例的电子设备5包括：至少一个处理器50(图5中仅示出一个)处理器、存储器51以及存储在上述存储器51中并可在上述至少一个处理器50上运行的计算机程序52，上述处理器50执行上述计算机程序52时实现以下步骤：
接收单个任务的执行指令；
将上述单个任务划分为有先后顺序的至少二个子任务；
将各个子任务分发到所述异构芯片中的不同的计算芯片上；
控制上述不同的计算芯片以第一流水线模式依次处理上述各个子任务，其中，第一流水线模式对应的第一流水线级数与子任务的个数相同，且上述第一流水线的一级运算时间包括一个子任务的执行时间和在相邻两个计算芯片之间传输上述子任务对应的数据的时间。
假设上述为第一种可能的实施方式，则在第一种可能的实施方式作为基础而提供的第二种可能的实施方式中，若接收到至少二个相同的单个任务的执行指令，则上述控制上述 不同的计算芯片以第一流水线模式依次处理上述各个子任务，包括：
根据单个任务的子任务的个数、子任务的运算时间以及在相邻两个计算芯片之间传输上述子任务对应的数据的时间，计算模式阈值；
若上述相同的单个任务的个数小于或等于上述模式阈值，则控制上述不同的计算芯片以第一流水线模式依次处理上述各个子任务。
在上述第二种可能的实施方式作为基础而提供的第三种可能的实施方式中，若上述相同的单个任务的个数大于上述模式阈值，则上述任务处理方法还包括：
控制上述不同的计算芯片以第二流水线模式依次处理上述各个子任务，其中，一个子任务的执行和上述子任务对应的数据在相邻两个计算芯片之间的传输分别作为上述第二流水线模式对应的第二流水线的一级，且上述第二流水线的一级运算时间等于一个子任务的执行时间。
在上述第一种可能的实施方式作为基础而提供的第四种可能的实施方式中，上述将上述单个任务划分为有先后顺序的至少二个子任务，包括：
根据上述单个任务的执行时间和上述异构芯片的硬件资源信息将上述单个任务划分为有先后顺序的至少二个子任务，其中，前一个子任务的输出作为与其相邻的后一个子任务的输入。
在上述第四种可能的实施方式作为基础而提供的第五种可能的实施方式中，上述根据上述单个任务的执行时间和上述异构芯片的硬件资源信息将上述单个任务划分为有先后顺序的至少二个子任务，包括：
根据上述单个任务的执行时间和上述异构芯片的硬件资源信息确定至少一个划分方案，上述划分方案为将单个任务划分为至少二个子任务的方案；
计算每个划分方案对应的资源转换效率，其中，上述资源转换效率指示了异构芯片的单位硬件资源的数据处理能力；
从上述至少一个划分方案中选取对应的资源转换效率最大的划分方案作为最终划分方案；
根据上述最终划分方案将上述单个任务划分为有先后顺序的至少二个子任务。
在上述第五种可能的实施方式作为基础而提供的第六种可能的实施方式中，上述计算每个划分方案对应的资源转换效率，包括：
根据预设的资源转换效率公式计算每个划分方案对应的资源转换效率，上述资源转换效率公式为γ＝Pβ/N，其中，γ为资源转换效率，P为单个任务的计算量，β为异构芯片 执行单个任务过程中的吞吐率，N为计算芯片的个数。
在上述第四种可能的实施方式作为基础而提供的第七种可能的实施方式中，上述根据上述单个任务的执行时间和上述异构芯片的硬件资源信息将上述单个任务划分为有先后顺序的至少二个子任务，包括：
根据上述单个任务的执行时间和上述异构芯片的硬件资源信息确定至少一个划分方案，上述划分方案为将单个任务划分为至少二个子任务的方案；
从上述至少一个划分方案中筛选出至少一个满足预设的筛选条件的初选划分方案，其中，上述筛选条件为划分方案对应的资源利用率大于预设的资源利用率阈值；
从至少一个初选划分方案中选取子任务数目最大的初选划分方案作为最终划分方案；
根据上述最终划分方案将上述单个任务划分为有先后顺序的至少二个子任务。
该电子设备可包括，但不仅限于，处理器50、存储器51。本领域技术人员可以理解，图5仅仅是电子设备5的举例，并不构成对电子设备5的限定，可以包括比图示更多或更少的部件，或者组合某些部件，或者不同的部件，例如还可以包括输入输出设备、网络接入设备等。
所称处理器50可以是中央处理单元(Central Processing Unit，CPU)，该处理器50还可以是其他通用处理器、数字信号处理器(Digital Signal Processor，DSP)、专用集成电路(Application Specific Integrated Circuit，ASIC)、现成可编程门阵列(Field-Programmable Gate Array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。
上述存储器51在一些实施例中可以是上述电子设备5的内部存储单元，例如电子设备5的硬盘或内存。上述存储器51在另一些实施例中也可以是上述电子设备5的外部存储设备，例如上述电子设备5上配备的插接式硬盘，智能存储卡(Smart Media Card,SMC)，安全数字(Secure Digital,SD)卡，闪存卡(Flash Card)等。进一步地，上述存储器51还可以既包括上述电子设备5的内部存储单元也包括外部存储设备。上述存储器51用于存储操作系统、应用程序、引导装载程序(BootLoader)、数据以及其他程序等，例如上述计算机程序的程序代码等。上述存储器51还可以用于暂时地存储已经输出或者将要输出的数据。
由上可见，本申请方案中首先接收单个任务的执行指令；然后将上述单个任务划分为有先后顺序的至少二个子任务并将各个子任务分发到所述异构芯片中的不同的计算芯片上；最后控制上述不同的计算芯片以第一流水线模式依次处理上述各个子任务，其中，第 一流水线模式对应的第一流水线级数与子任务的个数相同，且上述第一流水线的一级运算时间包括一个子任务的执行时间和在相邻两个计算芯片之间传输上述子任务对应的数据的时间。采用上述方法可以使计算芯片在处理完一个任务的子任务后，立即开始处理下一个任务的子任务，极大程度地降低处理资源在处理任务时的等待时间，提升硬件资源的处理效率。
需要说明的是，上述装置/单元之间的信息交互、执行过程等内容，由于与本申请方法实施例基于同一构思，其具体功能及带来的技术效果，具体可参见方法实施例部分，此处不再赘述。
所属领域的技术人员可以清楚地了解到，为了描述的方便和简洁，仅以上述各功能单元、模块的划分进行举例说明，实际应用中，可以根据需要而将上述功能分配由不同的功能单元、模块完成，即将上述装置的内部结构划分成不同的功能单元或模块，以完成以上描述的全部或者部分功能。实施例中的各功能单元、模块可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中，上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。另外，各功能单元、模块的具体名称也只是为了便于相互区分，并不用于限制本申请的保护范围。上述系统中单元、模块的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
本申请实施例还提供了一种计算机可读存储介质，上述计算机可读存储介质存储有计算机程序，上述计算机程序被处理器执行时实现可实现上述各个方法实施例中的步骤。
本申请实施例提供了一种计算机程序产品，当计算机程序产品在电子设备上运行时，使得电子设备执行时实现可实现上述各个方法实施例中的步骤。
上述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请实现上述实施例方法中的全部或部分流程，可以通过计算机程序来指令相关的硬件来完成，上述的计算机程序可存储于一计算机可读存储介质中，该计算机程序在被处理器执行时，可实现上述各个方法实施例的步骤。其中，上述计算机程序包括计算机程序代码，上述计算机程序代码可以为源代码形式、对象代码形式、可执行文件或某些中间形式等。上述计算机可读介质至少可以包括：能够将计算机程序代码携带到异构芯片的任务处理装置/电子设备的任何实体或装置、记录介质、计算机存储器、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、电载波信号、电信信号以及软件分发介质。例如U盘、移动硬盘、磁碟或者光盘等。在某些司法管辖区，根据立法和专利实践，计算机可读 介质不可以是电载波信号和电信信号。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述或记载的部分，可以参见其它实施例的相关描述。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
在本申请所提供的实施例中，应该理解到，所揭露的装置/网络设备和方法，可以通过其它的方式实现。例如，以上所描述的装置/网络设备实施例仅仅是示意性的，例如，上述模块或单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通讯连接可以是通过一些接口，装置或单元的间接耦合或通讯连接，可以是电性，机械或其它的形式。
上述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
以上上述实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围，均应包含在本申请的保护范围之内。

Claims (10)

  1. 一种异构芯片的任务处理方法，其特征在于，包括：
    接收单个任务的执行指令；
    将所述单个任务划分为有先后顺序的至少二个子任务；
    将各个子任务分发到所述异构芯片中的不同的计算芯片上；
    控制所述不同的计算芯片以第一流水线模式依次处理所述各个子任务，其中，第一流水线模式对应的第一流水线级数与子任务的个数相同，且所述第一流水线的一级运算时间包括一个子任务的执行时间和在相邻两个计算芯片之间传输所述子任务对应的数据的时间。
  2. 根据权利要求1所述的任务处理方法，其特征在于，若接收到至少二个相同的单个任务的执行指令，则所述控制所述不同的计算芯片以第一流水线模式依次处理所述各个子任务，包括：
    根据单个任务的子任务的个数、子任务的运算时间以及在相邻两个计算芯片之间传输所述子任务对应的数据的时间，计算模式阈值；
    若所述相同的单个任务的个数小于或等于所述模式阈值，则控制所述不同的计算芯片以第一流水线模式依次处理所述各个子任务。
  3. 根据权利要求2所述的任务处理方法，其特征在于，若所述相同的单个任务的个数大于所述模式阈值，则所述任务处理方法还包括：
    控制所述不同的计算芯片以第二流水线模式依次处理所述各个子任务，其中，一个子任务的执行和所述子任务对应的数据在相邻两个计算芯片之间的传输分别作为所述第二流水线模式对应的第二流水线的一级，且所述第二流水线的一级运算时间等于一个子任务的执行时间。
  4. 根据权利要求1所述的任务处理方法，其特征在于，所述将所述单个任务划分为有先后顺序的至少二个子任务，包括：
    根据所述单个任务的执行时间和所述异构芯片的硬件资源信息，将所述单个任务划分为有先后顺序的至少二个子任务，其中，前一个子任务的输出作为与其相邻的后一个子任务的输入。
  5. 根据权利要求4所述的任务处理方法，其特征在于，所述根据所述单个任务的执行时间和所述异构芯片的硬件资源信息，将所述单个任务划分为有先后顺序的至少二个子任务，包括：
    根据所述单个任务的执行时间和所述异构芯片的硬件资源信息，确定至少一个划分方 案，所述划分方案为将单个任务划分为至少二个子任务的方案；
    计算每个划分方案对应的资源转换效率，其中，所述资源转换效率指示了异构芯片的单位硬件资源的数据处理能力；
    从所述至少一个划分方案中选取对应的资源转换效率最大的划分方案作为最终划分方案；
    根据所述最终划分方案将所述单个任务划分为有先后顺序的至少二个子任务。
  6. 根据权利要求5所述的任务处理方法，其特征在于，所述计算每个划分方案对应的资源转换效率，包括：
    根据预设的资源转换效率公式计算每个划分方案对应的资源转换效率，所述资源转换效率公式为γ＝Pβ/N，其中，γ为资源转换效率，P为单个任务的计算量，β为异构芯片执行单个任务过程中的吞吐率，N为计算芯片的个数。
  7. 根据权利要求4所述的任务处理方法，其特征在于，所述根据所述单个任务的执行时间和所述异构芯片的硬件资源信息将所述单个任务划分为有先后顺序的至少二个子任务，包括：
    根据所述单个任务的执行时间和所述异构芯片的硬件资源信息确定至少一个划分方案，所述划分方案为将单个任务划分为至少二个子任务的方案；
    从所述至少一个划分方案中筛选出至少一个满足预设的筛选条件的初选划分方案，其中，所述筛选条件为划分方案对应的资源利用率大于预设的资源利用率阈值；
    从至少一个初选划分方案中选取子任务数目最大的初选划分方案作为最终划分方案；
    根据所述最终划分方案将所述单个任务划分为有先后顺序的至少二个子任务。
  8. 一种异构芯片的任务处理装置，其特征在于，包括：
    接收模块，用于接收单个任务的执行指令；
    划分模块，用于将所述单个任务划分为有先后顺序的至少二个子任务；
    分发模块，用于将各个子任务分发到所述异构芯片中的不同的计算芯片上；
    处理模块，用于控制所述不同的计算芯片以第一流水线模式依次处理所述各个子任务，其中，第一流水线模式对应的第一流水线级数与子任务的个数相同，且所述第一流水线的一级运算时间包括一个子任务的执行时间和在相邻两个计算芯片之间传输所述子任务对应的数据的时间。
  9. 一种电子设备，包括存储器、处理器以及存储在所述存储器中并可在所述处理器上 运行的计算机程序，其特征在于，所述处理器执行所述计算机程序时实现如权利要求1至7任一项所述的方法。
  10. 一种计算机可读存储介质，所述计算机可读存储介质存储有计算机程序，其特征在于，所述计算机程序被处理器执行时实现如权利要求1至7任一项所述的方法。
PCT/CN2019/124350 2019-11-20 2019-12-10 一种异构芯片的任务处理方法、任务处理装置及电子设备 WO2021097962A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201911142365 2019-11-20
CN201911142365.7 2019-11-20

Publications (1)

Publication Number Publication Date
WO2021097962A1 true WO2021097962A1 (zh) 2021-05-27

Family

ID=70517887

Family Applications (2)

Application Number Title Priority Date Filing Date
PCT/CN2019/124350 WO2021097962A1 (zh) 2019-11-20 2019-12-10 一种异构芯片的任务处理方法、任务处理装置及电子设备
PCT/CN2020/129492 WO2021115052A1 (zh) 2019-11-20 2020-11-17 一种异构芯片的任务处理方法、任务处理装置及电子设备

Family Applications After (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/129492 WO2021115052A1 (zh) 2019-11-20 2020-11-17 一种异构芯片的任务处理方法、任务处理装置及电子设备

Country Status (2)

Country Link
CN (1) CN111142938B (zh)
WO (2) WO2021097962A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114741202A (zh) * 2022-04-27 2022-07-12 苏州浪潮智能科技有限公司 一种fpga设备的算法配置方法、装置、设备及存储介质
CN115549854A (zh) * 2021-06-30 2022-12-30 上海寒武纪信息科技有限公司 循环冗余校验方法、装置、存储介质以及电子设备

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021097962A1 (zh) * 2019-11-20 2021-05-27 深圳先进技术研究院 一种异构芯片的任务处理方法、任务处理装置及电子设备
CN113742089B (zh) * 2021-11-04 2022-02-18 苏州浪潮智能科技有限公司 异构资源中神经网络计算任务的分配方法、装置和设备
CN115016847B (zh) * 2022-08-08 2022-12-20 沐曦集成电路(上海)有限公司 提高流水线吞吐的方法、装置及电子设备
CN115712499A (zh) * 2022-11-09 2023-02-24 北京城建设计发展集团股份有限公司 一种轨交业务ai芯片驱动任务处理方法及系统
CN116187399B (zh) * 2023-05-04 2023-06-23 北京麟卓信息科技有限公司 一种基于异构芯片的深度学习模型计算误差定位方法
CN116382880B (zh) * 2023-06-07 2023-08-11 成都登临科技有限公司 任务执行方法、装置、处理器、电子设备及存储介质

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101339523A (zh) * 2007-07-05 2009-01-07 国际商业机器公司 多处理器环境中的流水线处理方法和设备
CN103810137A (zh) * 2014-01-07 2014-05-21 南京大学 一种基于多fpga平台的ncs算法并行化的方法
CN103838552A (zh) * 2014-03-18 2014-06-04 北京邮电大学 4g宽带通信系统多核并行流水线信号的处理系统和方法
US20140317380A1 (en) * 2013-04-18 2014-10-23 Denso Corporation Multi-core processor
CN104615413A (zh) * 2015-02-13 2015-05-13 赛诺威盛科技（北京）有限公司 一种流水线任务自适应并行方法
CN108984283A (zh) * 2018-06-25 2018-12-11 复旦大学 一种自适应的动态流水线并行方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9122523B2 (en) * 2012-05-03 2015-09-01 Nec Laboratories America, Inc. Automatic pipelining framework for heterogeneous parallel computing systems
CN104866460B (zh) * 2015-06-04 2017-10-10 电子科技大学 一种基于SoC的容错自适应可重构系统与方法
CN106227591B (zh) * 2016-08-05 2019-10-25 中国科学院计算技术研究所 在异构多核片上系统上进行无线通信调度的方法和装置
CN108205465B (zh) * 2016-12-20 2021-06-15 北京中科晶上科技股份有限公司 流式应用程序的任务动态调度方法和装置
US10795729B2 (en) * 2018-04-28 2020-10-06 Cambricon Technologies Corporation Limited Data accelerated processing system
CN109857562A (zh) * 2019-02-13 2019-06-07 北京理工大学 一种众核处理器上访存距离优化的方法
WO2021097962A1 (zh) * 2019-11-20 2021-05-27 深圳先进技术研究院 一种异构芯片的任务处理方法、任务处理装置及电子设备

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101339523A (zh) * 2007-07-05 2009-01-07 国际商业机器公司 多处理器环境中的流水线处理方法和设备
US20140317380A1 (en) * 2013-04-18 2014-10-23 Denso Corporation Multi-core processor
CN103810137A (zh) * 2014-01-07 2014-05-21 南京大学 一种基于多fpga平台的ncs算法并行化的方法
CN103838552A (zh) * 2014-03-18 2014-06-04 北京邮电大学 4g宽带通信系统多核并行流水线信号的处理系统和方法
CN104615413A (zh) * 2015-02-13 2015-05-13 赛诺威盛科技（北京）有限公司 一种流水线任务自适应并行方法
CN108984283A (zh) * 2018-06-25 2018-12-11 复旦大学 一种自适应的动态流水线并行方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115549854A (zh) * 2021-06-30 2022-12-30 上海寒武纪信息科技有限公司 循环冗余校验方法、装置、存储介质以及电子设备
CN114741202A (zh) * 2022-04-27 2022-07-12 苏州浪潮智能科技有限公司 一种fpga设备的算法配置方法、装置、设备及存储介质

Also Published As

Publication number Publication date
CN111142938B (zh) 2023-07-07
CN111142938A (zh) 2020-05-12
WO2021115052A1 (zh) 2021-06-17

Similar Documents

Publication Publication Date Title
WO2021115052A1 (zh) 一种异构芯片的任务处理方法、任务处理装置及电子设备
US11836524B2 (en) Memory interface for a multi-threaded, self-scheduling reconfigurable computing fabric
US11868163B2 (en) Efficient loop execution for a multi-threaded, self-scheduling reconfigurable computing fabric
US11675598B2 (en) Loop execution control for a multi-threaded, self-scheduling reconfigurable computing fabric using a reenter queue
US11915057B2 (en) Computational partition for a multi-threaded, self-scheduling reconfigurable computing fabric
US11675734B2 (en) Loop thread order execution control of a multi-threaded, self-scheduling reconfigurable computing fabric
US11573796B2 (en) Conditional branching control for a multi-threaded, self-scheduling reconfigurable computing fabric
US11531543B2 (en) Backpressure control using a stop signal for a multi-threaded, self-scheduling reconfigurable computing fabric
US20210255864A1 (en) Multiple Types of Thread Identifiers for a Multi-Threaded, Self-Scheduling Reconfigurable Computing Fabric
US11635959B2 (en) Execution control of a multi-threaded, self-scheduling reconfigurable computing fabric
JP2020537784A (ja) ニューラルネットワークアクセラレーションのための機械学習ランタイムライブラリ
US11048656B2 (en) Multi-threaded, self-scheduling reconfigurable computing fabric
TWI827792B (zh) 多路徑神經網路、資源配置的方法及多路徑神經網路分析器
AU2014203218B2 (en) Memory configuration for inter-processor communication in an MPSoC
WO2005098623A2 (en) Prerequisite-based scheduler
WO2021249192A1 (zh) 图像处理方法及装置、机器视觉设备、电子设备和计算机可读存储介质
US11061654B1 (en) Synchronization of concurrent computation engines
WO2020156212A1 (zh) 一种数据处理的方法、装置及电子设备
CN113504893B (zh) 一种智能芯片架构和高效处理数据的方法
WO2022141321A1 (zh) Dsp处理器及其并行计算方法
CN115729704A (zh) 算力资源分配方法、装置及计算机可读存储介质
CN118504630A (zh) 基于fpga上的定制指令和dma的神经网络加速器架构
Schumacher et al. IMORC: an infrastructure for performance monitoring and optimization of reconfigurable computers
CN107844442A (zh) 请求源响应的仲裁方法及装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19952971

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19952971

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 110123)

122 Ep: pct application non-entry in european phase

Ref document number: 19952971

Country of ref document: EP

Kind code of ref document: A1