WO2021096883A1

WO2021096883A1 - Methods and apparatus for adaptive display frame scheduling

Info

Publication number: WO2021096883A1
Application number: PCT/US2020/059880
Authority: WO
Inventors: Srinivas PULLAKAVI; Dileep MARCHYA; Padmanabhan KOMANDURUV
Original assignee: Qualcomm Incorporated
Priority date: 2019-11-15
Filing date: 2020-11-10
Publication date: 2021-05-20

Abstract

The present disclosure relates to methods and apparatus for display or graphics processing, e.g., a CPU. In some aspects, the apparatus can determine whether a previous frame retirement time of a previous frame is after a current frame scheduled wake-up time of a current frame. The apparatus can also delay a current frame wake-up occasion of the current frame to be after the current frame scheduled wake-up time when the previous frame retirement time is after the current frame scheduled wake-up time. Further, the apparatus can execute the current frame wake-up occasion after the current frame scheduled wake-up time when the previous frame retirement time is after the current frame scheduled wake-up time. The apparatus can also execute the current frame wake-up occasion at the current frame scheduled wake-up time when the previous frame retirement time is before or equal to the current frame scheduled wake-up time.

Description

METHODS AND APPARATUS FOR ADAPTIVE DISPLAY FRAME

SCHEDULING

CROSS REFERENCE TO RELATED APPLICATION(S)

[0001] This application claims the benefit of Indian Provisional Application No.

201941046698, entitled “METHODS AND APPARATUS FOR ADAPTIVE DISPLAY FRAME SCHEDULING” and filed on November 15, 2019, which is expressly incorporated by reference herein in its entirety.

TECHNICAL FIELD

[0002] The present disclosure relates generally to processing systems and, more particularly, to one or more techniques for display or graphics processing.

INTRODUCTION

[0003] Computing devices often utilize a graphics processing unit (GPU) to accelerate the rendering of graphical data for display. Such computing devices may include, for example, computer workstations, mobile phones such as so-called smartphones, embedded systems, personal computers, tablet computers, and video game consoles. GPUs execute a graphics processing pipeline that includes one or more processing stages that operate together to execute graphics processing commands and output a frame. A central processing unit (CPU) may control the operation of the GPU by issuing one or more graphics processing commands to the GPU. Modern day CPUs are typically capable of concurrently executing multiple applications, each of which may need to utilize the GPU during execution.

[0004] An electronic device may execute a program to present graphics content on a display.

For example, an electronic device may execute a user interface application, video game application, and the like.

SUMMARY

[0005] The following presents a simplified summary of one or more aspects in order to provide a basic understanding of such aspects. This summary is not an extensive overview of all contemplated aspects, and is intended to neither identify key elements of all aspects nor delineate the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed description that is presented later.

[0006] In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a CPU, a display processing unit (DPU), a compositor, a GPU, a display engine, a display panel, or some other processor for display or graphics processing. In some aspects, the apparatus may receive a current frame from a graphics processing unit (GPU), the current frame associated with a current frame wake-up occasion and a current frame scheduled wake-up time. The apparatus may also determine a previous frame retirement time and a current frame scheduled wake-up time. The apparatus may also determine whether a previous frame retirement time of a previous frame is after a current frame scheduled wake-up time of a current frame, the previous frame and the current frame being part of a plurality of frames. The apparatus may also delay a current frame wake-up occasion of the current frame to be after the current frame scheduled wake- up time when the previous frame retirement time is after the current frame scheduled wake-up time. The apparatus may also execute the current frame wake-up occasion at the current frame scheduled wake-up time when the previous frame retirement time is before or equal to the current frame scheduled wake-up time. The apparatus may also execute the current frame wake-up occasion after the current frame scheduled wake-up time when the previous frame retirement time is after the current frame scheduled wake-up time. The apparatus may also transmit the current frame to a display processing unit (DPU).

[0007] The details of one or more examples of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will be apparent from the description and drawings, and from the claims.

BRIEF DESCRIPTION OF DRAWINGS

[0008] FIG. 1 is a block diagram that illustrates an example content generation system in accordance with one or more techniques of this disclosure.

[0009] FIG. 2 illustrates an example GPU in accordance with one or more techniques of this disclosure.

[0010] FIG. 3 illustrates an example timing diagram in accordance with one or more techniques of this disclosure. [0011] FIG. 4 illustrates an example timing diagram in accordance with one or more techniques of this disclosure.

[0012] FIG. 5A illustrates an example timing diagram in accordance with one or more techniques of this disclosure.

[0013] FIG. 5B illustrates an example timing diagram in accordance with one or more techniques of this disclosure.

[0014] FIG. 6 illustrates an example communication flow diagram of display processing components in accordance with one or more techniques of this disclosure.

[0015] FIG. 7 illustrates an example flowchart of an example method in accordance with one or more techniques of this disclosure.

DETAILED DESCRIPTION

[0016] In some aspects, software synchronization models can assume a constant vertical synchronization (Vsync) for a given display frame-per-second (FPS). Some aspects of adaptive synchronization technology for a frame display may cause the synchronization model to go into drift correction indefinitely. This can result in future frame drops or janks. It may be beneficial to provide a solution to synchronize the software synchronization model to reduce the amount of janks experienced, such as with adaptive synchronization technology. Aspects of the present disclosure can include an adaptive display frame scheduler to be enhanced to factor in adaptive synchronization technology drifts. For example, if the previous frame has not retired at the time of a frame scheduler wake-up, it can wait for the previous frame retirement until the maximum possible drift. Accordingly, aspects of the present disclosure can delay frame wake-ups and align to frame drift caused by adaptive synchronization technology stretch. In some aspects, the next frame can be committed after the previous frame retirement, and the future wake-up can be scheduled at next constant Vsync interval. By doing so, the amount of janks can be reduced.

[0017] Various aspects of systems, apparatuses, computer program products, and methods are described more fully hereinafter with reference to the accompanying drawings. This disclosure may, however, be embodied in many different forms and should not be construed as limited to any specific structure or function presented throughout this disclosure. Rather, these aspects are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art. Based on the teachings herein one skilled in the art should appreciate that the scope of this disclosure is intended to cover any aspect of the systems, apparatuses, computer program products, and methods disclosed herein, whether implemented independently of, or combined with, other aspects of the disclosure. For example, an apparatus may be implemented or a method may be practiced using any number of the aspects set forth herein. In addition, the scope of the disclosure is intended to cover such an apparatus or method which is practiced using other structure, functionality, or structure and functionality in addition to or other than the various aspects of the disclosure set forth herein. Any aspect disclosed herein may be embodied by one or more elements of a claim.

[0018] Although various aspects are described herein, many variations and permutations of these aspects fall within the scope of this disclosure. Although some potential benefits and advantages of aspects of this disclosure are mentioned, the scope of this disclosure is not intended to be limited to particular benefits, uses, or objectives. Rather, aspects of this disclosure are intended to be broadly applicable to different wireless technologies, system configurations, networks, and transmission protocols, some of which are illustrated by way of example in the figures and in the following description. The detailed description and drawings are merely illustrative of this disclosure rather than limiting, the scope of this disclosure being defined by the appended claims and equivalents thereof.

[0019] Several aspects are presented with reference to various apparatus and methods. These apparatus and methods are described in the following detailed description and illustrated in the accompanying drawings by various blocks, components, circuits, processes, algorithms, and the like (collectively referred to as “elements”). These elements may be implemented using electronic hardware, computer software, or any combination thereof. Whether such elements are implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system.

[0020] By way of example, an element, or any portion of an element, or any combination of elements may be implemented as a “processing system” that includes one or more processors (which may also be referred to as processing units). Examples of processors include microprocessors, microcontrollers, graphics processing units (GPUs), general purpose GPUs (GPGPUs), central processing units (CPUs), application processors, digital signal processors (DSPs), reduced instruction set computing (RISC) processors, systems-on-chip (SOC), baseband processors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functionality described throughout this disclosure. One or more processors in the processing system may execute software. Software can be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software components, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. The term application may refer to software. As described herein, one or more techniques may refer to an application, i.e., software, being configured to perform one or more functions. In such examples, the application may be stored on a memory, e.g., on-chip memory of a processor, system memory, or any other memory. Hardware described herein, such as a processor may be configured to execute the application. For example, the application may be described as including code that, when executed by the hardware, causes the hardware to perform one or more techniques described herein. As an example, the hardware may access the code from a memory and execute the code accessed from the memory to perform one or more techniques described herein. In some examples, components are identified in this disclosure. In such examples, the components may be hardware, software, or a combination thereof. The components may be separate components or sub-components of a single component.

[0021] Accordingly, in one or more examples described herein, the functions described may be implemented in hardware, software, or any combination thereof. If implemented in software, the functions may be stored on or encoded as one or more instructions or code on a computer-readable medium. Computer-readable media includes computer storage media. Storage media may be any available media that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can comprise a random access memory (RAM), a read-only memory (ROM), an electrically erasable programmable ROM (EEPROM), optical disk storage, magnetic disk storage, other magnetic storage devices, combinations of the aforementioned types of computer-readable media, or any other medium that can be used to store computer executable code in the form of instructions or data structures that can be accessed by a computer. [0022] In general, this disclosure describes techniques for having a graphics processing pipeline in a single device or multiple devices, improving the rendering of graphical content, and/or reducing the load of a processing unit, i.e., any processing unit configured to perform one or more techniques described herein, such as a GPU. For example, this disclosure describes techniques for graphics processing in any device that utilizes graphics processing. Other example benefits are described throughout this disclosure.

[0023] As used herein, instances of the term “content” may refer to “graphical content,” “image,” and vice versa. This is true regardless of whether the terms are being used as an adjective, noun, or other parts of speech. In some examples, as used herein, the term “graphical content” may refer to a content produced by one or more processes of a graphics processing pipeline. In some examples, as used herein, the term “graphical content” may refer to a content produced by a processing unit configured to perform graphics processing. In some examples, as used herein, the term “graphical content” may refer to a content produced by a graphics processing unit.

[0024] In some examples, as used herein, the term “display content” may refer to content generated by a processing unit configured to perform displaying processing. In some examples, as used herein, the term “display content” may refer to content generated by a display processing unit. Graphical content may be processed to become display content. For example, a graphics processing unit may output graphical content, such as a frame, to a buffer (which may be referred to as a framebuffer). A display processing unit may read the graphical content, such as one or more frames from the buffer, and perform one or more display processing techniques thereon to determine display content and/or generate display content. For example, a display processing unit may be configured to perform composition on one or more rendered layers to generate a frame. As another example, a display processing unit may be configured to compose, blend, or otherwise combine two or more layers together into a single frame. A display processing unit may be configured to perform scaling, e.g., upscaling or downscaling, on a frame. In some examples, a frame may referto a layer. In other examples, a frame may refer to two or more layers that have already been blended together to form the frame, i.e., the frame includes two or more layers, and the frame that includes two or more layers may subsequently be blended.

[0025] FIG. 1 is a block diagram that illustrates an example content generation system 100 configured to implement one or more techniques of this disclosure. The content generation system 100 includes a device 104. The device 104 may include one or more components or circuits for performing various functions described herein. In some examples, one or more components of the device 104 may be components of an SOC. The device 104 may include one or more components configured to perform one or more techniques of this disclosure. In the example shown, the device 104 may include a processing unit 120, and a system memory 124. In some aspects, the device 104 can include a number of optional components, e.g., a communication interface 126, a transceiver 132, a receiver 128, a transmitter 130, a display processor 127, and one or more displays 131. Reference to the display 131 may refer to the one or more displays 131. For example, the display 131 may include a single display or multiple displays. The display 131 may include a first display and a second display. The first display may be a left-eye display and the second display may be a right-eye display. In some examples, the first and second display may receive different frames for presentment thereon. In other examples, the first and second display may receive the same frames for presentment thereon. In further examples, the results of the graphics processing may not be displayed on the device, e.g., the first and second display may not receive any frames for presentment thereon. Instead, the frames or graphics processing results may be transferred to another device. In some aspects, this can be referred to as split-rendering.

[0026] The processing unit 120 may include an internal memory 121. The processing unit 120 may be configured to perform graphics processing, such as in a graphics processing pipeline 107. In some examples, the device 104 may include a display processor, such as the display processor 127, to perform one or more display processing techniques on one or more frames generated by the processing unit 120 before presentment by the one or more displays 131. The display processor 127 may be configured to perform display processing. For example, the display processor 127 may be configured to perform one or more display processing techniques on one or more frames generated by the processing unit 120. The one or more displays 131 may be configured to display or otherwise present frames processed by the display processor 127. In some examples, the one or more displays 131 may include one or more of: a liquid crystal display (LCD), a plasma display, an organic light emitting diode (OLED) display, a projection display device, an augmented reality display device, a virtual reality display device, a head-mounted display, or any other type of display device. [0027] Memory external to the processing unit 120, such as system memory 124, may be accessible to the processing unit 120. For example, the processing unit 120 may be configured to read from and/or write to external memory, such as the system memory 124. The processing unit 120 may be communicatively coupled to the system memory 124 over a bus. In some examples, the processing unit 120 may be communicatively coupled to each other over the bus or a different connection.

[0028] The internal memory 121 or the system memory 124 may include one or more volatile or non-volatile memories or storage devices. In some examples, internal memory 121 or the system memory 124 may include RAM, SRAM, DRAM, erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, a magnetic data media or an optical storage media, or any other type of memory.

[0029] The internal memory 121 or the system memory 124 may be a non-transitory storage medium according to some examples. The term “non-transitory” may indicate that the storage medium is not embodied in a carrier wave or a propagated signal. However, the term “non-transitory” should not be interpreted to mean that internal memory 121 or the system memory 124 is non-movable or that its contents are static. As one example, the system memory 124 may be removed from the device 104 and moved to another device. As another example, the system memory 124 may not be removable from the device 104.

[0030] The processing unit 120 may be a central processing unit (CP El), a graphics processing unit (GPE1), a general purpose GPE1 (GPGPE1), or any other processing unit that may be configured to perform graphics processing. In some examples, the processing unit 120 may be integrated into a motherboard of the device 104. In some examples, the processing unit 120 may be present on a graphics card that is installed in a port in a motherboard of the device 104, or may be otherwise incorporated within a peripheral device configured to interoperate with the device 104. The processing unit 120 may include one or more processors, such as one or more microprocessors, GPEls, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), arithmetic logic units (ALEls), digital signal processors (DSPs), discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuitry, or any combinations thereof. If the techniques are implemented partially in software, the processing unit 120 may store instructions for the software in a suitable, non-transitory computer-readable storage medium, e.g., internal memory 121, and may execute the instructions in hardware using one or more processors to perform the techniques of this disclosure. Any of the foregoing, including hardware, software, a combination of hardware and software, etc., may be considered to be one or more processors.

[0031] In some aspects, the content generation system 100 can include an optional communication interface 126. The communication interface 126 may include a receiver 128 and a transmitter 130. The receiver 128 may be configured to perform any receiving function described herein with respect to the device 104. Additionally, the receiver 128 may be configured to receive information, e.g., eye or head position information, rendering commands, or location information, from another device. The transmitter 130 may be configured to perform any transmitting function described herein with respect to the device 104. For example, the transmitter 130 may be configured to transmit information to another device, which may include a request for content. The receiver 128 and the transmitter 130 may be combined into a transceiver 132. In such examples, the transceiver 132 may be configured to perform any receiving function and/or transmitting function described herein with respect to the device 104.

[0032] Referring again to FIG. 1, in certain aspects, the graphics processing pipeline 107 may include a determination component 198 configured to receive the current frame from a graphics processing unit (GPU), the current frame associated with the current frame wake-up occasion and the current frame scheduled wake-up time. The determination component 198 may also be configured to determine the previous frame retirement time and the current frame scheduled wake-up time. The determination component 198 may also be configured to determine whether a previous frame retirement time of a previous frame is after a current frame scheduled wake-up time of a current frame, the previous frame and the current frame being part of a plurality of frames. The determination component 198 may also be configured to delay a current frame wake- up occasion of the current frame to be after the current frame scheduled wake-up time when the previous frame retirement time is after the current frame scheduled wake- up time. The determination component 198 may also be configured to execute the current frame wake-up occasion at the current frame scheduled wake-up time when the previous frame retirement time is before or equal to the current frame scheduled wake-up time. The determination component 198 may also be configured to execute the current frame wake-up occasion after the current frame scheduled wake-up time when the previous frame retirement time is after the current frame scheduled wake- up time. The determination component 198 may also be configured to transmit the current frame to a display processing unit (DPU).

[0033] As described herein, a device, such as the device 104, may refer to any device, apparatus, or system configured to perform one or more techniques described herein. For example, a device may be a server, a base station, user equipment, a client device, a station, an access point, a computer, e.g., a personal computer, a desktop computer, a laptop computer, a tablet computer, a computer workstation, or a mainframe computer, an end product, an apparatus, a phone, a smart phone, a server, a video game platform or console, a handheld device, e.g., a portable video game device or a personal digital assistant (PDA), a wearable computing device, e.g., a smart watch, an augmented reality device, or a virtual reality device, a non-wearable device, a display or display device, a television, a television set-top box, an intermediate network device, a digital media player, a video streaming device, a content streaming device, an in-car computer, any mobile device, any device configured to generate graphical content, or any device configured to perform one or more techniques described herein. Processes herein may be described as performed by a particular component (e.g., a GPU), but, in further embodiments, can be performed using other components (e.g., a CPU), consistent with disclosed embodiments.

[0034] GPUs can process multiple types of data or data packets in a GPU pipeline. For instance, in some aspects, a GPU can process two types of data or data packets, e.g., context register packets and draw call data. A context register packet can be a set of global state information, e.g., information regarding a global register, shading program, or constant data, which can regulate how graphics context will be processed. For example, context register packets can include information regarding a color format. In some aspects of context register packets, there can be a bit that indicates which workload belongs to a context register. Also, there can be multiple functions or programming running at the same time and/or in parallel. For example, functions or programming can describe a certain operation, e.g., the color mode or color format. Accordingly, a context register can define multiple states of a GPU.

[0035] Context states can be utilized to determine how an individual processing unit functions, e.g., a vertex fetcher (VFD), a vertex shader (VS), a shader processor, or a geometry processor, and/or in what mode the processing unit functions. In order to do so, GPUs can use context registers and programming data. In some aspects, a GPU can generate a workload, e.g., a vertex or pixel workload, in the pipeline.

[0036] FIG. 2 illustrates an example GPU 200 in accordance with one or more techniques of this disclosure. As shown in FIG. 2, GPU 200 includes command processor (CP) 210, draw call data packets 212, VFD 220, VS 222, vertex cache (VPC)224, triangle setup engine (TSE) 226, rasterizer (RAS) 228, Z process engine (ZPE) 230, pixel interpolator (PI) 232, fragment shader (FS) 234, render backend (RB) 236, L2 cache (UCHE) 238, and system memory 240. Although FIG. 2 displays that GPU 200 includes processing units 220-238, GPU 200 can include a number of additional processing units. Additionally, processing units 220-238 are merely an example and any combination or order of processing units can be used by GPUs according to the present disclosure. GPU 200 also includes command buffer 250, context register packets 260, and context states 261.

[0037] As shown in FIG. 2, a GPU can utilize a CP, e.g., CP 210, or hardware accelerator to parse a command buffer into context register packets, e.g., context register packets 260, and/or draw call data packets, e.g., draw call data packets 212. The CP 210 can then send the context register packets 260 or draw call data packets 212 through separate paths to the processing units or blocks in the GPU. Further, the command buffer 250 can alternate different states of context registers and draw calls. For example, a command buffer can be structured as follows: context register of context N, draw call(s) of context N, context register of context N+l, and draw call(s) of context N+l.

[0038] Aspects of mobile devices or smartphones can utilize buffer mechanisms to distribute or coordinate a buffer between an application rendering side of the device, e.g., a GPU or CPU, and a display or composition side of the device, e.g., a display engine. For instance, some mobile devices can utilize a buffer queue mechanism to distribute or coordinate a buffer between an application rendering side and a display or composition side, which can include a buffer compositor, e.g., a surface flinger (SF) or hardware compositor (HWC). In some aspects, the application rendering side can be referred to as a producer, while the display or composition side can be referred to as a consumer. Additionally, a synchronization divider or fence can be used to synchronize content between the application rendering side and the display or composition side. Accordingly, a fence can be referred to as a synchronization divider, and vice versa. [0039] A variety of factors can be performance indicators for display processing between an application rendering side and a display or composition side. For instance, frames per second (FPS) and janks, i.e., delays or pauses in frame rendering or composition, can be performance indicators. In some aspects, a jank can be a perceptible pause in the rendering of a software application’s user interface. In some applications, janks can be the result of a number of factors, such as slow operations or poor interface design. In some instances, a jank can also correspond to a change in the refresh rate of the display at the device. Janks can also impact a user experience.

[0040] In some instances, applications can run at a variety of different FPS modes. In some aspects, displays can run at 30 FPS mode. In other aspects, applications can run at different FPS modes, e.g., 20 or 60 FPS. Aspects of the present disclosure can include a current frame latency time, which can refer to the time difference between when a previous frame completes rendering a current frame completes rendering. The frame latency time can also refer to the time between successive refreshing frames. The frame latency time can also be based on a frame rate. For instance, the frame latency time for each frame can be 33.33 ms (e.g., corresponding to 30 FPS), 16.67 ms (e.g., corresponding to 60 FPS), or 50 ms (e.g., corresponding to 20 FPS).

[0041] Jank reduction technology can be utilized in a number of different scenarios. Additionally, in some instances, different mechanisms or designs may have the ability to detect janks. Moreover, once janks are detected, other mechanisms can be triggered. For example, a frame compositor or surface flinger (SF) mechanism can be directly triggered to bypass a vertical synchronization (Vsync) time in order to avoid janks.

[0042] Aspects of display processing can utilize adaptive synchronization technology, which can synchronize a display panel refresh time with a GPU rendering rate. By doing so, frames can be displayed the moment that they are rendered. In gaming applications, this technology can be a key element for smooth and/or jank-free game play. Adaptive synchronization technology can also improve the touch of game play, e.g., improve the touch to glass latency. There are a number of examples of adaptive synchronization technology that are currently being used in gaming applications.

[0043] Additionally, certain types of displays, e.g., 90 Hz or 120 Hz displays, may be utilized by original equipment manufacturers (OEMs) across a variety of gaming tier segments, e.g., premium or value tier segments. For instance, GPU rendering delays can be more evident on high refresh rate displays, so OEMs may be interested in reducing the amount of GPU rendering delays at high refresh rate displays. Thus, it may be beneficial to mitigate janks and deliver a fluid gaming experience.

[0044] FIG. 3 illustrates a timing diagram 300. As shown in FIG. 3, timing diagram 300 includes an application or CPU 302, a GPU 304, a hardware compositor (HWC) 306, and a number of Vsync time periods. FIG. 3 also shows a variety of content that is to be rendered and displayed, e.g., content B, content C, content D, content E, content F, content G, content H, content I, and content J. Further, FIG. 3 depicts a number of frames, e.g., frame 310, frame 311, frame 312, frame 313, frame 314, frame 315, frame 316, and frame 317. These frames correspond to the content to be rendered and displayed, e.g., content B corresponds to frame 311.

[0045] Additionally, FIG. 3 displays compositor scheduler wake-up times and a corrected compositor scheduler wake-up time. FIG. 3 also shows an adaptive synchronization component (adaptive sync) is utilized to adjust the Vsync time periods. As shown in FIG. 3, content Gand content I are skipped due to janks. FIG. 3 also displays that the GPU fence is not ready at frame 314, so ajank is experienced between frame 314 and frame 315. Accordingly, content Eis displayed twice at the display panel. Further, a jank is experienced between frame 315 and frame 316. Thus, content F is displayed twice at the display panel.

[0046] As depicted in FIG. 3, some software synchronization models can assume a constant Vsync for a given display panel frame-per-second (FPS), as well as cater for occasional drifts. Some aspects of adaptive synchronization technology for a frame display may cause the synchronization model to go into drift correction indefinite ly. This can result in future frame drops or janks, as well as increase the touch latency, e.g., increase to glass latency. As indicated herein, it may be beneficial to provide a solution to synchronize the software synchronization model for certain aspects of adaptive synchronization technology.

[0047] Aspects of the present disclosure may provide a solution to synchronize software synchronization models for certain aspects of adaptive synchronization technology. Also, aspects of the present disclosure include certain adaptive synchronization components, e.g., an adaptive display frame scheduler. Moreover, aspects of the present disclosure can include an adaptive display synchronization model. In some instances, this adaptive display synchronization model can feed on a retirement timeline of past frames, correct wake-ups instantly, and/or schedule frames dynamically. [0048] In some aspects of the present disclosure, adaptive display frame schedulers can rely on apast frame retirement instantaneous status, e.g., ata constant wake-uptime and/or before committing to a new frame. In some instances, if the previous frame has not yet retired, the adaptive display frame scheduler of the present disclosure may skip the current frame wake-up time and delay the current frame to the next wake-up time. By doing so, the adaptive display frame scheduler of the present disclosure can increase the amount of accumulated frames.

[0049] In some instances, the adaptive display frame scheduler of the present disclosure can be enhanced to factor in certain adaptive synchronization technology drifts. For example, if the previous frame has not retired at a frame scheduler wake-up time, the adaptive display frame scheduler can wait for the previous frame retirement time, i.e., wait until a maximum possible drift. Accordingly, frame wake-ups can be delayed and aligned to the drift caused by an adaptive synchronization technology stretch mechanism. In some aspects, a new frame can be committed soon after the previous frame retirement time, and the future wake-up times can be scheduled at a next constant Vsync interval. The synchronization model can also be re-synchronized with new samples until a frame convergence.

[0050] FIG. 4 illustrates a timing diagram 400 in accordance with one or more techniques of this disclosure. As shown in FIG. 4, timing diagram 400 includes an application or CPU 402, a GPU 404, a hardware compositor (HWC) 406, and a number of Vsync time periods. FIG. 4 also shows a variety of content that is to be rendered and displayed, e.g., content B, content C, content D, content E, content F, content G, content H, content I, and content J. Also, FIG. 4 depicts a number of frames, e.g., frame 410, frame 411, frame 412, frame 413, frame 414, frame 415, frame 416, frame 417, frame 418, and frame 419. These frames correspond to the content to be rendered and displayed, e.g., content B corresponds to frame 411.

[0051] Moreover, FIG. 4 displays compositor scheduler wake-up times and a corrected compositor scheduler wake-up time. FIG. 4 also shows an adaptive synchronization component (adaptive sync) is utilized to adjust the Vsync time periods. In FIG. 4, in contrast to FIG. 3, content G and content I are not skipped. FIG. 4 also displays that the GPU fence is not ready at frame 414, however, the GPU fence is ready after the adaptive synchronization technology (Adaptive sync) is activated, so a jank is not experienced between frame 414 and frame 415. As such, content Eis displayed once at the display panel. Further, no janks are experienced between frames 415-417, so content F-H is displayed once at the display panel. As shown in FIG. 4, the adaptive synchronization technology of the present disclosure can cause janks to be reduced, e.g., between frames 414-417.

[0052] FIGs. 5A and 5B illustrate timing diagrams 500 and 550, respectively, in accordance with one or more techniques of this disclosure. As shown in FIG. 5A, diagram 500 includes a GPU 502 and a number of Vsync periods. Also, FIG. 5 A depicts that a number of frames are skipped from being rendered by GPU 502. FIG. 5 A shows the frame rendering at GPU 502 without the use of the adaptive synchronization technology of the present disclosure. As shown in FIG. 5B, diagram 550 includes a GPU 552 and a number of Vsync periods. Further, FIG. 5B depicts that no frames are skipped from being rendered by GPU 552. FIG. 5B shows the frame rendering at GPU 552 with the use of the adaptive synchronization technology of the present disclosure. Accordingly, FIGs. 5A and 5B illustrate the difference in the amount of frames skipped during rendering at a GPU when utilizing the adaptive synchronization technology of the present disclosure.

[0053] Aspects of the present disclosure can include a number of different benefits or advantages. For example, aspects of the present disclosure can utilize an adaptive scheduler that matches a display rate to a content refresh rate. Also, aspects of the present disclosure can deliver a stutter-free user interface (UI) experience. Aspects of the present disclosure can also avoid pipeline stalling by instantly slowing the application. Moreover, aspects of the present disclosure can include a timely drift correction. Aspects of the present disclosure can also demonstrate a significant reduction in the amount of frame drops and/or a drop in stutter-free display by utilizing the aforementioned adaptive frame scheduler. In some instances, aspects of the present disclosure can reduce the amount of frames dropped by a certain percentage, e.g., 29.13% or 27.17%.

[0054] FIG. 6 illustrates an example diagram 600 of display processing components in accordance with one or more techniques of this disclosure. As shown in FIG. 6, diagram 600 includes GPU 602, CPU 604, DPU 606, and display 608. Diagram 600 depicts a number of components that may be utilized in display processing applications of the present disclosure. For instance, GPU 602, CPU 604, DPU 606, and display 608 may be utilized to perform the adaptive display frame scheduling techniques described herein. [0055] At610, CPU604 may receive a current frame, e.g., current frame 612, from agraphics processing unit (GPU), e.g., GPU 602, the current frame associated with a current frame wake-up occasion and a current frame scheduled wake-up time.

[0056] At 620, CPU 604 may determine a previous frame retirement time and a current frame scheduled wake-up time. In some aspects, the previous frame retirement time may be determined by at least one of a central processing unit (CPU) or a display processing unit (DPU). Also, the previous frame retirement time may be received from the DPU.

[0057] At 630, CPU 604 may determine whether a previous frame retirement time of a previous frame is after a current frame scheduled wake-up time of a current frame, the previous frame and the current frame being part of a plurality of frames.

[0058] At 640, CPU 604 may delay a current frame wake-up occasion of the current frame to be after the current frame scheduled wake-up time when the previous frame retirement time is after the current frame scheduled wake-up time.

[0059] At 650, CPU 604 may execute the current frame wake-up occasion at the current frame scheduled wake-up time when the previous frame retirement time is before or equal to the current frame scheduled wake-up time. In some aspects, the current frame wake-up occasion may be executed at a current frame ready time. Also, the current frame wake-up occasion may be executed at a subsequent frame scheduled wake-up time.

[0060] At 660, CPU 604 may execute the current frame wake-up occasion after the current frame scheduled wake-up time when the previous frame retirement time is after the current frame scheduled wake-up time. Further, the current frame wake-up occasion may be executed after a wake-up delay time period. The wake-up delay time period may be less than a difference between the current frame scheduled wake-up time and a subsequent frame scheduled wake-up time.

[0061] In some instances, executing the current frame wake-up occasion after the current frame scheduled wake-up time may reduce a difference between a source rate and a display rate, the source rate being a rate at which content is rendered at a graphics processing unit (GPU) and the display rate being a rate at which content is displayed at a display panel. Moreover, a current frame rendering time of the current frame may be synchronized with a current frame display time of the current frame when the current frame wake-up occasion is executed. A number of accumulated frames may be decreased when the current frame wake-up occasion is executed after the current frame scheduled wake-up time. Also, a previous frame execution time of the previous frame may be equal to the current frame scheduled wake-up time.

[0062] At 670, CPU 604 may transmit the current frame, e.g., current frame 612, to a display processing unit (DPU), e.g., DPU 606. Also, DPU 606 may transmit the current frame 612 to the display 608.

[0063] FIG. 7 illustrates flowchart 700 of an example method in accordance with one or more techniques of this disclosure. The method may be performed by an apparatus such as a CPU, a display processing unit (DPU), a compositor, a GPU, a display engine, a display panel, or some other processor for display or graphics processing.

[0064] At 702, the apparatus may receive a current frame from a graphics processing unit (GPU), the current frame associated with a current frame wake-up occasion and a current frame scheduled wake-up time, as described in connection with the examples in FIGs. 3, 4, 5A, 5B, and 6.

[0065] At 704, the apparatus may determine a previous frame retirement time and a current frame scheduled wake-up time, as described in connection with the examples in FIGs. 3, 4, 5A, 5B, and 6. In some aspects, the previous frame retirement time may be determined by at least one of a central processing unit (CPU) or a display processing unit (DPU), as described in connection with the examples in FIGs. 3, 4, 5A, 5B, and 6. Also, the previous frame retirement time may be received from the DPU, as described in connection with the examples in FIGs. 3, 4, 5A, 5B, and 6.

[0066] At 706, the apparatus may determine whether a previous frame retirement time of a previous frame is after a current frame scheduled wake-up time of a current frame, the previous frame and the current frame being part of a plurality of frames, as described in connection with the examples in FIGs. 3, 4, 5A, 5B, and 6.

[0067] At 708, the apparatus may delay a current frame wake-up occasion of the current frame to be after the current frame scheduled wake-up time when the previous frame retirement time is after the current frame scheduled wake-up time, as described in connection with the examples in FIGs. 3, 4, 5A, 5B, and 6.

[0068] At 710, the apparatus may execute the current frame wake-up occasion at the current frame scheduled wake-up time when the previous frame retirement time is before or equal to the current frame scheduled wake-up time, as described in connection with the examples in FIGs. 3, 4, 5A, 5B, and 6. In some aspects, the current frame wake- up occasion may be executed at a current frame ready time, as described in connection with the examples in FIGs. 3, 4, 5A, 5B, and 6. Also, the current frame wake-up occasion may be executed at a subsequent frame scheduled wake-up time, as described in connection with the examples in FIGs. 3, 4, 5A, 5B, and 6.

[0069] At 712, the apparatus may execute the current frame wake-up occasion after the current frame scheduled wake-up time when the previous frame retirement time is after the current frame scheduled wake-up time, as described in connection with the examples in FIGs. 3, 4, 5A, 5B, and 6. Further, the current frame wake-up occasion may be executed after a wake-up delay time period, as described in connection with the examples in FIGs. 3, 4, 5A, 5B, and 6. The wake-up delay time period may be less than a difference between the current frame scheduled wake-up time and a subsequent frame scheduled wake-up time, as described in connection with the examples in FIGs. 3, 4, 5 A, 5B, and 6.

[0070] In some instances, executing the current frame wake-up occasion after the current frame scheduled wake-up time may reduce a difference between a source rate and a display rate, the source rate being a rate at which content is rendered at a graphics processing unit (GPU) and the display rate being a rate at which content is displayed at a display panel, as described in connection with the examples in FIGs. 3, 4, 5A, 5B, and 6. Moreover, a current frame rendering time of the current frame may be synchronized with a current frame display time of the current frame when the current frame wake-up occasion is executed, as described in connection with the examples in FIGs. 3, 4, 5A, 5B, and 6. A number of accumulated frames may be decreased when the current frame wake-up occasion is executed after the current frame scheduled wake-up time, as described in connection with the examples in FIGs. 3, 4, 5A, 5B, and 6. Also, a previous frame execution time of the previous frame may be equal to the current frame scheduled wake-up time, as described in connection with the examples in FIGs. 3, 4, 5A, 5B, and 6.

[0071] At 714, the apparatus may transmit the current frame to a DPU, as described in connection with the examples in FIGs. 3, 4, 5A, 5B, and 6.

[0072] In one configuration, a method or apparatus for display or graphics processing is provided. The apparatus may be a CPU, a DPU, a compositor, a GPU, a display engine, a display panel, or some other processor that can perform display or graphics processing. In one aspect, the apparatus may be the processing unit 120 within the device 104, or may be some other hardware within device 104 or another device. The apparatus may include means for determining whether a previous frame retirement time of a previous frame is after a current frame scheduled wake-up time of a current frame, the previous frame and the current frame being part of a plurality of frames. The apparatus may also include means for delaying a current frame wake-up occasion of the current frame to be after the current frame scheduled wake-up time when the previous frame retirement time is after the current frame scheduled wake-up time. The apparatus may also include means for executing the current frame wake-up occasion after the current frame scheduled wake-up time when the previous frame retirement time is after the current frame scheduled wake-up time. The apparatus may also include means for executing the current frame wake-up occasion at the current frame scheduled wake-up time when the previous frame retirement time is before or equal to the current frame scheduled wake-up time. The apparatus may also include means for determining the previous frame retirement time and the current frame scheduled wake-up time. The apparatus may also include means for receiving the current frame from a graphics processing unit (GPU), the current frame associated with the current frame wake-up occasion and the current frame scheduled wake-up time. The apparatus may also include means for transmitting the current frame to a display processing unit (DPU).

[0073] The subject matter described herein can be implemented to realize one or more benefits or advantages. For instance, the described display or graphics processing techniques can be used by a CPU, a DPU, a compositor, a GPU, a display engine, a display panel, or some other processor that can perform display or graphics processing to reduce the processing time and/or power used. This can also be accomplished at a low cost compared to other display or graphics processing techniques. Moreover, the display or graphics processing techniques herein can improve or speed up the processing or execution time. Further, the display or graphics processing techniques herein can improve the resource or data utilization and/or resource efficiency. Additionally, aspects of the present disclosure can utilize adaptive display frame scheduling techniques in order to increase accuracy, save power, improve processing time, reduce latency, and/or reduce performance overhead.

[0074] In accordance with this disclosure, the term “or” may be interrupted as “and/or” where context does not dictate otherwise. Additionally, while phrases such as “one or more” or “at least one” or the like may have been used for some features disclosed herein but not others, the features for which such language was not used may be interpreted to have such a meaning implied where context does not dictate otherwise. [0075] In one or more examples, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. For example, although the term “processing unit” has been used throughout this disclosure, such processing units may be implemented in hardware, software, firmware, or any combination thereof. If any function, processing unit, technique described herein, or other module is implemented in software, the function, processing unit, technique described herein, or other module may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media may include computer data storage media or communication media including any medium that facilitates transfer of a computer program from one place to another. In this manner, computer-readable media generally may correspond to (1) tangible computer- readable storage media, which is non-transitory or (2) a communication medium such as a signal or carrier wave. Data storage media may be any available media that can be accessed by one or more computers or one or more processors to retrieve instructions, code and/or data structures for implementation of the techniques described in this disclosure. By way of example, and not limitation, such computer- readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices. Disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media. A computer program product may include a computer-readable medium.

[0076] The code may be executed by one or more processors, such as one or more digital signal processors (DSPs), general purpose microprocessors, application specific integrated circuits (ASICs), arithmetic logic units (ALUs), field programmable logic arrays (FPGAs), or other equivalent integrated or discrete logic circuitry. Accordingly, the term “processor,” as used herein may refer to any of the foregoing structure or any other structure suitable for implementation of the techniques described herein. Also, the techniques could be fully implemented in one or more circuits or logic elements.

[0077] The techniques of this disclosure may be implemented in a wide variety of devices or apparatuses, including a wireless handset, an integrated circuit (IC) or a set of ICs, e.g., a chip set. Various components, modules or units are described in this disclosure to emphasize functional aspects of devices configured to perform the disclosed techniques, but do not necessarily need realization by different hardware units. Rather, as described above, various units may be combined in any hardware unit or provided by a collection of interoperative hardware units, including one or more processors as described above, in conjunction with suitable software and/or firmware.

[0078] Various examples have been described. These and other examples are within the scope of the following claims.

[0079] The following aspects are illustrative only and may be combined with other aspects or teachings described herein, without limitation.

[0080] Aspect 1 is a method of display processing. The method includes determining whether a previous frame retirement time of a previous frame is after a current frame scheduled wake-up time of a current frame, the previous frame and the current frame being part of a plurality of frames; delaying a current frame wake-up occasion of the current frame to be after the current frame scheduled wake-up time when the previous frame retirement time is after the current frame scheduled wake-up time; and executing the current frame wake-up occasion after the current frame scheduled wake- up time when the previous frame retirement time is after the current frame scheduled wake-up time.

[0081] Aspect 2 is the method of aspect 1, further comprising executing the current frame wake-up occasion at the current frame scheduled wake-up time when the previous frame retirement time is before or equal to the current frame scheduled wake-up time.

[0082] Aspect 3 is the method of any of aspects 1 and 2, where the current frame wake-up occasion is executed at a current frame ready time.

[0083] Aspect 4 is the method of any of aspects 1 to 3, where the current frame wake-up occasion is executed at a subsequent frame scheduled wake-up time.

[0084] Aspect 5 is the method of any of aspects 1 to 4, where the current frame wake-up occasion is executed after a wake-up delay time period.

[0085] Aspect 6 is the method of any of aspects 1 to 5, where the wake-up delay time period is less than a difference between the current frame scheduled wake-up time and a subsequent frame scheduled wake-up time.

[0086] Aspect 7 is the method of any of aspects 1 to 6, further comprising determining the previous frame retirement time and the current frame scheduled wake-up time. [0087] Aspect 8 is the method of any of aspects 1 to 7, where a current frame rendering time of the current frame is synchronized with a current frame display time of the current frame when the current frame wake-up occasion is executed.

[0088] Aspect 9 is the method of any of aspects 1 to 8, where a number of accumulated frames is decreased when the current frame wake-up occasion is executed after the current frame scheduled wake-up time.

[0089] Aspect 10 is the method of any of aspects 1 to 9, where a previous frame execution time of the previous frame is equal to the current frame scheduled wake-up time.

[0090] Aspect 11 is the method of any of aspects 1 to 10, where executing the current frame wake-up occasion after the current frame scheduled wake-up time reduces a difference between a source rate and a display rate, the source rate being a rate at which content is rendered at a graphics processing unit (GPU) and the display rate being a rate at which content is displayed at a display panel.

[0091] Aspect 12 is the method of any of aspects 1 to 11, further comprising receiving the current frame from a graphics processing unit (GPU), the current frame associated with the current frame wake-up occasion and the current frame scheduled wake-up time.

[0092] Aspect 13 is the method of any of aspects 1 to 12, further comprising transmitting the current frame to a display processing unit (DPU).

[0093] Aspect 14 is the method of any of aspects 1 to 13, where the previous frame retirement time is determined by at least one of a central processing unit (CPU) or a display processing unit (DPU).

[0094] Aspect 15 is the method of any of aspects 1 to 14, where the previous frame retirement time is received from the DPU.

[0095] Aspect 16 is an apparatus for display processing including means for implementing a method as in any of aspects 1 to 15.

[0096] Aspect 17 is an apparatus for display processing including at least one processor coupled to a memory and configured to implement a method as in any of aspects 1 to 15.

[0097] Aspect 18 is a computer-readable medium storing computer executable code, where the code when executed by a processor causes the processor to implement a method as in any of aspects 1 to 15.

Claims

CLAIMS WHAT IS CLAIMED IS:

1. A method of display processing, comprising: determining whether a previous frame retirement time of a previous frame is after a current frame scheduled wake-up time of a current frame, the previous frame and the current frame being part of a plurality of frames; delaying a current frame wake-up occasion of the current frame to be after the current frame scheduled wake-up time when the previous frame retirement time is after the current frame scheduled wake-up time; and executing the current frame wake-up occasion after the current frame scheduled wake-up time when the previous frame retirement time is after the current frame scheduled wake-up time.

2. The method of claim 1, further comprising: executing the current frame wake-up occasion at the current frame scheduled wake-up time when the previous frame retirement time is before or equal to the current frame scheduled wake-up time.

3. The method of claim 1, wherein the current frame wake-up occasion is executed at a current frame ready time.

4. The method of claim 1, wherein the current frame wake-up occasion is executed at a subsequent frame scheduled wake-up time.

5. The method of claim 1, wherein the current frame wake-up occasion is executed after a wake-up delay time period.

6. The method of claim 5, wherein the wake-up delay time period is less than a difference between the current frame scheduled wake-up time and a subsequent frame scheduled wake-up time.

7. The method of claim 1, further comprising: determining the previous frame retirement time and the current frame scheduled wake-up time.

8. The method of claim 1, wherein a current frame rendering time of the current frame is synchronized with a current frame display time of the current frame when the current frame wake-up occasion is executed.

9. The method of claim 1, wherein a number of accumulated frames is decreased when the current frame wake-up occasion is executed after the current frame scheduled wake- up time.

10. The method of claim 1, wherein a previous frame execution time of the previous frame is equal to the current frame scheduled wake-up time.

11. The method of claim 1, wherein executing the current frame wake-up occasion after the current frame scheduled wake-up time reduces a difference between a source rate and a display rate, the source rate being a rate at which content is rendered at a graphics processing unit (GPU) and the display rate being a rate at which content is displayed at a display panel.

12. The method of claim 1, further comprising: receiving the current frame from a graphics processing unit (GPU), the current frame associated with the current frame wake-up occasion and the current frame scheduled wake-up time.

13. The method of claim 12, further comprising: transmitting the current frame to a display processing unit (DPU).

14. The method of claim 1, wherein the previous frame retirement time is determined by at least one of a central processing unit (CPU) or a display processing unit (DPU).

15. The method of claim 14, wherein the previous frame retirement time is received from the DPU.

16. An apparatus for display processing, comprising: a memory; and at least one processor coupled to the memory and configured to: determine whether a previous frame retirement time of a previous frame is after a current frame scheduled wake-up time of a current frame, the previous frame and the current frame being part of a plurality of frames; delay a current frame wake-up occasion of the current frame to be after the current frame scheduled wake-up time when the previous frame retirement time is after the current frame scheduled wake-up time; and execute the current frame wake-up occasion after the current frame scheduled wake-up time when the previous frame retirement time is after the current frame scheduled wake-up time.

17. The apparatus of claim 16, wherein the at least one processor is further configured to: execute the current frame wake-up occasion at the current frame scheduled wake- up time when the previous frame retirement time is before or equal to the current frame scheduled wake-up time.

18. The apparatus of claim 16, wherein the current frame wake-up occasion is executed at a current frame ready time.

19. The apparatus of claim 16, wherein the current frame wake-up occasion is executed at a subsequent frame scheduled wake-up time.

20. The apparatus of claim 16, wherein the current frame wake-up occasion is executed after a wake-up delay time period.

21. The apparatus of claim 20, wherein the wake-up delay time period is less than a difference between the current frame scheduled wake-up time and a subsequent frame scheduled wake-up time.

22. The apparatus of claim 16, wherein the at least one processor is further configured to: determine the previous frame retirement time and the current frame scheduled wake-up time.

23. The apparatus of claim 16, wherein a current frame rendering time of the current frame is synchronized with a current frame display time of the current frame when the current frame wake-up occasion is executed.

24. The apparatus of claim 16, wherein a number of accumulated frames is decreased when the current frame wake-up occasion is executed after the current frame scheduled wake-up time.

25. The apparatus of claim 16, wherein a previous frame execution time of the previous frame is equal to the current frame scheduled wake-up time.

26. The apparatus of claim 16, wherein executing the current frame wake-up occasion after the current frame scheduled wake-up time reduces a difference between a source rate and a display rate, the source rate being a rate at which content is rendered at a graphics processing unit (GPU) and the display rate being a rate at which content is displayed at a display panel.

27. The apparatus of claim 16, wherein the at least one processor is further configured to: receive the current frame from a graphics processing unit (GPU), the current frame associated with the current frame wake-up occasion and the current frame scheduled wake-up time.

28. The apparatus of claim 27, wherein the at least one processor is further configured to: transmit the current frame to a display processing unit (DPU).

29. An apparatus for display processing, comprising: means for determining whether a previous frame retirement time of a previous frame is after a current frame scheduled wake-up time of a current frame, the previous frame and the current frame being part of a plurality of frames; means for delaying a current frame wake-up occasion of the current frame to be after the current frame scheduled wake-up time when the previous frame retirement time is after the current frame scheduled wake-up time; and means for executing the current frame wake-up occasion after the current frame scheduled wake-up time when the previous frame retirement time is after the current frame scheduled wake-up time.

30. A computer-readable medium storing computer executable code for display processing, the code when executed by a processor causes the processor to: determine whether a previous frame retirement time of a previous frame is after a current frame scheduled wake-up time of a current frame, the previous frame and the current frame being part of a plurality of frames; delay a current frame wake-up occasion of the current frame to be after the current frame scheduled wake-up time when the previous frame retirement time is after the current frame scheduled wake-up time; and execute the current frame wake-up occasion after the current frame scheduled wake-up time when the previous frame retirement time is after the current frame scheduled wake-up time.