WO2021092942A1

WO2021092942A1 - Memory unit and manufacturing method therefor

Info

Publication number: WO2021092942A1
Application number: PCT/CN2019/118934
Authority: WO
Inventors: 刘峻志; 廖昱程; 邱泓瑜; 李宜政
Original assignee: 江苏时代全芯存储科技股份有限公司; 江苏时代芯存半导体有限公司
Priority date: 2019-11-15
Filing date: 2019-11-15
Publication date: 2021-05-20
Also published as: CN114762044A

Abstract

A memory unit, containing an active component (10), electrodes (20a, 20b), a heating unit (30), and a phase change unit (40). The electrodes (20a, 20b) are coupled to the active component (10), and the electrodes (20a, 20b) are located on the same layer as the active component (10). The heating unit (30) is formed above the electrodes (20a, 20b) and is coupled to the electrodes (20a, 20b). The phase change unit (40) is coupled to the heating unit (30), the phase change unit (40) being formed above the active component (10), and the phase change unit (40) and the active component (10) being connected in parallel.

Description

Memory unit and manufacturing method thereof

Technical field

The invention relates to a memory unit and a manufacturing method of the memory unit.

Background technique

Flash memory is a non-volatile memory. When the flash memory lacks an external power supply, the information content in the memory can also be saved. Flash memory is composed of many memory cells. The flash memory in the prior art uses a floating gate transistor as a unit for storing data, and determines the data storage state according to the amount of charge stored in the floating gate.

However, the flash memory in the prior art has disadvantages such as large operating voltage, complex structure and difficult manufacturing, slow programming and reading speed, and low cycle life. Therefore, there is an urgent need in the industry for a novel flash memory that does not have the above-mentioned shortcomings.

In recent years, memory devices that use phase change materials to store data have been developed. The memory devices store information through changes in the resistance of the phase change materials (for example, high resistance and low resistance). A phase change material refers to a material that can switch between different phase states (for example, a crystalline phase and an amorphous phase). The different phase states make the phase change materials have different resistance states to represent different values of the stored data. When operating the memory cell, current can be applied to increase the temperature of the memory component to change the phase state of the phase change material.

Summary of the invention

In view of the above problems, the present invention discloses a memory unit and a manufacturing method of the memory unit. Using this memory unit, a flash memory with high density, simple structure, fast writing and reading speed, and long cycle life can be prepared.

The memory unit disclosed in the present invention includes an active component, two electrodes, two heating units, and a phase change unit. The electrode is coupled to the active device, and the electrode and the active device are located on the same layer. The heating unit is respectively coupled to the two electrodes. The phase change unit is coupled to the two heating units, wherein the phase change unit is formed above the active component, and the phase change unit is connected in parallel with the active component.

The flash memory disclosed in the present invention includes a plurality of the above-mentioned memory cells connected in series.

The method for manufacturing a memory unit disclosed in the present invention includes: forming an active component; forming two electrodes coupled to the active component, and the electrodes and the active component are located on the same layer; forming two heating units located above the two electrodes, and two The heating unit is respectively coupled to the two electrodes; and a phase change unit is formed above the active component, the phase change unit is coupled to the heating unit, and the phase change unit is connected in parallel with the active component.

According to the method for manufacturing a memory cell disclosed in the present invention, the electrode and the active component are formed in the same dielectric layer, thereby simplifying the structure and manufacturing process of the memory cell. The phase change unit is connected in parallel with the active component, so the memory unit disclosed in the present invention can be applied to NAND type memory. The present invention further discloses a NAND type memory including a plurality of memory cells connected in series, which has a lower operating voltage and a higher writing and reading speed. In addition, floating gate transistors are often used in flash memory in the prior art, which are easily damaged due to higher operating voltages; in contrast, since the flash memory of the present invention has a lower operating voltage, it is less likely to damage the components in the memory. , Thereby improving the service life of the memory.

The above description of the present disclosure and the following description of the embodiments are used to demonstrate and explain the spirit and principle of the present invention, and to provide a further explanation of the scope of the patent application of the present invention.

Description of the drawings

FIG. 1 is a schematic circuit diagram of a flash memory according to an embodiment of the present invention.

2 is a schematic cross-sectional view of the memory unit according to the first embodiment of the present invention.

3 to 5 are schematic cross-sectional views of switches forming the memory cell in FIG. 2.

6 and 7 are schematic cross-sectional views of heaters forming the memory unit in FIG. 2.

8 and 9 are schematic cross-sectional views of a phase change unit forming the memory cell in FIG. 2.

Fig. 10 is a schematic cross-sectional view of a memory unit according to a second embodiment of the present invention.

11 and 12 are schematic cross-sectional views of heaters forming the memory unit in FIG. 10.

13 and 14 are schematic cross-sectional views of a phase change cell forming the memory cell in FIG. 10.

Among them, the reference signs:

Memory unit 1, 1-1, 1-2, 1"

Switching

transistor

11, 12

Character line WL0～WL7

Bit line BL1～BL3

Select control line CS

Switch control line SSG, DSG

Substrate 100

Active components 10

Source/Drain 110, 120

Grid 130

Channel 140

Gate conductive layer 131

Gate metal layer 132

Gate spacer 133

First electrode 20a

The second electrode 20b

Heating material HM

Heating unit 30

Phase change material PCM

Phase change unit 40

Thermal insulation material IM

Thermal insulation unit 50

Dielectric layer DL, ILD

Through hole TH

The first slot G1

The second slot G2

Horizontal width W1, W2

Detailed ways

The detailed features and advantages of the present invention will be described in detail in the following embodiments, and the content is sufficient to enable any person skilled in the art to understand the technical content of the present invention and implement it accordingly, and in accordance with the content disclosed in this specification, claims and drawings Anyone skilled in the art can easily understand the related objectives and advantages of the present invention. The following examples further illustrate the viewpoints of the present invention in detail, but do not limit the scope of the present invention by any viewpoint.

Spatial relative terms, such as "below", "above", "below", "above" and similar terms, are used to simplify the description of one component or structure and another component (or multiple components) shown in the drawings. Component) or structure (or multiple structures). In addition to the directions depicted in the drawings, spatially relative terms are intended to encompass different directions of the device in use or operation. The device can be in different directions (rotated by 90 degrees or in other directions), and the space-related descriptors used here can also be interpreted accordingly.

FIG. 1 is a schematic circuit diagram of a NAND-type memory according to an embodiment of the present invention. The NAND type memory includes multiple memory cells 1, two switching

transistors

11, 12, multiple word lines WL0 ~ WL7, multiple bit lines BL1 ~ BL3, multiple selection control lines CS, Two switch control lines SSG and DSG. These memory cells 1 are connected in series, and each memory cell includes active components (such as transistors) and phase change components connected in parallel. A plurality of memory cells 1 connected in series are coupled to the drain/source of the

control transistors

11 and 12. The above-mentioned control transistors and active components include N-type or P-type MOS transistors, but not limited to this, as long as the components that can function as switches can be the above-mentioned control transistors or active components.

The drain/source of the switching transistor 11 is coupled to one of the selection control lines CS, and the drain/source of the switching transistor 12 is coupled to one of the bit lines (for example, BL1). The gate of the switching transistor 11 is coupled to the switching control line SSG, and the gate of the switching transistor 12 is coupled to the switching control line DSG. The voltage signals of the switch control line SSG and the switch control line DSG can be used to control the on or off of the

switch transistors

11 and 12, so as to control the flow of current into and out of the plurality of memory cells 1 connected in series. The active device of each memory cell 1 includes a gate, which is coupled to one of the word lines WL0 to WL7. Therefore, the voltage signals of the word lines WL0 to WL7 can be used to control whether the current flows through the phase change component to write and read the memory cell 1.

Please also refer to FIG. 2, which is a schematic cross-sectional view of the memory unit according to the first embodiment of the present invention. In this embodiment, the memory unit 1 includes an active component 10, a first electrode 20 a, a second electrode 20 b, two heating units 30 and a phase change unit 40.

The active device 10 is formed on the substrate 100, and the active device 10 is, for example, a transistor, which includes a source/drain 110, a source/drain 120 and a gate 130. The source/

drain

110 and 120 are located in the doped region of the substrate, and the gate 130 is disposed on the substrate 100 and is located between the source/drain 110 and the source/drain 120. In some embodiments of the present invention, the substrate 100 also has a shallow trench isolation (STI) structure to electrically separate adjacent active components 10. The material of the substrate 100 includes, for example, silicon or other semiconductor elements, such as germanium or III-V elements, but not limited to this. The material of the shallow trench isolation structure includes silicon oxide, silicon nitride, silicon oxynitride, or other suitable materials. Electrical insulation material.

In this embodiment, the gate 130 includes a gate conductive layer 131, a gate metal layer 132 and a gate spacer 133. As shown in FIG. 2, the gate metal layer 132 is disposed on the gate conductive layer 131, and the gate spacers 133 are disposed on two opposite sidewalls of the gate conductive layer 131 so as to be aligned with the opposite sides of the gate metal layer 132. On the wall. The gate conductive layer 131 includes, for example, doped polysilicon. The gate metal layer 132 includes, for example, titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), nickel silicide (NiSi), or cobalt silicide (CoSi). By providing the gate metal layer 132 in contact with the gate conductive layer 131, the resistive load effect of the gate can be reduced, thereby improving the RC (resistance-capacitance) delay problem. The gate spacer 133 may have a single-layer structure or a multi-layer structure. In some embodiments, the gate spacer 133 includes oxide, nitride, oxynitride, or a combination thereof. For example, in this embodiment, the gate spacer 133 is a single layer of silicon oxide and a single layer of silicon nitride.

The first electrode 20 a is coupled to the source/drain 110 of the active device 10, and the second electrode 20 b is coupled to the source/drain 120 of the active device 10. The material of the first electrode 20a and the second electrode 20b includes tungsten (W), for example. The first electrode 20 a and the second electrode 20 b are located on the same layer as the gate 130 of the active device 10. Specifically, as shown in FIG. 2, the gate 130, the first electrode 20a, and the second electrode 20b are all located in the same dielectric layer DL.

Two heating units 30 are respectively formed on the first electrode 20a and the second electrode 20b, and the two heating units 30 are respectively coupled to the first electrode 20a and the second electrode 20b. The material of the heating unit 30 includes, for example, titanium, tungsten (W), platinum (Pt), titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), or tantalum aluminum nitride (TaAlN).

The phase change unit 40 is formed on the top surface of the dielectric layer DL, and the phase change unit 40 is located above the gate 130 of the active device 10. The phase change unit 40 is coupled to the two heating units 30. In detail, the phase change unit 40 is interposed between the two heating units 30, and the phase change unit 40 is coupled to the respective sides of the two heating units 30. The material of the phase change unit 40 includes, for example, germanium antimony tellurium (GST), nitrogen-doped germanium antimony tellurium (nitrogen-doped GST), antimony telluride (Sb2Te), antimony germanium (GeSb), or indium-doped antimony telluride (GST). In-doped Sb2Te).

Please refer to Figure 1 and Figure 2 together. The voltage signals of the word lines WL0˜WL7 can be controlled to control whether current flows through the phase change unit 40 for writing and reading. Specifically, when a proper bias is applied to the gate conductive layer 131 through the word line, a channel 140 will be formed between the source/drain 110 and the source/drain 120, so the resistance value of the active device 10 changes relatively. The resistance value of the cell 40 is low, so current can flow from the source/drain 110 to the source/drain 120 through the channel 140. Conversely, when a proper bias is not applied to the gate conductive layer 131, there is no channel between the source/drain 110 and the source/drain 120, so the resistance value of the active device 10 is much higher than that of the phase change unit 40 Resistance value. At this time, current will flow from the source/drain 110 to the source/drain 120 through the first electrode 20a, the heating unit 30, the phase change unit 40, the other heating unit 30, and the second electrode 20b. Accordingly, during writing, the phase change unit 40 is heated by ohmic heating, and the current through the phase change layer and the cooling speed are used to make the phase change of the phase change unit 40 between the crystalline state and the non-crystalline state. Convert between crystalline states, and then can store different values of data.

Hereinafter, a method of manufacturing the memory cell 1 of FIG. 2 will be described. First, the formation of the electrodes of the memory cell will be explained. Please also refer to FIGS. 3 to 5, which are schematic cross-sectional views of the electrodes forming the memory cell in FIG. 2. Hereinafter, a plurality of memory cells 1 that are connected in series at the same time are drawn.

First, the active device 10 is formed on the substrate 100 by the existing semiconductor process. As shown in FIG. 3, a dielectric layer DL is formed on the substrate 100 to cover the active device 10. The material of the dielectric layer DL includes, for example, an electrically insulating material such as silicon oxide, silicon carbide, or silicon nitride. Next, as shown in FIG. 4, part of the dielectric layer DL is removed to form a plurality of through holes TH. Specifically, the dielectric layer DL may be removed by an etching process to form the through hole TH. The through hole TH exposes the source/drain 110 or the source/drain 120 of the active device 10. The two active components 10 at the far left and right in FIG. 3 and FIG. 4 can be used as the switching

transistors

11 and 12 of the NAND-type memory in FIG. 1, respectively.

As shown in FIG. 5, a conductive material is filled in the through hole TH to form a first electrode 20a and a second electrode 20b. Specifically, a titanium film or a titanium nitride film may be deposited on the sidewall of the through hole TH as an adhesion layer first, and then tungsten may be deposited to fill the through hole TH. The conductive material filled in the through hole TH exposing the source/drain 110 serves as the first electrode 20a of one of the memory cells, and the conductive material filled in the through hole TH exposing the source/drain 120 serves as the first electrode 20a therein. The second electrode 20b of a memory cell. After the conductive material is filled, the excess conductive material can be removed by a chemical mechanical polishing process to flatten the top surfaces of the dielectric layer DL, the first electrode 20a and the second electrode 20b.

In the case where a plurality of memory cells are connected in series, the first electrode 20a of one memory cell may share the second electrode 20b of another adjacent memory cell. For example, the second electrode 20b of the leftmost memory cell 1-1 in FIG. 5 simultaneously serves as the first electrode 20a of the adjacent memory cell 1-2. In addition, the source/drain 120 of one of the memory cells can be used as the source/drain 110 of another adjacent memory cell 1, for example, the source/drain of the leftmost memory cell 1-1 in FIG. 5 At the same time, 120 serves as the source/drain 110 of the adjacent memory cell 1-2.

6 and 7 are schematic cross-sectional views of the heating unit 30 forming the memory unit in FIG. 2. The heating material HM is formed above the first electrode 20a and the second electrode 20b. Specifically, as shown in FIG. 6, a heating material HM (such as titanium, titanium nitride, tantalum nitride, aluminum titanium nitride, or aluminum nitride) can be deposited on the top surface of the dielectric layer DL and the first electrode 20a And the top surface of the second electrode 20b. Subsequently, as shown in FIG. 7, the heating material HM can be patterned using lithography processing and etching processing. After patterning, part of the heating material HM on the top surface of the dielectric layer DL is removed, thereby forming a plurality of heating units 30.

8 and 9 are schematic cross-sectional views of the phase change unit 40 forming the memory cell in FIG. 2. The phase change unit 40 is formed above the gate 130 of the active device 10. Specifically, as shown in FIG. 8, a phase change material PCM is formed on the top surface of the dielectric layer DL. Subsequently, as shown in FIG. 8, the phase change material PCM can be patterned into a plurality of phase change units 40 by using lithography processing and etching processing. Alternatively, a chemical mechanical polishing method can also be used to remove part of the phase change material PCM to form the phase change unit 40. As shown in FIG. 9, the phase change unit 40 is formed between two adjacent heating units 30. The phase change unit 40 contacts the side surface of the heating unit 30, that is, the top surface of the phase change unit 40 and the top surface of the heating unit 30 are located at the same level. In FIG. 9, the two ends of the active component 10 and the phase change unit 40 are respectively connected to two nodes, and the first electrode 20a and the second electrode 20b serve as the aforementioned two nodes, thereby implementing the phase change unit 40 and the active Parallel connection of components 10.

After the phase change unit 40 is formed, another dielectric layer can be further formed on the dielectric layer ILD to cover the heating unit 30 and the phase change unit 40. Subsequently, a through hole may be formed in the dielectric layer through an etching process, and a metal material may be filled in the through hole to form a conductive pillar. Aluminum or copper can be further deposited on the dielectric layer to serve as bit lines.

Fig. 10 is a schematic cross-sectional view of a memory unit according to a second embodiment of the present invention. Since the second embodiment is similar to the first embodiment, the differences will be described below. In this embodiment, the memory unit 1" further includes two thermal insulation units 50, wherein the heating unit 30 may be a titanium nitride layer, and the thermal insulation unit 50 may be a tantalum nitride layer. The two thermal insulation units 50 are formed separately Above the two heating units 30, and the phase change unit 40 contacts the respective sides of the two thermal insulation units 50. The maximum line width of the thermal insulation unit 50 is smaller than the minimum line width of the heating unit 30, and the phase change unit 40 contacts the heating unit 30 The top and side surfaces. The thermal insulation unit 50 helps to prevent thermal energy from escaping into the dielectric layer DL from the side of the phase change unit 40 when the heating unit 30 heats the phase change unit 40.

The manufacturing method of the memory cell 1" in FIG. 10 is described below. FIGS. 11 and 12 are schematic cross-sectional views of the thermal insulation unit 50 forming the memory cell in FIG. 10. In the following, a plurality of memory cells 1 connected in series are simultaneously formed. ". 2 to 7 steps to form the active component 10, the first electrode 20a, the second electrode 20b, and the heating unit 30 of the memory cell 1". Then, as shown in FIG. 11, a thermal insulating material IM is formed on the dielectric layer DL The top surface and the top surface of the heating unit 30. Subsequently, as shown in Figure 12, the thermal insulation material IM can be patterned by lithography and etching. After patterning, the dielectric layer DL is located on the top surface of the dielectric layer DL. The residual heat insulation material IM is removed, thereby forming a plurality of thermal insulation units 50.

In addition, as shown in FIG. 12, in each memory unit 1", the heating material HM is patterned to form the heating unit 30, and further to form a first slot G1 between the two heating units 30. First The through groove G1 is located above the gate 130 of the active device 10, and the first through groove G1 exposes the dielectric layer DL. In addition, after the thermal insulation material IM is patterned, in addition to forming the thermal insulation unit 50, a second A through groove G2 is above the first through groove G1. The second through groove G2 is connected to the first through groove G1, and the horizontal width W2 of the second through groove G2 is greater than the horizontal width W1 of the first through groove G1. In this way, The first piercing groove G1 and the second piercing groove G2 jointly form a accommodating space that is wide in shape and narrow in the bottom.

13 and 14 are schematic cross-sectional views of the phase change unit 40 forming the memory cell in FIG. 10. A phase change material PCM is formed on the top surface of the dielectric layer DL. Subsequently, as shown in FIG. 13, the phase change material PCM can be patterned into a plurality of phase change units 40 by using lithography processing and etching processing. As shown in FIG. 14, for example, a part of the phase change material PCM is removed by a chemical mechanical polishing method to form a phase change unit 40 between two adjacent heating units 30, and the top surface of the phase change unit 40 is The top surface of the insulation unit 50 is located at the same level. Since the phase change unit 40 is filled in the first through slot G1 and the second through slot G2, the phase change unit 40 also has a shape with a wide top and a narrow bottom.

When the phase change material PCM is planarized by the chemical mechanical polishing process, the thermal insulation unit 50 can be used as a stop layer for the chemical mechanical polishing process, which helps prevent the heating unit 30 from being over-polished by the polishing pad and the thickness becomes excessive. thin.

In summary, according to the method for manufacturing a memory cell disclosed in the present invention, the electrodes and the active components are formed in the same dielectric layer, thus simplifying the structure and manufacturing process of the memory cell. The phase change unit is connected in parallel with the active component, so the memory unit disclosed in the present invention can be applied to NAND type memory. The present invention further discloses a NAND type memory including a plurality of memory cells connected in series, which has a lower operating voltage and a higher writing and reading speed. In addition, floating gate transistors are often used in flash memory in the prior art, which are easily damaged due to higher operating voltages; in contrast, since the flash memory of the present invention has a lower operating voltage, it is less likely to damage the components in the memory. , Thereby improving the service life of the memory.

Claims

A memory unit that contains:

Active component

Two electrodes, coupled to the active component, and the two electrodes and the active component are located on the same layer;

Two heating units, and the two heating units are respectively coupled to the two electrodes; and

The phase change unit is coupled to the two heating units, the phase change unit is formed above the active component, and the phase change unit is connected in parallel with the active component.
2. The memory cell of claim 1, wherein the two electrodes are respectively coupled to the source and drain of the active device, the two electrodes and the gate of the active device are located on the same layer, and the phase change unit is formed Above the gate of the active device.
3. The memory unit of claim 1, wherein the phase change unit is coupled to the respective sides of the two heating units.
3. The memory unit of claim 3, further comprising two thermal insulation units, the two thermal insulation units are respectively formed above the two heating units, and the phase change unit contacts respective sides of the two thermal insulation units.
4. The memory unit of claim 4, wherein the phase change unit has a shape with a wide top and a narrow bottom.
A NAND-type memory comprising a plurality of memory cells according to claim 1 connected in series.
A method for manufacturing a memory unit, including:

Form active components;

Forming two electrodes coupled to the active component, and the two electrodes and the active component are located on the same layer;

Forming two heating units respectively located above the two electrodes, and the two heating units are respectively coupled to the two electrodes; and

A phase change unit is formed above the active component, the phase change unit is coupled to the two heating units, and the phase change unit is connected in parallel with the active component.
8. The method of manufacturing a memory cell according to claim 7, wherein forming the two electrodes comprises:

Forming a dielectric layer to cover the active component;

Removing part of the dielectric layer to form two through holes to respectively expose the source and drain of the active device; and

The two electrodes are respectively formed in the two through holes.
8. The method of manufacturing a memory unit according to claim 8, wherein the two heating units and the phase change unit are formed above the dielectric layer, and the phase change unit contacts the respective sides of the two heating units.
8. The method of manufacturing a memory unit according to claim 8, further comprising:

Before forming the phase change unit, two thermal insulation units are formed respectively above the two heating units; and

The phase change unit is formed above the dielectric layer, and the phase change unit contacts the respective top surfaces and side surfaces of the two heating units and the respective side surfaces of the two thermal insulation units.
10. The method of manufacturing a memory unit according to claim 10, wherein a first through slot is formed between the two heating units, the first through slot is located above the active component and exposes the dielectric layer, and the two thermally insulated A second through slot communicating with the first through slot is formed between the units, the second through slot is located above the first through slot, the horizontal width of the second through slot is greater than the horizontal width of the first through slot, and The phase change unit is formed in the first through groove and the second through groove.
7. The method of manufacturing a memory cell according to claim 7, wherein the two electrodes are respectively coupled to the source and drain of the active device, the two electrodes and the gate of the active device are located on the same layer, and the phase The change unit is formed above the gate of the active device.