WO2021078367A1

WO2021078367A1 - High speed digital to analogue converter

Info

Publication number: WO2021078367A1
Application number: PCT/EP2019/078720
Authority: WO
Inventors: Denise LEE
Original assignee: Huawei Technologies Co., Ltd.
Priority date: 2019-10-22
Filing date: 2019-10-22
Publication date: 2021-04-29
Also published as: EP4046278A1

Abstract

A digital to analogue converter (DAC) comprising: a plurality of segments each comprising a first output stage and a second output stage, each output stage of a segment being configured to receive a digital input signal and the output stages being configured to cooperatively form a differential output in dependence on the input signal; wherein: each output stage of a segment comprises a first transistor device configured to operate as a regulated current source for driving a part of the differential output and to be switched in a source degenerate manner in dependence on the state of a second transistor of the respective output stage; and each segment is configured to form a unary segment and the plurality of segments cooperatively implement the DAC. Advantages include high bandwidth, good resolution and linearity and complementary current steering.

Description

HIGH SPEED DIGITAL TO ANALOGUE CONVERTER

FIELD OF THE INVENTION

The present invention relates to digital analogue converters.

BACKGROUND

A digital to analogue converter (DAC) receives a digital signal and outputs an analogue signal in dependence on the digital signal. Typically the voltage of the analogue signal is dependent on a numeric value represented by the digital signal. Known designs can be used in applications requiring a differential voltage output, matched impedance and high resolution (for example, 12 bit), with excellent linearity (INL).

One prior art DAC is described in Matteo Bassi, A High-Swing 45 Gb/s Hybrid Voltage and Current-Mode PAM-4 Transmitter in 28 nm CMOS FDSOI, IEEE Journal of Solid-State Circuits, Vol. 51 , No. 11 , November 2016. Another prior art high speed DAC design is described in ISSCC 2015, Tutorial: High-Speed Current-Steering DACs, Jan Mulder, Broadcom Netherlands BV.

It is desirable to develop a digital to analogue converter that can achieve high bandwidth, good resolution and linearity and complementary current steering.

SUMMARY OF THE INVENTION

According to a first aspect there is provided a digital to analogue converter comprising: a plurality of segments each comprising a first output stage and a second output stage, each output stage of a segment being configured to receive a digital input signal and the output stages being configured to cooperatively form a differential output in dependence on the input signal; wherein: each output stage of a segment comprises a first transistor device configured to operate as a regulated current source for driving a part of the differential output and to be switched in a source degenerate manner in dependence on the state of a second transistor of the respective output stage; and each segment is configured to form a unary segment and the plurality of segments cooperatively implement the digital to analogue converter.

The first transistor may have a first gate oxide layer and the second transistor may have a second gate oxide layer and the first gate oxide layer may be thicker than the second gate oxide layer. This may permit the relative behaviour of the transistors to be controlled advantageously.

The second transistor may be configured so that its state is dependent on a state of the input signal. That may permit the second transistor to control other circuit components in dependence on the input signal.

The digital to analogue converter may comprise a capacitor configured for charge pumping the gate capacitance of the second transistor. This may be a convenient way of controlling the state of the second transistor.

The capacitor may be reset under the control of a switching arrangement cross-coupled between the output stages of a segment operating in the opposite phase. This may be a convenient way of controlling the state of the second transistor.

The digital to analogue converter may be implemented as an integrated circuit and the capacitor may at least partially overlie one or both of the first transistor and second transistors. This may be a convenient way to package the circuit.

In each output stage: the source and drain of the second transistor may be coupled between a first voltage reference and a first node; the source and drain of a third transistor may be coupled between the first node and a second node; the source and drain of the first transistor may be coupled between the second node and a third node; the source and drain of a fourth transistor may be coupled between the third node and a second voltage reference; and a part of the differential output may be coupled to the second node. This may be a convenient architecture to generate a suitable analogue output signal.

The first transistor and the third transistor may be configured to receive complementary bias voltages at their gates. This may provide a convenient mechanism for controlling the behaviour of those transistors.

The second transistor and the fourth transistor may be configured to be switched in complementary fashion in dependence on the input. This may provide a convenient mechanism for controlling the behaviour of those transistors. One of the second and fourth transistors may be a P-type transistor and the other of the second and fourth transistors may be an N-type transistor. Transistors arranged in this way may provide good performance in a DAC of the type described herein.

The digital to analogue converter may be arranged to be subject to closed loop compensating control whereby gain of a transfer function of each segment over temperature is maintained. This may provide temperature invariant performance.

According to a second aspect there is provided a data processing circuit comprising a digital to analogue converter as claimed in any preceding claim and a digital signal processor configured to form a digital signal as the input to the digital to analogue converter, wherein the digital to analogue converter and the digital signal processor are configured to operate in the same voltage domain.

BRIEF DESCRIPTION OF THE FIGURES

The present invention will now be described by way of example with reference to the accompanying drawings. In the drawings:

Figure 1 shows a unary segment of a DAC circuit.

Figure 2 shows a golden unary segment identical to the output unary segment utilized to generate the static voltage biasing which sets the output switched current.

Figure 3(a) illustrates a simplified schematic view of the half circuit of a prior art current mode DAC output, where an ON’ state switch is represented as a resistor, Rds. Figure 3(b) illustrates, in a similar state of operation, the DAC described herein.

Figures 4(a) and 4(b) illustrate the headroom limitation of a prior art design compared to the DAC described herein, respectively. Figure 4(b) highlights the reduced operating headroom, as indicated by the required overdrive or excess voltage required to keep a MOSFET device in the saturation region of operation, compared to the arrangement of Figure 4(a).

DETAILED DESCRIPTION OF THE INVENTION

Figure 1 shows an example of a DAC comprising a plurality of segments. The DAC is a digitally switched DAC with a charge coupled level shifter. This architecture has unary (i.e. base-1 ) segmentation with output transfer function gain adjustment, which enables reconfigurable DAC resolution with ganging via digital control. Such unary segments may operate together to form a multi-bit DAC. The DAC may be implemented in a data processing circuit comprising a digital signal processor configured to form a digital signal as the input to the digital to analogue converter. In this implementation, the digital to analogue converter and the digital signal processor can be configured to operate in the same voltage domain.

Each unary segment comprises a first output stage and a second output stage, shown generally at 101 and 102 respectively in Figure 1 . Each output stage is configured to receive a digital input signal. In Figure 1 , the output stages of the circuit receive the input signals SEL and SELB. The first and second output stages 101 and 102 cooperatively form a differential output (VOUTP/VOUTN) in dependence on the input signal.

Each output stage of a segment comprises the following components. The components are shown and described here with respect to the output stage shown generally at 101 in Figure 1 . Each output stage comprises a first transistor 103 which operates as a regulated current source for driving a part of the differential output. The first transistor 103 is switched in a source degenerate manner in dependence on the state of a second transistor 104 of the respective output stage 101. The second transistor 104 is configured so that its state is dependent on a state of the input signal.

In a preferred implementation, the transistors 103 and 104 are MOSFET switches, which have gate oxide (GO) layers. Preferably, the gate oxide layer of the first transistor 103 is thicker than the gate oxide layer of the second transistor 104. For example, the second transistor 304 may comprise a G01 (gate oxide layer 1) switch, which is a thin oxide MOSFET device, and the first transistor 103 may comprise a G02 (gate oxide layer 2) switch, which is a thick oxide MOSFET device, which has a higher electric overstress voltage tolerance than a G01 switch.

The DAC has a capacitor Cs configured for charge pumping the gate capacitance of the second transistor 104. The capacitor may be reset under the control of a switching arrangement cross-coupled between the output stages of a segment operating in the opposite phase.

In a preferred implementation, the DAC is implemented in an integrated circuit. In this implementation, the capacitor may at least partially overlie one or both of the transistors in each output segment. In each output stage, the source and drain of the second transistor 104 are coupled between a first voltage reference VDD (the supply voltage) and a first node 105. The source and drain of a third transistor 106 are coupled between the first node 105 and a second node 107. The source and drain of the first transistor 103 are coupled between the second node 107 and a third node 108. The source and drain of a fourth transistor 109 are coupled between the third node 108 and a second voltage reference GND (ground). A part of the differential output (VOUTP) is coupled to the second node 107.

One of the second and fourth transistors is a P-type transistor and the other of the second and fourth transistors is an N-type transistor.

The transistors are configured to be switched in complementary fashion in dependence on the input. In this implementation, the first transistor 103 and the third transistor 106 are configured to receive complementary bias voltages, VBIASN and VBIASP respectively, at their gates.

In this arrangement, the activation of the current source is controlled by the switching of an equivalent degenerate (impedance) with two threshold of operation (i.e. a state of high impedance (OFF) and low impedance (ON)). In the preferred implementation, this equivalent source degenerate comprises a G01 switch. For each output stage, which comprises a complimentary pair of switches 104 and 109 in each unary segmentation, the high side and low side equivalent degenerates switch in compliment: that is, G01 104 turns OFF whilst G01 109 turns ON, and vice versa.

As described above, the DAC topology is a current steering DAC with differential output, utilizing a push-pull architecture with regulated switched current source. In each unary segmentation (i.e. division of equal weights, in constitution, which make up a monotonic transfer function of the DAC output) of the DAC weighted current, the DAC comprises a complimentary pair of output stages which make up a differential output.

As described above with respect to Figure 1 , each driving output stage comprises an arrangement in a manner typical to a logic inverter with push-pull output drive. However, both high side and low side G02 I/O devices (103 and 106) are in essence source degenerated. The switching of an equivalent degenerate (impedance) with two threshold of operation (i.e. a state of high impedance (OFF) and low impedance (ON)) controls the activation of the current source. This manner of operation facilitates the exclusion of level shifting to a different voltage domain in manner typical of a CML DAC architecture. The N G01 switches can be directly driven by standard cell (SC) logic from the digital voltage domain. Likewise, only a single bit line controls the switching, in that the G01 switches 104 and 109 operate in phase. This means that, for example, the N G01 switches ON with an applied gate voltage from GND (Logic O’) to DVDD (Logic ), and the P G01 switches OFF from VDD-DVDD (Logic ) to VDD (Logic O’), with the N G01 source tied to GND, and the P G01 tied to VDD.

A single digital bit line drives each unary segment of the DAC. This also simplifies the synchronized clocking of data (i.e. the latching of data), moving to the digital back end. This may limit DAC cell related timing delay errors (i.e. dynamic errors attributable to driving AFE output stages), in effect relying more on the high speed offered by the core logic G01 domain with its routing efficiency. The other dynamic temporal error is code-dependent error, that is a stepping of DAC output voltage in relation to code transition. This aspect is addressed by design with the said push-pull output stage. This can improve both the positive and negative slope of output transition, which can provide an improvement over CML DAC designs.

The in-phase switching facilitates the use of charge coupling capacitors (Cs) to charge pump the gate capacitance (Cg) of the P G01 device. The coupling capacitor preferably has a capacitance an order of magnitude greater than the gate capacitance of the P G01 device for the generation of a logic level. For example, GND (Logic O’) to DVDD (Logic ‘T), charge coupled to, VDD-DVDD^*Cs/(Cg+Cs) (Logic ‘T) to VDD (Logic O’). The ratio of Cs/(Cg+Cs) may be corrected by a closed loop voltage biasing generator for the P G02 device.

The use of capacitors and the sizing area penalty that might typically result is mitigated by the low gate capacitance Cg of G01 devices (its width (W) and length (L) are set with consideration to the value W/L, which sets the device Rds, and with respect to Lmin and to W^*L, which determines its gate capacitance). The capacitors may be Metal-On-Metal capacitors (CMOM) or Metal-lnsulator-Metal capacitors (CMIM), both of which may be placed on top of active devices (N/P G01 or G02), minimizing layout impact.

The use of capacitors requires the resetting of its voltage value. In an ideal mode of operation, the voltage across the coupling capacitor should be kept nominally at VDD-DVDD. With the complimentary pair of output stages, a pair of cross-coupled reset switches driven by opposite phase are implemented. This ensures the discharged Cs is replenished via charge division with Cg. In a preferred implementation, the I/O devices (such as 103 in output stage 101 ) comprise G02 devices. In this implementation, the switching of state is performed via the G01 device and the gate voltage of the G02 device is held static as the voltage biasing sets the magnitude of the switched current. In contrast to previous CML DACs (without cascoding devices), where the gate drain capacitance sees a larger delta voltage change (i.e. V_gate decreases while V_drain increases), in this implementation, V_gate is unchanged (i.e. the biasing voltage is static) while Vdrain increases.

This may result in two advantages. Firstly, the lower voltage delta means that a device of lower voltage tolerance can be used to realize the output stage (i.e. the gate drain voltage (Vg_S) difference is lower). Secondly, for a device with lower voltage tolerance this also reduces the capacitance seen on the differential output with the reduction of its gate length, for example, an under driven or UD I/O device (G02 can be used). This can enable a higher switching speed, lowering loading capacitance.

If the G02 devices on the high side and low side of the output (i.e. 106 and 103) are of equal size (i.e. their W^*L are equal) but with different V_gate biasing, the push-pull output also enables a similar slew-rate on the positive and negative slopes to be obtained.

The generation of a voltage bias applied to the G02 devices fulfils two functional purposes. Firstly, it is used to set the output gain of the DAC transfer function, tracking the variation of a static reference current. Secondly, it allows for compensation of temperature variance when static reference current with zero temperature coefficient is utilized (which may be realized with a band gap reference). An accurate current reference DAC for static operation can be realized without accuracy tradeoff. This current reference DAC can be made to be over-range (i.e. with resolution greater than the required output gain trimming steps) for the purpose of calibrating the output gain linearity (i.e. the swing of the said DAC would nevertheless suffer from distortion, with finite output impedance in a physical implementation).

In the generation of voltage biasing to the G02 devices, a golden unary segment identical to the output unary segment may be utilized to generate the static voltage biasing which sets the output switched current (i.e. of unary weight). This is shown in Figure 2.

As the N devices typically exhibit higher charge carrier mobility, they have a higher transconductance (gm) than the P devices. The N voltage bias (VBIASN, node 201 ) may be first determined as a design parameter. For better matching, a device sizing to a high over- drive voltage (V_gs - V_th) may be chosen. This may be beneficial for reducing output load capacitance (i.e. for high speed operation).

A closed loop regulation of an operational amplifier (OpAmp, 202) driving the P voltage biasing (VBIASP, node 203), referencing the DAC output common mode voltage (VCM, node 204), with feedback taken from the output of the golden unary segment (GUS), sets up a sourcing current (push) from the P device equal to that of the sinking current (pull) of the N device. This forms the static voltage biasing (VBIASN and VBIASP) common to the unary segmented output stages. If the P and N G02 output devices are sized dimensionally equal, the loop regulation would bias VBIASP (V_gs of P device) greater than that of VBIASN. Thus, for safe operation within the voltage tolerance, VBIASN may also be set suitably to avoid exceeding this condition.

The closed loop regulation bandwidth sets the update rate of the gain adjustment. The static voltage biasing will see complimentary switching of the gate capacitive load (i.e. C_gs of G01 switching from Ό’ to T has a compliment, switching from to O’) and thus in operation the need for decoupling (i.e. the output capacitive load of the op amp) is not significant. This may be advantageous for achieving high loop bandwidth (i.e. a high update rate of gain adjustment).

In considering aspects of potential process manufacturing mismatch, for the source degenerate output stage, mismatch can be expected to be dominated by the G02 I/O devices (106 and 103 in Figure 1 ). This can be observed by examining the effective Gm of the source degenerate, Gm = 1/(1 /gm + R_dS), where gm is the transconductance of G02 devices and R_ds is the ON resistance of the G01 switches (104 and 109 in Figure 1 ). A study of sensitivity of Gm to variance in device Vth has shown that the gm term dominates. This can be advantageous. In “Parametric Analog Signal Amplification Applied to Nanoscale CMOS Technologies” by Joao Oliveira, Joao Goes, Section 1.3.5, a process technology dependent coefficient which captures threshold voltage matching is discussed as being approximately proportional to gate oxide thickness (i.e. for a given device of equal area, matching improves with process shrink) but as the process node scales down, gate leakage, a quantum tunnelling phenomenon, negates further improvement in matching in relation to device area (W^*L viz. Pelgrom’s Law).

VBIASP is generated in a suitable manner. However, in operation, the implementation of charge coupled level shifting is a dynamic phenomenon. Within the golden unary segment, a current trim scheme is applied for the adjustment of the P G01 switch (205 in Figure 2) gate voltage bias. The feedback for correction is to observe the current drawn from the common mode voltage source (VCM) in dynamic DAC operation. The trim set point is to reduce the dynamic current (by VCM source) to a minimum, where VCM is deemed a low impedance AC GND. The closed loop feedback is taken from the output of the golden unary segment. The GUS output stage has its operating condition matched to the full-scale voltage swing of intended operation together with output load, with respect to a common mode voltage (VCM). The output load may, for example, be a matched termination load of a transmission line.

Generally, the VCM is set at VDD/2. However, if the conditions discussed herein are suitably satisfied, the VCM may be lower so as to keep operational devices in saturation. Generally, the modulus of VBIASP may be arranged to be greater than VBIASN.

The use of G01 SC as pre-drivers to the output stage may result in a reduction in dynamic current, where it follows that the dynamic power dissipation is given by P = f.C.V² (where f=switching frequency, C=capacitive load of G01 switches, V=supply domain, DVDD). This addresses both the issues of integration (i.e. smaller device implementation of the DAC) and increasing power dissipation of a System-on-Chip (SOC) or Application Specific Integrated Circuit (ASIC) (i.e. contributes less and lowers overall power dissipation).

This allows the DAC to be implemented in applications such as a data communication analogue front end (AFE), where typically the transmitter AFE operates at an upscaling of the clocking frequency (i.e. the corresponding receiver may operate in the opposite way). The filtering of switching transients through the DVDD voltage domain regulator can aid the reduction of any EMI contribution, for example, cross-talk between the transmitter and receiver through supply noise or any emitted EM via conduction of supply current loop at circuit board level.

As mentioned above, manufacturing mismatch may be reduced using this topology. Ease of compatibility with the data path is a key advantage of this DAC architecture. To eliminate mismatches, dynamic element matching (DEM) can be applied. In the scheme described herein, the unary elements switch in a stochastic order in a current steering DAC. The stochastic switching order is offloaded to the digital domain for implementation. An implementation of pseudo-random ordering can be performed with a linear feedback shift register (LFSR). In an ideal DAC of N-bit with resolution 2^N, a synthesized sinusoid would result in the generation of harmonics in the frequency domain, for which the output SFDR (spurious-free dynamic range) can be approximated to SFDR [dBc] = 8.2N + 2.2. Other non-ideal transistor behaviors (such as the contribution of finite output impedance, capacitive loading of settling time, device mismatch and timing errors) may further degrade performance, with the generation of more harmonic spurs. Dynamic element matching (DEM), as described in IEEE Circuit and System Magazine, Compensation and Calibration Techniques for Current Steering DACs, Samantha M. McDonnell, Vipul J. Patel, Luke Duncan, Brian Dupaix and Waleed Khalil, is a digital signal processing method to minimize DAC cell mismatch. It can in effect translate mismatched induced distortion to white noise. This temporal approach (i.e. the pseudo random interchanging switching taps of unary segmented DAC weights) can effectively average the output mismatch errors (including timing errors, attributable to layout spatial effect), thus improving DAC integral non-linearity (INL).

As level shifting to the high side switch is implemented by charge coupling, trimming for process variation may be necessary. This covers device Cox (Cg), and thus the charge coupling ratio Cs/(Cg+Cs), where Cs is the (AC) charge coupling capacitor, which may be a MOM, MIM or MOS capacitor.

Some further advantages of embodiments of the DAC described herein will now be described.

The DAC architecture described herein requires no level shifting of the data path to the DAC current steering element (output stage). The signalling is in the same voltage domain as the DSP, digital filter or data serializer. The current steering element may be an analog front end (AFE) or PHY, which drives the output load (the transmission line with matching termination load).

The architecture relieves voltage tolerance of the output stage I/O devices, reducing the capacitive loading on its output. The push-pull output stage improves output slew rate and also reduces the headroom limitation by removing the need for a tail current source (common to a CML DAC) to keep operation in saturation, enabling a wide output signal swing. Closed loop regulation of the gain adjustment may also compensate for temperature variance.

The architecture described herein may also allow for easier digital interfacing when considering integration with designs comprising high performance digital cores for signal processing (which are required for high data throughput), together with the design tradeoff for bandwidth and mitigation of mismatch. Linearity of the DAC is offloaded to the digital core, where techniques of dynamic element matching may be applied. For example, 5 bit segmentation entails 31 segments, for 2Bit {16+4, 8+2}, 3Bit {16, 8, 4}, 4Bit (16, 8, 4, 2) and 5Bit {16, 8, 4, 2, 1}. Because not all of the unary segments are utilized in some uses: e.g. 30 (for 2 bit), 28 (for 3 bit), 30 (for 4 bit), 31 (for 5 bit), trimming of the reference current can be used to adjust the output swing (increasing or decreasing the gain, for example, nominal output = 30 segment weights, up trim +7.1% for 28 segment to equal nominal output, down trim -3.2% for 31 segment to equal nominal output) and hence enabling compensation to obtain the same output swing.

Embodiments of the DAC described herein may have an intrinsically faster switching speed (signaling with logic devices implemented on the process smallest feature length (Lmin)), eliminating any level shifting bottleneck.

A cross (voltage) domain level-shifter typically requires input/output (I/O) devices with higher overstressed voltage tolerance. In comparison, for the same gm, this presents a larger driver capacitance load, which follows the dynamic power dissipation P = f.C.V² (where f=switching frequency, C=capacitive load, V=supply domain), versus the logic devices.

The present architecture has an improved output signal swing limitation in comparison to traditional DAC resolution weighted (for example, for binary or unary weighting) current mode logic (CML) implementations, which impose headroom limitations to maintain devices in saturation (i.e. for both the differential pair and a shared tail current source).

The common mode voltage ideally can be at half of the supply rail voltage. EOS limitation of input/output devices is better tolerated (for example, for P/N channel devices, each sees half of the output voltage swing). A lower EOS voltage limit accommodates for devices of smaller minimum length. For example, a MOSFET device reliably qualified for operating at 1 8V may have its minimum gate length further reduced (for example, from 150nm to 90nm) to reliably qualify for a de-rated operation up to only 1.2 V. This effectively reduces capacitive load by the same ratio (as calculated per unit area, W^*L, around a 40% reduction). This can be expected to provide an improvement in bandwidth.

Mismatch between segments may also be mitigated with spatial interleaving, using layout common centroid techniques, whether in 1 -dimension or in a folded layout, in both X and Y.

Other applicable layout techniques may be used to embed a spatially distributed array of the feedback segments used to generate the biasing voltage. Dynamic element matching can also be implemented, given the compatibility of the architecture with ease of digital interfacing, thus compensating for segment mismatch.

Increasing data throughput requirements of a communication system requiries advances in design topology favorable to high speed modulation, offloading linearity correction to digital processing techniques. This is commonly referred to as Digitally Assisted Analog Design. This may simplify the design topology of an Analog Front-End (AFE) output stage.

This may allow for the integration of a digital processed signal with an AFE with increasingly smaller geometry process nodes, which requires compatibility with reduced signal headroom (to maximize signal swing with reduced voltage headroom limitation) as well as compatibility with digital driven pre-processing.

The design may also maintain or enhance signal integrity, thereupon improving figure of merits relating to signal linearity or distortion and increasing DAC resolution (i.e. facilitating increasing data throughput). The improvement may be dependent on the implemented modulation scheme (for example PAM-4, PAM-16, DMT, OFDM), as well as electrical noise and fabrication process manufacturing variation (i.e. intrinsic manufacturing mismatches or stochastic variation).

In maintenance of a communication channel characteristic (for example, bit error rate (BER)), there may be correction of variability attributable to the modulator’s operating temperature variation (for example, laser diode output optical power or Mach-Zehnder phase modulation transfer function). Tracking gain adjustment to the transfer function (i.e. the maximum output signal swing) can be applied, and therefore a correction can be applied to compensate.

As described above, the DAC topology may use G01 devices as switches. The switching noise from the SC pre-drivers directly drives the output stage without the need for level- shifting, and are further low pass filtered through the G01 power domain voltage regulator (for example, through the regulators output decoupling capacitor). This may be beneficial to reduce the EMI signature.

Closed loop regulation of the gain adjustment may also compensate for temperature variance. The ease of digital interface is key when considering integration with designs comprsing high performance digital cores for signal processing (as per the need with increasing data throughput), together with the design tradeoff for bandwidth and mitigation of mismatch. Linearity of the DAC is offloaded to the digital core, where techniques of dynamic element matching may be applied.

Figure 3(a) illustrates a simplified schematic view of the half circuit of a prior art current mode DAC output, where an ON’ state switch is represented as a resistor, Rds. This demonstrates that, in dynamic operation, the charging and discharging of gate capacitance (Cg) is limited by a biasing current (which is equivalent to the switched current). Figure 3(b) illustrates, in a similar state of operation to the DAC shown in Figure 3(a), the DAC described herein, where charging and discharging of the gate capacitance operates in the same way as a first order resistor-capacitor (RC) network.

In comparison to the arrangement of Figure 3(a), the arrangement of Figure 3(b) may not suffer from the limitation of switching speed that is attributable to the exercising of dv/dt of the switching node (i.e. for 3(a), ibias = c. dv/dt) to turn on the switched current with an application of gate voltage delta.

The applicant hereby discloses in isolation each individual feature described herein and any combination of two or more such features, to the extent that such features or combinations are capable of being carried out based on the present specification as a whole in the light of the common general knowledge of a person skilled in the art, irrespective of whether such features or combinations of features solve any problems disclosed herein, and without limitation to the scope of the claims. The applicant indicates that aspects of the present invention may consist of any such individual feature or combination of features. In view of the foregoing description it will be evident to a person skilled in the art that various modifications may be made within the scope of the invention.

Claims

1 . A digital to analogue converter comprising: a plurality of segments each comprising a first output stage and a second output stage, each output stage of a segment being configured to receive a digital input signal and the output stages being configured to cooperatively form a differential output in dependence on the input signal; wherein: each output stage of a segment comprises a first transistor device configured to operate as a regulated current source for driving a part of the differential output and to be switched in a source degenerate manner in dependence on the state of a second transistor of the respective output stage; and each segment is configured to form a unary segment and the plurality of segments cooperatively implement the digital to analogue converter.

2. A digital to analogue converter as claimed in claim 1 , wherein the first transistor has first gate oxide layer and the second transistor has a second gate oxide layer and the first gate oxide layer is thicker than the second gate oxide layer.

3. A digital to analogue converter as claimed in claim 1 or 2, wherein the second transistor is configured so that its state is dependent on a state of the input signal.

4. A digital to analogue converter as claimed in any preceding claim, comprising a capacitor configured for charge pumping the gate capacitance of the second transistor.

5. A digital to analogue converter as claimed in claim 4, wherein the capacitor is reset under the control of a switching arrangement cross-coupled between the output stages of a segment operating in the opposite phase.

6. A digital to analogue converter as claimed in claim 4 or 5, wherein the digital to analogue converter is implemented as an integrated circuit and the capacitor at least partially overlies one or both of the first transistor and second transistors.

7. A digital to analogue converter as claimed in any preceding claim, wherein in each output stage: the source and drain of the second transistor are coupled between a first voltage reference and a first node; the source and drain of a third transistor are coupled between the first node and a second node; the source and drain of the first transistor are coupled between the second node and a third node; the source and drain of a fourth transistor are coupled between the third node and a second voltage reference; and a part of the differential output is coupled to the second node.

8. A digital to analogue converter as claimed in claim 7, wherein the first transistor and the third transistor are configured to receive complementary bias voltages at their gates.

9. A digital to analogue converter as claimed in claim 7 or 8, wherein the second transistor and the fourth transistor are configured to be switched in complementary fashion in dependence on the input.

10. A digital to analogue converter as claimed in any of claims 7 to 9, wherein one of the second and fourth transistors is a P-type transistor and the other of the second and fourth transistors is an N-type transistor.

11. A digital to analogue converter as claimed in any preceding claim, arranged to be subject to closed loop compensating control whereby gain of a transfer function of each segment over temperature is maintained.

12. A data processing circuit comprising a digital to analogue converter as claimed in any preceding claim and a digital signal processor configured to form a digital signal as the input to the digital to analogue converter, wherein the digital to analogue converter and the digital signal processor are configured to operate in the same voltage domain.