WO2021068103A1 - System and method for efficient power delivery - Google Patents

System and method for efficient power delivery Download PDF

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Publication number
WO2021068103A1
WO2021068103A1 PCT/CN2019/109907 CN2019109907W WO2021068103A1 WO 2021068103 A1 WO2021068103 A1 WO 2021068103A1 CN 2019109907 W CN2019109907 W CN 2019109907W WO 2021068103 A1 WO2021068103 A1 WO 2021068103A1
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WO
WIPO (PCT)
Prior art keywords
voltage
power
power domain
transistors
array
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Application number
PCT/CN2019/109907
Other languages
French (fr)
Inventor
Yu PU
Jianyi MENG
Maoyuan LAO
Yuan Xie
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Alibaba Group Holding Limited
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Publication date
Application filed by Alibaba Group Holding Limited filed Critical Alibaba Group Holding Limited
Priority to CN201980101137.7A priority Critical patent/CN114503049A/en
Priority to PCT/CN2019/109907 priority patent/WO2021068103A1/en
Publication of WO2021068103A1 publication Critical patent/WO2021068103A1/en

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/59—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices including plural semiconductor devices as final control devices for a single load
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/575—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/577—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices for plural loads
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0063—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with circuits adapted for supplying loads from the battery

Definitions

  • the present disclosure relates to the technical field of circuit design, and particularly, to circuits, systems, and methods for efficient power delivery.
  • SoC System-on-chip
  • SoC System-on-chip
  • voice signals are collected by a microphone array and inputted into a voice activity detection (VAD) module located at one power domain.
  • VAD voice activity detection
  • a voice signal processor located at a different power domain is activated to analyze and process the voice signals.
  • the voice signal processor can be put in a power gated mode, i.e., a deep sleep mode, to save power.
  • the SoC interface circuit is powered by an external battery.
  • the voltage supplied by the external battery is converted to an intermediate voltage and supplied to a low dropout regulator (LDO) in the SoC.
  • the intermediate voltage is further regulated by the LDO to provide suitable voltages to the modules at different power domains.
  • Analog LDOs have been widely used in the voltage regulators but a recent trend is to replace the analog LDO with a digital LDO.
  • the digital LDO may simplify the circuit design, improve transmission bandwidth and response rate.
  • the voltage output of the digital LDO still experiences two levels of voltage drop before being supplied to the modules at the different power domains, causing power consumption and slow response rate. To reduce power consumption and improve a real-time response rate of the regulator circuit is still challenging.
  • FIG. 1 illustrates an example circuit for a voice recognition SoC according to current technology.
  • FIGs. 2 (a) and 2 (b) illustrate example circuits of an analog LDO and a digital LDO according to current technology.
  • FIG. 3 illustrates an example circuit for a voice recognition SoC in accordance with an embodiment of the present disclosure.
  • FIG. 4 illustrates a power distribution in the example circuit for a voice recognition SoC shown in FIG. 3.
  • FIG. 5 illustrates a power distribution in another example circuit for a voice recognition SoC in accordance with an embodiment of the present disclosure.
  • FIG. 6 illustrates another example circuit for a voice recognition SoC in accordance with an embodiment of the present disclosure.
  • FIG. 7 illustrates a power distribution in the example circuit for a voice recognition SoC shown in FIG. 6.
  • FIG. 8 illustrates an example process for power regulation in a voice recognition SoC in accordance with an embodiment of the present disclosure.
  • FIG. 9 illustrates another example process for power regulation in a voice recognition SoC in accordance with an embodiment of the present disclosure.
  • FIG. 10 illustrates another example process for power regulation in a voice recognition SoC in accordance with an embodiment of the present disclosure.
  • Systems and methods discussed herein are directed to reducing power consumption and improving response rate of the circuit for a voice recognition SoC.
  • the present disclosure replaces the analog LDO in the voice recognition SoC with the digital LDO to simplify the fabrication design, improve the transmission bandwidth, and improve the response speed.
  • the present disclosure further eliminates one layer of transistors for power delivery, thus, reducing the fabrication area and improving the power delivery efficiency. Because one layer of transistors for power delivery is eliminated, the voltage supplied to the modules in different power domains of the voice recognition SoC can be directly sensed, thus, reducing the power consumption and improving the response speed.
  • FIG. 1 illustrates an example circuit 100 for a voice recognition SoC 110 according to current technologies.
  • the voice recognition SoC 110 may include a voice activity detection (VAD) module 114 and a digital signal processing (DSP) +artificial intelligence (AI) processor 116.
  • VAD voice activity detection
  • DSP digital signal processing
  • AI artificial intelligence
  • the VAD module 114 and the DSP + AI processor 116 are disposed at different power domains. Both the VAD module 114 and the DSP+AI processor 116 are powered by a low dropout regulator (LDO) 112.
  • the LDO 112 regulates the voltage supplied to the VAD module 114 and the DSP+AI processor 116 utilizing a feedback voltage signal V SENS .
  • the VAD module 114 may detect an external voice signal through a microphone or a microphone array 130. When the voice signal strength meets or exceeds a preset threshold, the DSP+AI processor 116 may be waken up, i.e., activated, to analyze and process the detected voice signal.
  • the voice recognition SoC 110 is powered by an external battery 102.
  • the output voltage of the external battery 102 may be converted to an intermediate voltage V IN (for example, 1.8V, 1.5V, etc. ) by a switch mode power supply (SMPS) 104 and further provided to the LDO 112.
  • SMPS switch mode power supply
  • the voice recognition SoC 110 may further include a first transistor 118 coupled between the LDO 112 and the VAD module 114, and a second transistor 120 coupled between the LDO 112 and the DSP+AI processor 116.
  • Both the first transistor 118 and the second transistor 120 may operate as head switches to provide different voltage levels to the VAD module 114 and the DSP+AI module 116, respectively, which causes the VAD module 114 and the DSP+AI module 116 to operate at either an ungated power mode or a gated power mode.
  • the electric current flowing through the circuit blocks of the DSP+AI module 116 that are not in use may be shut off, thus, reducing power consumption of the circuit.
  • FIGs. 2 (a) and 2 (b) illustrate example circuits of an analog LDO and a digital LDO according to current technologies.
  • An analog LDO 202 shown in FIG. 2 (a) is commonly used in the voice recognition SoC 110 shown in FIG. 1.
  • the analog LDO 202 may include a comparator 204, a transistor 206, a capacitance 208, and a load 210.
  • the analog LDO 202 may utilize an analog voltage signal feedbacked from a source of the transistor 206 to control a gate voltage of the transistor 206 and to further regulate the output voltage V out and a current flowing through the load 210.
  • FIG. 2 (b) shows an example circuit of a digital LDO 220.
  • the digital LDO 220 may include a comparator 222, a digital controller 224, an array of transistors 226, a capacitance 228, and a load 230.
  • the digital LDO 220 may control the array of transistors 226 in a digital switching manner to further regulate the output voltage V out and a current flowing through the load 230.
  • the transistors in the array of transistors 226 may be block head-switch transistors or distributed head-switch transistors.
  • FIG. 3 illustrates an example circuit for a voice recognition SoC in accordance with an embodiment of the present disclosure.
  • the analog LDO in a voice recognition SoC is replaced with a digital LDO (D-LDO) .
  • D-LDO digital LDO
  • the voice recognition SoC 310 may include a digital LDO (D-LDO) 312, a VAD module 314, and a DSP+AI processor 316.
  • Voice signals may be inputted through a microphone array 330 operatively connected to the voice recognition SoC 310.
  • the VAD module 314 and the DSP+AI processor 316 may be disposed at different power domains in the circuit of the voice recognition SoC 310. As the DSP+AI processor 316 consumes more power than the VAD module 314, by disposing the DSP+AI processor 316 in a separate power domain from the VAD module 314 and waking it up only when a voice signal is detected at the VAD module 314, power consumption of the voice recognition SoC circuit can be greatly saved.
  • the VAD module 314 may implement a variety of computer algorithms to determine whether a speech is present or absent.
  • the VAD module 314 may pre-process the detected voice signal, such as noise reduction via spectral subtraction.
  • the VAD module 314 may extract features from a segment of the detected voice signal and determine whether the segment is speech or non-speech based on pre-set classification rules.
  • the pre-set classification rules may be based on comparing the strength of the detected voice signal with a threshold. If the strength of the detected voice signal meets or exceeds the threshold, the VAD module 314 may output a signal indicating a speech is present, causing the DSP+AI processor 316 being waken up from deep sleep, i.e., switching from the gated power? mode to an ungated power mode. If the strength of the detected voice signal is below the threshold, the VAD module 314 may determine a speech is absent.
  • the DSP+AI processor 316 may process the voice signal detected by the VAD module 314 or the voice signal pre-processed by the VAD module 314.
  • the DSP+AI processor 316 may perform actions such as noise suppression, echo cancellation, etc. to facilitate voice recognition and translation from speech into text.
  • the DSP+AI processor 316 may apply neuro network models to analyze the detected voice signal. Further, the DSP+AI processor 316 may be trained to identify a speaker rather than the speech for security purpose.
  • the D-LDO 312 may implement the circuit design as illustrated in FIG. 2 (b) . However, the present disclosure is not intended to be limiting. The D-LDO 312 may implement other circuit designs that perform the same voltage regulating functions. Unlike the analog LDO 202, the digital LDO 220 may control an array of transistors in a digital switching manner to further regulate the output voltage to the VAD module 314 and the DSP+AI processor 316.
  • the voice recognition SoC 310 may be powered by an external battery 302.
  • a switch mode power supply (SMPS) 304 may convert the voltage output of the external battery 302 to an intermediate voltage V IN and provide it to the D-LDO 312.
  • SMPS switch mode power supply
  • a first voltage drop ⁇ v 1 may be generated at an ungated power rail
  • a second voltage drop ⁇ v 2 may be generated at a gated rail through a first transistor 318 or the second transistor 320.
  • the voltage level at the ungated power rail may be a desired operating voltage of the VAD module 314 or the DSP+AI processor 316, for example, 1.1v.
  • the voltage level at the gated power rail after the second voltage drop ⁇ v 2 may be a desired gating voltage that causes the VAD module 314 or the DSP+AI processor 316 to enter a gated power mode to save power consumption, for example, 0.7v.
  • the voltage level at the ungated power rail may be sensed and feedbacked to the D-LDO 312 as V SENS to compare with a reference voltage V REF .
  • the D-LDO 312 may regulate the voltage at the ungated power rail at a preset voltage level, for example, 1.1v, based on the comparison result.
  • Using a digital LDO in a voice recognition SoC has greater advantages than using an analog LDO.
  • the comparator design can be simplified, and the circuit area and power consumption can be reduced.
  • the digital controller can be designed to optimize the switching frequency and algorithm, greater transmission bandwidth and faster response speed can be achieved.
  • the digital circuits used in the D-LDO facilitates the integration of the digital modules and can be scaled to 16nm, 10nm, 7nm, 5nm, etc., by more advanced fabrication techniques.
  • the voice recognition SoC may include digital modules other than the VAD module 314 and the DISP+AI processor 316 that are disposed in different power domains.
  • FIG. 4 illustrates a power distribution in the example circuit for a voice recognition SoC shown in FIG. 3.
  • a first voltage drop ⁇ v 1 may be generated at an ungated power rail 402 when the current passes through a first array of transistors 404
  • a second voltage drop ⁇ v 2 may be generated at a gated rail 406 when the current further passes through a second array of transistors 408.
  • the first array of transistors 404 and the second array of transistors 408 may be the array of power MOSFETs (metal-oxide-semiconductor field-effect transistor) designed to handle significant power levels.
  • MOSFETs metal-oxide-semiconductor field-effect transistor
  • the variation of the current may be detected at a sensing point 410 after a first time period t 1 .
  • a voltage V SENS at the sensing point 410 i.e., a real-time voltage at the ungated power rail 402 due to the current variation, may be feedbacked to a comparator 412.
  • the voltage V SENS at the sensing point 410 may be further compared with a reference voltage V REF .
  • the reference voltage V REF may be a programmable voltage generated by a voltage dividing circuit (not shown) .
  • the comparison result may be further transmitted to a digital controller 414.
  • the digital controller 414 may respond to the current variation by controlling the digital bits to be transmitted to the first array of transistors 404 via a system bus 416. For example, when V SENS is greater than V REF , the digital controller 414 may control the on/off status of the transistors in the first array, causing the output voltage to be reduced to a pre-set threshold level. Assuming the current passes from gates of the first array of transistors 404 to reach the sensing point 410 at the ungated power rail in a second time period t 2 , a response to the current variation may be received at the sensing point 410 after t 1 + t 2 .
  • the second voltage drop ⁇ v 2 may be around 50mV.
  • a margin has to be set at the output voltage of the D-LDO.
  • 50mV is a big power loss and hard to ignore.
  • the bandwidth of the SoC system and response rate are limited.
  • FIG. 5 illustrates a power distribution in another example circuit for a voice recognition SoC in accordance with an embodiment of the present disclosure.
  • the embodiment illustrated in FIG. 5 is intended to further reduce power consumption and improve the bandwidth and response rate of the circuit.
  • one layer of transistors for power delivery is eliminated.
  • the output of a digital controller 502 may be coupled directly to gates of an array of transistors 504 via a system bus 506 to regulate the output voltage.
  • the eliminated layer of transistors may be the first transistor 318 and the second transistor 320 as discussed above with reference to FIG. 3.
  • the eliminated layer of transistors may be implemented on the D-LDO, e.g., the D-LDO 312 in FIG. 3.
  • the load e.g., the load 230 shown in FIG. 2
  • the variation of the current may be instantly detected at a sensing point 520. Comparing to the embodiment shown in FIG. 4, the time delay, i.e., the first time period t 1 , for the current variation being detected at the sensing point 410 is avoided, thus achieving a faster real-time response to the current variation in the circuit.
  • a multiplier 508 may be coupled between the output of the digital controller 502 and the array of transistors 504 through a system bus 506.
  • the multiplier 508 may receive a mask signal, e.g., a set of mask bits, and multiply the set of mask bits with the output of the digital controller 502.
  • the mask signal may convey instructions to place the digital module in a power gated mode.
  • the output of the digital controller 502 may be voided to place the digital module in deep sleep, i.e., the power gated mode.
  • the output of the digital controller 502 may be voided by the set of masking bits received at the multiplier 508.
  • the present embodiment may provide an alternative and efficient control to overwrite a current trigger signal that has activated the digital module to operate at a power ungated mode and force the digital module, e.g., the VAD module 314 or the DSP+AI processor 316, to enter the power gated mode.
  • an external signal EN 514 may be inputted to the digital controller 502 so that the digital module, e.g., the VAD module 314 or the DSP+AI processor 316, can be instantly switched between the power ungated mode and the power gated mode.
  • the EN signal 514 may overwrite the current trigger signal that has activated the digital module to operate at the power ungated mode and force the digital module, e.g., the VAD module 314 or the DSP+AI processor 316, to enter the power gated mode.
  • the EN signal 514 may be supplies to overwrite the output of the digital controller 502 such that the voltage level at the ungated power rail maintains.
  • the supply of the mask signal or the EN signal may be achieved by programmable hardware elements implemented on the voice recognition SoC circuit.
  • the supply of the mask signal or the EN signal may be achieved by programmable software.
  • the supply of the mask signal or the EN signal may be achieved by a combination of programmable hardware elements and software.
  • FIG. 6 illustrates another example circuit for a voice recognition SoC in accordance with an embodiment of the present disclosure.
  • one layer of transistors for power delivery is eliminated.
  • the present embodiment eliminates using the first transistor 318 and the second transistor 320 to allow power delivery directly from the D-LDO 612 to the VAD module 614 and the DSP+AI processor 616.
  • the voice recognition SoC 610 may include a digital LDO (D-LDO) 612, a VAD module 614, and a DSP+AI processor 616.
  • the D-LDO 612 may implement the circuit design as illustrated in FIG. 2 (b) .
  • the D-LDO 612 may implement other circuit designs that perform the same voltage regulating functions.
  • the VAD module 614 and the DSP+AI processor 616 may perform the similar functions as those described with respect to the VAD module 314 and the DSP+AI processor 316, and thus, are not detailed herein.
  • Voice signals may be inputted through a microphone array 630 operatively connected to the voice recognition SoC 610.
  • the voice recognition SoC 610 may be powered by an external battery 602.
  • a switch mode power supply (SMPS) 604 may convert the voltage output of the external battery 602 to an intermediate voltage V IN and provide it to the D-LDO 612.
  • the D-LDO 612 may deliver the power to the VAD module 614 and a DSP+AI processor 616 without passing through an additional layer of transistors.
  • the voice recognition SoC 610 may further include a first switch 620 coupled between the D-LDO 612 and the VAD module 614 and a second switch 622 coupled between the D-LDO 612 and the DSP+AI processor 616. When the DSP+AI processor 616 operates in the power gated mode, the second switch 622 may be turned off.
  • the second switch 622 may be turned on, allowing the feedback voltage to be sensed at the gated power rail.
  • the first switch 620 may be turned off.
  • the first switch 610 may be turned on, allowing the feedback voltage V SENS to be sensed at the gated power rail.
  • FIG. 7 illustrates a power distribution in the example circuit for a voice recognition SoC shown in FIG. 6.
  • a first digital controller 702 may be configured to regulate the voltage outputted to a first digital module located in a first power domain of the SoC circuit, for example, the VAD module 614 in FIG. 6.
  • a second digital controller 704 may be configured to regulate the voltage outputted to a second digital module located in a second power domain of the SoC circuit, for example, the DSP+AI processor 616 in FIG. 6.
  • the first digital controller 702 and the second digital controller 704 may share a same comparator 706.
  • the output of the first digital controller 702 may be coupled directly to gates of a first array of transistors 708 to regulate the voltage supplied to the first digital module, for example, the VAD module 614 in FIG. 6.
  • the output of the second digital controller 704 may be coupled directly to gates of a second array of transistors 710 to regulate the voltage supplied to the second digital module, for example, the DSP+AI processor 616 in FIG. 6.
  • An intermediate voltage V IN may be supplied to drains of the first array of transistors 708, i.e., to the ungated power rail.
  • the intermediate voltage V IN may be supplied to drains of the second array of transistors 710, i.e., to the ungated power rail.
  • a first output voltage V OUT_1 may be generated after the current flows through the first array of transistors 708 and supplied to the first digital module, for example, the VAD module 614 in FIG. 6.
  • a second output voltage V OUT_1 may be generated after the current flows through the second array of transistors 710 and supplied to the second digital module, for example, the DSP+AI processor 616 in FIG. 6.
  • the first output voltage V OUT_1 may be directly sensed at a first sending point 730 and feedbacked to the comparator 706 and the second output voltage V OUT_2 may be directly sensed at a second sensing point 732 and feedbacked to the comparator 706.
  • the voice recognition SoC circuit may further include a first switch 720 and a second switch 722.
  • the first switch 720 When the first digital module operates in the power ungated mode, the first switch 720 may be turned on, allowing the first output voltage V OUT_1 being directly sensed and feedbacked to regulate the first output voltage.
  • the second switch 722 when the second digital module operates in the power gated mode and the first digital module operates in the power ungated mode, there may be no need to constantly sense the feedback voltage at the sensing point 732 and the second switch 722 may be turned off.
  • the second switch 722 When the second digital module operates in the power ungated mode, the second switch 722 may be turned on, allowing the second output voltage V OUT_2 being directly sensed and feedbacked to regulate the second output voltage.
  • the first switch 720 and the second switch 722 may be both turned on, allowing the first output voltage V OUT_1 and the second output voltage V OUT_2 being directly sensed and feedbacked to regulate the first output voltage and the second output voltage, respectively.
  • the first digital module and the second digital module may share the comparator 706.
  • the comparator 706 may set a same reference voltage V REF to be used to compare with the first output voltage V OUT_1 and the second output voltage V OUT_2 , causing the first digital module and the second digital module to be regulated at a same voltage level.
  • the comparator 706 may set individual reference voltages to be used to compare with the first output voltage V OUT_1 and the second output voltage V OUT_2 , respectively, causing the first digital module and the second digital module to be regulated at different voltage levels.
  • the first switch 720 and the second switch 722 may be both turned off to further save power.
  • the first digital module for example, the VAD module 614
  • the first digital module may be activated to switch from the power gated mode to the power ungated mode to pre-assess the voice signal.
  • the first switch 720 may be turned on, allowing voltage regulation through direct sensing.
  • the second digital module may be activated to switch from the power gated mode to the power ungated mode to further analyze and process the voice signal.
  • the second switch 722 may be turned on, allowing voltage regulation through direct sensing.
  • the voice recognition SoC circuit may further include a first multiplier 724 coupled between the first digital controller 702 and the first array of transistors 708 through a first system bus 712 and a second multiplier 726 coupled between the second digital controller 704 and the second array of transistors 710 through a second system bus 714.
  • the first multiplier 724 may be configured to receive a set of mask bits that conveys instructions to place the digital module in a power gated mode.
  • the output of the first digital controller 702 may be voided by a first set of mask bits received at the first multiplier 724 to place the VAD module 614 in deep sleep, i.e., the power gated mode.
  • the second multiplier 726 may be configured to receive a set of mask bits that conveys instructions to place the digital module in a power gated mode.
  • the output of the second digital controller 704 may be voided by a second set of mask bits received at the second multiplier 726 to place the DSP+AI processor 616 in deep sleep, i.e., the power gated mode.
  • the first set of mask bits and the second set of mask bits may be configured as the same. In other embodiments, the first set of mask bits and the second set of mask bits may be configured as different, depending on different configurations of the power rails. Comparing to the embodiment illustrated in FIG. 3 and FIG.
  • the present embodiment may provide an alternative and efficient control to overwrite a current trigger signal that has activated the digital module to operate at a power ungated mode and force the digital module, e.g., the VAD module 614 or the DSP+AI processor 616, to enter the power gated mode.
  • a current trigger signal that has activated the digital module to operate at a power ungated mode and force the digital module, e.g., the VAD module 614 or the DSP+AI processor 616, to enter the power gated mode.
  • an external signal EN may be inputted to the digital controller so that the digital module implemented on the voice recognition SoC circuit can be instantly switched between the power ungated mode and the power gated mode.
  • a first EN signal 716 may overwrite the current trigger signal that has activated the VAD module 614 to operate at a power ungated mode and force the VAD module 614 to enter the power gated mode.
  • the first EN signal 716 may be supplies to overwrite the output of the first digital controller 702 such that the voltage level at the ungated power rail maintains.
  • a second EN signal 718 may overwrite the current trigger signal that has activated the DSP+AI processor 616 to operate at a power ungated mode and force the DSP+AI processor 616 to enter the power gated mode.
  • the second EN signal 718 may be supplies to overwrite the output of the second digital controller 704 such that the voltage level at the ungated power rail maintains.
  • FIG. 8 illustrates an example process for power regulation in a voice recognition SoC in accordance with an embodiment of the present disclosure.
  • a first voltage may be provided to drains of a first array of transistors.
  • the first voltage may be an intermediate voltage V IN outputted by a switch mode power supply (SMPS) , e.g., V IN shown in FIGs. 5-7.
  • the first array of transistors may be the array of power MOSFETs (metal-oxide-semiconductor field-effect transistor) designed to handle significant power levels.
  • the process described with respect to block 802 may be performed by a switch mode power supply (SMPS) , such as the SMPS 304 in FIG. 3 and the SMPS 604 in FIG. 6.
  • the first array of transistors may be the array of transistor in FIG. 5, the first array of transistors 708 or the second array of transistors 710 in FIG. 7.
  • an output of a first digital controller may be coupled to gates of the first array of transistors.
  • the digital controller may control the output voltage of the first array of transistors by inputting a set of digital bits via a system bus to the gates of the first array of transistors.
  • the digital controller may be the digital controller 502 in FIG. 5, the first digital controller 702, or the second digital controller 704 in FIG. 7.
  • sources of the first array of transistors may be coupled to a first power domain to provide a second voltage to the first power domain.
  • the voice recognition SoC circuit may include one or more power domains. Each power domain may include one or more digital modules. Each power domain is individually supplied with power from the D-LDO.
  • the first power domain may include a VAD module 614 or a DSP+AI module 616.
  • the second voltage may be compared with a reference voltage.
  • the second voltage may be a voltage level at the gated power rail.
  • the second voltage may be sensed and feedback to a comparator to compare with a reference voltage.
  • the second voltage may be V SENS in FIGs. 5-6, V SENS_1 or V SENS_2 in FIG. 7.
  • the process described with respect to block 808 may be performed by a comparator, such as the comparator 412 in FIG. 4, the comparator 512 in FIG. 5, or the comparator 706 in FIG. 6.
  • the second voltage provided to the first power domain may be regulated at a preset voltage level based on the comparison.
  • the variation may be captured by the second voltage sensed at the gated power rail.
  • the digital controller may respond to the current variation based on comparing the second voltage with a reference voltage by controlling the status of the transistors in the array to regulate the output voltage.
  • the processor described with respect to block 810 may be performed by a digital controller, such as the digital controller 414 in FIG. 4, the digital controller 502 in FIG. 5, the first digital controller 702 in FIG. 7, or the second digital controller 704 in FIG. 7.
  • FIG. 9 illustrates an example process for power regulation in a voice recognition SoC in accordance with an embodiment of the present disclosure.
  • the processes described in blocks 902, 904, 906, 908, and 910 may be similar to those describes above in blocks 802, 804, 806, 808, and 810. Those processes therefore, are not detailed herein.
  • the output of the first digital controller to the gates of the first array of transistors may be masked, causing the first power domain to operate at a power gated mode.
  • the voice recognition SoC may apply a mask signal, i.e., a set of mask bits, to force the first power domain to operate at the power gated mode.
  • the processor described with respect to block 912 may be performed by a multiplier coupled between the output of a digital controller and a system bus, such as, the multiplier 508 in FIG. 5, the multiplier 724 in FIG. 7, or the multiplier 726 in FIG. 7.
  • FIG. 10 illustrates an example process for power regulation in a voice recognition SoC in accordance with an embodiment of the present disclosure.
  • the processes described in blocks 1002, 1004, 1006, 1008, and 1010 may be similar to those describes above in blocks 802, 804, 806, 808, and 810. Those processes therefore, are not detailed herein.
  • a control signal may be applied to the first digital controller, causing the first power domain to operate at a power ungated mode.
  • the control signal may be the EN signal 514 described with respect to FIG. 5, the EN signal 716 with respect to FIG. 7, or the EN signal with respect 718 with respect to FIG. 7.
  • the EN signal may overwrite the current trigger signal that has activated the digital module to operate at a power ungated mode and force the digital module to enter the power gated mode.
  • the EN signal may be supplies to overwrite the output of a digital controller such that the voltage level at the ungated power rail maintains.
  • the supply of the mask signal or the EN signal may be achieved by programmable hardware elements implemented on the voice recognition SoC circuit, programmable software, or the combination thereof.
  • Computer-readable instructions include routines, applications, application modules, program modules, programs, components, data structures, algorithms, and the like.
  • Computer-readable instructions can be implemented on various system configurations, including single-processor or multiprocessor systems, minicomputers, mainframe computers, personal computers, hand-held computing devices, microprocessor-based, programmable consumer electronics, combinations thereof, and the like.
  • the computer-readable storage media may include volatile memory (such as random-access memory (RAM) ) and/or non-volatile memory (such as read-only memory (ROM) , flash memory, etc. ) .
  • volatile memory such as random-access memory (RAM)
  • non-volatile memory such as read-only memory (ROM) , flash memory, etc.
  • the computer-readable storage media may also include additional removable storage and/or non-removable storage including, but not limited to, flash memory, magnetic storage, optical storage, and/or tape storage that may provide non-volatile storage of computer-readable instructions, data structures, program modules, and the like.
  • a non-transient computer-readable storage medium is an example of computer-readable media.
  • Computer-readable media includes at least two types of computer-readable media, namely computer-readable storage media and communications media.
  • Computer-readable storage media includes volatile and non-volatile, removable and non-removable media implemented in any process or technology for storage of information such as computer-readable instructions, data structures, program modules, or other data.
  • Computer-readable storage media includes, but is not limited to, phase change memory (PRAM) , static random-access memory (SRAM) , dynamic random-access memory (DRAM) , other types of random-access memory (RAM) , read- only memory (ROM) , electrically erasable programmable read-only memory (EEPROM) , flash memory or other memory technology, compact disk read-only memory (CD-ROM) , digital versatile disks (DVD) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information for access by a computing device.
  • communication media may embody computer-readable instructions, data structures, program modules, or other data in a modulated data signal, such as a carrier wave, or other transmission mechanism. As defined herein, computer-readable storage media do not include communication media.
  • the computer-readable instructions stored on one or more non-transitory computer-readable storage media that, when executed by one or more processors, may perform operations described above with reference to FIGs. 8-10.
  • computer-readable instructions include routines, programs, objects, components, data structures, and the like that perform particular functions or implement particular abstract data types.
  • the order in which the operations are described is not intended to be construed as a limitation, and any number of the described operations can be combined in any order and/or in parallel to implement the processes.
  • a method comprising: providing a first voltage to drains of a first array of transistors; coupling an output of a first digital controller to gates of the first array of transistors; coupling sources of the first array of transistors to a first power domain to provide a second voltage to the first power domain; comparing the second voltage with a reference voltage; and regulating the second voltage provided to the first power domain at a preset voltage level based on the comparison.
  • the first power domain includes a voice activity detection (VAD) module
  • the second power domain includes a digital signal processing (DSP) module
  • the DSP module is integrated with an artificial intelligence (AI) processor
  • the method further comprises: detecting a voice signal at the VAD module located at the first power domain; and in response the voice signal meets or exceeds a signal level, causing the DSP module located at the second power domain to switch from the power gated mode to a power ungated mode to process the voice signal.
  • VAD voice activity detection
  • DSP digital signal processing
  • AI artificial intelligence
  • a system comprising: a first power domain; and a voltage regulating circuit to receive a first voltage and provide a second voltage to the first power domain, the voltage regulating circuit including: a comparator; a first digital controller; and a first array of transistors, wherein: gates of the first array of transistors are coupled to the first controller; drains of the first array of transistors are provided with the first voltage; and sources of the first array of transistors are coupled to the first power domain and provide the second voltage to the first power domain, wherein: the voltage regulation circuit regulates the second voltage at a preset voltage level based at least on comparing the second voltage with a reference voltage.
  • the voltage regulating circuit further provides a third voltage to the second power domain and comprises: the comparator; a second digital controller; and a second array of transistors, wherein: gates of the second array of transistors are coupled to the first controller; drains of the second array of transistors are provided with the first voltage; and sources of the second array of transistors are coupled to the second power domain and provide the third voltage to the second power domain, wherein: the voltage regulation circuit regulates the third voltage at the preset voltage level based at least on comparing the third voltage with the reference voltage.
  • N The system as recited in paragraph M, further comprising: a second switch coupled between sources of the second array of transistors and the comparator, wherein: when the second power domain operates at a power ungated mode and the first power domain operates at a power gated mode, the second switch is turned on, allowing the third voltage provided to the second power domain being sensed and compared with the reference voltage at the comparator.
  • the first power domain includes a voice activity detection (VAD) module to detect a voice signal
  • the second power domain includes a digital signal processing (DSP) module to process the voice signal, wherein: in response the voice signal meets or exceeds a signal level, the DSP module is switched from a power gated mode to a power ungated mode to process the voice signal, and the DSP module is integrated with an artificial intelligence (AI) processor.
  • VAD voice activity detection
  • DSP digital signal processing
  • a circuit comprising: a comparator; a first digital controller; and a first array of transistors, wherein: gates of the first array of transistors are coupled to the first controller; drains of the first array of transistors are provided with the first voltage; and sources of the first array of transistors are coupled to the first power domain and provide the second voltage to the first power domain.
  • circuit as recited in paragraph R further comprising: a first multiplier to receive a first masking signal and mask an output of the first digital controller to gates of the first array of transistors, causing the first power domain to operate at a power gated mode.
  • circuit as recited in paragraph S, further comprising: a first switch coupled between sources of the first array of transistors and the comparator, wherein: when the first power domain operates at a power ungated mode, the first switch is turned on, allowing the second voltage provided to the first power domain being sensed and compared with a reference voltage at the comparator.
  • the first power domain includes a voice activity detection (VAD) module to detect a voice signal
  • the second power domain includes a digital signal processing (DSP) module to process the voice signal, wherein: in response the voice signal meets or exceeds a signal level, the DSP module is switched from a power gated mode to a power ungated mode to process the voice signal, and the DSP module is integrated with an artificial intelligence (AI) processor.
  • VAD voice activity detection
  • DSP digital signal processing

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Abstract

Methods and systems for power regulation in a voice recognition System-on-Chip (SoC) are provided. The methods include providing a first voltage to drains of a first array of transistors; coupling an output of a first digital controller to gates of the first array of transistors; coupling sources of the first array of transistors to a first power domain to provide a second voltage to the first power domain; comparing the second voltage with a reference voltage; and regulating the second voltage provided to the first power domain at a preset voltage level based on the comparison.

Description

SYSTEM AND METHOD FOR EFFICIENT POWER DELIVERY TECHNICAL FIELD
The present disclosure relates to the technical field of circuit design, and particularly, to circuits, systems, and methods for efficient power delivery.
BACKGROUND
System-on-chip (SoC) is widely used in interactive voice services. In an SoC interface design, multiple power domains are normally adopted to reduce power consumption in the circuit. In a voice SoC interface, voice signals are collected by a microphone array and inputted into a voice activity detection (VAD) module located at one power domain. When the voice signals are detected at the VAD module, a voice signal processor located at a different power domain is activated to analyze and process the voice signals. When no voice signals are detected by the VAD module, the voice signal processor can be put in a power gated mode, i.e., a deep sleep mode, to save power.
The SoC interface circuit is powered by an external battery. The voltage supplied by the external battery is converted to an intermediate voltage and supplied to a low dropout regulator (LDO) in the SoC. The intermediate voltage is further regulated by the LDO to provide suitable voltages to the modules at different power domains. Analog LDOs have been widely used in the voltage regulators but a recent trend is to replace the analog LDO with a digital LDO. The digital LDO may simplify the circuit design, improve transmission bandwidth and response rate. However, in the current circuit design for the voice recognition SoC, the voltage output of the digital LDO still  experiences two levels of voltage drop before being supplied to the modules at the different power domains, causing power consumption and slow response rate. To reduce power consumption and improve a real-time response rate of the regulator circuit is still challenging.
BRIEF DESCRIPTION OF THE DRAWINGS
The detailed description is set forth with reference to the accompanying figures. In the figures, the left-most digit (s) of a reference number identifies the figure in which the reference number first appears. The use of the same reference numbers in different figures indicates similar or identical items or features.
FIG. 1 illustrates an example circuit for a voice recognition SoC according to current technology.
FIGs. 2 (a) and 2 (b) illustrate example circuits of an analog LDO and a digital LDO according to current technology.
FIG. 3 illustrates an example circuit for a voice recognition SoC in accordance with an embodiment of the present disclosure.
FIG. 4 illustrates a power distribution in the example circuit for a voice recognition SoC shown in FIG. 3.
FIG. 5 illustrates a power distribution in another example circuit for a voice recognition SoC in accordance with an embodiment of the present disclosure.
FIG. 6 illustrates another example circuit for a voice recognition SoC in accordance with an embodiment of the present disclosure.
FIG. 7 illustrates a power distribution in the example circuit for a voice recognition SoC shown in FIG. 6.
FIG. 8 illustrates an example process for power regulation in a voice recognition SoC in accordance with an embodiment of the present disclosure.
FIG. 9 illustrates another example process for power regulation in a voice recognition SoC in accordance with an embodiment of the present disclosure.
FIG. 10 illustrates another example process for power regulation in a voice recognition SoC in accordance with an embodiment of the present disclosure.
DETAILED DESCRIPTION
Systems and methods discussed herein are directed to reducing power consumption and improving response rate of the circuit for a voice recognition SoC. The present disclosure replaces the analog LDO in the voice recognition SoC with the digital LDO to simplify the fabrication design, improve the transmission bandwidth, and improve the response speed. The present disclosure further eliminates one layer of transistors for power delivery, thus, reducing the fabrication area and improving the power delivery efficiency. Because one layer of transistors for power delivery is eliminated, the voltage supplied to the modules in different power domains of the voice recognition SoC can be directly sensed, thus, reducing the power consumption and improving the response speed.
FIG. 1 illustrates an example circuit 100 for a voice recognition SoC 110 according to current technologies. The voice recognition SoC 110 may  include a voice activity detection (VAD) module 114 and a digital signal processing (DSP) +artificial intelligence (AI) processor 116. The VAD module 114 and the DSP + AI processor 116 are disposed at different power domains. Both the VAD module 114 and the DSP+AI processor 116 are powered by a low dropout regulator (LDO) 112. The LDO 112 regulates the voltage supplied to the VAD module 114 and the DSP+AI processor 116 utilizing a feedback voltage signal V SENS. The VAD module 114 may detect an external voice signal through a microphone or a microphone array 130. When the voice signal strength meets or exceeds a preset threshold, the DSP+AI processor 116 may be waken up, i.e., activated, to analyze and process the detected voice signal.
The voice recognition SoC 110 is powered by an external battery 102. The output voltage of the external battery 102 may be converted to an intermediate voltage V IN (for example, 1.8V, 1.5V, etc. ) by a switch mode power supply (SMPS) 104 and further provided to the LDO 112. The voice recognition SoC 110 may further include a first transistor 118 coupled between the LDO 112 and the VAD module 114, and a second transistor 120 coupled between the LDO 112 and the DSP+AI processor 116. Both the first transistor 118 and the second transistor 120 may operate as head switches to provide different voltage levels to the VAD module 114 and the DSP+AI module 116, respectively, which causes the VAD module 114 and the DSP+AI module 116 to operate at either an ungated power mode or a gated power mode. When operating at the gated power mode, for example, the electric current flowing through the circuit blocks of the DSP+AI module 116 that are not in use may be shut off, thus, reducing power consumption of the circuit.
FIGs. 2 (a) and 2 (b) illustrate example circuits of an analog LDO and a digital LDO according to current technologies. An analog LDO 202 shown in FIG. 2 (a) is commonly used in the voice recognition SoC 110 shown in FIG. 1. The analog LDO 202 may include a comparator 204, a transistor 206, a capacitance 208, and a load 210. The analog LDO 202 may utilize an analog voltage signal feedbacked from a source of the transistor 206 to control a gate voltage of the transistor 206 and to further regulate the output voltage V out and a current flowing through the load 210.
A recent trend in the SoC design is to replace the analog LDO with a digital LDO. FIG. 2 (b) shows an example circuit of a digital LDO 220. The digital LDO 220 may include a comparator 222, a digital controller 224, an array of transistors 226, a capacitance 228, and a load 230. The digital LDO 220 may control the array of transistors 226 in a digital switching manner to further regulate the output voltage V out and a current flowing through the load 230. The transistors in the array of transistors 226 may be block head-switch transistors or distributed head-switch transistors.
FIG. 3 illustrates an example circuit for a voice recognition SoC in accordance with an embodiment of the present disclosure. According to the present embodiment, the analog LDO in a voice recognition SoC is replaced with a digital LDO (D-LDO) .
The voice recognition SoC 310 may include a digital LDO (D-LDO) 312, a VAD module 314, and a DSP+AI processor 316. Voice signals may be inputted through a microphone array 330 operatively connected to the voice recognition SoC 310. The VAD module 314 and the DSP+AI processor 316 may be disposed at different power domains in the circuit of the voice  recognition SoC 310. As the DSP+AI processor 316 consumes more power than the VAD module 314, by disposing the DSP+AI processor 316 in a separate power domain from the VAD module 314 and waking it up only when a voice signal is detected at the VAD module 314, power consumption of the voice recognition SoC circuit can be greatly saved.
The VAD module 314 may implement a variety of computer algorithms to determine whether a speech is present or absent. The VAD module 314 may pre-process the detected voice signal, such as noise reduction via spectral subtraction. In embodiments, the VAD module 314 may extract features from a segment of the detected voice signal and determine whether the segment is speech or non-speech based on pre-set classification rules. For example, the pre-set classification rules may be based on comparing the strength of the detected voice signal with a threshold. If the strength of the detected voice signal meets or exceeds the threshold, the VAD module 314 may output a signal indicating a speech is present, causing the DSP+AI processor 316 being waken up from deep sleep, i.e., switching from the gated power? mode to an ungated power mode. If the strength of the detected voice signal is below the threshold, the VAD module 314 may determine a speech is absent.
The DSP+AI processor 316 may process the voice signal detected by the VAD module 314 or the voice signal pre-processed by the VAD module 314. The DSP+AI processor 316 may perform actions such as noise suppression, echo cancellation, etc. to facilitate voice recognition and translation from speech into text. In embodiments, the DSP+AI processor 316 may apply neuro network models to analyze the detected voice signal. Further,  the DSP+AI processor 316 may be trained to identify a speaker rather than the speech for security purpose.
The D-LDO 312 may implement the circuit design as illustrated in FIG. 2 (b) . However, the present disclosure is not intended to be limiting. The D-LDO 312 may implement other circuit designs that perform the same voltage regulating functions. Unlike the analog LDO 202, the digital LDO 220 may control an array of transistors in a digital switching manner to further regulate the output voltage to the VAD module 314 and the DSP+AI processor 316. The voice recognition SoC 310 may be powered by an external battery 302. A switch mode power supply (SMPS) 304 may convert the voltage output of the external battery 302 to an intermediate voltage V IN and provide it to the D-LDO 312. When D-LDO 312 supplies the voltage to the VAD module 314 or the DSP+AI processor 316, a first voltage drop Δv 1 may be generated at an ungated power rail, and a second voltage drop Δv 2 may be generated at a gated rail through a first transistor 318 or the second transistor 320. The voltage level at the ungated power rail may be a desired operating voltage of the VAD module 314 or the DSP+AI processor 316, for example, 1.1v. The voltage level at the gated power rail after the second voltage drop Δv 2 may be a desired gating voltage that causes the VAD module 314 or the DSP+AI processor 316 to enter a gated power mode to save power consumption, for example, 0.7v. The voltage level at the ungated power rail may be sensed and feedbacked to the D-LDO 312 as V SENS to compare with a reference voltage V REF. The D-LDO 312 may regulate the voltage at the ungated power rail at a preset voltage level, for example, 1.1v, based on the comparison result.
Using a digital LDO in a voice recognition SoC has greater advantages than using an analog LDO. The comparator design can be simplified, and the circuit area and power consumption can be reduced. Further, as the digital controller can be designed to optimize the switching frequency and algorithm, greater transmission bandwidth and faster response speed can be achieved. In addition, the digital circuits used in the D-LDO facilitates the integration of the digital modules and can be scaled to 16nm, 10nm, 7nm, 5nm, etc., by more advanced fabrication techniques.
It should be understood that the example circuit for a voice recognition SoC in FIG. 3 is for illustration purpose. The present disclosure is not intended to be limiting. The voice recognition SoC may include digital modules other than the VAD module 314 and the DISP+AI processor 316 that are disposed in different power domains.
FIG. 4 illustrates a power distribution in the example circuit for a voice recognition SoC shown in FIG. 3. As shown in FIG. 4, a first voltage drop Δv 1 may be generated at an ungated power rail 402 when the current passes through a first array of transistors 404, and a second voltage drop Δv 2 may be generated at a gated rail 406 when the current further passes through a second array of transistors 408. The first array of transistors 404 and the second array of transistors 408 may be the array of power MOSFETs (metal-oxide-semiconductor field-effect transistor) designed to handle significant power levels.
In real-time, when the current flowing through the load (e.g., the load 230 shown in FIG. 2 (b) varies, the variation of the current may be detected at a sensing point 410 after a first time period t 1. A voltage V SENS at the sensing  point 410, i.e., a real-time voltage at the ungated power rail 402 due to the current variation, may be feedbacked to a comparator 412. The voltage V SENS at the sensing point 410 may be further compared with a reference voltage V REF. The reference voltage V REF may be a programmable voltage generated by a voltage dividing circuit (not shown) . The comparison result may be further transmitted to a digital controller 414. Based on the comparison result, the digital controller 414 may respond to the current variation by controlling the digital bits to be transmitted to the first array of transistors 404 via a system bus 416. For example, when V SENS is greater than V REF, the digital controller 414 may control the on/off status of the transistors in the first array, causing the output voltage to be reduced to a pre-set threshold level. Assuming the current passes from gates of the first array of transistors 404 to reach the sensing point 410 at the ungated power rail in a second time period t 2, a response to the current variation may be received at the sensing point 410 after t 1 + t 2.
The second voltage drop Δv 2 may be around 50mV. To compensate the second voltage drop, a margin has to be set at the output voltage of the D-LDO. In a low voltage power supply system as the SoC, 50mV is a big power loss and hard to ignore. Further, as the response to a real-time current variation has to pass through two levels of transistor arrays, the bandwidth of the SoC system and response rate are limited.
FIG. 5 illustrates a power distribution in another example circuit for a voice recognition SoC in accordance with an embodiment of the present disclosure. The embodiment illustrated in FIG. 5 is intended to further reduce power consumption and improve the bandwidth and response rate of the circuit.
According to the embodiment illustrated in FIG. 5, one layer of transistors for power delivery is eliminated. The output of a digital controller 502 may be coupled directly to gates of an array of transistors 504 via a system bus 506 to regulate the output voltage. In one embodiment, the eliminated layer of transistors may be the first transistor 318 and the second transistor 320 as discussed above with reference to FIG. 3. In another embodiment, the eliminated layer of transistors may be implemented on the D-LDO, e.g., the D-LDO 312 in FIG. 3. In one embodiment, when the load (e.g., the load 230 shown in FIG. 2) current varies, the variation of the current may be instantly detected at a sensing point 520. Comparing to the embodiment shown in FIG. 4, the time delay, i.e., the first time period t 1, for the current variation being detected at the sensing point 410 is avoided, thus achieving a faster real-time response to the current variation in the circuit.
In embodiments, a multiplier 508 may be coupled between the output of the digital controller 502 and the array of transistors 504 through a system bus 506. The multiplier 508 may receive a mask signal, e.g., a set of mask bits, and multiply the set of mask bits with the output of the digital controller 502. In one embodiment, the mask signal may convey instructions to place the digital module in a power gated mode. When a digital module implemented on the SoC, e.g., the VAD module 314 or the DSP+AI processor 316, needs to operate in the power gated mode, the output of the digital controller 502 may be voided to place the digital module in deep sleep, i.e., the power gated mode. In one embodiment, the output of the digital controller 502 may be voided by the set of masking bits received at the multiplier 508. Comparing to the embodiment illustrated in FIG. 3 and FIG. 4, where switching between a power ungated  mode and a power gated mode relies on the voltage regulation of a D-LDO, the present embodiment may provide an alternative and efficient control to overwrite a current trigger signal that has activated the digital module to operate at a power ungated mode and force the digital module, e.g., the VAD module 314 or the DSP+AI processor 316, to enter the power gated mode.
In another embodiment, an external signal EN 514 may be inputted to the digital controller 502 so that the digital module, e.g., the VAD module 314 or the DSP+AI processor 316, can be instantly switched between the power ungated mode and the power gated mode. For example, the EN signal 514 may overwrite the current trigger signal that has activated the digital module to operate at the power ungated mode and force the digital module, e.g., the VAD module 314 or the DSP+AI processor 316, to enter the power gated mode. In another example, when the digital module, e.g., the VAD module 314 or the DSP+AI processor 316, is desired to operate continuously on the power ungated mode, the EN signal 514 may be supplies to overwrite the output of the digital controller 502 such that the voltage level at the ungated power rail maintains.
In an embodiment, the supply of the mask signal or the EN signal may be achieved by programmable hardware elements implemented on the voice recognition SoC circuit. In another embodiment, the supply of the mask signal or the EN signal may be achieved by programmable software. In yet another embodiment, the supply of the mask signal or the EN signal may be achieved by a combination of programmable hardware elements and software.
FIG. 6 illustrates another example circuit for a voice recognition SoC in accordance with an embodiment of the present disclosure. According to the  present embodiment, one layer of transistors for power delivery is eliminated. Comparing to the embodiment illustrated in FIG. 3, the present embodiment eliminates using the first transistor 318 and the second transistor 320 to allow power delivery directly from the D-LDO 612 to the VAD module 614 and the DSP+AI processor 616.
The voice recognition SoC 610 may include a digital LDO (D-LDO) 612, a VAD module 614, and a DSP+AI processor 616. The D-LDO 612 may implement the circuit design as illustrated in FIG. 2 (b) . However, the present disclosure is not intended to be limiting. The D-LDO 612 may implement other circuit designs that perform the same voltage regulating functions. The VAD module 614 and the DSP+AI processor 616 may perform the similar functions as those described with respect to the VAD module 314 and the DSP+AI processor 316, and thus, are not detailed herein. Voice signals may be inputted through a microphone array 630 operatively connected to the voice recognition SoC 610.
The voice recognition SoC 610 may be powered by an external battery 602. A switch mode power supply (SMPS) 604 may convert the voltage output of the external battery 602 to an intermediate voltage V IN and provide it to the D-LDO 612. The D-LDO 612 may deliver the power to the VAD module 614 and a DSP+AI processor 616 without passing through an additional layer of transistors. In embodiments, the voice recognition SoC 610 may further include a first switch 620 coupled between the D-LDO 612 and the VAD module 614 and a second switch 622 coupled between the D-LDO 612 and the DSP+AI processor 616. When the DSP+AI processor 616 operates in the power gated mode, the second switch 622 may be turned off. When the DSP+AI processor  616 operates in the power ungated mode, the second switch 622 may be turned on, allowing the feedback voltage to be sensed at the gated power rail. Similarly, when the VAD module 614 operates in the power gated mode, there may be no need to constantly sense the voltage at the gated power rail and the first switch 620 may be turned off. When the VAD module 614 operates in the power ungated mode, the first switch 610 may be turned on, allowing the feedback voltage V SENS to be sensed at the gated power rail. By implementing the first switch 620 and the second switch 622 to control whether to sense the voltage at the gated power rail related to the digital module, further power saving in the voice recognition SoC circuits can be achieved.
FIG. 7 illustrates a power distribution in the example circuit for a voice recognition SoC shown in FIG. 6. As illustrated in FIG. 7, a first digital controller 702 may be configured to regulate the voltage outputted to a first digital module located in a first power domain of the SoC circuit, for example, the VAD module 614 in FIG. 6. A second digital controller 704 may be configured to regulate the voltage outputted to a second digital module located in a second power domain of the SoC circuit, for example, the DSP+AI processor 616 in FIG. 6. The first digital controller 702 and the second digital controller 704 may share a same comparator 706. The output of the first digital controller 702 may be coupled directly to gates of a first array of transistors 708 to regulate the voltage supplied to the first digital module, for example, the VAD module 614 in FIG. 6. The output of the second digital controller 704 may be coupled directly to gates of a second array of transistors 710 to regulate the voltage supplied to the second digital module, for example, the DSP+AI processor 616 in FIG. 6.
An intermediate voltage V IN may be supplied to drains of the first array of transistors 708, i.e., to the ungated power rail. Meantime, the intermediate voltage V IN may be supplied to drains of the second array of transistors 710, i.e., to the ungated power rail. A first output voltage V OUT_1 may be generated after the current flows through the first array of transistors 708 and supplied to the first digital module, for example, the VAD module 614 in FIG. 6. A second output voltage V OUT_1 may be generated after the current flows through the second array of transistors 710 and supplied to the second digital module, for example, the DSP+AI processor 616 in FIG. 6.
In embodiments, the first output voltage V OUT_1 may be directly sensed at a first sending point 730 and feedbacked to the comparator 706 and the second output voltage V OUT_2 may be directly sensed at a second sensing point 732 and feedbacked to the comparator 706. In other embodiments, the voice recognition SoC circuit may further include a first switch 720 and a second switch 722. When the first digital module, for example, the VAD module 614 in FIG. 6, operates in the power gated mode, and the second digital module, for example, the DSP+AI processor 616 in FIG. 6, operates in the power ungated mode, there may be no need to constantly sense the feedback voltage at the sensing point 730 and the first switch 720 may be turned off. When the first digital module operates in the power ungated mode, the first switch 720 may be turned on, allowing the first output voltage V OUT_1 being directly sensed and feedbacked to regulate the first output voltage. Similarly, when the second digital module operates in the power gated mode and the first digital module operates in the power ungated mode, there may be no need to constantly sense the feedback voltage at the sensing point 732 and the second switch 722 may  be turned off. When the second digital module operates in the power ungated mode, the second switch 722 may be turned on, allowing the second output voltage V OUT_2 being directly sensed and feedbacked to regulate the second output voltage.
In embodiments, when the first digital module, for example, the VAD module 614, and the second digital module, for example, the DSP+AI processor 616, both operate in the power ungated mode, the first switch 720 and the second switch 722 may be both turned on, allowing the first output voltage V OUT_1 and the second output voltage V OUT_2 being directly sensed and feedbacked to regulate the first output voltage and the second output voltage, respectively. The first digital module and the second digital module may share the comparator 706. The comparator 706 may set a same reference voltage V REF to be used to compare with the first output voltage V OUT_1 and the second output voltage V OUT_2, causing the first digital module and the second digital module to be regulated at a same voltage level. In other embodiments, the comparator 706 may set individual reference voltages to be used to compare with the first output voltage V OUT_1 and the second output voltage V OUT_2, respectively, causing the first digital module and the second digital module to be regulated at different voltage levels.
In embodiments, when the first digital module, for example, the VAD module 614, and the second digital module, for example, the DSP+AI processor 616, both operate in the power gated mode, the first switch 720 and the second switch 722 may be both turned off to further save power. When a voice signal is detected at the first digital module, for example, the VAD module 614, the first digital module may be activated to switch from the power gated mode to  the power ungated mode to pre-assess the voice signal. Meantime, the first switch 720 may be turned on, allowing voltage regulation through direct sensing. When the strength of the voice signal meets or exceeds a preset threshold, the first digital module determines that a voice is present, the second digital module, for example, the DSP+AI processor 616, may be activated to switch from the power gated mode to the power ungated mode to further analyze and process the voice signal. Meantime, the second switch 722 may be turned on, allowing voltage regulation through direct sensing.
In embodiments, the voice recognition SoC circuit may further include a first multiplier 724 coupled between the first digital controller 702 and the first array of transistors 708 through a first system bus 712 and a second multiplier 726 coupled between the second digital controller 704 and the second array of transistors 710 through a second system bus 714. The first multiplier 724 may be configured to receive a set of mask bits that conveys instructions to place the digital module in a power gated mode. When the first digital module implemented on the SoC, for example, the VAD module 614, needs to operate in the power gated mode, the output of the first digital controller 702 may be voided by a first set of mask bits received at the first multiplier 724 to place the VAD module 614 in deep sleep, i.e., the power gated mode. The second multiplier 726 may be configured to receive a set of mask bits that conveys instructions to place the digital module in a power gated mode. When the second digital module implemented on the SoC, for example, the DSP+AI processor 616, needs to operate in the power gated mode, the output of the second digital controller 704 may be voided by a second set of mask bits received at the second multiplier 726 to place the DSP+AI processor 616 in  deep sleep, i.e., the power gated mode. In embodiments, the first set of mask bits and the second set of mask bits may be configured as the same. In other embodiments, the first set of mask bits and the second set of mask bits may be configured as different, depending on different configurations of the power rails. Comparing to the embodiment illustrated in FIG. 3 and FIG. 4, where switching between a power ungated mode and a power gated mode relies on the voltage regulation of a D-LDO, the present embodiment may provide an alternative and efficient control to overwrite a current trigger signal that has activated the digital module to operate at a power ungated mode and force the digital module, e.g., the VAD module 614 or the DSP+AI processor 616, to enter the power gated mode.
In another embodiment, an external signal EN may be inputted to the digital controller so that the digital module implemented on the voice recognition SoC circuit can be instantly switched between the power ungated mode and the power gated mode. For example, a first EN signal 716 may overwrite the current trigger signal that has activated the VAD module 614 to operate at a power ungated mode and force the VAD module 614 to enter the power gated mode. In another example, when the VAD module 614 is desired to operate continuously on the power ungated mode, the first EN signal 716 may be supplies to overwrite the output of the first digital controller 702 such that the voltage level at the ungated power rail maintains. Similarly, a second EN signal 718 may overwrite the current trigger signal that has activated the DSP+AI processor 616 to operate at a power ungated mode and force the DSP+AI processor 616 to enter the power gated mode. In another example, when the DSP+AI processor 616 is desired to operate continuously on the power ungated  mode, the second EN signal 718 may be supplies to overwrite the output of the second digital controller 704 such that the voltage level at the ungated power rail maintains.
FIG. 8 illustrates an example process for power regulation in a voice recognition SoC in accordance with an embodiment of the present disclosure.
At block 802, a first voltage may be provided to drains of a first array of transistors. The first voltage may be an intermediate voltage V IN outputted by a switch mode power supply (SMPS) , e.g., V IN shown in FIGs. 5-7. The first array of transistors may be the array of power MOSFETs (metal-oxide-semiconductor field-effect transistor) designed to handle significant power levels. In embodiments, the process described with respect to block 802 may be performed by a switch mode power supply (SMPS) , such as the SMPS 304 in FIG. 3 and the SMPS 604 in FIG. 6. The first array of transistors may be the array of transistor in FIG. 5, the first array of transistors 708 or the second array of transistors 710 in FIG. 7.
At block 804, an output of a first digital controller may be coupled to gates of the first array of transistors. The digital controller may control the output voltage of the first array of transistors by inputting a set of digital bits via a system bus to the gates of the first array of transistors. In embodiments, the digital controller may be the digital controller 502 in FIG. 5, the first digital controller 702, or the second digital controller 704 in FIG. 7.
At block 806, sources of the first array of transistors may be coupled to a first power domain to provide a second voltage to the first power domain. The voice recognition SoC circuit may include one or more power domains. Each power domain may include one or more digital modules. Each power  domain is individually supplied with power from the D-LDO. In embodiments, the first power domain may include a VAD module 614 or a DSP+AI module 616.
At block 808, the second voltage may be compared with a reference voltage. The second voltage may be a voltage level at the gated power rail. The second voltage may be sensed and feedback to a comparator to compare with a reference voltage. The second voltage may be V SENS in FIGs. 5-6, V SENS_1 or V SENS_2 in FIG. 7. In embodiments, the process described with respect to block 808 may be performed by a comparator, such as the comparator 412 in FIG. 4, the comparator 512 in FIG. 5, or the comparator 706 in FIG. 6.
At block 810, the second voltage provided to the first power domain may be regulated at a preset voltage level based on the comparison. When a current variation occurs in the load, the variation may be captured by the second voltage sensed at the gated power rail. The digital controller may respond to the current variation based on comparing the second voltage with a reference voltage by controlling the status of the transistors in the array to regulate the output voltage. In embodiments, the processor described with respect to block 810 may be performed by a digital controller, such as the digital controller 414 in FIG. 4, the digital controller 502 in FIG. 5, the first digital controller 702 in FIG. 7, or the second digital controller 704 in FIG. 7.
It should be understood for those of ordinary skilled in the art that the processes described above are intended to be illustrative. In embodiments, a process may be accomplished with one or more additional operations not described, and/or without one or more of the operations discussed. Further,  the order in which the operations of the process as illustrated in FIG. 8 and set forth above is not intended to be limiting.
FIG. 9 illustrates an example process for power regulation in a voice recognition SoC in accordance with an embodiment of the present disclosure. The processes described in  blocks  902, 904, 906, 908, and 910 may be similar to those describes above in  blocks  802, 804, 806, 808, and 810. Those processes therefore, are not detailed herein.
At block 912, the output of the first digital controller to the gates of the first array of transistors may be masked, causing the first power domain to operate at a power gated mode. In addition to relying on the direct sensing and voltage regulation in response to the sensed voltage change, the voice recognition SoC may apply a mask signal, i.e., a set of mask bits, to force the first power domain to operate at the power gated mode. In embodiments, the processor described with respect to block 912 may be performed by a multiplier coupled between the output of a digital controller and a system bus, such as, the multiplier 508 in FIG. 5, the multiplier 724 in FIG. 7, or the multiplier 726 in FIG. 7.
It should be understood for those of ordinary skilled in the art that the processes described above are intended to be illustrative. In embodiments, a process may be accomplished with one or more additional operations not described, and/or without one or more of the operations discussed. Further, the order in which the operations of the process as illustrated in FIG. 9 and set forth above is not intended to be limiting.
FIG. 10 illustrates an example process for power regulation in a voice recognition SoC in accordance with an embodiment of the present disclosure.  The processes described in  blocks  1002, 1004, 1006, 1008, and 1010 may be similar to those describes above in  blocks  802, 804, 806, 808, and 810. Those processes therefore, are not detailed herein.
At block 1012, a control signal may be applied to the first digital controller, causing the first power domain to operate at a power ungated mode. In embodiment, the control signal may be the EN signal 514 described with respect to FIG. 5, the EN signal 716 with respect to FIG. 7, or the EN signal with respect 718 with respect to FIG. 7. The EN signal may overwrite the current trigger signal that has activated the digital module to operate at a power ungated mode and force the digital module to enter the power gated mode. In another example, when the digital module is desired to operate continuously on the power ungated mode, the EN signal may be supplies to overwrite the output of a digital controller such that the voltage level at the ungated power rail maintains.
The supply of the mask signal or the EN signal may be achieved by programmable hardware elements implemented on the voice recognition SoC circuit, programmable software, or the combination thereof.
It should be understood for those of ordinary skilled in the art that the processes described above are intended to be illustrative. In embodiments, a process may be accomplished with one or more additional operations not described, and/or without one or more of the operations discussed. Further, the order in which the operations of the process as illustrated in FIG. 10 and set forth above is not intended to be limiting.
Some or all operations of the methods described above can be performed by execution of computer-readable instructions stored on a  computer-readable storage medium, as defined below. The term “computer-readable instructions” as used in the description and claims, include routines, applications, application modules, program modules, programs, components, data structures, algorithms, and the like. Computer-readable instructions can be implemented on various system configurations, including single-processor or multiprocessor systems, minicomputers, mainframe computers, personal computers, hand-held computing devices, microprocessor-based, programmable consumer electronics, combinations thereof, and the like.
The computer-readable storage media may include volatile memory (such as random-access memory (RAM) ) and/or non-volatile memory (such as read-only memory (ROM) , flash memory, etc. ) . The computer-readable storage media may also include additional removable storage and/or non-removable storage including, but not limited to, flash memory, magnetic storage, optical storage, and/or tape storage that may provide non-volatile storage of computer-readable instructions, data structures, program modules, and the like.
A non-transient computer-readable storage medium is an example of computer-readable media. Computer-readable media includes at least two types of computer-readable media, namely computer-readable storage media and communications media. Computer-readable storage media includes volatile and non-volatile, removable and non-removable media implemented in any process or technology for storage of information such as computer-readable instructions, data structures, program modules, or other data. Computer-readable storage media includes, but is not limited to, phase change memory (PRAM) , static random-access memory (SRAM) , dynamic random-access memory (DRAM) , other types of random-access memory (RAM) , read- only memory (ROM) , electrically erasable programmable read-only memory (EEPROM) , flash memory or other memory technology, compact disk read-only memory (CD-ROM) , digital versatile disks (DVD) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information for access by a computing device. In contrast, communication media may embody computer-readable instructions, data structures, program modules, or other data in a modulated data signal, such as a carrier wave, or other transmission mechanism. As defined herein, computer-readable storage media do not include communication media.
The computer-readable instructions stored on one or more non-transitory computer-readable storage media that, when executed by one or more processors, may perform operations described above with reference to FIGs. 8-10. Generally, computer-readable instructions include routines, programs, objects, components, data structures, and the like that perform particular functions or implement particular abstract data types. The order in which the operations are described is not intended to be construed as a limitation, and any number of the described operations can be combined in any order and/or in parallel to implement the processes.
EXAMPLE CLAUSES
A. A method comprising: providing a first voltage to drains of a first array of transistors; coupling an output of a first digital controller to gates of the first array of transistors; coupling sources of the first array of transistors to a first power domain to provide a second voltage to the first power domain; comparing the second voltage with a reference voltage; and regulating the second voltage provided to the first power domain at a preset voltage level based on the comparison.
B. The method as recited in paragraph A, further comprising: masking the output of the first digital controller to the gates of the first array of transistors, causing the first power domain to operate at a power gated mode.
C. The method as recited in paragraph A, further comprising: applying a control signal to the first digital controller, causing the first power domain to operate at a power ungated mode.
D. The method as recited in paragraph A, further comprising: providing the first voltage to drains of a second array of transistors; coupling an output of a second digital controller to gates of the second array of transistors; coupling sources of the second array of transistors to a second power domain to provide a third voltage to the second power domain; comparing the third voltage with the reference voltage; and regulating the third voltage provided to the second power domain at the preset voltage level based on the comparison.
E. The method as recited in paragraph D, further comprising: when the first power domain operates at a power ungated mode and the second power domain operates at a power gated mode, sensing the second voltage  provided to the first power domain; and comparing the second voltage with the reference voltage to regulate the second voltage.
F. A method as recited in paragraph D, wherein: the first power domain includes a voice activity detection (VAD) module; and the second power domain includes a digital signal processing (DSP) module, wherein the DSP module is integrated with an artificial intelligence (AI) processor, and the method further comprises: detecting a voice signal at the VAD module located at the first power domain; and in response the voice signal meets or exceeds a signal level, causing the DSP module located at the second power domain to switch from the power gated mode to a power ungated mode to process the voice signal.
G. The method as recited in paragraph D, further comprising: applying a control signal to the second digital controller, causing the second power domain to switch from the power gated mode to operate at a power ungated mode.
H. The method as recited in paragraph D, further comprising: when the first power domain and the second power domain operate at a power ungated mode, sensing the second voltage provided to the first power domain; sensing the third voltage provided to the second power domain; comparing the second voltage with the reference voltage to regulate the second voltage; and comparing the third voltage with the reference voltage to regulate the third voltage.
I. A system comprising: a first power domain; and a voltage regulating circuit to receive a first voltage and provide a second voltage to the first power domain, the voltage regulating circuit including: a comparator; a first  digital controller; and a first array of transistors, wherein: gates of the first array of transistors are coupled to the first controller; drains of the first array of transistors are provided with the first voltage; and sources of the first array of transistors are coupled to the first power domain and provide the second voltage to the first power domain, wherein: the voltage regulation circuit regulates the second voltage at a preset voltage level based at least on comparing the second voltage with a reference voltage.
J. The system as recited in paragraph I, further comprising: a second power domain, wherein: the voltage regulating circuit further provides a third voltage to the second power domain and comprises: the comparator; a second digital controller; and a second array of transistors, wherein: gates of the second array of transistors are coupled to the first controller; drains of the second array of transistors are provided with the first voltage; and sources of the second array of transistors are coupled to the second power domain and provide the third voltage to the second power domain, wherein: the voltage regulation circuit regulates the third voltage at the preset voltage level based at least on comparing the third voltage with the reference voltage.
K. The system as recited in paragraph I, further comprising: a first multiplier to receive a first masking signal and mask an output of the first digital controller to gates of the first array of transistors, causing the first power domain to operate at a power gated mode.
L. The system as recited in paragraph K, further comprising: a first switch coupled between sources of the first array of transistors and the comparator, wherein: when the first power domain operates at a power ungated mode and the second power domain operates at a power ungated mode, the  first switch is turned on, allowing the second voltage provided to the first power domain being sensed and compared with the reference voltage at the comparator.
M. The system as recited in paragraph J, further comprising: a second multiplier to receive a second masking signal and mask an output of the second digital controller to gates of the second array of transistors, causing the second power domain to operate at a power gated mode.
N. The system as recited in paragraph M, further comprising: a second switch coupled between sources of the second array of transistors and the comparator, wherein: when the second power domain operates at a power ungated mode and the first power domain operates at a power gated mode, the second switch is turned on, allowing the third voltage provided to the second power domain being sensed and compared with the reference voltage at the comparator.
O. The system as recited in paragraph J, wherein: the first power domain includes a voice activity detection (VAD) module to detect a voice signal; and the second power domain includes a digital signal processing (DSP) module to process the voice signal, wherein: in response the voice signal meets or exceeds a signal level, the DSP module is switched from a power gated mode to a power ungated mode to process the voice signal, and the DSP module is integrated with an artificial intelligence (AI) processor.
P. The system as recited in paragraph I, wherein: the first digital controller further receives a control signal, causing the first power domain to operate at a power ungated mode.
Q. The as recited in paragraph J, wherein: the second digital controller further receives a control signal, causing the second power domain to operate at a power ungated mode.
R. A circuit comprising: a comparator; a first digital controller; and a first array of transistors, wherein: gates of the first array of transistors are coupled to the first controller; drains of the first array of transistors are provided with the first voltage; and sources of the first array of transistors are coupled to the first power domain and provide the second voltage to the first power domain.
S. The circuit as recited in paragraph R, further comprising: a first multiplier to receive a first masking signal and mask an output of the first digital controller to gates of the first array of transistors, causing the first power domain to operate at a power gated mode.
T. The circuit as recited in paragraph S, further comprising: a first switch coupled between sources of the first array of transistors and the comparator, wherein: when the first power domain operates at a power ungated mode, the first switch is turned on, allowing the second voltage provided to the first power domain being sensed and compared with a reference voltage at the comparator.
U. The circuit as recited in paragraph R, further comprising: a second digital controller; and a second array of transistors, wherein: gates of the second array of transistors are coupled to the first controller; drains of the second array of transistors are provided with the first voltage; and sources of the second array of transistors are coupled to the second power domain and provide the third voltage to the second power domain.
V. The circuit as recited in paragraph U, further comprising: a second multiplier to receive a second masking signal and mask an output of the second digital controller to gates of the second array of transistors, causing the second power domain to operate at a power gated mode.
W. The circuit as recited in paragraph V, further comprising: a second switch coupled between sources of the second array of transistors and the comparator, wherein: when the second power domain operates at a power ungated mode, the second switch is turned on, allowing the third voltage provided to the second power domain being sensed and compared with a reference voltage at the comparator.
X. The circuit as recited in paragraph U, wherein: the first power domain includes a voice activity detection (VAD) module to detect a voice signal; and the second power domain includes a digital signal processing (DSP) module to process the voice signal, wherein: in response the voice signal meets or exceeds a signal level, the DSP module is switched from a power gated mode to a power ungated mode to process the voice signal, and the DSP module is integrated with an artificial intelligence (AI) processor.
Y. The circuit as recited in paragraph R, wherein: the first digital controller further receives a control signal, causing the first power domain to operate at a power ungated mode.
Z. The as recited in paragraph U, wherein: the second digital controller further receives a control signal, causing the second power domain to operate at a power ungated mode.
CONCLUSION
Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described. Rather, the specific features and acts are disclosed as exemplary forms of implementing the claims.

Claims (22)

  1. A method comprising:
    providing a first voltage to drains of a first array of transistors;
    coupling an output of a first digital controller to gates of the first array of transistors;
    coupling sources of the first array of transistors to a first power domain to provide a second voltage to the first power domain;
    comparing the second voltage with a reference voltage; and
    regulating the second voltage provided to the first power domain at a preset voltage level based on the comparison.
  2. The method of claim 1, further comprising:
    masking the output of the first digital controller to the gates of the first array of transistors, causing the first power domain to operate at a power gated mode.
  3. The method of claim 1, further comprising:
    applying a control signal to the first digital controller, causing the first power domain to operate at a power ungated mode.
  4. The method of claim 1, further comprising:
    providing the first voltage to drains of a second array of transistors;
    coupling an output of a second digital controller to gates of the second array of transistors;
    coupling sources of the second array of transistors to a second power domain to provide a third voltage to the second power domain;
    comparing the third voltage with the reference voltage; and
    regulating the third voltage provided to the second power domain at the preset voltage level based on the comparison.
  5. The method of claim 4, further comprising:
    when the first power domain operates at a power ungated mode and the second power domain operates at a power gated mode:
    sensing the second voltage provided to the first power domain; and
    comparing the second voltage with the reference voltage to regulate the second voltage.
  6. The method of claim 4, wherein:
    the first power domain includes a voice activity detection (VAD) module; and
    the second power domain includes a digital signal processing (DSP) module, wherein the DSP module is integrated with an artificial intelligence (AI) processor, and the method further comprises:
    detecting a voice signal at the VAD module located at the first power domain; and
    in response the voice signal meets or exceeds a signal level, causing the DSP module located at the second power domain to switch from a power gated mode to a power ungated mode to process the voice signal.
  7. The method of claim 4, further comprising:
    applying a control signal to the second digital controller, causing the second power domain to switch from the power gated mode to operate at a power ungated mode.
  8. The method of claim 4, further comprising:
    when the first power domain and the second power domain operate at a power ungated mode:
    sensing the second voltage provided to the first power domain;
    sensing the third voltage provided to the second power domain;
    comparing the second voltage with the reference voltage to regulate the second voltage; and
    comparing the third voltage with the reference voltage to regulate the third voltage.
  9. A system comprising:
    a first power domain; and
    a voltage regulating circuit to receive a first voltage and provide a second voltage to the first power domain, the voltage regulating circuit including:
    a comparator;
    a first digital controller; and
    a first array of transistors, wherein:
    gates of the first array of transistors are coupled to the first controller;
    drains of the first array of transistors are provided with the first voltage; and
    sources of the first array of transistors are coupled to the first power domain and provide the second voltage to the first power domain, wherein:
    the voltage regulation circuit regulates the second voltage at a preset voltage level based at least on comparing the second voltage with a reference voltage.
  10. The system of claim 9, further comprising:
    a second power domain, wherein:
    the voltage regulating circuit further provides a third voltage to the second power domain and comprises:
    the comparator;
    a second digital controller; and
    a second array of transistors, wherein:
    gates of the second array of transistors are coupled to the first controller;
    drains of the second array of transistors are provided with the first voltage; and
    sources of the second array of transistors are coupled to the second power domain and provide the third voltage to the second power domain, wherein:
    the voltage regulation circuit regulates the third voltage at the preset voltage level based at least on comparing the third voltage with the reference voltage.
  11. The system of claim 9, further comprising:
    a first multiplier to receive a first masking signal and mask an output of the first digital controller to gates of the first array of transistors, causing the first power domain to operate at a power gated mode.
  12. The system of claim 11, further comprising:
    a first switch coupled between sources of the first array of transistors and the comparator, wherein:
    when the first power domain operates at a power ungated mode and the second power domain operates at a power ungated mode, the first switch is turned on, allowing the second voltage provided to the first power domain being sensed and compared with the reference voltage at the comparator.
  13. The system of claim 10, further comprising:
    a second multiplier to receive a second masking signal and mask an output of the second digital controller to gates of the second array of transistors, causing the second power domain to operate at a power gated mode.
  14. The system of claim 13, further comprising:
    a second switch coupled between sources of the second array of transistors and the comparator, wherein:
    when the second power domain operates at a power ungated mode and the first power domain operates at a power gated mode, the second switch is turned on, allowing the third voltage provided to the  second power domain being sensed and compared with the reference voltage at the comparator.
  15. The system of claim 10, wherein:
    the first power domain includes a voice activity detection (VAD) module to detect a voice signal; and
    the second power domain includes a digital signal processing (DSP) module to process the voice signal, wherein:
    in response the voice signal meets or exceeds a signal level, the DSP module is switched from a power gated mode to a power ungated mode to process the voice signal, and
    the DSP module is integrated with an artificial intelligence (AI) processor.
  16. A circuit comprising:
    a comparator;
    a first digital controller; and
    a first array of transistors, wherein:
    gates of the first array of transistors are coupled to the first controller;
    drains of the first array of transistors are provided with the first voltage; and
    sources of the first array of transistors are coupled to the first power domain and provide the second voltage to the first power domain, wherein:
    the circuit regulates the second voltage at a preset voltage level based at least on comparing the second voltage with a reference voltage.
  17. The circuit of claim 16, further comprising:
    a first multiplier to receive a first masking signal and mask an output of the first digital controller to gates of the first array of transistors, causing the first power domain to operate at a power gated mode.
  18. The circuit of claim 17, further comprising:
    a first switch coupled between sources of the first array of transistors and the comparator, wherein:
    when the first power domain operates at a power ungated mode and the second power domain operates at a power gated mode, the first switch is turned on, allowing the second voltage provided to the first power domain being sensed and compared with a reference voltage at the comparator.
  19. The circuit of claim 16, further comprising:
    a second digital controller; and
    a second array of transistors, wherein:
    gates of the second array of transistors are coupled to the first controller;
    drains of the second array of transistors are provided with the first voltage; and
    sources of the second array of transistors are coupled to the second power domain and provide the third voltage to the second power domain, wherein:
    the circuit regulates the third voltage at a preset voltage level based at least on comparing the third voltage with the reference voltage.
  20. The circuit of claim 19, further comprising:
    a second multiplier to receive a second masking signal and mask an output of the second digital controller to gates of the second array of transistors, causing the second power domain to operate at a power gated mode.
  21. The circuit of claim 20, further comprising:
    a second switch coupled between sources of the second array of transistors and the comparator, wherein:
    when the second power domain operates at a power ungated mode and the first power domain operates at a power gated mode, the second switch is turned on, allowing the third voltage provided to the second power domain being sensed and compared with a reference voltage at the comparator.
  22. The circuit of claim 19, wherein:
    the first power domain includes a voice activity detection (VAD) module to detect a voice signal; and
    the second power domain includes a digital signal processing (DSP) module to process the voice signal, wherein:
    in response the voice signal meets or exceeds a signal level, the DSP module is switched from a power gated mode to a power ungated mode to process the voice signal, and
    the DSP module is integrated with an artificial intelligence (AI) processor.
PCT/CN2019/109907 2019-10-08 2019-10-08 System and method for efficient power delivery WO2021068103A1 (en)

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CN101847928A (en) * 2010-04-14 2010-09-29 广州市广晟微电子有限公司 Quick starting circuit and method of low-noise linear regulator
CN101881983A (en) * 2010-04-16 2010-11-10 北京利云技术开发公司 Numerical-control low-noise high-power-supply-rejection-ratio low-dropout regulator
CN204231474U (en) * 2014-06-26 2015-03-25 帝奥微电子有限公司 Signal processing system
CN105843318A (en) * 2016-03-23 2016-08-10 深圳芯智汇科技有限公司 Low dropout regulator circuit
CN107924206A (en) * 2015-08-21 2018-04-17 高通股份有限公司 For the single LDO of multiple voltage domains

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US20100109435A1 (en) * 2008-09-26 2010-05-06 Uti Limited Partnership Linear Voltage Regulator with Multiple Outputs
CN101667046A (en) * 2009-09-28 2010-03-10 中国科学院微电子研究所 Low-voltage difference voltage adjuster
CN101847928A (en) * 2010-04-14 2010-09-29 广州市广晟微电子有限公司 Quick starting circuit and method of low-noise linear regulator
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