WO2021062798A1 - 栈溢出的检测方法、装置、电子设备及存储介质 - Google Patents

栈溢出的检测方法、装置、电子设备及存储介质 Download PDF

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Publication number
WO2021062798A1
WO2021062798A1 PCT/CN2019/109723 CN2019109723W WO2021062798A1 WO 2021062798 A1 WO2021062798 A1 WO 2021062798A1 CN 2019109723 W CN2019109723 W CN 2019109723W WO 2021062798 A1 WO2021062798 A1 WO 2021062798A1
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stack
address
memory
boundary
register
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PCT/CN2019/109723
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English (en)
French (fr)
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银国超
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深圳市汇顶科技股份有限公司
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Priority to PCT/CN2019/109723 priority Critical patent/WO2021062798A1/zh
Publication of WO2021062798A1 publication Critical patent/WO2021062798A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
    • G06F21/52—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity ; Preventing unwanted data erasure; Buffer overflow
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode

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  • This application relates to the field of computer technology, and in particular to a detection method, device, electronic device, and storage medium for stack overflow.
  • stack overflow is one of the important causes of system instability. Therefore, it is necessary to detect whether there is a stack overflow in a timely manner.
  • the above method requires the central processing unit to detect the value of the stack register in real time while it is running.
  • the value of the stack register can be any value, so it cannot be accurately judged. Whether there is a stack overflow. And when it is not in the OS scene, it is impossible to judge whether a stack overflow occurs in real time.
  • the present application provides a stack overflow detection method, device, electronic equipment, and storage medium, which can accurately determine the stack overflow exception in time without modifying the kernel.
  • an embodiment of the present application provides a stack overflow detection method, including:
  • the stack boundary information in the stack boundary configuration register determine whether the current access to the memory address is an illegal access event
  • the preset condition includes: the currently accessed memory address is between the stack top address and the stack bottom address indicated by the stack register;
  • it also includes:
  • the memory access of the central processing unit is interrupted.
  • it also includes:
  • the setting the stack boundary information in the stack boundary configuration register includes:
  • the stack boundary information is written in the stack boundary configuration register through the central processing unit; wherein, the stack boundary information includes: the start address of the stack boundary, the end address of the stack boundary, and the stack bottom address; the stack The bottom address and the end address of the stack boundary are used to define the range of the stack memory.
  • the stack boundary information in the stack boundary configuration register it is determined whether the current access to the memory address is an illegal access event, including:
  • the current access memory address is between the start address of the stack boundary and the end address of the stack boundary, it is determined that the current access address is an illegal access event.
  • it also includes:
  • the state of the stack overflow status register is set to the overflow state.
  • it also includes:
  • the stack overflow status register Through the stack overflow status register, the corresponding context information in the overflow state is stored.
  • an embodiment of the present application provides a stack overflow detection device, including: a memory protection unit and an interrupt controller that are connected in communication;
  • the memory protection unit is used to determine whether the currently accessed memory address is an illegal access event; if it is an illegal access event, determine whether the currently accessed memory address meets a preset condition; wherein, the preset condition includes: the currently accessed memory address is on the stack Between the address of the top of the stack and the address of the bottom of the stack indicated by the register; if the preset condition is met, the stack overflow is determined. ;
  • it further includes: an interrupt controller communicatively connected with the memory protection unit;
  • the memory protection unit is also used to: send a trigger signal to the interrupt controller;
  • the interrupt controller is used to interrupt the memory access of the central processing unit according to the trigger signal.
  • it further includes a stack register communicatively connected with the memory protection unit, and the memory protection unit obtains the stack top address from the stack register.
  • the memory protection unit obtains the stack top address from the stack register through a stack register access port exposed by the central processing unit; or, obtains the stack top address from the stack register through a debug port The top address of the stack.
  • it further includes: a stack boundary configuration register communicatively connected with the memory protection unit, the stack boundary configuration register is used to store stack boundary information; the stack boundary information includes: the start of the stack boundary The address, the end address of the stack boundary, and the bottom address of the stack; the stack bottom address and the end address of the stack boundary are used to define the range of the stack memory.
  • the central processing unit is in communication connection with the stack boundary configuration register, and is configured to write the stack boundary information into the stack boundary configuration register.
  • the memory protection unit is further configured to determine whether the current access to the memory address is an illegal access event according to the stack boundary information in the stack boundary configuration register.
  • the illegal access event means that the current access memory address is located between the start address of the stack boundary and the end address of the stack boundary.
  • it further includes: a stack overflow status register communicatively connected with the memory protection unit;
  • the memory protection unit is also used to set the state of the stack overflow status register to the overflow state when the current access memory address is between the stack top address and the stack bottom address indicated by the stack register.
  • the stack overflow status register is used to store the corresponding context information in the overflow state.
  • an embodiment of the present application provides an electronic device, including: a processor and a memory; the memory stores an algorithm program, and the processor is used to retrieve the algorithm program in the memory, and execute it as in the first aspect Any one of the stack overflow detection methods.
  • an embodiment of the present application provides a computer-readable storage medium, including: program instructions, which when run on a computer, cause the computer to execute the program instructions, so as to implement the program instructions described in any one of the first aspect Stack overflow detection method.
  • the stack overflow detection method, device, device, and storage medium provided in this application determine whether the current memory address is an illegal access event according to the stack boundary information in the stack boundary configuration register; if it is an illegal access event, it is determined Whether the currently accessed memory address meets a preset condition; wherein, the preset condition includes: the currently accessed memory address is between the stack top address and the stack bottom address indicated by the stack register; if the preset condition is met, it is determined to be a stack overflow.
  • This application comprehensively uses the detection of memory access permissions and stack range to determine whether a stack overflow occurs, so that it can accurately determine whether there is a stack overflow in a timely manner without changing the kernel, and reduce misjudgments.
  • Figure 1 is a schematic diagram of the principle of an application scenario of this application.
  • Figure 2 is a schematic diagram of the address space comparison between ordinary illegal access events and illegal access events caused by stack overflow provided by this application;
  • FIG. 3 is a flowchart of a method for detecting stack overflow provided in Embodiment 1 of the application;
  • FIG. 4 is a schematic structural diagram of a stack overflow detection device provided in Embodiment 2 of this application;
  • FIG. 5 is a schematic structural diagram of a stack overflow detection device provided in Embodiment 3 of this application.
  • FIG. 6 is a schematic structural diagram of an electronic device provided in Embodiment 4 of this application.
  • stack overflow is an important cause of system instability. Therefore, it is necessary to detect whether there is a stack overflow in a timely manner.
  • There are two main methods for detecting stack overflow 1) judging whether the value of the stack register exceeds the preset address boundary; 2) initializing the stack space with a special value, and judging whether there is an out-of-bounds event by judging whether the initial value of the stack boundary has changed.
  • the above method requires the central processing unit to be able to detect the value of the stack register in real time when it is running.
  • the value of the stack register can be any value, the real-time and accuracy of the detection cannot be guaranteed, resulting in A misjudgment of stack overflow occurs.
  • this application provides a stack overflow detection method, device, electronic device, and storage medium, which comprehensively utilizes the detection of memory access permissions and stack range to determine whether a stack overflow occurs, so that the kernel can be changed without changing the kernel. On the basis of, timely and accurately judge whether there is a stack overflow, and reduce misjudgment.
  • the kernel in this application can be the core computing unit in products such as Microcontroller Unit (MCU), Central Processing Unit/Processor (CPU), etc., used to complete calculations, receive/storage commands, data processing, etc. And so on.
  • Figure 1 is a schematic diagram of the principle of an application scenario of this application.
  • the current access address is obtained, and the stack boundary information is obtained from the stack boundary configuration register.
  • the stack boundary refers to a protected memory space preset in the memory, and the memory space is not allowed to be accessed. If the current access address is within the memory space range corresponding to the above-mentioned stack boundary, that is, the kernel accesses the protected memory space, it is determined to be an illegal access. Then it is further judged that the current access memory address is between the stack top address and the stack bottom address indicated by the stack register.
  • the status of the stack overflow status register can be set to the overflow status, and the overflow status can be stored through the stack overflow status register Download the corresponding context information, and finally send a trigger signal to the interrupt controller, thereby interrupting the memory access of the central processing unit. If the current access memory address is not between the stack top address and the stack bottom address indicated by the stack register, it can be determined as the normal memory illegal access process, and it can be handled as normal memory illegal access without involving stack overflow.
  • the memory protection unit may obtain the top address of the stack from the stack register through the stack register access port exposed by the central processing unit, or obtain the top address of the stack from the stack register through the debug port.
  • the method provided in this embodiment is suitable for MCU/CPU products that need to support stack overflow detection.
  • the number of stack boundary information in the stack boundary configuration register may be multiple. For scenarios with multiple stacks, multiple stack boundary addresses can be set, and there is only one stack bottom address, and the stack bottom address needs to be dynamically set every time the stack is switched. In the OS scenario, the value of the bottom of the stack can be dynamically set to the stack boundary register when the kernel task is switched.
  • the stack boundary is set as a protected address.
  • the kernel access is suspended, and it is judged whether the illegal access memory address is between the stack register value and the current stack bottom; if it is, an interrupt trigger signal is sent to the interrupt controller and the stack overflow status register is set at the same time. Therefore, it is possible to accurately and timely determine whether there is a stack overflow without changing the kernel, and reduce misjudgments.
  • Figure 2 is a schematic diagram of the address space comparison between ordinary illegal access events and illegal access events caused by stack overflow provided by this application.
  • it is generally determined whether the stack overflow occurs by judging whether the current access address of the CPU is the memory space corresponding to the stack boundary.
  • the CPU access to the memory space corresponding to the stack boundary is not necessarily caused by the stack overflow, so a misjudgment of the stack overflow may occur.
  • the CPU writes the start address and the end address of the memory space corresponding to the stack boundary in the stack boundary configuration register in advance; wherein the memory space corresponding to the stack boundary is located at the end of the stack memory . Then, according to the stack boundary information in the stack boundary configuration register (including the stack boundary start address and the stack boundary end address), determine whether the current access memory address is located in the memory space corresponding to the stack boundary, if it is located in the memory space corresponding to the stack boundary , It is determined as an illegal access event. Further, it is judged whether the current access memory address is between the stack top address and the stack bottom address of the stack register.
  • the detection of memory access permissions and stack range is comprehensively used to determine whether a stack overflow occurs, so as to realize timely and accurate judgment whether there is a stack overflow without changing the kernel, and reduce misjudgments.
  • FIG. 3 is a flowchart of a method for detecting stack overflow provided in Embodiment 1 of this application. As shown in FIG. 3, the method in this embodiment may include:
  • S101 Determine whether the current access to the memory address is an illegal access event according to the stack boundary information in the stack boundary configuration register.
  • the method provided in this embodiment is applicable to Microcontroller Unit (MCU) and Central Processing Unit/Processor (CPU) products that need to support stack overflow detection.
  • MCU Microcontroller Unit
  • CPU Central Processing Unit/Processor
  • a CPU is taken as an example for description.
  • the current access address can be obtained through the memory protection unit, and the stack boundary information can be obtained from the stack boundary configuration register.
  • the Memory Protection Unit (MPU) is a kind of hardware equipped in ARM to effectively protect system resources, and it provides a memory area protection function.
  • the stack boundary refers to a protected memory space preset in the memory, and the memory space is not allowed to be accessed.
  • the CPU accesses a protected memory space, it is determined to be an illegal access. If there is no access to the protected memory space, it is a legal access, and the CPU can continue to allow access to the memory information.
  • the stack boundary information can be stored in the stack boundary configuration register.
  • the stack boundary information includes the start address of the stack boundary, the end address of the stack boundary, and the stack bottom address; and the stack bottom address and the end address of the stack boundary are used to define the range of the stack memory.
  • the stack boundary can be set by the CPU, and the stack boundary information can be stored in the stack boundary configuration register.
  • the number of stack boundary information in the stack boundary configuration register may be multiple. For scenarios with multiple stacks, you can set the start address of multiple stack boundaries and the end address of the corresponding stack boundary, but there is only one stack bottom address. Therefore, it is necessary to dynamically set the bottom address of the stack every time the stack is switched. In the OS scenario, the value of the bottom of the stack can be dynamically set to the stack boundary register when the kernel task is switched.
  • the memory protection unit determines whether the currently accessed memory address is an illegal access event, it further determines whether the currently accessed memory address is between the stack top address and the stack bottom address indicated by the stack register.
  • the method of obtaining the top address of the stack may be that the memory protection unit obtains the top address of the stack from the stack register through the stack register access port exposed by the central processing unit, or obtains the top address of the stack from the stack register through the debug port. If the currently accessed memory address is between the top address and the bottom address of the stack indicated by the stack register, it is determined that the stack overflows. If the current access memory address is not between the stack top address and the stack bottom address indicated by the stack register, it can be determined as the normal memory illegal access process, and the normal memory illegal access process can be handled without involving stack overflow.
  • the state of the stack overflow status register is set to the overflow state by the memory protection unit.
  • the stack overflow status register can be used to store the corresponding context information in the overflow state.
  • the stack overflow status register when it is determined that a stack overflow occurs, the stack overflow status register is set to the overflow state and the context information in the overflow state is stored to store the scene information of the stack overflow.
  • the scene information can be retrieved by the CPU, thereby It is convenient for CPU to debug the program.
  • a trigger signal may also be sent to the interrupt controller through the memory protection unit, so that the interrupt controller interrupts the memory access of the central processing unit according to the trigger signal.
  • the memory protection unit sends a trigger signal to the interrupt controller.
  • a non-maskable interrupt request such as NMI (Non Maskable Interrupt) can be sent to the interrupt controller.
  • the interrupt controller after the interrupt controller receives the trigger signal from the memory protection unit, it can interrupt the memory access of the CPU.
  • the stack boundary information in the stack boundary configuration register it is determined whether the currently accessed memory address is an illegal access event; if it is an illegal access event, it is determined whether the currently accessed memory address meets a preset condition; wherein, the preset condition Including: the current access memory address is between the stack top address and the stack bottom address indicated by the stack register; if the preset condition is met, the stack overflow is determined.
  • This application comprehensively uses the detection of memory access permissions and stack range to determine whether a stack overflow occurs, so that it can accurately determine whether there is a stack overflow in a timely manner without changing the kernel, and reduce misjudgments.
  • FIG. 4 is a schematic structural diagram of a stack overflow detection device provided in Embodiment 2 of the application.
  • the stack overflow detection device in this embodiment may include: a memory protection unit 31;
  • the memory protection unit 31 is used to determine whether the currently accessed memory address is an illegal access event; if it is an illegal access event, determine whether the currently accessed memory address meets a preset condition; the preset conditions include: the currently accessed memory address is in the stack register Between the indicated stack top address and stack bottom address; if the preset condition is met, it is determined to be a stack overflow.
  • the memory protection unit 31 is in communication connection with the interrupt controller 32; when it is determined that the stack overflows, the memory protection unit 31 sends a trigger signal to the interrupt controller 32;
  • the interrupt controller 32 is used to interrupt the memory access of the central processing unit according to the trigger signal.
  • the Memory Protection Unit is a kind of hardware equipped in ARM to effectively protect system resources, and it provides a memory area protection function.
  • the stack overflow detection apparatus of this embodiment can execute the technical solution in the method shown in FIG. 3, and for the specific implementation process and technical principle, please refer to the related description in the method shown in FIG. 3, which will not be repeated here.
  • the stack boundary information in the stack boundary configuration register it is determined whether the currently accessed memory address is an illegal access event; if it is an illegal access event, it is determined whether the currently accessed memory address meets a preset condition; wherein, the preset condition Including: the current access memory address is between the stack top address and the stack bottom address indicated by the stack register; if the preset condition is met, the stack overflow is determined.
  • This application comprehensively uses the detection of memory access permissions and stack range to determine whether a stack overflow occurs, so that it can accurately determine whether there is a stack overflow in a timely manner without changing the kernel, and reduce misjudgments.
  • FIG. 5 is a schematic structural diagram of a stack overflow detection device provided in Embodiment 3 of the application. As shown in FIG. 5, the stack overflow detection device of this embodiment may further include: and memory protection on the basis of FIG. 4 The stack register 33 of the unit communication connection, and the memory protection unit 31 obtains the top address of the stack from the stack register 33.
  • the memory protection unit 31 obtains the top address of the stack from the stack register 33 through the stack register access port exposed by the central processing unit; or, obtains the top address of the stack from the stack register 33 through the debug port.
  • it further includes: a stack boundary configuration register 34 communicatively connected with the memory protection unit, and the stack boundary configuration register 34 is used to store stack boundary information.
  • the central processing unit communicates with the stack boundary configuration register 34, and is used to write stack boundary information into the stack boundary configuration register 34;
  • the stack boundary information includes: the start address of the stack boundary and the end of the stack boundary Address, and the address of the bottom of the stack; the bottom address of the stack and the end address of the stack boundary are used to define the range of the stack memory.
  • the memory protection unit 31 is also used to determine whether the current access to the memory address is an illegal access event according to the stack boundary information in the stack boundary configuration register.
  • the stack boundary refers to a protected memory space preset in the memory, and the memory space is not allowed to be accessed.
  • an illegal access event means that the memory address currently accessed is between the start address of the stack boundary and the end address of the stack boundary.
  • a stack overflow status register 35 communicatively connected with the memory protection unit 31;
  • the memory protection unit 31 is also used to set the state of the stack overflow status register 35 to an overflow state when the currently accessed memory address is between the stack top address and the stack bottom address indicated by the stack register.
  • the stack overflow status register 35 is used to store the corresponding context information in the overflow state.
  • the stack overflow detection apparatus of this embodiment can execute the technical solution in the method shown in FIG. 3, and for the specific implementation process and technical principle, please refer to the related description in the method shown in FIG. 3, which will not be repeated here.
  • the stack boundary information in the stack boundary configuration register it is determined whether the currently accessed memory address is an illegal access event; if it is an illegal access event, it is determined whether the currently accessed memory address meets a preset condition; wherein, the preset condition Including: the current access memory address is between the stack top address and the stack bottom address indicated by the stack register; if the preset condition is met, a trigger signal is sent to the interrupt controller; according to the trigger signal, the memory access of the central processing unit is interrupted.
  • This application comprehensively uses the detection of memory access permissions and stack range to determine whether a stack overflow occurs, so that it can accurately determine whether there is a stack overflow in a timely manner without changing the kernel, and reduce misjudgments.
  • FIG. 6 is a schematic structural diagram of the electronic device provided in the fourth embodiment of this application.
  • the electronic device 40 in this embodiment may include a processor 41 and a memory 42.
  • the memory 42 is used to store programs; the memory 42 may include volatile memory (English: volatile memory), such as random-access memory (English: random-access memory, abbreviation: RAM), such as static random-access memory (English: volatile memory) : Static random-access memory, abbreviation: SRAM), double data rate synchronous dynamic random access memory (English: Double Data Rate Synchronous Dynamic Random Access Memory, abbreviation: DDR SDRAM), etc.; memory can also include non-volatile memory (English: non-volatile memory), such as flash memory (English: flash memory).
  • the memory 42 is used to store computer programs (such as application programs and functional modules that implement the above methods), computer instructions, etc., and the above computer programs, computer instructions, etc. may be partitioned and stored in one or more memories 42. In addition, the above-mentioned computer programs, computer instructions, data, etc. can be called by the processor 41.
  • the above-mentioned computer programs, computer instructions, etc. may be partitioned and stored in one or more memories 42.
  • the above-mentioned computer programs, computer instructions, data, etc. can be called by the processor 41.
  • the processor 41 is configured to execute a computer program stored in the memory 42 to implement each step in the method involved in the foregoing embodiment.
  • the processor 41 and the memory 42 may be independent structures, or may be an integrated structure integrated together. When the processor 41 and the memory 42 are independent structures, the memory 42 and the processor 41 may be coupled and connected through the bus 43.
  • the electronic device of this embodiment can execute the technical solution in the method shown in FIG. 3, and for the specific implementation process and technical principle, please refer to the related description in the method shown in FIG. 3, which will not be repeated here.
  • the stack boundary information in the stack boundary configuration register it is determined whether the currently accessed memory address is an illegal access event; if it is an illegal access event, it is determined whether the currently accessed memory address meets a preset condition; wherein, the preset condition Including: the current access memory address is between the stack top address and the stack bottom address indicated by the stack register; if the preset condition is met, the stack overflow is determined.
  • This application comprehensively uses the detection of memory access permissions and stack range to determine whether a stack overflow occurs, so that it can accurately determine whether there is a stack overflow in a timely manner without changing the kernel, and reduce misjudgments.
  • the embodiments of the present application also provide a computer-readable storage medium.
  • the computer-readable storage medium stores computer-executable instructions.
  • the user equipment executes the aforementioned various possibilities. Methods.
  • the computer-readable medium includes a computer storage medium and a communication medium, where the communication medium includes any medium that facilitates the transfer of a computer program from one place to another.
  • the storage medium may be any available medium that can be accessed by a general-purpose or special-purpose computer.
  • An exemplary storage medium is coupled to the processor, so that the processor can read information from the storage medium and write information to the storage medium.
  • the storage medium may also be an integral part of the processor.
  • the processor and the storage medium may be located in an application specific integrated circuit (ASIC).
  • ASIC application specific integrated circuit
  • the application specific integrated circuit may be located in the user equipment.
  • the processor and the storage medium may also exist as discrete components in the communication device.
  • ROM read-only memory
  • RAM random access memory
  • magnetic disks magnetic disks, or optical disks, etc., which can store program code medium.

Abstract

一种栈溢出的检测方法、装置、电子设备及存储介质。该方法，包括：根据栈边界配置寄存器中的栈边界信息，确定当前访问内存地址是否为非法访问事件（S101）；若为非法访问事件，则判断所述当前访问内存地址是否满足预设条件，其中，所述预设条件包括：当前访问内存地址处于栈顶地址和栈底地址之间（S102）；若满足预设条件，则确定为栈溢出（S103）。从而可以在不修改内核的情况下，及时准确地判断出栈溢出异常。

Description

栈溢出的检测方法、装置、电子设备及存储介质 技术领域
本申请涉及计算机技术领域，尤其涉及一种栈溢出的检测方法、装置、电子设备及存储介质。
背景技术
无论是带有操作系统还是不带操作系统，栈溢出都是导致系统不稳定的重要原因之一，因此需要及时地检测是否存在栈溢出的情况。
目前，检测栈溢出的方法主要有两类，1)判断栈寄存器的值是否超过了预设的地址边界；2)以特殊值初始化栈空间，通过判断栈边界初始值是否改变来判断是否有越界事件。
但是，上述方式需要中央处理器能够在运行时，实时地检测栈寄存器的值，当处于操作系统(Operating System，OS)场景下时，由于栈寄存器的值可以是任意值，因此无法准确地判断是否出现栈溢出。而当不处于OS场景下时，又无法实时判断是否出现栈溢出。
发明内容
本申请提供一种栈溢出的检测方法、装置、电子设备及存储介质，可以在不修改内核的情况下，及时准确地判断出栈溢出异常。
第一方面，本申请实施例提供一种栈溢出的检测方法，包括：
根据栈边界配置寄存器中的栈边界信息，确定当前访问内存地址是否为非法访问事件；
若为非法访问事件，则判断所述当前访问内存地址是否满足预设条件；其中，所述预设条件包括：当前访问内存地址处于栈寄存器指示的栈顶地址和栈底地址之间；
若满足预设条件，则确定为栈溢出。
在一种可能的设计中，还包括：
向中断控制器发送触发信号；
根据所述触发信号，中断中央处理器的内存访问。
在一种可能的设计中，还包括：
设置栈边界配置寄存器中的栈边界信息。
在一种可能的设计中，所述设置栈边界配置寄存器中的栈边界信息，包括：
通过中央处理器在所述栈边界配置寄存器中写入所述栈边界信息；其中，所述栈边界信息包括：栈边界的起始地址、栈边界的结束地址，以及栈底地址；所述栈底地址和栈边界的结束地址用于界定栈内存的范围。
在一种可能的设计中，根据栈边界配置寄存器中的栈边界信息，确定当前访问内存地址是否为非法访问事件，包括：
若当前访问内存地址位于所述栈边界的起始地址和所述栈边界的结束地址之间，则确定当前访问地址为非法访问事件。
在一种可能的设计中，还包括：
在当前访问内存地址处于栈寄存器指示的栈顶地址和栈底地址之间时，设置栈溢出状态寄存器的状态为溢出状态。
在一种可能的设计中，还包括：
通过所述栈溢出状态寄存器，存储溢出状态下对应的上下文信息。
第二方面，本申请实施例提供一种栈溢出的检测装置，包括：通信连接的内存保护单元和中断控制器；
内存保护单元，用于确定当前访问内存地址是否为非法访问事件；若为非法访问事件，则判断当前访问内存地址是否满足预设条件；其中，所述预设条件包括：当前访问内存地址处于栈寄存器指示的栈顶地址和栈底地址之间；若满足预设条件，则确定为栈溢出。；
在一种可能的设计中，还包括：与所述内存保护单元通信连接的中断控制器；
所述内存保护单元，还用于：向中断控制器发送触发信号；
中断控制器，用于根据所述触发信号，中断中央处理器的内存访问。
在一种可能的设计中，还包括与所述内存保护单元通信连接的栈寄存器，所述内存保护单元从所述栈寄存器中获取所述栈顶地址。
在一种可能的设计中，所述内存保护单元通过所述中央处理器暴露的栈寄存器访问端口从所述栈寄存器中获取所述栈顶地址；或者，通过调试端口从所述栈寄存器中获取所述栈顶地址。
在一种可能的设计中，还包括：与所述内存保护单元通信连接的栈边界配置寄存器，所述栈边界配置寄存器用于存储栈边界信息；所述栈边界信息包括：栈边界的起始地址、栈边界的结束地址，以及栈底地址；所述栈底地址和栈边界的结束地址用于界定栈内存的范围。
在一种可能的设计中，所述中央处理器与所述栈边界配置寄存器通信连接，用于将所述栈边界信息写入所述栈边界配置寄存器。
在一种可能的设计中，所述内存保护单元，还用于根据所述栈边界配置寄存器中的栈边界信息，确定当前访问内存地址是否为非法访问事件。
在一种可能的设计中，所述非法访问事件是指当前访问内存地址位于所述栈边界的起始地址和所述栈边界的结束地址之间。
在一种可能的设计中，还包括：与所述内存保护单元通信连接的栈溢出状态寄存器；
所述内存保护单元，还用于在当前访问内存地址处于栈寄存器指示的栈顶地址和栈底地址之间时，设置栈溢出状态寄存器的状态为溢出状态。
在一种可能的设计中，所述栈溢出状态寄存器，用于存储溢出状态下对应的上下文信息。
第三方面，本申请实施例提供一种电子设备，包括：处理器和存储器；所述存储器中存储有算法程序所述处理器用于调取所述存储器中的算法程序，执行如第一方面中任一项所述的栈溢出的检测方法。
第四方面，本申请实施例提供一种计算机可读存储介质，包括：程序指令，当其在计算机上运行时，使得计算机执行所述程序指令，以实现如第一方面中任一项所述的栈溢出的检测方法。
本申请提供的栈溢出的检测方法、装置、设备及存储介质，通过根据栈边界配置寄存器中的栈边界信息，确定当前访问内存地址是否为非法访问事件；若为非法访问事件，则判断所述当前访问内存地址是否满足预设条件；其中，所述预设条件包括：当前访问内存地址处于栈寄存器指示的栈顶地址和栈底地址之间；若满足预设条件，则确定为栈溢出。本申请综合利用了内存访问权限和栈范围的检测来判断是否出现栈溢出的情况，从 而可以在不改变内核的基础上，及时准确地判断是否存在栈溢出，减少误判情况。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图进行简单的介绍。显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为本申请一应用场景的原理示意图；
图2为本申请提供的普通非法访问事件和栈溢出引起的非法访问事件的地址空间对比示意图；
图3为本申请实施例一提供的栈溢出的检测方法的流程图；
图4为本申请实施例二提供的栈溢出的检测装置的结构示意图；
图5为本申请实施例三提供的栈溢出的检测装置的结构示意图；
图6为本申请实施例四提供的电子设备的结构示意图。
通过上述附图，已示出本公开明确的实施例，后文中将有更详细的描述。这些附图和文字描述并不是为了通过任何方式限制本公开构思的范围，而是通过参考特定实施例为本领域技术人员说明本公开提到的概念。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整的描述。显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”、“第三”、“第四”等(如果存在)是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本申请的实施例，能够以除了在这里图示或描述的那些以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在 于覆盖不排他的包含。例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
下面以具体的实施例对本申请的技术方案进行详细说明。下面这几个具体的实施例可以相互结合，对于相同或相似的概念或过程可能在某些实施例不再赘述。
以带有操作系统的系统为例，在操作系统的运行过程中，栈溢出是导致系统不稳定的重要原因，因此需要及时地检测是否存在栈溢出的情况。检测栈溢出的方法主要有两类，1)判断栈寄存器的值是否超过了预设的地址边界；2)以特殊值初始化栈空间，通过判断栈边界初始值是否改变来判断是否有越界事件。
但是，上述方式需要中央处理器能够在运行时，实时地检测栈寄存器的值，当处于OS场景下时，由于栈寄存器的值可以是任意值，因此无法保证检测的实时性和准确性，导致出现栈溢出误判的情况。
针对上述技术问题，本申请提供一种栈溢出的检测方法、装置、电子设备及存储介质，综合利用了内存访问权限和栈范围的检测来判断是否出现栈溢出的情况，从而可以在不改变内核的基础上，及时准确地判断是否存在栈溢出，减少误判情况。本申请中的内核可以是微控制单元(Microcontroller Unit，MCU)、中央处理器(Central Processing Unit/Processor，CPU)等产品中的核心运算单元，用来完成计算、接收/存储命令、数据处理等等操作。
图1为本申请一应用场景的原理示意图，如图1所示，当内核对栈进行访问时，获取当前访问地址，并且从栈边界配置寄存器中获取栈边界信息。栈边界是指内存中预先设置的一个受保护的内存空间，该内存空间不允许被访问。若当前访问地址在上述栈边界对应的内存空间范围内，即内核访问的是受保护的内存空间，则确定为非法访问。然后进一步判断当前访问内存地址处于栈寄存器指示的栈顶地址和栈底地址之间。若当前访问内存地址处于栈寄存器指示的栈顶地址和栈底地址之间，则确定发生了栈溢出，此时可以设置栈溢出状态寄存器的状态为溢出状态，并通过栈溢出状态寄存器存储溢出状态下对应的上下文信息，最后再向中断控制器发送触发信号，从而中断中央处理器的内存访问。若当前访问内存地址不处于 栈寄存器指示的栈顶地址和栈底地址之间，则可以确定为普通内存非法访问流程，按普通的内存非法访问处理即可，不涉及栈溢出。
本实施例中，对内存地址的访问是否为非法访问，可以通过内存保护单元实现。若没有访问受保护区域，则为合法访问，内核可以继续访问内存信息。关于栈顶地址的获取方式，可以是内存保护单元通过中央处理器暴露的栈寄存器访问端口从栈寄存器中获取栈顶地址，也可以是通过调试端口从栈寄存器中获取栈顶地址。
需要说明的是，本实施例提供的方法适用于需要支持栈溢出检测的MCU/CPU产品。栈边界配置寄存器中的栈边界信息的数量可以是多个。对于有多个栈的场景，可以设置多个栈边界地址，栈底地址只有1个，需要在每次栈切换时动态设置栈底地址。在OS的场景，可以在内核任务切换时，动态设置栈底的值到栈边界寄存器中。
本实施例，通过利用内存访问权限控制和栈范围检查，基于内存保护单元，设置栈边界为保护地址。当出现内存非法访问时，暂停内核访问，并判断非法访问内存地址是否在栈寄存器值和当前栈底之间；如果是，则向中断控制器发送中断触发信号，同时设置栈溢出状态寄存器。从而可以在不改变内核的基础上，及时准确地判断是否存在栈溢出，减少误判情况。
下面以具体地实施例对本申请的技术方案以及本申请的技术方案如何解决上述技术问题进行详细说明。下面这几个具体的实施例可以相互结合，对于相同或相似的概念或过程可能在某些实施例中不再赘述。下面将结合附图，对本申请的实施例进行描述。
图2为本申请提供的普通非法访问事件和栈溢出引起的非法访问事件的地址空间对比示意图。现有的技术中，一般是通过判断CPU的当前访问地址是否为栈边界对应的内存空间来确定是否出现栈溢出的情况。然而，CPU访问栈边界对应的内存空间并不一定是由栈溢出引起的，因此会出现栈溢出误判的情况。
针对现有技术中存在的问题，本申请中预先通过CPU在栈边界配置寄存器中写入栈边界对应的内存空间的起始地址和结束地址；其中栈边界对应的内存空间位于栈内存的结束位置。然后根据栈边界配置寄存器中的栈边界信息(包含栈边界起始地址和栈边界结束地址)，确定当前访问内存地址是否为位于栈边界对应的内存空间内，若位于栈边界对应的内存空间 内，则确定为非法访问事件。进一步地，判断当前访问内存地址是否位于栈寄存器的栈顶地址和栈底地址之间，若位于栈寄存器的栈顶地址和栈底地址之间，则确定为栈溢出引起的非法访问事件。从而综合利用了内存访问权限和栈范围的检测来判断是否出现栈溢出的情况，实现在不改变内核的基础上，及时准确地判断是否存在栈溢出，减少误判情况。
图3为本申请实施例一提供的栈溢出的检测方法的流程图，如图3所示，本实施例中的方法可以包括：
S101、根据栈边界配置寄存器中的栈边界信息，确定当前访问内存地址是否为非法访问事件。
本实施例提供的方法适用于需要支持栈溢出检测的微控制单元(Microcontroller Unit，MCU)、中央处理器(Central Processing Unit/Processor，CPU)产品。本实施例中，以CPU为例进行说明。当CPU对栈进行访问时，可以通过内存保护单元获取当前访问地址，并且从栈边界配置寄存器中获取栈边界信息。内存保护单元(Memory Protection Unit，MPU)是ARM中配备的有效保护系统资源硬件的一种，提供了内存区域保护功能。栈边界是指内存中预先设置的一个受保护的内存空间，该内存空间不允许被访问。若当前访问地址在上述栈边界中，即CPU访问的是受保护的内存空间，则确定为非法访问。若没有访问受保护的内存空间，则为合法访问，可以继续允许CPU访问内存信息。
本实施例中，可以将栈边界信息保存在栈边界配置寄存器中栈边界信息。其中，栈边界信息包括栈边界的起始地址、栈边界的结束地址，以及栈底地址；而栈底地址和栈边界的结束地址用于界定栈内存的范围。
示例性的，由于CPU与栈边界配置寄存器通信连接。因此，可以通过CPU设置栈边界，并将栈边界信息存入栈边界配置寄存器中。
需要说明的是，栈边界配置寄存器中的栈边界信息的数量可以是多个。对于有多个栈的场景，可以设置多个栈边界的起始地址和对应的栈边界的结束地址，但是栈底地址只有1个。因此，需要在每次栈切换时，动态设置栈底地址。在OS的场景，可以在内核任务切换时，动态设置栈底的值到栈边界寄存器中。
S102、若为非法访问事件，则判断当前访问内存地址是否满足预设条件。
本实施例中，当内存保护单元确定当前访问内存地址为非法访问事件时，则进一步判断当前访问内存地址是否处于栈寄存器指示的栈顶地址和栈底地址之间。栈顶地址的获取方式，可以是内存保护单元通过中央处理器暴露的栈寄存器访问端口从栈寄存器中获取栈顶地址，也可以是通过调试端口从栈寄存器中获取栈顶地址。若当前访问内存地址处于栈寄存器指示的栈顶地址和栈底地址之间，则确定栈溢出。若当前访问内存地址不处于栈寄存器指示的栈顶地址和栈底地址之间，则可以确定为普通内存非法访问流程，按普通的内存非法访问处理即可，不涉及栈溢出。
S103、若满足预设条件，则确定为栈溢出。
本实施例中，若当前访问内存地址处于栈寄存器指示的栈顶地址和栈底地址之间，则通过内存保护单元设置栈溢出状态寄存器的状态为溢出状态。其中，栈溢出状态寄存器可以用于存储溢出状态下对应的上下文信息。
本实施例中，当确定发生栈溢出之后，通过设置栈溢出状态寄存器的状态为溢出状态，并存储溢出状态下的上下文信息来存储栈溢出的现场信息，这些现场信息可以被CPU调取，从而方便CPU进行程序调试。
在执行步骤S101～步骤S103之后，还可以通过内存保护单元向中断控制器发送触发信号，以使得中断控制器根据触发信号，中断中央处理器的内存访问。
本实施例中，若满足预设条件，则内存保护单元向中断控制器发送触发信号。例如，可以向中断控制器发送NMI(Non Maskable Interrupt，不可屏蔽请求)等非屏蔽中断请求。
本实施例中，当中断控制器接收到来自内存保护单元的触发信号之后，可以中断CPU的内存访问。
本实施例，通过根据栈边界配置寄存器中的栈边界信息，确定当前访问内存地址是否为非法访问事件；若为非法访问事件，则判断当前访问内存地址是否满足预设条件；其中，预设条件包括：当前访问内存地址处于栈寄存器指示的栈顶地址和栈底地址之间；若满足预设条件，则确定为栈溢出。本申请综合利用了内存访问权限和栈范围的检测来判断是否出现栈溢出的情况，从而可以在不改变内核的基础上，及时准确地判断是否存在栈溢出，减少误判情况。
图4为本申请实施例二提供的栈溢出的检测装置的结构示意图，如图 4所示，本实施例的栈溢出的检测装置可以包括：内存保护单元31；
内存保护单元31，用于确定当前访问内存地址是否为非法访问事件；若为非法访问事件，则判断当前访问内存地址是否满足预设条件；其中，预设条件包括：当前访问内存地址处于栈寄存器指示的栈顶地址和栈底地址之间；若满足预设条件，则确定为栈溢出。
可选地，该内存保护单元31与中断控制器32通信连接；当确定为栈溢出时，内存保护单元31向中断控制器32发送触发信号；
中断控制器32，用于根据触发信号，中断中央处理器的内存访问。
本实施例中，适用于需要支持栈溢出检测的MCU/CPU产品。内存保护单元(Memory Protection Unit，MPU)是ARM中配备的有效保护系统资源硬件的一种，提供了内存区域保护功能。
本实施例的栈溢出的检测装置，可以执行图3所示方法中的技术方案，其具体实现过程和技术原理参见图3所示方法中的相关描述，此处不再赘述。
本实施例，通过根据栈边界配置寄存器中的栈边界信息，确定当前访问内存地址是否为非法访问事件；若为非法访问事件，则判断当前访问内存地址是否满足预设条件；其中，预设条件包括：当前访问内存地址处于栈寄存器指示的栈顶地址和栈底地址之间；若满足预设条件，则确定为栈溢出。本申请综合利用了内存访问权限和栈范围的检测来判断是否出现栈溢出的情况，从而可以在不改变内核的基础上，及时准确地判断是否存在栈溢出，减少误判情况。
图5为本申请实施例三提供的栈溢出的检测装置的结构示意图，如图5所示，本实施例的栈溢出的检测装置在图4所示的基础上，还可以包括：与内存保护单元通信连接的栈寄存器33，内存保护单元31从栈寄存器33中获取栈顶地址。
在一种可能的设计中，内存保护单元31通过中央处理器暴露的栈寄存器访问端口从栈寄存器33中获取栈顶地址；或者，通过调试端口从栈寄存器33中获取栈顶地址。
在一种可能的设计中，还包括：与内存保护单元通信连接的栈边界配置寄存器34，栈边界配置寄存器34用于存储栈边界信息。
在一种可能的设计中，中央处理器与栈边界配置寄存器34通信连接， 用于将栈边界信息写入栈边界配置寄存器34；栈边界信息包括：栈边界的起始地址、栈边界的结束地址，以及栈底地址；栈底地址和栈边界的结束地址用于界定栈内存的范围。
在一种可能的设计中，内存保护单元31，还用于根据栈边界配置寄存器中的栈边界信息，确定当前访问内存地址是否为非法访问事件。栈边界是指内存中预先设置的一个受保护的内存空间，该内存空间不允许被访问。
在一种可能的设计中，非法访问事件是指当前访问内存地址位于栈边界的起始地址和栈边界的结束地址之间。
在一种可能的设计中，还包括：与内存保护单元31通信连接的栈溢出状态寄存器35；
内存保护单元31，还用于在当前访问内存地址处于栈寄存器指示的栈顶地址和栈底地址之间时，设置栈溢出状态寄存器35的状态为溢出状态。
在一种可能的设计中，栈溢出状态寄存器35，用于存储溢出状态下对应的上下文信息。
本实施例的栈溢出的检测装置，可以执行图3所示方法中的技术方案，其具体实现过程和技术原理参见图3所示方法中的相关描述，此处不再赘述。
本实施例，通过根据栈边界配置寄存器中的栈边界信息，确定当前访问内存地址是否为非法访问事件；若为非法访问事件，则判断当前访问内存地址是否满足预设条件；其中，预设条件包括：当前访问内存地址处于栈寄存器指示的栈顶地址和栈底地址之间；若满足预设条件，则向中断控制器发送触发信号；根据触发信号，中断中央处理器的内存访问。本申请综合利用了内存访问权限和栈范围的检测来判断是否出现栈溢出的情况，从而可以在不改变内核的基础上，及时准确地判断是否存在栈溢出，减少误判情况。
图6为本申请实施例四提供的电子设备的结构示意图，如图6所示，本实施例的电子设备40可以包括：处理器41和存储器42。
存储器42，用于存储程序；存储器42，可以包括易失性存储器(英文：volatile memory)，例如随机存取存储器(英文：random-access memory，缩写：RAM)，如静态随机存取存储器(英文：static random-access memory，缩写：SRAM)，双倍数据率同步动态随机存取存储器(英文：Double Data  Rate Synchronous Dynamic Random Access Memory，缩写：DDR SDRAM)等；存储器也可以包括非易失性存储器(英文：non-volatile memory)，例如快闪存储器(英文：flash memory)。存储器42用于存储计算机程序(如实现上述方法的应用程序、功能模块等)、计算机指令等，上述的计算机程序、计算机指令等可以分区存储在一个或多个存储器42中。并且上述的计算机程序、计算机指令、数据等可以被处理器41调用。
上述的计算机程序、计算机指令等可以分区存储在一个或多个存储器42中。并且上述的计算机程序、计算机指令、数据等可以被处理器41调用。
处理器41，用于执行存储器42存储的计算机程序，以实现上述实施例涉及的方法中的各个步骤。
具体可以参见前面方法实施例中的相关描述。
处理器41和存储器42可以是独立结构，也可以是集成在一起的集成结构。当处理器41和存储器42是独立结构时，存储器42、处理器41可以通过总线43耦合连接。
本实施例的电子设备可以执行图3所示方法中的技术方案，其具体实现过程和技术原理参见图3所示方法中的相关描述，此处不再赘述。
本实施例，通过根据栈边界配置寄存器中的栈边界信息，确定当前访问内存地址是否为非法访问事件；若为非法访问事件，则判断当前访问内存地址是否满足预设条件；其中，预设条件包括：当前访问内存地址处于栈寄存器指示的栈顶地址和栈底地址之间；若满足预设条件，则确定为栈溢出。本申请综合利用了内存访问权限和栈范围的检测来判断是否出现栈溢出的情况，从而可以在不改变内核的基础上，及时准确地判断是否存在栈溢出，减少误判情况。
此外，本申请实施例还提供一种计算机可读存储介质，计算机可读存储介质中存储有计算机执行指令，当用户设备的至少一个处理器执行该计算机执行指令时，用户设备执行上述各种可能的方法。
其中，计算机可读介质包括计算机存储介质和通信介质，其中通信介质包括便于从一个地方向另一个地方传送计算机程序的任何介质。存储介质可以是通用或专用计算机能够存取的任何可用介质。一种示例性的存储介质耦合至处理器，从而使处理器能够从该存储介质读取信息，且可向该存储介质写入信息。当然，存储介质也可以是处理器的组成部分。处理器 和存储介质可以位于应用专用集成电路(ASIC)中。另外，该应用专用集成电路可以位于用户设备中。当然，处理器和存储介质也可以作为分立组件存在于通信设备中。
本领域普通技术人员可以理解：实现上述各方法实施例的全部或部分步骤可以通过程序指令相关的硬件来完成。前述的程序可以存储于一计算机可读取存储介质中。该程序在执行时，执行包括上述各方法实施例的步骤；而前述的存储介质包括：只读存储器(ROM)、随机存取存储器(RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由下面的权利要求书指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求书来限制。

Claims (19)

  1. 一种栈溢出的检测方法，其特征在于，包括：
    根据栈边界配置寄存器中的栈边界信息，确定当前访问内存地址是否为非法访问事件；
    若为非法访问事件，则判断所述当前访问内存地址是否满足预设条件；其中，所述预设条件包括：当前访问内存地址处于栈寄存器指示的栈顶地址和栈底地址之间；
    若满足预设条件，则确定为栈溢出。
  2. 根据权利要求1所述的方法，其特征在于，还包括：
    向中断控制器发送触发信号；
    根据所述触发信号，中断中央处理器的内存访问。
  3. 根据权利要求1所述的方法，其特征在于，还包括：
    设置栈边界配置寄存器中的栈边界信息。
  4. 根据权利要求3所述的方法，其特征在于，所述设置栈边界配置寄存器中的栈边界信息，包括：
    通过中央处理器在所述栈边界配置寄存器中写入所述栈边界信息；其中，所述栈边界信息包括：栈边界的起始地址、栈边界的结束地址，以及栈底地址；所述栈底地址和栈边界的结束地址用于界定栈内存的范围。
  5. 根据权利要求4所述的方法，其特征在于，根据栈边界配置寄存器中的栈边界信息，确定当前访问内存地址是否为非法访问事件，包括：
    若当前访问内存地址位于所述栈边界的起始地址和所述栈边界的结束地址之间，则确定当前访问地址为非法访问事件。
  6. 根据权利要求1-5中任一项所述的方法，其特征在于，还包括：
    在当前访问内存地址处于栈寄存器指示的栈顶地址和栈底地址之间时，设置栈溢出状态寄存器的状态为溢出状态。
  7. 根据权利要求6所述的方法，其特征在于，还包括：
    通过所述栈溢出状态寄存器，存储溢出状态下对应的上下文信息。
  8. 一种栈溢出的检测装置，其特征在于，包括：与中央处理器通信连接的内存保护单元；
    内存保护单元，用于确定所述中央处理器的当前访问内存地址是否为 非法访问事件；若为非法访问事件，则判断当前访问内存地址是否满足预设条件；其中，所述预设条件包括：当前访问内存地址处于栈寄存器指示的栈顶地址和栈底地址之间；若满足预设条件，则确定为栈溢出。
  9. 根据权利要求8所述的装置，其特征在于，还包括：与所述内存保护单元通信连接的中断控制器；
    所述内存保护单元，还用于：向中断控制器发送触发信号；
    中断控制器，用于根据所述触发信号，中断中央处理器的内存访问。
  10. 根据权利要求8所述的装置，其特征在于，还包括与所述内存保护单元通信连接的栈寄存器，所述内存保护单元从所述栈寄存器中获取所述栈顶地址。
  11. 根据权利要求10所述的装置，其特征在于，所述内存保护单元通过所述中央处理器暴露的栈寄存器访问端口从所述栈寄存器中获取所述栈顶地址；或者，通过调试端口从所述栈寄存器中获取所述栈顶地址。
  12. 根据权利要求8所述的装置，其特征在于，还包括：与所述内存保护单元通信连接的栈边界配置寄存器，所述栈边界配置寄存器用于存储栈边界信息；所述栈边界信息包括：栈边界的起始地址、栈边界的结束地址，以及栈底地址；所述栈底地址和栈边界的结束地址用于界定栈内存的范围。
  13. 根据权利要求12所述的装置，其特征在于，所述中央处理器与所述栈边界配置寄存器通信连接，用于将所述栈边界信息写入所述栈边界配置寄存器。
  14. 根据权利要求12所述的装置，其特征在于，所述内存保护单元，还用于根据所述栈边界配置寄存器中的栈边界信息，确定当前访问内存地址是否为非法访问事件。
  15. 根据权利要求14所述的装置，其特征在于，所述非法访问事件是指当前访问内存地址位于所述栈边界的起始地址和所述栈边界的结束地址之间。
  16. 根据权利要求8-15中任一项所述的装置，其特征在于，还包括：与所述内存保护单元通信连接的栈溢出状态寄存器；
    所述内存保护单元，还用于在当前访问内存地址处于栈寄存器指示的栈顶地址和栈底地址之间时，设置栈溢出状态寄存器的状态为溢出状态。
  17. 根据权利要求16所述的装置，其特征在于，所述栈溢出状态寄存器，用于存储溢出状态下对应的上下文信息。
  18. 一种电子设备，其特征在于，包括：处理器和存储器；所述存储器中存储有算法程序，所述处理器用于调取所述存储器中的算法程序，执行如权利要求1-7中任一项所述的栈溢出的检测方法。
  19. 一种计算机可读存储介质，其特征在于，包括：程序指令，当其在计算机上运行时，使得计算机执行所述程序指令，以实现如权利要求1-7中任一项所述的栈溢出的检测方法。
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