WO2021059687A1 - Semiconductor device, method for producing same, and electronic device - Google Patents

Semiconductor device, method for producing same, and electronic device Download PDF

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Publication number
WO2021059687A1
WO2021059687A1 PCT/JP2020/027548 JP2020027548W WO2021059687A1 WO 2021059687 A1 WO2021059687 A1 WO 2021059687A1 JP 2020027548 W JP2020027548 W JP 2020027548W WO 2021059687 A1 WO2021059687 A1 WO 2021059687A1
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region
type
electrode
electrode region
pixel
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PCT/JP2020/027548
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French (fr)
Japanese (ja)
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北野　良昭
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ソニーセミコンダクタソリューションズ株式会社
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Priority to US17/760,744 priority Critical patent/US20220336504A1/en
Publication of WO2021059687A1 publication Critical patent/WO2021059687A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14689—MOS based technologies
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/48—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S17/00
    • G01S7/483—Details of pulse systems
    • G01S7/486—Receivers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/1461—Pixel-elements with integrated switching, control, storage or amplification elements characterised by the photosensitive area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14625—Optical elements or arrangements associated with the device
    • H01L27/14627—Microlenses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1463—Pixel isolation structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14634—Assemblies, i.e. Hybrid structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14636—Interconnect structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
    • H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
    • H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
    • H01L31/107—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier working in avalanche mode, e.g. avalanche photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked

Definitions

  • the present technology (technology according to the present disclosure) is applied to semiconductor devices, their manufacturing methods, and electronic devices, and particularly to semiconductor devices having an avalanche photodiode (APD), a manufacturing method thereof, and electronic devices. It is about effective technology.
  • APD avalanche photodiode
  • This distance image sensor includes a pixel array unit in which a plurality of pixels are arranged in a matrix. The efficiency of the entire device is determined by the pixel size and pixel structure.
  • Patent Document 1 discloses a pixel structure using an APD element as a photoelectric conversion element mounted on a pixel.
  • This pixel structure is provided by forming a pn junction on the upper portion of the semiconductor layer on the first surface side of the pixel forming region, and a p-type first electrode in which an avalanche multiplication region is formed at the interface portion of the pn junction.
  • a region p-type semiconductor region
  • an n-type second electrode region n-type semiconductor region
  • a charge storage region provided around the first electrode region and the second electrode region, and an upper portion of the pixel forming region. It includes a p-type contact region provided electrically connected to the charge storage region.
  • This pixel structure can reduce crosstalk and suppress dark count rate (DCR: Dark Count Rate).
  • distance image sensors are also required to be miniaturized as the electronic devices mounted on them are miniaturized.
  • miniaturization of pixels is useful.
  • the purpose of this technology is to provide a semiconductor device, a manufacturing method thereof, and an electronic device capable of miniaturizing pixels while ensuring device withstand voltage.
  • the semiconductor device is A pixel array unit in which a plurality of pixels having an avalanche photodiode element are arranged in a matrix is provided.
  • Avalanche photodiode elements A pn junction is provided on the first surface side of the first surface and the second surface located on opposite sides of the pixel forming region of the semiconductor layer, and the avalanche is multiplied at the interface portion of the pn junction.
  • An insulating portion provided between the contact region and the second electrode region, Have.
  • a method for manufacturing a semiconductor device is as follows. A step of forming a first conductive type first electrode region on the first surface side of the semiconductor layer and forming a second conductive type second electrode region forming a pn junction with the upper side of the first electrode region. , A step of forming a first conductive type contact region electrically connected to the first electrode region on the first surface side of the semiconductor layer, and A step of forming an insulating portion between the second electrode region and the contact region, and To be equipped.
  • An electronic device includes the semiconductor device and an optical system for forming an image light from a subject on a second surface of the pixel forming region.
  • FIG. 5 is an enlarged cross-sectional view of a main part obtained by enlarging a part of FIG.
  • FIG. 7 It is a process sectional view of the manufacturing method of the distance image sensor which concerns on 1st Embodiment of this technique. It is a process sectional view following FIG. 7 of the manufacturing method of the distance image sensor which concerns on 1st Embodiment of this technique. It is a process sectional view following FIG. 8 of the manufacturing method of the distance image sensor which concerns on 1st Embodiment of this technique. It is a process sectional view following FIG. 9 of the manufacturing method of the distance image sensor which concerns on 1st Embodiment of this technique. It is a process sectional view following FIG. 10 of the manufacturing method of the distance image sensor which concerns on 1st Embodiment of this technique. It is a process sectional view following FIG.
  • FIG. 11 of the manufacturing method of the distance image sensor which concerns on 1st Embodiment of this technique. It is a process sectional view following FIG. 12 of the manufacturing method of the distance image sensor which concerns on 1st Embodiment of this technique. It is a process sectional view following FIG. 13 of the manufacturing method of the distance image sensor which concerns on 1st Embodiment of this technique. It is a process sectional view following FIG. 14 of the manufacturing method of the distance image sensor which concerns on 1st Embodiment of this technique. It is a process sectional view following FIG. 15 of the manufacturing method of the distance image sensor which concerns on 1st Embodiment of this technique. It is a process sectional view following FIG.
  • FIG. 16 of the manufacturing method of the distance image sensor which concerns on 1st Embodiment of this technique. It is a process sectional view following FIG. 17 of the manufacturing method of the distance image sensor which concerns on 1st Embodiment of this technique. It is a process sectional view following FIG. 18 of the manufacturing method of the distance image sensor which concerns on 1st Embodiment of this technique. It is a process sectional view following FIG. 19 of the manufacturing method of the distance image sensor which concerns on 1st Embodiment of this technique. It is a top view which shows the 1st modification. It is a top view which shows the 2nd modification. It is sectional drawing which shows the cross-sectional structure cut at the position of the III-III cutting line of FIG. 22A.
  • the first direction and the second direction orthogonal to each other in the same plane are set to the X direction and the Y direction, respectively, and the first direction and the second direction
  • the third direction orthogonal to each of the second directions is defined as the Z direction.
  • the distance image sensor 1 is mainly composed of a sensor chip 2 having a rectangular shape in a plan view.
  • the sensor chip 2 has a pixel array portion 2A arranged in the center of a rectangle, a peripheral region 2B arranged outside the pixel array portion 2A so as to surround the pixel array portion 2A, and a peripheral region 2B outside the peripheral region 2B. It includes a pad area 2C arranged so as to surround it.
  • the pixel array unit 2A is a light receiving surface that receives light collected by an optical system (not shown). Then, in the pixel array unit 2A, a plurality of pixels 3 are arranged in a matrix in a two-dimensional plane including the X direction and the Y direction.
  • the bias voltage application unit 5 shown in FIG. 2 and other circuit units are arranged in the peripheral region 2B. The bias voltage application unit 5 applies a bias voltage to each of the plurality of pixels 3 arranged in the pixel array unit 2A.
  • a plurality of electrode pads 4 are arranged along each side of the plane of the sensor chip 2. The electrode pad 4 is used when the sensor chip 2 is electrically connected to an external device (not shown).
  • the pixel 3 is complemented with, for example, an APD (Avalanche photodiode) element 6 as a photoelectric conversion element and a quenching resistance element 7 composed of, for example, a p-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor). It is equipped with an inverter 8 made of MOSFET (Complementary MOS).
  • APD Anavalanche photodiode
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • the anode is connected to the bias voltage application unit 5 (see FIG. 2), and the cathode is connected to the source terminal of the quenching resistance element 7.
  • a bias voltage VB is applied to the anode of the APD element 6 from the bias voltage application unit 5.
  • the APD element 6 forms an avalanche multiplication region 23 (see FIG. 6) by applying a large negative voltage to the cathode, and can multiply the electrons generated by the incident of one font.
  • the quenching resistance element 7 is connected in series with the APD element 6, the source terminal is connected to the cathode of the APD element 6, and the drain terminal is connected to a power supply (not shown).
  • An excitation voltage VE is applied from the power source to the drain terminal of the quenching resistance element 7.
  • the quenching resistance element 7 emits the multiplied electrons in the APD element 6 to return the voltage to the initial voltage. Perform (quenting).
  • the cathode voltage of the APD element 6 reaches the negative voltage VBD, the quenching resistance element 7 performs quenching by emitting electrons multiplied by the APD element 6.
  • the input terminal is connected to the cathode of the APD element 6 and the source terminal of the quenching resistance element 7, and the output terminal is connected to a subsequent arithmetic processing unit (not shown).
  • the inverter 8 outputs a light receiving signal based on the electrons multiplied by the APD element 6. More specifically, the inverter 8 shapes the voltage generated by the electrons multiplied by the APD element 6. Then, the inverter 8 outputs a light receiving signal (APD OUT) in which the pulse waveform shown in FIG. 3, for example, is generated starting from the arrival time of one font to the arithmetic processing unit.
  • the arithmetic processing unit performs arithmetic processing for obtaining the distance to the subject based on the timing at which a pulse indicating the arrival time of one font is generated in each received signal, and obtains the distance for each pixel 3. Then, based on those distances, a distance image in which the distances to the subject detected by the plurality of pixels 3 are arranged in a plane is generated.
  • the sensor chip 2 has a laminated structure in which a sensor substrate 10 as a semiconductor layer, a sensor-side wiring layer 30, and a logic-side wiring layer 40 are laminated in this order.
  • a logic circuit board (not shown) is laminated on the logic side wiring layer 40.
  • the bias voltage application unit 5 shown in FIG. 2, the quenching resistance element 7, the inverter 8, and the like are formed on the logic circuit board.
  • the sensor board 10 and the logic circuit board are electrically connected by the sensor side wiring layer 30 and the logic side wiring layer 40, which are wiring layers.
  • the sensor chip 2 is provided with the sensor-side wiring layer 30 facing the sensor board 10, and after providing the logic-side wiring layer 40 with respect to the logic circuit board, the sensor-side wiring layer 30 and the logic-side wiring layer 40.
  • the sensor substrate 10 is formed of, for example, a semiconductor substrate made of single crystal silicon.
  • the concentration of impurities exhibiting p-type (first conductive type) or n-type (second conductive type) is controlled, and the APD element 6 is formed for each pixel 3.
  • the surface facing the lower side of the sensor substrate 10 is a light receiving surface that receives light, and the sensor side wiring layer 30 with respect to the surface opposite to the light receiving surface (the surface facing upward in FIG. 5).
  • An on-chip lens 50 is provided for each pixel 3 on the light receiving surface of the sensor substrate 10.
  • the light receiving surface of the sensor substrate 10 may be referred to as a second surface or a light incident surface, and the surface opposite to the light receiving surface may be referred to as a first surface or a back surface.
  • the second surface side of the sensor substrate 10 may be referred to as an upper portion, and the second surface side may be referred to as a lower portion.
  • the sensor-side wiring layer 30 and the logic-side wiring layer 40 are used for wiring for supplying a voltage applied to the APD element 6 from the bias voltage application unit 5 and for extracting electrons generated by the APD element 6 from the sensor substrate 10. Wiring etc. are formed.
  • the pixel 3 includes a pixel forming region 10a of the sensor substrate 10 and an inter-pixel separation region 15 for partitioning the pixel forming region 10a.
  • the pixel forming region 10a has a rectangular pattern when viewed in a plane toward the first surface (the surface opposite to the light receiving surface) of the sensor substrate 10.
  • a plurality of pixel forming regions 10a are arranged in each of the X direction and the Y direction orthogonal to each other via the inter-pixel separation region 15.
  • the pixel-to-pixel separation region 15 electrically separates the pixel-forming regions 10a adjacent to each other.
  • the inter-pixel separation region 15 has, for example, an STI (Shallow Trench Isolation) structure, and extends from the first surface (main surface) of the sensor substrate 10 in the depth direction (thickness direction).
  • the inter-pixel separation region 15 corresponding to one pixel 3 has a grid-like (mesh-like) plane pattern when viewed in a plane toward the first surface of the sensor substrate 10. ing.
  • the plane pattern of the inter-pixel separation region 15 corresponding to the pixel array portion 2A is a composite plane pattern having a grid-like plane pattern in the rectangular annular plane pattern.
  • Pixel 3 has an APD element 6 as described above.
  • the APD element 6 has an n-type (second conductive type) well region 11 provided in the pixel forming region 10a of the sensor substrate 10 and a pixel forming region of the sensor substrate 10.
  • the APD element 6 has a p-type contact region 26 provided above the pixel forming region 10a of the sensor substrate 10 by being electrically connected to the p-type first electrode region 19, and a p-type contact region 26. It has an insulating portion 25 provided between the surface and the n-type second electrode region 22. Further, the APD element 6 has a p-type charge storage region 12 provided in the pixel forming region 10a of the sensor substrate 10 by being electrically connected to the p-type contact region 26, and an n-type second electrode region. It has an n-shaped contact area 27 provided on the upper part of the 22.
  • the pixel 3 has an APD element 6 and an insulating portion 25 provided between the n-type second electrode region 22 and the p-type contact region 26 of the APD element 6.
  • the first electrode region 19, the n-type second electrode region 22, and the insulating portion 25 are provided in the n-type well region 11.
  • the n-type well region 11 is provided from the first surface (the surface opposite to the light receiving surface) side to the second surface (light receiving surface) side of the sensor substrate 10. It forms an electric field that transfers the electrons generated by the photoelectric conversion of the APD element 6 to the avalanche multiplication region 23.
  • a p-type well region may be used instead of the n-type well region 11.
  • the insulating portion 25 extends in the thickness direction (Z direction) of the pixel forming region 10a of the sensor substrate 10.
  • the p-type first electrode region 19 and the n-type second electrode region 22 forming a pn junction are formed on a second surface side (upper portion) opposite to the first surface side of the pixel forming region 10a of the sensor substrate 10.
  • the first portion 19a of the p-type first electrode region 19 and the first portion 22a of the n-type second electrode region 22 are the first portions on the opposite side from the first surface side in the thickness direction of the pixel formation region 10a.
  • the first portion 22a and the first portion 19a are arranged in this order toward the surface side of 2.
  • the second portion 19b of the p-type first electrode region 19 and the second portion 22b of the n-type second electrode region 22 are the n-type contact region 27 from the insulating portion 25 side in the plane direction of the pixel forming region 10a.
  • the second portion 22b and the second portion 19b are arranged in this order toward the side.
  • the second portion 19b of the p-type first electrode region 19 extends from the first portion 19a to the lower side of the pixel forming region 10a of the insulating portion 25 opposite to the first surface side, and is a p-type contact region. Is reached and is electrically and mechanically connected.
  • the second portion 22b of the n-type second electrode region 22 is terminated immediately below the lower portion of the insulating portion 25.
  • the first portion 22a of the n-type second electrode region 22 is on the upper side of the first portion 19a of the p-type first electrode region 19 with the first portion 19a of the first electrode region 19. It is pn-junctioned.
  • the second portion 22b of the n-type second electrode region 22 is pn-junctioned with the second portion 19b of the first electrode region 19 on the upper side of the second portion 19b of the p-type first electrode region 19.
  • the first portion 19a is composed of the p-type semiconductor region 13 (first semiconductor region), and the second portion 19b is the p-type semiconductor region 18 (p-type semiconductor region 18). It is composed of a third semiconductor region).
  • the semiconductor regions 13 and 18 have substantially the same impurity concentration, and the respective thicknesses are substantially uniform.
  • the first portion 22a is composed of the n-type semiconductor region 14 (second semiconductor region), and the second portion 22b is composed of the n-type semiconductor region 21 (fourth semiconductor region).
  • the semiconductor regions 14 and 21 have substantially the same impurity concentration, and their respective thicknesses are substantially uniform.
  • the avalanche multiplication region 23 is a pn junction between the p-type first electrode region 19 and the n-type second electrode region 22 due to a large negative voltage applied to the p-type contact region 26. It is a high electric field region (depletion layer) formed at the interface portion of the APD element 6, and multipliers the electrons (e ⁇ ) generated by one font incident on the APD element 6.
  • the p-type charge storage region 12 is provided along the wall surface of the inter-pixel separation region 15. Then, in this first embodiment, the charge storage region 12 is provided along the bottom surface of the lower portion on the second surface side of the pixel formation region 10a. That is, the charge storage region 12 is provided so as to surround the well region 11 with a first portion 12a in contact with the side surface of the well region 11 and a second portion 12b in contact with the bottom surface of the well region 11.
  • the p-type charge storage region 12 is composed of, for example, a p-type semiconductor region having a higher impurity concentration than the n-type well region 11 and accumulates holes.
  • the p-type charge storage region 12 is electrically connected to the p-type contact region 26 that functions as an anode, and bias adjustment is possible. As a result, the hole concentration in the p-type charge storage region 12 is strengthened and the pinning is strengthened, so that, for example, the generation of dark current can be suppressed.
  • the p-type contact region 26 surrounds the outer periphery of the well region 11 on the upper surface (first surface) of the pixel forming region 10a of the sensor substrate 10 and has a p-type charge. It is provided so as to overlap the first portion 12a of the storage region 12. That is, in the p-type contact region, the plane pattern when viewed in a plan view is a rectangular annular plane pattern, and the contact with the first portion 12a of the charge storage region 12 over the entire circumference of the annular plane pattern is electrically charged. Is connected.
  • the contact region 26 reduces the ohmic contact resistance with the contact electrode 32 described later and functions as an anode.
  • the p-type contact region 26 is composed of a p-type semiconductor region having a higher impurity concentration than the p-type first electrode region 19 and the p-type charge storage region 12.
  • the n-type contact region 27 is provided in the upper part of the first portion 22a of the first electrode region 22.
  • the n-type contact region 27 reduces the ohmic contact resistance with the contact electrode 31, which will be described later, and functions as a cathode.
  • the n-type contact region 27 is composed of an n-type semiconductor region having a higher impurity concentration than the n-type second electrode region 22.
  • the insulating portion 25 includes a recess 16 recessed from the upper surface (first surface) of the pixel forming region 10a of the sensor substrate 10, and silicon oxide, for example, as an insulator provided in the recess 16. It has an insulating film 24 made of. In this embodiment, the recess 16 is embedded with an insulating film 24.
  • the insulating portion 25 surrounds the first portions 19a and 22a of the p-shaped first electrode region 19 and the second electrode region 22, respectively, and has a planar pattern when viewed in a plan view. It has a square ring pattern.
  • the wall surface (side surface) of the insulating portion 25 in contact with the second electrode region 22 is inclined with respect to the thickness direction of the sensor substrate 10.
  • the wall surface in contact with the second electrode region 22 of the insulating film 24 embedded in the recess 16 in other words, the wall surface on the second electrode region 22 side of the island region partitioned by the recess 16, in other words, the sensor.
  • the wall surface on the second electrode region 22 side in the recess 16 of the substrate 10 is inclined with respect to the Z direction orthogonal to the second surface of the sensor substrate 10.
  • the p-type semiconductor region 18 has a thickness from the inner surface to the inside in the recess 16 of the pixel forming region 10a of the sensor substrate 10 and is integrated with the p-type semiconductor region 13. Is electrically connected.
  • the n-type semiconductor region 21 has a thickness from the inner surface to the inside in the recess 16 of the pixel forming region 10a of the sensor substrate 10, and is integrated with the n-type semiconductor region 14 and electrically connected. At the same time, it is pn-junctioned with the upper side of the p-type semiconductor region 18.
  • the sensor-side wiring layer 30 is provided with contact electrodes 31, 32, metal wirings 33, 34, contact electrodes 35, 36, and metal pads 37, 38.
  • the contact electrode 31 electrically connects the n-type contact region 27 and the metal wiring 33
  • the contact electrode 32 electrically connects the p-type contact region 26 and the metal wiring 34.
  • the metal wiring 33 is formed wider than the avalanche multiplication region 23 so as to cover at least the avalanche multiplication region 23. Then, the metal wiring 33 reflects the light transmitted through the APD element 6 to the APD element 6.
  • the metal wiring 34 is formed so as to surround the outer circumference of the metal wiring 33 and overlap with the p-shaped contact region 26.
  • the contact electrode 35 electrically connects the metal wiring 33 and the metal pad 37
  • the contact electrode 36 electrically connects the metal wiring 34 and the metal pad 38.
  • the metal pads 37 and 38 are electrically and mechanically connected to the metal pads 47 and 48 provided on the logic side wiring layer 40 by metal-to-metal joints, respectively.
  • the logic side wiring layer 40 is provided with electrode pads 41, 42, insulating layers 43, contact electrodes 44, 45, and metal pads 47, 48.
  • the electrode pads 41 and 42 are connected to logic circuit boards (not shown), respectively, and the insulating layer 43 insulates the electrode pads 41 and the electrode pads 42 from each other.
  • the contact electrode 44 electrically connects the electrode pad 41 and the metal pad 47
  • the contact electrode 45 electrically connects the electrode pad 42 and the metal pad 48.
  • the metal pad 37 is joined to the metal pad 47
  • the metal pad 38 is joined to the metal pad 48.
  • the electrode pad 41 is n-type via the contact electrode 44, the metal pad 47, the metal pad 37, the contact electrode 35, the metal wiring 33, the contact electrode 31, and the n-type contact region 27. It is electrically connected to the second electrode region 22. Therefore, in the pixel 3, a large negative voltage applied to the n-type second electrode region 22 can be supplied from the logic circuit board to the electrode pad 41.
  • the electrode pad 42 is electrically connected to the p-type first electrode region 19 via the contact electrode 45, the metal pad 48, the metal pad 38, the contact electrode 36, the metal wiring 34, the contact electrode 32 and the n-type contact region 27. Is connected. Therefore, in the pixel 3, the anode of the APD element 6 electrically connected to the p-type charge storage region 12 is electrically connected to the electrode pad 42, so that the p-type charge is accumulated via the electrode pad 42. Bias adjustment for the region 12 can be made possible.
  • the pixel 3 of the distance image sensor 1 has a pn junction, and a p-type first electrode having an avalanche multiplication region 23 formed at an interface portion of the pn junction.
  • a region 19 and an n-type second electrode region 22 and a p-type contact region 26 functioning as an anode are provided on the upper portion (first surface side) of the pixel forming region 10a of the sensor substrate 10.
  • An insulating portion 25 is provided between the p-type contact region 26 and the n-type second electrode region 22.
  • the distance image sensor 1 of the first embodiment even if the p-type contact region 26 and the n-type second electrode region 22 approach each other as the pixel 3 becomes finer, in other words, the p-type Even if the distance between the contact region 26 and the n-type second electrode region 22 is shortened, the device withstand voltage between the p-type contact region 26 and the n-type second electrode region 22 is maintained by the insulating portion 25. Can be secured. As a result, the pixel 3 can be miniaturized while ensuring the device withstand voltage between the p-type contact region 26 and the n-type second electrode region 22. As a result, the distance image sensor 1 can be miniaturized.
  • the p-type first electrode region 19 and the n-type second electrode region 22 in which the avalanche multiplication region 23 is formed at the pn junction interface are the upper surfaces of the pixel formation region 10a of the sensor substrate 10.
  • the n-type second electrode region 22 (n-type semiconductor region 14) and the p-type first electrode region 19 (p-type semiconductor region 13) are arranged in this order from the first surface) in the depth direction.
  • the first portions 19a and 22a are formed, and the second portions 19b and 22b extend from the first portions 19a and 22a along the wall surface of the insulating portion 25 in the depth direction of the insulating portion 25.
  • the surface areas of the first portions 19a and 22a of the p-type first electrode region 19 and the n-type second electrode region 22 as the pixel 3 becomes finer. Since the surface area of the second portions 19b and 22b can be increased even if the surface area is reduced, the avalanche increase formed at the pn junction interface between the p-type first electrode region 19 and the n-type second electrode region 22.
  • the pixel 3 can be miniaturized while ensuring the surface area (total area) of the double region 23. As a result, the distance image sensor 1 can be miniaturized. It is also possible to increase the amplification factor to suppress a decrease in sensitivity and high child detection efficiency.
  • the wall surface of the insulating portion 25 in contact with the n-type second electrode region 22 is inclined with respect to the thickness direction (Z direction) of the sensor substrate 10. Therefore, according to the distance image sensor 1 of the first embodiment, p is compared with the case where the wall surface in contact with the second electrode region 22 of the insulating portion 25 is parallel to the thickness direction (Z direction) of the sensor substrate 10.
  • the surface areas of the second portions 19b and 22b of the first electrode region 19 of the mold and the second electrode region 22 of the n mold can be increased.
  • the surface area (total area) of the avalanche multiplication region 23 formed at the pn junction interface between the p-type first electrode region 19 and the n-type second electrode region 22 is further secured, and the pixel 3 It can be miniaturized.
  • the sensor substrate 10 made of single crystal silicon is prepared.
  • an n-type well region 11 is formed on the entire surface including the upper portion of the pixel forming region 10a of the sensor substrate 10.
  • the well region 11 is formed by injecting, for example, phosphorus (P) ions or arsenic (As) ions as n-type impurity ions into the upper part of the sensor substrate 10 and then performing a heat treatment to activate the injected impurity ions. It is formed.
  • a p-type charge storage region 12 surrounding the side surface and the bottom surface of the well region 11 is formed for each pixel formation region 10a of the sensor substrate 10.
  • impurity ions for forming the first portion 12a in contact with the side surface of the well region 11 are selectively injected into the pixel forming region 10a of the sensor substrate 10, and the well region 11 is formed.
  • Impurity ions for forming the second portion 12b in contact with the bottom portion are selectively injected into the pixel forming region 10a of the sensor substrate 10.
  • the p-type charge storage region 12 is formed by performing a heat treatment for activating the impurity ions injected into the pixel forming region 10a.
  • the impurity ion for example, a boron (B) ion or a boron difluoride (BF2) ion exhibiting a p-type is used.
  • the p-type semiconductor region 13 is located above the well region 11 which is the upper portion of the pixel forming region 10a of the sensor substrate 10 on the first surface side and is surrounded by the charge storage region 12.
  • an n-type semiconductor region 14 forming a pn junction with the upper side of the p-type semiconductor region 13 is formed.
  • impurity ions exhibiting p-type are selectively injected into the upper part of the well region 11, and impurity ions exhibiting n-type are injected into the upper part of the well region 11.
  • the p-type semiconductor region 13 and the n-type semiconductor region 14 are formed by performing a heat treatment for activating the impurity ions injected into the well region 11.
  • the impurity ion exhibiting p-type for example, B ion or BF2 ion is used.
  • As the impurity ion exhibiting n-type for example, As ion or P ion is used. Impurity ions exhibiting p-type are injected deeper than impurity ions exhibiting n-type.
  • the p-type semiconductor region 13 constitutes the first portion 19a of the p-type first electrode region 19, and the n-type semiconductor region 14 constitutes the first portion 22a of the n-type second electrode region 22.
  • the p-type semiconductor region 13 and the n-type semiconductor region 14 are arranged in this order from the upper surface (first surface) of the pixel forming region 10a of the sensor substrate 10 in the depth direction to form a pn junction.
  • an inter-pixel separation region 15 that electrically separates the pixel formation regions 10a is formed on the upper part of the sensor substrate 10.
  • the pixel forming region 10a is surrounded by a pixel-to-pixel separation region 15 and is partitioned.
  • the inter-pixel separation region 15 forms a separation groove extending in the depth direction from the first surface (main surface) of the sensor substrate 10 by using, for example, a well-known photolithography technique and anisotropic dry etching technique, and then the inter-pixel separation region 15 is formed. It is formed by selectively embedding an insulating film in the separation groove.
  • a silicon oxide film is formed on the entire surface of the sensor substrate 10 including the inside of the separation groove by the CVD (Chemical Vapor Deposition) method, and then on the first surface of the sensor substrate 10. This is performed by selectively removing the insulating film of the above by the etch back method or the CMP (Chemical Mechanical Polishing) method.
  • CVD Chemical Vapor Deposition
  • CMP Chemical Mechanical Polishing
  • a recess 16 extending from the upper surface of the pixel forming region 10a of the sensor substrate 10 in the depth direction is formed.
  • the recess 16 is formed by using a well-known photolithography technique and a crystal anisotropic etching technique that depends on the crystal axis of the sensor substrate, so that the wall surface in the recess 16 of the sensor substrate 10 is formed in the thickness direction of the sensor substrate 10 ( It can be tilted with respect to (Z direction).
  • the recess 16 is formed with a rectangular annular plane pattern when viewed in a plane so that the central portion of the pixel formation region 10a of the sensor substrate 10 is an island region.
  • a polycrystalline silicon film 17 as a first impurity iontophoresis material is formed on the entire surface of the sensor substrate 10 including the inside of the recess 16 by a CVD method.
  • Impurity ions exhibiting p-type are injected into the polycrystalline silicon film 17 during or after deposition.
  • the impurities exhibiting the p-type for example, boron ion or boron difluoride ion is used.
  • the polycrystalline silicon film 17 is formed along the inner surface including the wall surface and the bottom surface in the recess 16 of the sensor substrate 10.
  • heat treatment is performed to diffuse the impurity ions of the polycrystalline silicon film 17 from the recess 16 of the sensor substrate 10 into the sensor substrate 10, and as shown in FIG. 13, the wall surface and the bottom surface in the recess 16 of the sensor substrate 10 are subjected to heat treatment.
  • a p-type semiconductor region 18 is formed on the first surface of the sensor substrate 10.
  • the p-type semiconductor region 18 is integrally connected to the p-type semiconductor region 13 to form a second portion 19b of the p-type first electrode region 19. Since the p-type semiconductor region 18 is formed by solid-phase diffusion (drive-in diffusion) of impurity ions from the polycrystalline silicon film 17 to the sensor substrate 10, it is formed with a uniform thickness.
  • the p-type semiconductor region 18 is formed along the inner surface including the wall surface and the bottom surface in the recess 16 of the sensor substrate 10.
  • the p-type first electrode region 19 in which the first portion 19a composed of the p-type semiconductor region 13 and the second portion 19b composed of the p-type semiconductor region 18 are integrated is formed.
  • the polycrystalline silicon film 17 is removed.
  • a polycrystalline silicon film 20 as a second impurity iontophoresis material is formed on the entire surface of the sensor substrate 10 including the inside of the recess 16 by a CVD method.
  • the polycrystalline silicon film 20 is injected with impurity ions (for example, P ions or As ions) that exhibit n-type during or after deposition.
  • the polycrystalline silicon film 20 is formed along the inner surface including the wall surface and the bottom surface in the recess 16 of the sensor substrate 10.
  • the wall surface on the side opposite to the n-type semiconductor region 14 side in the recess 16 of the sensor substrate 10 and The polycrystalline silicon film 20 covering the upper surface is selectively removed.
  • the polycrystalline silicon film 20 covers the wall surface on the semiconductor region 14 side and the semiconductor region 14 in the recess 16 of the sensor substrate 10 and terminates on the bottom surface in the recess 16.
  • heat treatment is performed to diffuse the impurity ions of the polycrystalline silicon film 20 from the recess 16 of the sensor substrate 10 into the sensor substrate 10, and as shown in FIG. 17, the semiconductor region 14 side in the recess 16 of the sensor substrate 10 is subjected to heat treatment.
  • the n-type semiconductor region 21 is selectively formed on the wall surface and the bottom surface of the surface.
  • the n-type semiconductor region 21 is integrally formed with the n-type semiconductor region 14, and is pn-junctioned to the upper side of the p-type semiconductor region 18.
  • the n-type semiconductor region 21 constitutes a second portion 22b of the n-type second electrode region 22.
  • the n-type semiconductor region 21 is formed by solid-phase diffusion (drive-in diffusion) of impurity ions from the polycrystalline silicon film 20 to the sensor substrate 10, it is formed with a uniform thickness.
  • the first portion 22a composed of the n-type semiconductor region 14 and the second portion 22b composed of the n-type semiconductor region 21 are integrated, and the second portion 22b is the p-type first electrode region 19.
  • An n-type second electrode region 22 pn-junctioned with the upper side of the second portion 19b of the above is formed.
  • an insulating film 24 is embedded as an insulator in the recess 16 of the sensor substrate 10.
  • an insulating film made of, for example, a silicon oxide film is formed on the entire surface of the first surface of the sensor substrate 10 including the recess 16 by a CVD method, and then on the second surface of the sensor substrate 10. This is done by selectively removing the insulating film of the above by the etchback method or the CMP method.
  • an insulating portion 25 including a recess 16 recessed from the upper surface of the sensor substrate 10 and an insulating film 24 as an insulator provided in the recess 16 is formed.
  • a p-type contact region 26 is formed on the charge storage region 12 which is the upper portion of the sensor substrate 10 and is connected to the charge storage region 12, and is also the upper portion of the sensor substrate 10.
  • An n-type contact region 27 is formed above the first portion 22a (n-type semiconductor region 14) of the n-type second electrode region 22.
  • the p-type contact region 26 selectively injects p-type impurity ions (for example, B ions or BF2 ions) into the upper part between the inter-pixel separation region 15 and the insulating portion 25 of the sensor substrate 10, and then selectively injects them. It is formed by performing a heat treatment that activates the injected impurity ions.
  • an impurity ion exhibiting n-type (for example, P ion or As ion) is selectively injected into the upper part of the n-type semiconductor region 14, and then the injected impurity ion is activated. It is formed by subjecting it to heat treatment. By this step, the APD element 6 is formed in the pixel forming region 10a of the sensor substrate 10.
  • the sensor-side wiring layer 30 is provided on the second surface of the sensor board 10, the logic-side wiring layer 40 is provided on the logic circuit board, and then the sensor-side wiring layer 30 and the logic-side wiring layer 40 are provided on the joint surface.
  • the second surface of the sensor substrate 10 is ground by CMP or the like until the inter-pixel separation region 15 is exposed to reduce the thickness of the sensor substrate 10.
  • an on-chip lens 50 is provided on the second surface of the sensor substrate 10.
  • the insulating portion 25 is formed between the n-type second electrode region 22 and the p-type contact region 26, so that the n-type second electrode region 22 is formed. It is possible to manufacture the distance image sensor 1 in which the pixel 3 is miniaturized while ensuring the device withstand voltage between the electrode region 22 and the p-type contact region 26.
  • the p-type first electrode region 19 and the n-type second electrode region 22 forming a pn junction are formed on the first surface of the sensor substrate 10. Since it is formed in the two-dimensional plane parallel to and in the depth direction of the sensor substrate 10, the avalanche multiplication region formed at the pn junction interface between the p-type first electrode region 19 and the n-type second electrode region 22. It is possible to manufacture the distance image sensor 1 in which the pixels 3 are miniaturized while securing the surface area (total area) of 23.
  • the second portions 19a and 22b of the p-type first electrode region 19 and the n-type second electrode region 22 forming a pn junction respectively. Is formed on the wall surface in the recess 16 of the sensor substrate 10 by solid-phase diffusion from the impurity ion-introduced material, so that each of the p-type first electrode region 19 and the n-type second electrode region 22 forming a pn junction is formed.
  • the second portions 19b and 22b can be formed with a uniform thickness in the depth direction from the wall surface.
  • the second portion 22b of the n-type second electrode region 22 is terminated immediately below the lower portion of the insulating portion 25 .
  • the present technology is not limited to the first embodiment.
  • the second portion 22b of the n-type second electrode region 22 may be terminated inside the lower portion of the insulating portion 25 (n-type contact region 27 side), or may be terminated with the p-type contact region 26. As long as there is no joint leakage between them, it may be terminated on the outside of the lower part of the insulating portion 25 (on the side of the p-type contact region 26).
  • the second portion 22b of the n-type second electrode region 22 is terminated directly below the lower portion of the insulating portion 25 as in the first embodiment described above.
  • the insulating film 24 is used as an insulator in the recess 16 of the insulating portion 25 has been described.
  • the present technology is not limited to the insulating film 24.
  • the recess 16 may be filled with air, an inert gas, or the like as an insulator.
  • the plane pattern of the insulating portion 25 is formed by a rectangular annular plane pattern.
  • the present technology is not limited to this rectangular cyclic pattern.
  • the plane pattern of the insulating portion 25 may be a circular annular plane pattern.
  • the plane pattern of the insulating portion 25 may be a composite plane pattern having a grid pattern in a rectangular annular pattern.
  • the junction area of the pn junction formed by the p-type first electrode region 19 and the n-type second electrode region 22 is increased as compared with the first embodiment described above. can do.
  • the surface area of the avalanche multiplication region 23 formed at the pn junction interface between the p-type first electrode region 19 and the n-type second electrode region 22 can be increased.
  • the plane pattern of the insulating portion 25 may be a composite plane pattern having a grid pattern in a circular annular pattern. Also in the composite pattern of the third modification, as in the composite plane pattern of the second modification, the p-type first electrode region 19 and the n-type second electrode region are compared with the above-described first embodiment. The junction area of the pn junction formed by 22 can be increased. As a result, the surface area of the avalanche multiplication region 23 formed at the pn junction interface between the p-type first electrode region 19 and the n-type second electrode region 22 can be increased.
  • the first portion 22a (n-type semiconductor region 14) of the n-type second electrode region 22 is 1.
  • a plurality of pixels are individually scattered in the pixel 3 while being surrounded by the insulating portions 25, but are electrically connected to each other via the second portion 22b. Therefore, the n-type contact region 27 may be provided in at least one first portion 22a of the plurality of first portions 22a, as shown in FIGS. 22A, 22B, and 23. Although not shown, it may be provided in all the first portions 22a.
  • the plane pattern of the p-type contact region 26 is formed by a rectangular cyclic plane pattern.
  • the present technology is not limited to this rectangular annular plane pattern.
  • the plane pattern of the p-type contact region 26 is made into a dot plane pattern individually scattered around the insulating portion 25 in one pixel 3. Also, although not shown, a single dot plane pattern may be used.
  • the electric field is concentrated in the vicinity of the p-type contact region 26 that functions as an anode. Therefore, in order to secure the device withstand voltage between the p-type contact region 26 and the n-type second electrode region 22, at least between the p-type contact region 26 and the n-type second electrode region 22.
  • the insulating portion 25 may be provided. Therefore, when the plane pattern of the p-type contact region 26 is a rectangular annular plane pattern as in the first embodiment described above, the plane pattern of the insulating portion 25 is matched with the plane pattern of the p-type contact region 26. It is preferable to use a rectangular or circular annular plane pattern.
  • the plane pattern of the insulating portion 25 does not necessarily have to be an annular plane pattern.
  • the insulating portion 25 since it is sufficient that the insulating portion 25 is provided between at least the p-type contact region 26 where the electric field is concentrated and the n-type second electrode region 22, the p-type contact region 26 and the n-type second electrode region 22 need to be provided.
  • the plane pattern of the insulating portion 25 in one pixel 3 may have any shape as long as a bonding leak does not occur between the two electrode regions 22.
  • a plane pattern such as a straight line, a C-shape, or an L-shape may be used.
  • the distance image sensor according to the second embodiment of the present technology has substantially the same configuration as the distance image sensor 1 according to the first embodiment described above, and has a different pixel configuration.
  • the pixel 3 of the first embodiment has a p-type first electrode region 19 and an n-type second electrode region 22 and p.
  • the structure is provided with the contact region 26 of the mold.
  • the p-type first electrode region 19 and the n-type second electrode region 22 are provided above the pixel forming region 10a of the sensor substrate 10, and the pixels of the sensor substrate 10 are provided.
  • the structure is such that a p-type contact region 26 is provided below the formation region 10a.
  • Other configurations are the same as those in the first embodiment.
  • the device withstand voltage between the p-type contact region 26 and the n-type second electrode region 22 is similar to the distance image sensor 1 according to the first embodiment described above.
  • the pixel 3A can be miniaturized while ensuring the above. Further, the pixel 3A is miniaturized while ensuring the surface area (total area) of the avalanche multiplication region 23 formed at the pn junction interface between the p-type first electrode region 19 and the n-type second electrode region 22. Can be planned.
  • the distance image device 201 as an electronic device includes an optical system 202, a sensor chip 2, an image processing circuit 203, a monitor 204, and a memory 205.
  • the distance image device 201 acquires a distance image according to the distance to the subject by receiving light (modulated light or pulsed light) that is projected from the light source device 211 toward the subject and reflected on the surface of the subject. can do.
  • the optical system 202 is configured to have one or a plurality of lenses, guides the image light (incident light) from the subject to the sensor chip 2, and forms an image on the light receiving surface (sensor unit) of the sensor chip 2.
  • the sensor chip 2 of each of the above-described embodiments is applied, and a distance signal indicating a distance obtained from a light receiving signal (APD OUT) output from the sensor chip 2 is supplied to the image processing circuit 203.
  • the image processing circuit 203 performs image processing for constructing a distance image based on the distance signal supplied from the sensor chip 2, and the distance image (image data) obtained by the image processing is supplied to the monitor 204 and displayed. Or it is supplied to the memory 205 and stored (recorded).
  • the distance image device 201 configured in this way, by applying the sensor chip 2 of the above-described embodiment, the distance to the subject is calculated based only on the received signal from the highly stable pixel 3, and the accuracy is improved. It is possible to generate a high-distance image. That is, the distance image device 201 can acquire a more accurate distance image.
  • the sensor chip 2 (image sensor) described above can be used in various cases for sensing light such as visible light, infrared light, ultraviolet light, and X-ray, as described below.
  • ⁇ For safe driving such as automatic stop, recognition of the driver's condition, etc.
  • Devices and user gestures used for traffic such as in-vehicle sensors that photograph the rear, surroundings, and interior of vehicles, surveillance cameras that monitor traveling vehicles and roads, and distance measurement sensors that measure distance between vehicles.
  • Devices and endoscopes used in home appliances such as TVs, refrigerators, and air conditioners, and devices that take blood vessels by receiving infrared light, etc., in order to take pictures and operate the equipment according to the gesture.
  • Equipment used for medical and healthcare surveillance cameras for crime prevention, cameras for person authentication, etc., equipment used for security, skin measuring instruments for taking pictures of the skin, and taking pictures of the scalp
  • Equipment used for beauty such as microscopes, action cameras and wearable cameras for sports applications, equipment used for sports, cameras for monitoring the condition of fields and crops, etc.
  • Equipment used for agriculture such as microscopes, action cameras and wearable cameras for sports applications, equipment used for sports, cameras for monitoring the condition of fields and crops, etc.
  • Equipment used for agriculture Equipment used for agriculture
  • the present technology may have the following configuration.
  • a pixel array unit in which a plurality of pixels having an avalanche photodiode element are arranged in a matrix is provided.
  • the avalanche photodiode element is Avalanche is provided on the first surface side of the first surface and the second surface located on opposite sides of the pixel forming region of the semiconductor layer by forming a pn junction, and at the interface portion of the pn junction.
  • a first conductive type contact region provided on the first surface side of the pixel forming region by being electrically connected to the first electrode region.
  • An insulating portion provided between the contact region and the second electrode region Semiconductor device with.
  • the insulating portion extends from the first surface of the pixel forming region toward the second surface side.
  • the first electrode region and the second electrode region are A first portion of the pixel forming region arranged from the first surface side toward the second surface side, and A second portion extending from the first portion along the insulating portion, The semiconductor device according to (1) above.
  • (3) The second portion of the first electrode region reaches the contact region from the first portion of the first electrode region beyond the second surface side of the pixel forming region of the insulating portion.
  • (14) A step of forming a first conductive type first electrode region on the first surface side of the semiconductor layer and forming a second conductive type second electrode region forming a pn junction with the first electrode region.
  • An electronic device comprising the semiconductor device according to any one of (1) to (13) above, and an optical system for forming an image light from a subject on the second surface of the pixel forming region.
  • p-type semiconductor region (third semiconductor region) 19 ... p-type first electrode region 19a ... first part 19b ... second part 20 ... polycrystalline silicon film (second impurity diffusing material) 21 ... n-type semiconductor region (third semiconductor region) 22 ... n-type second electrode region 22a ... first part 22b ... second part 23 ... avalanche multiplication region 24 ... insulating film (insulator) 25 ... Insulation part 26 ... P-type contact area 27 ... n-type contact area 30 ... Sensor side wiring layer 31, 32 ... Contact electrode 33, 34 ... Metal wiring 35, 36 ... Contact electrode 37, 38 ... Metal pad 40 ... Logic side wiring layer 41, 42 ... Electrode pad 43 ... Insulation layer 44, 45 ... Contact electrode 47, 48 ... Metal pad 50 ... On-chip lens

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Abstract

The present invention provides a semiconductor device which enables miniaturization of pixels, while ensuring the withstand voltage of the device. A semiconductor device according to the present invention is provided with a pixel array part where a plurality of pixels each having an avalanche photodiode element are arranged in a matrix form; and the avalanche photodiode element is provided so as to form a pn junction on a first surface side of a pixel formation region of a semiconductor layer. With respect to this semiconductor device, the avalanche photodiode element comprises: a first electrode region of a first conductivity type and a second electrode region of a second conductivity type at the interface part of the pn junction, said electrode regions being provided with avalanche multiplication regions; a contact region of the first conductivity type on the first surface side of the pixel formation region, said contact region being electrically connected to the first electrode region; and an insulation part which is provided between the contact region and the second electrode region.

Description

半導体装置及びその製造方法、並びに電子機器Semiconductor devices, their manufacturing methods, and electronic devices
　本技術（本開示に係る技術）は、半導体装置及びその製造方法、並びに電子機器に関し、特に、アバランシェフォトダイオード（ＡＰＤ：Ａvalanche Ｐhoto Ｄiode）を有する半導体装置及びその製造方法、並びに電子機器に適用して有効な技術に関するものである。 The present technology (technology according to the present disclosure) is applied to semiconductor devices, their manufacturing methods, and electronic devices, and particularly to semiconductor devices having an avalanche photodiode (APD), a manufacturing method thereof, and electronic devices. It is about effective technology.
　半導体装置として、近年、ＴｏＦ（Time of Flight）法により距離計測を行う距離画像センサ（固体撮像装置）が注目されている。この距離画像センサは、複数の画素が行列状に配置された画素アレイ部を備えている。そして、画素の寸法や画素構造によってデバイス全体の効率が決まる。 As a semiconductor device, a distance image sensor (solid-state image sensor) that measures a distance by the ToF (Time of Flight) method has been attracting attention in recent years. This distance image sensor includes a pixel array unit in which a plurality of pixels are arranged in a matrix. The efficiency of the entire device is determined by the pixel size and pixel structure.
　特許文献１には、画素に搭載される光電変換素子としてＡＰＤ素子を用いた画素構造が開示されている。この画素構造は、半導体層の画素形成領域の第１の面側である上部にｐｎ接合をなして設けられ、かつｐｎ接合の界面部にアバランシェ増倍領域が形成されるｐ型の第１電極領域（ｐ型半導体領域）及びｎ型の第２電極領域（ｎ型半導体領域）と、この第１電極領域及び第２電極領域の周囲に設けられた電荷蓄積領域と、画素形成領域の上部に電荷蓄積領域と電気的に接続して設けられたｐ型のコンタクト領域とを含む。この画素構造は、クロストークを低減し、ダークカウントレート（ＤＣＲ：Dark Count Rate（暗電流率））を抑制することが可能である。 Patent Document 1 discloses a pixel structure using an APD element as a photoelectric conversion element mounted on a pixel. This pixel structure is provided by forming a pn junction on the upper portion of the semiconductor layer on the first surface side of the pixel forming region, and a p-type first electrode in which an avalanche multiplication region is formed at the interface portion of the pn junction. A region (p-type semiconductor region), an n-type second electrode region (n-type semiconductor region), a charge storage region provided around the first electrode region and the second electrode region, and an upper portion of the pixel forming region. It includes a p-type contact region provided electrically connected to the charge storage region. This pixel structure can reduce crosstalk and suppress dark count rate (DCR: Dark Count Rate).
特開２０１８－２０１００５号公報JP-A-2018-201005
　ところで、距離画像センサにおいても、搭載される電子機器の小型化に伴い小型化が要求されている。距離画像センサの小型化を図るためには、画素の微細化が有用である。 By the way, distance image sensors are also required to be miniaturized as the electronic devices mounted on them are miniaturized. In order to reduce the size of the range image sensor, miniaturization of pixels is useful.
　しかしながら、特許文献１の画素構造ように、ｐｎ接合をなすｐ型の第１電極領域及びｎ型の第２電極領域と、ｐ型のコンタクト領域とが画素形成領域の上部に設けられたラテラル構造では、画素の微細化に伴ってｎ型の第２電極領域とｐ型のコンタクト領域とが近づき、このｎ型の第２電極領域とｐ型のコンタクト領域との間の耐圧（デバイス耐圧）を確保することが困難となる。したがって、画素の微細化を図るためには、デバイス耐圧を確保する必要があり、改良の余地があった。 However, like the pixel structure of Patent Document 1, a lateral structure in which a p-type first electrode region and an n-type second electrode region forming a pn junction and a p-type contact region are provided above the pixel forming region. Then, as the pixel becomes finer, the n-type second electrode region and the p-type contact region come closer to each other, and the withstand voltage (device withstand voltage) between the n-type second electrode region and the p-type contact region is reduced. It becomes difficult to secure. Therefore, in order to miniaturize the pixels, it is necessary to secure the device withstand voltage, and there is room for improvement.
　本技術は、デバイス耐圧を確保しつつ、画素の微細化図ることが可能な半導体装置及びその製造方法、並びに電子機器を供することを目的とする。 The purpose of this technology is to provide a semiconductor device, a manufacturing method thereof, and an electronic device capable of miniaturizing pixels while ensuring device withstand voltage.
　本技術の一態様に係る半導体装置は、
　アバランシェフォトダイオード素子を有する画素が行列状に複数配置された画素アレイ部を備え、
　アバランシェフォトダイオード素子は、
　半導体層の画素形成領域の互に反対側に位置する第１の面及び第２の面のうちの第１の面側にｐｎ接合をなして設けられ、かつｐｎ接合の界面部にアバランシェ増倍領域が形成される第１導電型の第１電極領域及び第２導電型の第２電極領域と、
　半導体層の画素形成領域の第１の面側に、第１電極領域と電気的に接続して設けられた第１導電型のコンタクト領域と、
　コンタクト領域と第２電極領域との間に設けられた絶縁部と、
　を有する。 The semiconductor device according to one aspect of the present technology is
A pixel array unit in which a plurality of pixels having an avalanche photodiode element are arranged in a matrix is provided.
Avalanche photodiode elements
A pn junction is provided on the first surface side of the first surface and the second surface located on opposite sides of the pixel forming region of the semiconductor layer, and the avalanche is multiplied at the interface portion of the pn junction. A first conductive type first electrode region and a second conductive type second electrode region in which a region is formed,
A first conductive contact region provided on the first surface side of the pixel forming region of the semiconductor layer by being electrically connected to the first electrode region.
An insulating portion provided between the contact region and the second electrode region,
Have.
　本技術の他の態様に係る半導体装置の製造方法は、
　半導体層の第１の面側に、第１導電型の第１電極領域を形成するとともに、第１電極領域の上部側とｐｎ接合をなす第２導電型の第２電極領域を形成する工程と、
　半導体層の第１の面側に、第１電極領域と電気的に接続する第１導電型のコンタクト領域を形成する工程と、
　第２電極領域と前記コンタクト領域との間に絶縁部を形成する工程と、
　を備える。 A method for manufacturing a semiconductor device according to another aspect of the present technology is as follows.
A step of forming a first conductive type first electrode region on the first surface side of the semiconductor layer and forming a second conductive type second electrode region forming a pn junction with the upper side of the first electrode region. ,
A step of forming a first conductive type contact region electrically connected to the first electrode region on the first surface side of the semiconductor layer, and
A step of forming an insulating portion between the second electrode region and the contact region, and
To be equipped.
　本技術の他の態様に係る電子機器は、上記半導体装置と、上記画素形成領域の第２の面に被写体からの像光を結像させる光学系と、を備える。 An electronic device according to another aspect of the present technology includes the semiconductor device and an optical system for forming an image light from a subject on a second surface of the pixel forming region.
本技術の第１実施形態に係る距離画像センサの一構成例を示すチップレイアウト図である。It is a chip layout figure which shows one configuration example of the distance image sensor which concerns on 1st Embodiment of this technique. 本技術の第１実施形態に係る距離画像センサの一構成例を示すブロック図である。It is a block diagram which shows one configuration example of the distance image sensor which concerns on 1st Embodiment of this technique. 画素の一構成例を示す等価回路図である。It is an equivalent circuit diagram which shows one configuration example of a pixel. 画素の一構成例を示す要部平面図である。It is a main part plan view which shows one composition example of a pixel. 図４のII－II切断線の位置で切った断面構造を示す要部断面図である。It is a cross-sectional view of a main part which shows the cross-sectional structure cut at the position of the II-II cutting line of FIG. 図５の一部を拡大した要部拡大断面図である。FIG. 5 is an enlarged cross-sectional view of a main part obtained by enlarging a part of FIG. 本技術の第１実施形態に係る距離画像センサの製造方法の工程断面図である。It is a process sectional view of the manufacturing method of the distance image sensor which concerns on 1st Embodiment of this technique. 本技術の第１実施形態に係る距離画像センサの製造方法の図７に引き続く工程断面図である。It is a process sectional view following FIG. 7 of the manufacturing method of the distance image sensor which concerns on 1st Embodiment of this technique. 本技術の第１実施形態に係る距離画像センサの製造方法の図８に引き続く工程断面図である。It is a process sectional view following FIG. 8 of the manufacturing method of the distance image sensor which concerns on 1st Embodiment of this technique. 本技術の第１実施形態に係る距離画像センサの製造方法の図９に引き続く工程断面図である。It is a process sectional view following FIG. 9 of the manufacturing method of the distance image sensor which concerns on 1st Embodiment of this technique. 本技術の第１実施形態に係る距離画像センサの製造方法の図１０に引き続く工程断面図である。It is a process sectional view following FIG. 10 of the manufacturing method of the distance image sensor which concerns on 1st Embodiment of this technique. 本技術の第１実施形態に係る距離画像センサの製造方法の図１１に引き続く工程断面図である。It is a process sectional view following FIG. 11 of the manufacturing method of the distance image sensor which concerns on 1st Embodiment of this technique. 本技術の第１実施形態に係る距離画像センサの製造方法の図１２に引き続く工程断面図である。It is a process sectional view following FIG. 12 of the manufacturing method of the distance image sensor which concerns on 1st Embodiment of this technique. 本技術の第１実施形態に係る距離画像センサの製造方法の図１３に引き続く工程断面図である。It is a process sectional view following FIG. 13 of the manufacturing method of the distance image sensor which concerns on 1st Embodiment of this technique. 本技術の第１実施形態に係る距離画像センサの製造方法の図１４に引き続く工程断面図である。It is a process sectional view following FIG. 14 of the manufacturing method of the distance image sensor which concerns on 1st Embodiment of this technique. 本技術の第１実施形態に係る距離画像センサの製造方法の図１５に引き続く工程断面図である。It is a process sectional view following FIG. 15 of the manufacturing method of the distance image sensor which concerns on 1st Embodiment of this technique. 本技術の第１実施形態に係る距離画像センサの製造方法の図１６に引き続く工程断面図である。It is a process sectional view following FIG. 16 of the manufacturing method of the distance image sensor which concerns on 1st Embodiment of this technique. 本技術の第１実施形態に係る距離画像センサの製造方法の図１７に引き続く工程断面図である。It is a process sectional view following FIG. 17 of the manufacturing method of the distance image sensor which concerns on 1st Embodiment of this technique. 本技術の第１実施形態に係る距離画像センサの製造方法の図１８に引き続く工程断面図である。It is a process sectional view following FIG. 18 of the manufacturing method of the distance image sensor which concerns on 1st Embodiment of this technique. 本技術の第１実施形態に係る距離画像センサの製造方法の図１９に引き続く工程断面図である。It is a process sectional view following FIG. 19 of the manufacturing method of the distance image sensor which concerns on 1st Embodiment of this technique. 第１変形例を示す平面図である。It is a top view which shows the 1st modification. 第２変形例を示す平面図である。It is a top view which shows the 2nd modification. 図２２ＡのIII－III切断線の位置で切った断面構造を示す断面図である。It is sectional drawing which shows the cross-sectional structure cut at the position of the III-III cutting line of FIG. 22A. 第３変形例を示す平面図である。It is a top view which shows the 3rd modification. 第４変形例を示す平面図である。It is a top view which shows the 4th modification. 本技術の第２実施形態に係る距離画像センサの画素の構成を示す要部断面図である。It is sectional drawing of the main part which shows the structure of the pixel of the distance image sensor which concerns on 2nd Embodiment of this technique. 本技術のセンサチップを利用した距離画像機器の構成例を示すブロック図である。It is a block diagram which shows the configuration example of the distance image apparatus using the sensor chip of this technology.
　以下において、図面を参照して本技術の実施形態を説明する。以下の説明で参照する図面の記載において、同一又は類似の部分には同一又は類似の符号を付している。ただし、図面は模式的なものであり、厚みと平面寸法との関係、各層の厚みの比率等は現実のものとは異なることに留意すべきである。したがって、具体的な厚みや寸法は以下の説明を参酌して判断すべきものである。また、図面相互間においても互いの寸法の関係や比率が異なる部分が含まれていることは勿論である。なお、本明細書中に記載された効果はあくまで例示であって限定されるものでは無く、また他の効果があってもよい。 Hereinafter, embodiments of the present technology will be described with reference to the drawings. In the description of the drawings referred to in the following description, the same or similar parts are designated by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the plane dimensions, the ratio of the thickness of each layer, etc. are different from the actual ones. Therefore, the specific thickness and dimensions should be determined in consideration of the following explanation. In addition, it goes without saying that the drawings include parts having different dimensional relationships and ratios from each other. It should be noted that the effects described in the present specification are merely examples and are not limited, and other effects may be obtained.
　また、以下の実施形態では、空間内で互に直交する三方向において、同一平面内で互に直交する第１の方向及び第２の方向をそれぞれＸ方向、Ｙ方向とし、第１の方向及び第２の方向のそれぞれと直交する第３の方向をＺ方向とする。
　また、本明細書及び添付図面において、「ｎ」又は「ｐ」を冠記した層や領域では、それぞれ電子又は正孔が多数キャリアであることを意味する。 Further, in the following embodiment, in the three directions orthogonal to each other in the space, the first direction and the second direction orthogonal to each other in the same plane are set to the X direction and the Y direction, respectively, and the first direction and the second direction The third direction orthogonal to each of the second directions is defined as the Z direction.
Further, in the present specification and the accompanying drawings, it means that the electrons or holes are a large number of carriers in the layers and regions marked with "n" or "p", respectively.
　（第１実施形態）
　この第１実施形態では、半導体装置として、裏面照射型の距離画像センサに本技術を適用した一例について説明する。
　＜距離画像センサの構成＞
　図１に示すように、本技術の第１実施形態に係る距離画像センサ１は、平面視の形状が矩形のセンサチップ２を主体に構成されている。センサチップ２は、矩形の中央に配置された画素アレイ部２Ａと、画素アレイ部２Ａの外側に画素アレイ部２Ａを囲むようにして配置された周辺領域２Ｂと、周辺領域２Ｂの外側に周辺領域２Ｂを囲むようにして配置されたパッド領域２Ｃとを備えている。 (First Embodiment)
In this first embodiment, an example in which the present technology is applied to a back-illuminated distance image sensor as a semiconductor device will be described.
<Structure of distance image sensor>
As shown in FIG. 1, the distance image sensor 1 according to the first embodiment of the present technology is mainly composed of a sensor chip 2 having a rectangular shape in a plan view. The sensor chip 2 has a pixel array portion 2A arranged in the center of a rectangle, a peripheral region 2B arranged outside the pixel array portion 2A so as to surround the pixel array portion 2A, and a peripheral region 2B outside the peripheral region 2B. It includes a pad area 2C arranged so as to surround it.
　画素アレイ部２Ａは、図示しない光学系により集光される光を受光する受光面である。そして、画素アレイ部２Ａには、Ｘ方向及びＹ方向を含む二次元平面において複数の画素３が行列状に配置されている。
　周辺領域２Ｂには、図２に示すバイアス電圧印加部５や、その他の回路部が配置されている。バイアス電圧印加部５は、画素アレイ部２Ａに配置された複数の画素３のそれぞれに対してバイアス電圧を印加する。
　図１に示すように、パッド領域２Ｃには、センサチップ２の平面の各辺に沿って複数の電極パッド４が配置されている。電極パッド４は、センサチップ２を図示しない外部装置と電気的に接続する際に用いられる。 The pixel array unit 2A is a light receiving surface that receives light collected by an optical system (not shown). Then, in the pixel array unit 2A, a plurality of pixels 3 are arranged in a matrix in a two-dimensional plane including the X direction and the Y direction.
The bias voltage application unit 5 shown in FIG. 2 and other circuit units are arranged in the peripheral region 2B. The bias voltage application unit 5 applies a bias voltage to each of the plurality of pixels 3 arranged in the pixel array unit 2A.
As shown in FIG. 1, in the pad region 2C, a plurality of electrode pads 4 are arranged along each side of the plane of the sensor chip 2. The electrode pad 4 is used when the sensor chip 2 is electrically connected to an external device (not shown).
　図３に示すように、画素３は、光電変換素子として例えばＡＰＤ（アバランシェフォトダイオード）素子６と、例えばｐ型ＭＯＳＦＥＴ（Ｍetal Ｏxide Ｓemiconductor Ｆield Ｅffect Ｔransistor）からなるクエンチング抵抗素子７と、例えば相補型ＭＯＳＦＥＴ（Ｃomplementary ＭＯＳ）からなるインバータ８とを備えている。 As shown in FIG. 3, the pixel 3 is complemented with, for example, an APD (Avalanche photodiode) element 6 as a photoelectric conversion element and a quenching resistance element 7 composed of, for example, a p-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor). It is equipped with an inverter 8 made of MOSFET (Complementary MOS).
　ＡＰＤ素子６は、アノードがバイアス電圧印加部５（図２参照）と接続され、カソードがクエンチング抵抗素子７のソース端子と接続されている。ＡＰＤ素子６のアノードは、バイアス電圧印加部５からバイアス電圧ＶＢが印加される。ＡＰＤ素子６は、カソードに大きな負電圧が印加されることによってアバランシェ増倍領域２３（図６参照）を形成し、１フォントの入射で発生する電子をアバランシェ増倍させることができる。 In the APD element 6, the anode is connected to the bias voltage application unit 5 (see FIG. 2), and the cathode is connected to the source terminal of the quenching resistance element 7. A bias voltage VB is applied to the anode of the APD element 6 from the bias voltage application unit 5. The APD element 6 forms an avalanche multiplication region 23 (see FIG. 6) by applying a large negative voltage to the cathode, and can multiply the electrons generated by the incident of one font.
　クエンチング抵抗素子７は、ＡＰＤ素子６と直列に接続され、ソース端子がＡＰＤ素子６のカソードと接続され、ドレイン端子が図示しない電源と接続されている。クエンチング抵抗素子７のドレイン端子には、電源から励起電圧ＶＥが印加される。クエンチング抵抗素子７は、ＡＰＤ素子６でアバランシェ増倍された電子による電圧が負電圧ＶＢＤに達すると、ＡＰＤ素子６で増倍された電子を放出して、当該電圧を初期電圧に戻すクエンチング（quenting）を行う。クエンチング抵抗素子７は、ＡＰＤ素子６のカソード電圧が負電圧ＶＢＤに達すると、ＡＰＤ素子６で増倍された電子を放出させることによりクエンチングを行う。 The quenching resistance element 7 is connected in series with the APD element 6, the source terminal is connected to the cathode of the APD element 6, and the drain terminal is connected to a power supply (not shown). An excitation voltage VE is applied from the power source to the drain terminal of the quenching resistance element 7. When the voltage due to the avalanche-multiplied electrons in the APD element 6 reaches the negative voltage VBD, the quenching resistance element 7 emits the multiplied electrons in the APD element 6 to return the voltage to the initial voltage. Perform (quenting). When the cathode voltage of the APD element 6 reaches the negative voltage VBD, the quenching resistance element 7 performs quenching by emitting electrons multiplied by the APD element 6.
　インバータ８は、入力端子がＡＰＤ素子６のカソード及びクエンチング抵抗素子７のソース端子と接続され、出力端子が図示しない後段の演算処理部と接続されている。インバータ８は、ＡＰＤ素子６で増倍された電子に基づいて受光信号を出力する。より具体的には、インバータ８は、ＡＰＤ素子６で増倍された電子により発生する電圧を整形する。そして、インバータ８は、１フォントの到来時刻を始点として例えば図３に示すパルス波形が発生する受光信号（ＡＰＤ　ＯＵＴ）を演算処理部に出力する。例えば、演算処理部は、それぞれの受光信号において１フォントの到来時刻を示すパルスが発生したタイミングに基づいて、被写体までの距離を求める演算処理を行って、画素３ごとに距離を求める。そして、それらの距離に基づいて、複数の画素３により検出された被写体までの距離を平面的に並べた距離画像が生成される。 In the inverter 8, the input terminal is connected to the cathode of the APD element 6 and the source terminal of the quenching resistance element 7, and the output terminal is connected to a subsequent arithmetic processing unit (not shown). The inverter 8 outputs a light receiving signal based on the electrons multiplied by the APD element 6. More specifically, the inverter 8 shapes the voltage generated by the electrons multiplied by the APD element 6. Then, the inverter 8 outputs a light receiving signal (APD OUT) in which the pulse waveform shown in FIG. 3, for example, is generated starting from the arrival time of one font to the arithmetic processing unit. For example, the arithmetic processing unit performs arithmetic processing for obtaining the distance to the subject based on the timing at which a pulse indicating the arrival time of one font is generated in each received signal, and obtains the distance for each pixel 3. Then, based on those distances, a distance image in which the distances to the subject detected by the plurality of pixels 3 are arranged in a plane is generated.
　図５に示すように、センサチップ２は、半導体層としてのセンサ基板１０、センサ側配線層３０及びロジック側配線層４０がこの順で積層された積層構造になっている。そして、ロジック側配線層４０に対して、図示しないロジック回路基板が積層されている。 As shown in FIG. 5, the sensor chip 2 has a laminated structure in which a sensor substrate 10 as a semiconductor layer, a sensor-side wiring layer 30, and a logic-side wiring layer 40 are laminated in this order. A logic circuit board (not shown) is laminated on the logic side wiring layer 40.
　ロジック回路基板には、例えば、図２に示すバイアス電圧印加部５や、クエンチング抵抗素子７、インバータ８などが形成されている。図５に示すように、センサ基板１０及びロジック回路基板は、配線層であるセンサ側配線層３０及びロジック側配線層４０により電気的に接続される。例えば、センサチップ２は、センサ基板１０に対向してセンサ側配線層３０を設けるとともに、ロジック回路基板に対してロジック側配線層４０を設けた後、センサ側配線層３０及びロジック側配線層４０を接合面（図５の破線で示す面）で接合する製造方法により製造することができる。 For example, the bias voltage application unit 5 shown in FIG. 2, the quenching resistance element 7, the inverter 8, and the like are formed on the logic circuit board. As shown in FIG. 5, the sensor board 10 and the logic circuit board are electrically connected by the sensor side wiring layer 30 and the logic side wiring layer 40, which are wiring layers. For example, the sensor chip 2 is provided with the sensor-side wiring layer 30 facing the sensor board 10, and after providing the logic-side wiring layer 40 with respect to the logic circuit board, the sensor-side wiring layer 30 and the logic-side wiring layer 40. Can be manufactured by a manufacturing method in which is joined at a joining surface (the surface shown by the broken line in FIG. 5).
　センサ基板１０は、例えば、単結晶シリコンからなる半導体基板で形成されている。センサ基板１０は、ｐ型（第１導電型）又はｎ型（第２導電型）を呈する不純物の濃度が制御されており、画素３ごとにＡＰＤ素子６が形成されている。また、図５においてセンサ基板１０の下側を向く面が光を受光する受光面とされ、その受光面の反対側となる面（図５において上側を向く面）に対してセンサ側配線層３０が積層されている。センサ基板１０の受光面には、オンチップレンズ５０が画素３ごとに設けられている。
　ここで、センサ基板１０の受光面を第２の面又は光入射面、受光面とは反対側の面を第１の面又は裏面と呼ぶこともある。また、センサ基板１０の第２の面側を上部、第２の面側を下部と呼ぶこともある。 The sensor substrate 10 is formed of, for example, a semiconductor substrate made of single crystal silicon. In the sensor substrate 10, the concentration of impurities exhibiting p-type (first conductive type) or n-type (second conductive type) is controlled, and the APD element 6 is formed for each pixel 3. Further, in FIG. 5, the surface facing the lower side of the sensor substrate 10 is a light receiving surface that receives light, and the sensor side wiring layer 30 with respect to the surface opposite to the light receiving surface (the surface facing upward in FIG. 5). Are stacked. An on-chip lens 50 is provided for each pixel 3 on the light receiving surface of the sensor substrate 10.
Here, the light receiving surface of the sensor substrate 10 may be referred to as a second surface or a light incident surface, and the surface opposite to the light receiving surface may be referred to as a first surface or a back surface. Further, the second surface side of the sensor substrate 10 may be referred to as an upper portion, and the second surface side may be referred to as a lower portion.
　センサ側配線層３０及びロジック側配線層４０には、バイアス電圧印加部５からＡＰＤ素子６に印加する電圧を供給するための配線や、ＡＰＤ素子６で発生した電子をセンサ基板１０から取り出すための配線などが形成されている。 The sensor-side wiring layer 30 and the logic-side wiring layer 40 are used for wiring for supplying a voltage applied to the APD element 6 from the bias voltage application unit 5 and for extracting electrons generated by the APD element 6 from the sensor substrate 10. Wiring etc. are formed.
　図４及び図５に示すように、画素３は、センサ基板１０の画素形成領域１０ａと、この画素形成領域１０ａを区画する画素間分離領域１５とを含む。画素形成領域１０ａは、センサ基板１０の第１の面（受光面とは反対側の面）に向かって平面視したときの平面パターンが方形状パターンになっている。そして、画素形成領域１０ａは、互いに直交するＸ方向及びＹ方向のそれぞれに画素間分離領域１５を介して複数配置されている。 As shown in FIGS. 4 and 5, the pixel 3 includes a pixel forming region 10a of the sensor substrate 10 and an inter-pixel separation region 15 for partitioning the pixel forming region 10a. The pixel forming region 10a has a rectangular pattern when viewed in a plane toward the first surface (the surface opposite to the light receiving surface) of the sensor substrate 10. A plurality of pixel forming regions 10a are arranged in each of the X direction and the Y direction orthogonal to each other via the inter-pixel separation region 15.
　画素間分離領域１５は、互に隣り合う画素形成領域１０ａ間を電気的に分離する。画素間分離領域１５は、例えばＳＴＩ（Ｓhallow Ｔrench Ｉsolation）構造を有し、センサ基板１０の第１の面（主面）から深さ方向（厚さ方向）に延伸している。１つの画素３に対応する画素間分離領域１５は、図４に示すように、センサ基板１０の第１の面に向かって平面視したときの平面パターンが格子状（メッシュ状）平面パターンになっている。そして、詳細に図示していないが、画素アレイ部２Ａに対応する画素間分離領域１５の平面パターンは、方形の環状平面パターンの中に格子状平面パターンを有する複合平面パターンになっている。 The pixel-to-pixel separation region 15 electrically separates the pixel-forming regions 10a adjacent to each other. The inter-pixel separation region 15 has, for example, an STI (Shallow Trench Isolation) structure, and extends from the first surface (main surface) of the sensor substrate 10 in the depth direction (thickness direction). As shown in FIG. 4, the inter-pixel separation region 15 corresponding to one pixel 3 has a grid-like (mesh-like) plane pattern when viewed in a plane toward the first surface of the sensor substrate 10. ing. Although not shown in detail, the plane pattern of the inter-pixel separation region 15 corresponding to the pixel array portion 2A is a composite plane pattern having a grid-like plane pattern in the rectangular annular plane pattern.
　画素３は、上述したように、ＡＰＤ素子６を有している。そして、図５及び図６に示すように、ＡＰＤ素子６は、センサ基板１０の画素形成領域１０ａに設けられたｎ型（第２導電型）のウエル領域１１と、センサ基板１０の画素形成領域１０ａの上部（第１の面側）にｐｎ接合をなして設けられ、かつｐｎ接合の界面部にアバランシェ増倍領域２３が形成されるｐ型（第１導電型）の第１電極領域１９及びｎ型の第２電極領域２２とを有する。また、ＡＰＤ素子６は、センサ基板１０の画素形成領域１０ａの上部にｐ型の第１電極領域１９と電気的に接続して設けられたｐ型のコンタクト領域２６と、ｐ型のコンタクト領域２６とｎ型の第２電極領域２２との間に設けられた絶縁部２５とを有する。また、更に、ＡＰＤ素子６は、センサ基板１０の画素形成領域１０ａにｐ型のコンタクト領域２６と電気的に接続して設けられたｐ型の電荷蓄積領域１２と、ｎ型の第２電極領域２２の上部に設けられたｎ型のコンタクト領域２７とを有する。すなわち、画素３は、ＡＰＤ素子６を有するとともに、ＡＰＤ素子６のｎ型の第２電極領域２２とｐ型のコンタクト領域２６との間に設けられた絶縁部２５を有する。第１電極領域１９、ｎ型の第２電極領域２２及び絶縁部２５は、ｎ型のウエル領域１１の中に設けられている。 Pixel 3 has an APD element 6 as described above. Then, as shown in FIGS. 5 and 6, the APD element 6 has an n-type (second conductive type) well region 11 provided in the pixel forming region 10a of the sensor substrate 10 and a pixel forming region of the sensor substrate 10. A p-type (first conductive type) first electrode region 19 and a p-type (first conductive type) first electrode region 19 and a p-type (first conductive type) in which a pn junction is provided on the upper portion (first surface side) of 10a and an avalanche multiplication region 23 is formed at the interface portion of the pn junction. It has an n-type second electrode region 22. Further, the APD element 6 has a p-type contact region 26 provided above the pixel forming region 10a of the sensor substrate 10 by being electrically connected to the p-type first electrode region 19, and a p-type contact region 26. It has an insulating portion 25 provided between the surface and the n-type second electrode region 22. Further, the APD element 6 has a p-type charge storage region 12 provided in the pixel forming region 10a of the sensor substrate 10 by being electrically connected to the p-type contact region 26, and an n-type second electrode region. It has an n-shaped contact area 27 provided on the upper part of the 22. That is, the pixel 3 has an APD element 6 and an insulating portion 25 provided between the n-type second electrode region 22 and the p-type contact region 26 of the APD element 6. The first electrode region 19, the n-type second electrode region 22, and the insulating portion 25 are provided in the n-type well region 11.
　図６に示すように、ｎ型のウエル領域１１は、センサ基板１０の第１の面（受光面とは反対側の面）側から第２の面（受光面）側に亘って設けられ、ＡＰＤ素子６の光電変換により発生した電子をアバランシェ増倍領域２３へ転送する電界を形成する。この第１実施形態ではｎ型のウエル領域１１を用いているが、ｎ型のウエル領域１１に替えてｐ型のウエル領域を用いてもよい。 As shown in FIG. 6, the n-type well region 11 is provided from the first surface (the surface opposite to the light receiving surface) side to the second surface (light receiving surface) side of the sensor substrate 10. It forms an electric field that transfers the electrons generated by the photoelectric conversion of the APD element 6 to the avalanche multiplication region 23. Although the n-type well region 11 is used in this first embodiment, a p-type well region may be used instead of the n-type well region 11.
　図６に示すように、絶縁部２５は、センサ基板１０の画素形成領域１０ａの厚さ方向（Ｚ方向）に延びている。そして、ｐｎ接合をなすｐ型の第１電極領域１９及びｎ型の第２電極領域２２は、センサ基板１０の画素形成領域１０ａの第１の面側から反対側の第２の面側（上部表面から深さ方向（Ｚ方向））に向かってｎ型の第２電極領域２２及びｐ型の第１電極領域１９がこの順で配置された第１部分１９ａ，２２ａと、この第１部分１９ａ，２２ａから絶縁部２５に沿って延伸する第２部分１９ｂ，２２ｂと、を有する。すなわち、ｐ型の第１電極領域１９の第１部分１９ａ及びｎ型の第２電極領域２２の第１部分２２ａは、画素形成領域１０ａの厚さ方向において第１の面側から反対側の第２の面側に向かって第１部分２２ａ、第１部分１９ａの順で配置されている。また、ｐ型の第１電極領域１９の第２部分１９ｂ及びｎ型の第２電極領域２２の第２部分２２ｂは、画素形成領域１０ａの平面方向において絶縁部２５側からｎ型のコンタクト領域２７側に向かって第２部分２２ｂ、第２部分１９ｂの順で配置されている。 As shown in FIG. 6, the insulating portion 25 extends in the thickness direction (Z direction) of the pixel forming region 10a of the sensor substrate 10. The p-type first electrode region 19 and the n-type second electrode region 22 forming a pn junction are formed on a second surface side (upper portion) opposite to the first surface side of the pixel forming region 10a of the sensor substrate 10. The first portions 19a and 22a in which the n-type second electrode region 22 and the p-type first electrode region 19 are arranged in this order from the surface to the depth direction (Z direction), and the first portion 19a. , 22a with second portions 19b, 22b extending along the insulating portion 25. That is, the first portion 19a of the p-type first electrode region 19 and the first portion 22a of the n-type second electrode region 22 are the first portions on the opposite side from the first surface side in the thickness direction of the pixel formation region 10a. The first portion 22a and the first portion 19a are arranged in this order toward the surface side of 2. Further, the second portion 19b of the p-type first electrode region 19 and the second portion 22b of the n-type second electrode region 22 are the n-type contact region 27 from the insulating portion 25 side in the plane direction of the pixel forming region 10a. The second portion 22b and the second portion 19b are arranged in this order toward the side.
　ｐ型の第１電極領域１９の第２部分１９ｂは、第１部分１９ａから絶縁部２５の画素形成領域１０ａの第１の面側とは反対側である下部側を越えてｐ型のコンタクト領域に到達し、電気的及び機械的に接続されている。一方、ｎ型の第２電極領域２２の第２部分２２ｂは、絶縁部２５の下部直下で終端している。 The second portion 19b of the p-type first electrode region 19 extends from the first portion 19a to the lower side of the pixel forming region 10a of the insulating portion 25 opposite to the first surface side, and is a p-type contact region. Is reached and is electrically and mechanically connected. On the other hand, the second portion 22b of the n-type second electrode region 22 is terminated immediately below the lower portion of the insulating portion 25.
　図６に示すように、ｎ型の第２電極領域２２の第１部分２２ａは、ｐ型の第１電極領域１９の第１部分１９ａの上部側で第１電極領域１９の第１部分１９ａとｐｎ接合されている。ｎ型の第２電極領域２２の第２部分２２ｂは、ｐ型の第１電極領域１９の第２部分１９ｂの上部側で第１電極領域１９の第２部分１９ｂとｐｎ接合されている。 As shown in FIG. 6, the first portion 22a of the n-type second electrode region 22 is on the upper side of the first portion 19a of the p-type first electrode region 19 with the first portion 19a of the first electrode region 19. It is pn-junctioned. The second portion 22b of the n-type second electrode region 22 is pn-junctioned with the second portion 19b of the first electrode region 19 on the upper side of the second portion 19b of the p-type first electrode region 19.
　図６に示すように、ｐ型の第１電極領域１９において、第１部分１９ａはｐ型の半導体領域１３（第１半導体領域）で構成され、第２部分１９ｂはｐ型の半導体領域１８（第３半導体領域）で構成されている。半導体領域１３及び１８はほぼ同一の不純物濃度になっており、更にそれぞれの厚さがほぼ均一になっている。 As shown in FIG. 6, in the p-type first electrode region 19, the first portion 19a is composed of the p-type semiconductor region 13 (first semiconductor region), and the second portion 19b is the p-type semiconductor region 18 (p-type semiconductor region 18). It is composed of a third semiconductor region). The semiconductor regions 13 and 18 have substantially the same impurity concentration, and the respective thicknesses are substantially uniform.
　ｎ型の第２電極領域２２において、第１部分２２ａはｎ型の半導体領域１４（第２半導体領域）で構成され、第２部分２２ｂはｎ型の半導体領域２１（第４半導体領域）で構成されている。半導体領域１４及び２１はほぼ同一の不純物濃度になっており、更にそれぞれの厚さがほぼ均一になっている。 In the n-type second electrode region 22, the first portion 22a is composed of the n-type semiconductor region 14 (second semiconductor region), and the second portion 22b is composed of the n-type semiconductor region 21 (fourth semiconductor region). Has been done. The semiconductor regions 14 and 21 have substantially the same impurity concentration, and their respective thicknesses are substantially uniform.
　図６に示すように、アバランシェ増倍領域２３は、ｐ型のコンタクト領域２６に印加される大きな負電圧によって、ｐ型の第１電極領域１９とｎ型の第２電極領域２２とのｐｎ接合の界面部に形成される高電界領域（空乏層）であり、ＡＰＤ素子６に入射する１フォントで発生する電子（ｅ－）を増倍する。 As shown in FIG. 6, the avalanche multiplication region 23 is a pn junction between the p-type first electrode region 19 and the n-type second electrode region 22 due to a large negative voltage applied to the p-type contact region 26. It is a high electric field region (depletion layer) formed at the interface portion of the APD element 6, and multipliers the electrons (e−) generated by one font incident on the APD element 6.
　図６に示すように、ｐ型の電荷蓄積領域１２は、画素間分離領域１５の壁面に沿って設けられている。そして、この第１実施形態では、電荷蓄積領域１２は、画素形成領域１０ａの第２の面側である下部の底面に沿って設けられている。すなわち、電荷蓄積領域１２は、ウエル領域１１の側面と接する第１部分１２ａと、ウエル領域１１の底面と接する第２部分１２ｂとでウエル領域１１を囲むようにして設けられている。 As shown in FIG. 6, the p-type charge storage region 12 is provided along the wall surface of the inter-pixel separation region 15. Then, in this first embodiment, the charge storage region 12 is provided along the bottom surface of the lower portion on the second surface side of the pixel formation region 10a. That is, the charge storage region 12 is provided so as to surround the well region 11 with a first portion 12a in contact with the side surface of the well region 11 and a second portion 12b in contact with the bottom surface of the well region 11.
　ｐ型の電荷蓄積領域１２は、例えばｎ型のウエル領域１１よりも不純物濃度が高いｐ型の半導体領域で構成され、ホールを蓄積する。ｐ型の電荷蓄積領域１２は、アノードとして機能するｐ型のコンタクト領域２６と電気的に接続されており、バイアス調整を可能とする。これにより、ｐ型の電荷蓄積領域１２のホール濃度が強化され、ピニングが強固になることによって、例えば暗電流の発生を抑制することができる。 The p-type charge storage region 12 is composed of, for example, a p-type semiconductor region having a higher impurity concentration than the n-type well region 11 and accumulates holes. The p-type charge storage region 12 is electrically connected to the p-type contact region 26 that functions as an anode, and bias adjustment is possible. As a result, the hole concentration in the p-type charge storage region 12 is strengthened and the pinning is strengthened, so that, for example, the generation of dark current can be suppressed.
　図６及び図４に示すように、ｐ型のコンタクト領域２６は、センサ基板１０の画素形成領域１０ａの上部表面（第１の面）において、ウエル領域１１の外周を囲い、かつｐ型の電荷蓄積領域１２の第１部分１２ａと重なるようにして設けられている。すなわち、ｐ型のコンタクト領域は、平面視したときの平面パターンが方形の環状平面パターンになっており、環状平面パターンの全周に亘って電荷蓄積領域１２の第１部分１２ａと接触して電気的に接続されている。コンタクト領域２６は、後述するコンタクト電極３２とのオーミックコンタクト抵抗を低減するとともに、アノードとして機能する。ｐ型のコンタクト領域２６は、ｐ型の第１電極領域１９及びｐ型の電荷蓄積領域１２よりも不純物濃度が高いｐ型の半導体領域で構成されている。 As shown in FIGS. 6 and 4, the p-type contact region 26 surrounds the outer periphery of the well region 11 on the upper surface (first surface) of the pixel forming region 10a of the sensor substrate 10 and has a p-type charge. It is provided so as to overlap the first portion 12a of the storage region 12. That is, in the p-type contact region, the plane pattern when viewed in a plan view is a rectangular annular plane pattern, and the contact with the first portion 12a of the charge storage region 12 over the entire circumference of the annular plane pattern is electrically charged. Is connected. The contact region 26 reduces the ohmic contact resistance with the contact electrode 32 described later and functions as an anode. The p-type contact region 26 is composed of a p-type semiconductor region having a higher impurity concentration than the p-type first electrode region 19 and the p-type charge storage region 12.
　図６及び図４に示すように、ｎ型のコンタクト領域２７は、第１電極領域２２の第１部分２２ａの上部の中に設けられている。ｎ型のコンタクト領域２７は、後述するコンタクト電極３１とのオーミックコンタクト抵抗を低減するとともに、カソードとして機能する。ｎ型のコンタクト領域２７は、ｎ型の第２電極領域２２よりも不純物濃度が高いｎ型の半導体領域で構成されている。 As shown in FIGS. 6 and 4, the n-type contact region 27 is provided in the upper part of the first portion 22a of the first electrode region 22. The n-type contact region 27 reduces the ohmic contact resistance with the contact electrode 31, which will be described later, and functions as a cathode. The n-type contact region 27 is composed of an n-type semiconductor region having a higher impurity concentration than the n-type second electrode region 22.
　図６に示すように、絶縁部２５は、センサ基板１０の画素形成領域１０ａの上部表面（第１の面）から窪む凹部１６と、この凹部１６内に設けられた絶縁体として例えば酸化シリコンからなる絶縁膜２４とを有する。この実施形態において、凹部１６の中は、絶縁膜２４で埋め込まれている。 As shown in FIG. 6, the insulating portion 25 includes a recess 16 recessed from the upper surface (first surface) of the pixel forming region 10a of the sensor substrate 10, and silicon oxide, for example, as an insulator provided in the recess 16. It has an insulating film 24 made of. In this embodiment, the recess 16 is embedded with an insulating film 24.
　図６及び図４に示すように、絶縁部２５は、ｐ型の第１電極領域１９及び第２電極領域２２の各々の第１部分１９ａ及び２２ａを囲い、かつ平面視したときの平面パターンが方形の環状パターンになっている。 As shown in FIGS. 6 and 4, the insulating portion 25 surrounds the first portions 19a and 22a of the p-shaped first electrode region 19 and the second electrode region 22, respectively, and has a planar pattern when viewed in a plan view. It has a square ring pattern.
　図６に示すように、絶縁部２５の第２電極領域２２と接する壁面（側面）は、センサ基板１０の厚さ方向に対して傾斜している。換言すれば、凹部１６に埋め込まれた絶縁膜２４の第２電極領域２２と接する壁面、更に換言すれば凹部１６で区画された島領域の第２電極領域２２側の壁面、更に換言すればセンサ基板１０の凹部１６内における第２電極領域２２側の壁面は、センサ基板１０の第２の面と直交するＺ方向に対して傾斜している。 As shown in FIG. 6, the wall surface (side surface) of the insulating portion 25 in contact with the second electrode region 22 is inclined with respect to the thickness direction of the sensor substrate 10. In other words, the wall surface in contact with the second electrode region 22 of the insulating film 24 embedded in the recess 16, in other words, the wall surface on the second electrode region 22 side of the island region partitioned by the recess 16, in other words, the sensor. The wall surface on the second electrode region 22 side in the recess 16 of the substrate 10 is inclined with respect to the Z direction orthogonal to the second surface of the sensor substrate 10.
　図６に示すように、ｐ型の半導体領域１８は、センサ基板１０の画素形成領域１０ａの凹部１６内における内面から内方に向かって厚さを有し、ｐ型の半導体領域１３と一体化されて電気的に接続されている。ｎ型の半導体領域２１は、センサ基板１０の画素形成領域１０ａの凹部１６内における内面から内方に向かって厚さを有し、ｎ型の半導体領域１４と一体化されて電気的に接続されているとともに、ｐ型の半導体領域１８の上部側とｐｎ接合されている。 As shown in FIG. 6, the p-type semiconductor region 18 has a thickness from the inner surface to the inside in the recess 16 of the pixel forming region 10a of the sensor substrate 10 and is integrated with the p-type semiconductor region 13. Is electrically connected. The n-type semiconductor region 21 has a thickness from the inner surface to the inside in the recess 16 of the pixel forming region 10a of the sensor substrate 10, and is integrated with the n-type semiconductor region 14 and electrically connected. At the same time, it is pn-junctioned with the upper side of the p-type semiconductor region 18.
　図５に示すように、センサ側配線層３０には、コンタクト電極３１，３２、メタル配線３３，３４、コンタクト電極３５，３６、及びメタルパッド３７，３８が設けられている。
　コンタクト電極３１は、ｎ型のコンタクト領域２７とメタル配線３３とを電気的に接続し、コンタクト電極３２は、ｐ型のコンタクト領域２６とメタル配線３４とを電気的に接続している。
　メタル配線３３は、例えば、図５に示すように、少なくともアバランシェ増倍領域２３を覆うように、アバランシェ増倍領域２３よりも広く形成されている。そして、メタル配線３３は、ＡＰＤ素子６を透過した光をＡＰＤ素子６に反射する。
　メタル配線３４は、メタル配線３３の外周を囲い、かつｐ型のコンタクト領域２６と重なるようにして形成されている。 As shown in FIG. 5, the sensor-side wiring layer 30 is provided with contact electrodes 31, 32, metal wirings 33, 34, contact electrodes 35, 36, and metal pads 37, 38.
The contact electrode 31 electrically connects the n-type contact region 27 and the metal wiring 33, and the contact electrode 32 electrically connects the p-type contact region 26 and the metal wiring 34.
As shown in FIG. 5, for example, the metal wiring 33 is formed wider than the avalanche multiplication region 23 so as to cover at least the avalanche multiplication region 23. Then, the metal wiring 33 reflects the light transmitted through the APD element 6 to the APD element 6.
The metal wiring 34 is formed so as to surround the outer circumference of the metal wiring 33 and overlap with the p-shaped contact region 26.
　コンタクト電極３５は、メタル配線３３とメタルパッド３７とを電気的に接続し、コンタクト電極３６は、メタル配線３４とメタルパッド３８とを電気的に接続している。
　メタルパッド３７及び３８は、ロジック側配線層４０に設けられたメタルパッド４７及び４８と、それぞれの金属間接合により電気的及び機械的に接続されている。 The contact electrode 35 electrically connects the metal wiring 33 and the metal pad 37, and the contact electrode 36 electrically connects the metal wiring 34 and the metal pad 38.
The metal pads 37 and 38 are electrically and mechanically connected to the metal pads 47 and 48 provided on the logic side wiring layer 40 by metal-to-metal joints, respectively.
　図５に示すように、ロジック側配線層４０には、電極パッド４１，４２、絶縁層４３、コンタクト電極４４，４５、及びメタルパッド４７，４８が設けられている。
　電極パッド４１，４２は、それぞれ図示しないロジック回路基板と接続され、絶縁層４３は、電極パッド４１と電極パッド４２とを互に絶縁している。 As shown in FIG. 5, the logic side wiring layer 40 is provided with electrode pads 41, 42, insulating layers 43, contact electrodes 44, 45, and metal pads 47, 48.
The electrode pads 41 and 42 are connected to logic circuit boards (not shown), respectively, and the insulating layer 43 insulates the electrode pads 41 and the electrode pads 42 from each other.
　コンタクト電極４４は、電極パッド４１とメタルパッド４７とを電気的に接続し、コンタクト電極４５は、電極パッド４２とメタルパッド４８とを電気的に接続している。
　メタルパッド３７はメタルパッド４７と接合され、メタルパッド３８はメタルパッド４８と接合されている。 The contact electrode 44 electrically connects the electrode pad 41 and the metal pad 47, and the contact electrode 45 electrically connects the electrode pad 42 and the metal pad 48.
The metal pad 37 is joined to the metal pad 47, and the metal pad 38 is joined to the metal pad 48.
　このような配線構造により、例えば、電極パッド４１は、コンタクト電極４４、メタルパッド４７、メタルパッド３７、コンタクト電極３５、メタル配線３３、コンタクト電極３１及びｎ型のコンタクト領域２７を介してｎ型の第２電極領域２２と電気的に接続されている。したがって、画素３では、ｎ型の第２電極領域２２に印加される大きな負電圧を、ロジック回路基板から電極パッド４１に対して供給することができる。 With such a wiring structure, for example, the electrode pad 41 is n-type via the contact electrode 44, the metal pad 47, the metal pad 37, the contact electrode 35, the metal wiring 33, the contact electrode 31, and the n-type contact region 27. It is electrically connected to the second electrode region 22. Therefore, in the pixel 3, a large negative voltage applied to the n-type second electrode region 22 can be supplied from the logic circuit board to the electrode pad 41.
　また、電極パッド４２は、コンタクト電極４５、メタルパッド４８、メタルパッド３８、コンタクト電極３６、メタル配線３４、コンタクト電極３２及びｎ型のコンタクト領域２７を介してｐ型の第１電極領域１９と電気的に接続されている。したがって、画素３では、ｐ型の電荷蓄積領域１２と電気的に接続されるＡＰＤ素子６のアノードが電極パッド４２に電気的に接続されることで、電極パッド４２を介してｐ型の電荷蓄積領域１２に対するバイアス調整を可能とすることができる。 Further, the electrode pad 42 is electrically connected to the p-type first electrode region 19 via the contact electrode 45, the metal pad 48, the metal pad 38, the contact electrode 36, the metal wiring 34, the contact electrode 32 and the n-type contact region 27. Is connected. Therefore, in the pixel 3, the anode of the APD element 6 electrically connected to the p-type charge storage region 12 is electrically connected to the electrode pad 42, so that the p-type charge is accumulated via the electrode pad 42. Bias adjustment for the region 12 can be made possible.
　この第１実施形態に係る距離画像センサ１の画素３は、上述したように、ｐｎ接合をなし、かつ、このｐｎ接合の界面部にアバランシェ増倍領域２３が形成されるｐ型の第１電極領域１９及びｎ型の第２電極領域２２と、アノードとして機能するｐ型のコンタクト領域２６とがセンサ基板１０の画素形成領域１０ａの上部（第１の面側）に設けられている。そして、ｐ型のコンタクト領域２６とｎ型の第２電極領域２２との間に絶縁部２５が設けられている。したがって、この第１実施形態の距離画像センサ１によれば、画素３の微細化に伴ってｐ型のコンタクト領域２６とｎ型の第２電極領域２２とが近づいても、換言すればｐ型のコンタクト領域２６とｎ型の第２電極領域２２との間の距離が短くなっても、ｐ型のコンタクト領域２６とｎ型の第２電極領域２２との間のデバイス耐圧を絶縁部２５で確保することができる。これにより、ｐ型のコンタクト領域２６とｎ型の第２電極領域２２との間のデバイス耐圧を確保しつつ、画素３の微細化を図ることができる。そして、この結果、距離画像センサ１の小型化を図ることができる。 As described above, the pixel 3 of the distance image sensor 1 according to the first embodiment has a pn junction, and a p-type first electrode having an avalanche multiplication region 23 formed at an interface portion of the pn junction. A region 19 and an n-type second electrode region 22 and a p-type contact region 26 functioning as an anode are provided on the upper portion (first surface side) of the pixel forming region 10a of the sensor substrate 10. An insulating portion 25 is provided between the p-type contact region 26 and the n-type second electrode region 22. Therefore, according to the distance image sensor 1 of the first embodiment, even if the p-type contact region 26 and the n-type second electrode region 22 approach each other as the pixel 3 becomes finer, in other words, the p-type Even if the distance between the contact region 26 and the n-type second electrode region 22 is shortened, the device withstand voltage between the p-type contact region 26 and the n-type second electrode region 22 is maintained by the insulating portion 25. Can be secured. As a result, the pixel 3 can be miniaturized while ensuring the device withstand voltage between the p-type contact region 26 and the n-type second electrode region 22. As a result, the distance image sensor 1 can be miniaturized.
　ｐｎ接合界面部にアバランシェ増倍領域２３が形成されるｐ型の第１電極領域１９及びｎ型の第２電極領域２２は、上述したように、センサ基板１０の画素形成領域１０ａの上部表面（第１の面）から深さ方向に向かってｎ型の第２電極領域２２（ｎ型の半導体領域１４）及びｐ型の第１電極領域１９（ｐ型の半導体領域１３）がこの順で配置された第１部分１９ａ，２２ａと、この第１部分１９ａ，２２ａから絶縁部２５の深さ方向に絶縁部２５の壁面に沿って延伸する第２部分１９ｂ，２２ｂと、を有する。したがって、この第１実施形態の距離画像センサ１によれば、画素３の微細化に伴ってｐ型の第１電極領域１９及びｎ型の第２電極領域２２の第１部分１９ａ，２２ａの表面積が縮小されても第２部分１９ｂ，２２ｂの表面積を広くすることができるため、ｐ型の第１電極領域１９とｎ型の第２電極領域２２とのｐｎ接合界面部に形成されるアバランシェ増倍領域２３の表面積（延べ面積）を確保しつつ、画素３の微細化を図ることができる。そして、この結果、距離画像センサ１の小型化を図ることができる。また、増幅率を高くして感度や高子検出効率の低下を抑制することもできる。 As described above, the p-type first electrode region 19 and the n-type second electrode region 22 in which the avalanche multiplication region 23 is formed at the pn junction interface are the upper surfaces of the pixel formation region 10a of the sensor substrate 10. The n-type second electrode region 22 (n-type semiconductor region 14) and the p-type first electrode region 19 (p-type semiconductor region 13) are arranged in this order from the first surface) in the depth direction. The first portions 19a and 22a are formed, and the second portions 19b and 22b extend from the first portions 19a and 22a along the wall surface of the insulating portion 25 in the depth direction of the insulating portion 25. Therefore, according to the distance image sensor 1 of the first embodiment, the surface areas of the first portions 19a and 22a of the p-type first electrode region 19 and the n-type second electrode region 22 as the pixel 3 becomes finer. Since the surface area of the second portions 19b and 22b can be increased even if the surface area is reduced, the avalanche increase formed at the pn junction interface between the p-type first electrode region 19 and the n-type second electrode region 22. The pixel 3 can be miniaturized while ensuring the surface area (total area) of the double region 23. As a result, the distance image sensor 1 can be miniaturized. It is also possible to increase the amplification factor to suppress a decrease in sensitivity and high child detection efficiency.
　絶縁部２５のｎ型の第２電極領域２２と接する壁面は、上述したように、センサ基板１０の厚さ方向（Ｚ方向）に対して傾斜している。したがって、この第１実施形態の距離画像センサ１によれば、絶縁部２５の第２電極領域２２と接する壁面をセンサ基板１０の厚さ方向（Ｚ方向）と平行にした場合と比較してｐ型の第１電極領域１９及びｎ型の第２電極領域２２の第２部分１９ｂ，２２ｂの表面積を広くすることができる。これにより、ｐ型の第１電極領域１９とｎ型の第２電極領域２２とのｐｎ接合界面部に形成されるアバランシェ増倍領域２３の表面積（延べ面積）を更に確保しつつ、画素３の微細化を図ることができる。 As described above, the wall surface of the insulating portion 25 in contact with the n-type second electrode region 22 is inclined with respect to the thickness direction (Z direction) of the sensor substrate 10. Therefore, according to the distance image sensor 1 of the first embodiment, p is compared with the case where the wall surface in contact with the second electrode region 22 of the insulating portion 25 is parallel to the thickness direction (Z direction) of the sensor substrate 10. The surface areas of the second portions 19b and 22b of the first electrode region 19 of the mold and the second electrode region 22 of the n mold can be increased. As a result, the surface area (total area) of the avalanche multiplication region 23 formed at the pn junction interface between the p-type first electrode region 19 and the n-type second electrode region 22 is further secured, and the pixel 3 It can be miniaturized.
　＜距離画像センサの製造方法＞
　次に、図７から図２０を参照して、第１実施形態に係る距離画像センサの製造方法の一例を説明する。 <Manufacturing method of distance image sensor>
Next, an example of the method for manufacturing the distance image sensor according to the first embodiment will be described with reference to FIGS. 7 to 20.
　まず、単結晶シリコンからなるセンサ基板１０を準備する。 First, the sensor substrate 10 made of single crystal silicon is prepared.
　次に、図７に示すように、センサ基板１０の画素形成領域１０ａの上部を含む全面にｎ型のウエル領域１１を形成する。ウエル領域１１は、ｎ型を呈する不純物イオンとして例えばリン（Ｐ）イオン又はヒ素（Ａｓ）イオンをセンサ基板１０の上部に注入し、その後、注入された不純物イオンを活性化させる熱処理を施すことによって形成される。 Next, as shown in FIG. 7, an n-type well region 11 is formed on the entire surface including the upper portion of the pixel forming region 10a of the sensor substrate 10. The well region 11 is formed by injecting, for example, phosphorus (P) ions or arsenic (As) ions as n-type impurity ions into the upper part of the sensor substrate 10 and then performing a heat treatment to activate the injected impurity ions. It is formed.
　次に、図８に示すように、センサ基板１０の画素形成領域１０ａごとにウエル領域１１の側面及び底面を囲むｐ型の電荷蓄積領域１２を形成する。ｐ型の電荷蓄積領域１２は、まず、ウエル領域１１の側面と接する第１部分１２ａを形成するための不純物イオンをセンサ基板１０の画素形成領域１０ａに選択的に注入するとともに、ウエル領域１１の底部と接する第２部分１２ｂを形成するための不純物イオンをセンサ基板１０の画素形成領域１０ａに選択的に注入する。そして、ｐ型の電荷蓄積領域１２は、画素形成領域１０ａに注入された不純物イオンを活性化させる熱処理を施すことによって形成される。不純物イオンとしては、ｐ型を呈する例えばボロン（Ｂ）イオン又は二フッ化ボロン（ＢＦ２）イオンを用いる。 Next, as shown in FIG. 8, a p-type charge storage region 12 surrounding the side surface and the bottom surface of the well region 11 is formed for each pixel formation region 10a of the sensor substrate 10. In the p-type charge storage region 12, first, impurity ions for forming the first portion 12a in contact with the side surface of the well region 11 are selectively injected into the pixel forming region 10a of the sensor substrate 10, and the well region 11 is formed. Impurity ions for forming the second portion 12b in contact with the bottom portion are selectively injected into the pixel forming region 10a of the sensor substrate 10. Then, the p-type charge storage region 12 is formed by performing a heat treatment for activating the impurity ions injected into the pixel forming region 10a. As the impurity ion, for example, a boron (B) ion or a boron difluoride (BF2) ion exhibiting a p-type is used.
　次に、図９に示すように、センサ基板１０の画素形成領域１０ａの第１の面側の上部であって電荷蓄積領域１２で囲まれたウエル領域１１の上部に、ｐ型の半導体領域１３を形成するとともに、このｐ型の半導体領域１３の上部側とｐｎ接合をなすｎ型の半導体領域１４を形成する。ｐ型の半導体領域１３及びｎ型の半導体領域１４は、まず、ウエル領域１１の上部にｐ型を呈する不純物イオンを選択的に注入するとともに、ウエル領域１１の上部にｎ型を呈する不純物イオンを選択的に注入する。そして、ｐ型の半導体領域１３及びｎ型の半導体領域１４は、ウエル領域１１に注入された不純物イオンを活性化させる熱処理を施すことによって形成される。ｐ型を呈する不純物イオンとしては、例えばＢイオン又はＢＦ２イオンを用いる。ｎ型を呈する不純物イオンとしては、例えばＡｓイオン又はＰイオンを用いる。ｐ型を呈する不純物イオンは、ｎ型を呈する不純物イオンよりも深く注入する。ｐ型の半導体領域１３はｐ型の第１電極領域１９の第１部分１９ａを構成し、ｎ型の半導体領域１４はｎ型の第２電極領域２２の第１部分２２ａを構成する。ｐ型の半導体領域１３及びｎ型の半導体領域１４は、この順でセンサ基板１０の画素形成領域１０ａの上部表面（第１の面）から深さ方向に向かって配置され、ｐｎ接合をなす。 Next, as shown in FIG. 9, the p-type semiconductor region 13 is located above the well region 11 which is the upper portion of the pixel forming region 10a of the sensor substrate 10 on the first surface side and is surrounded by the charge storage region 12. At the same time, an n-type semiconductor region 14 forming a pn junction with the upper side of the p-type semiconductor region 13 is formed. In the p-type semiconductor region 13 and the n-type semiconductor region 14, first, impurity ions exhibiting p-type are selectively injected into the upper part of the well region 11, and impurity ions exhibiting n-type are injected into the upper part of the well region 11. Selectively inject. The p-type semiconductor region 13 and the n-type semiconductor region 14 are formed by performing a heat treatment for activating the impurity ions injected into the well region 11. As the impurity ion exhibiting p-type, for example, B ion or BF2 ion is used. As the impurity ion exhibiting n-type, for example, As ion or P ion is used. Impurity ions exhibiting p-type are injected deeper than impurity ions exhibiting n-type. The p-type semiconductor region 13 constitutes the first portion 19a of the p-type first electrode region 19, and the n-type semiconductor region 14 constitutes the first portion 22a of the n-type second electrode region 22. The p-type semiconductor region 13 and the n-type semiconductor region 14 are arranged in this order from the upper surface (first surface) of the pixel forming region 10a of the sensor substrate 10 in the depth direction to form a pn junction.
　次に、図１０に示すように、センサ基板１０の上部に画素形成領域１０ａ間を電気的に分離する画素間分離領域１５を形成する。画素形成領域１０ａは画素間分離領域１５で周囲を囲まれて区画される。画素間分離領域１５は、例えば、周知のフォトリソグラフィ技術及び異方性ドライエッチング技術を用いてセンサ基板１０の第１の面（主面）から深さ方向に伸びる分離溝を形成し、その後、この分離溝内に絶縁膜を選択的に埋め込むことによって形成される。絶縁膜の埋め込みは、分離溝内を含むセンサ基板１０の第１の面上の全面に例えば酸化シリコン膜をＣＶＤ（Ｃhemical Ｖapor Ｄeposition）法で形成し、その後、センサ基板１０の第１の面上の絶縁膜をエッチバック法やＣＭＰ（Ｃhemical Ｍechanical Ｐolishing）法で選択的に除去することによって行われる。 Next, as shown in FIG. 10, an inter-pixel separation region 15 that electrically separates the pixel formation regions 10a is formed on the upper part of the sensor substrate 10. The pixel forming region 10a is surrounded by a pixel-to-pixel separation region 15 and is partitioned. The inter-pixel separation region 15 forms a separation groove extending in the depth direction from the first surface (main surface) of the sensor substrate 10 by using, for example, a well-known photolithography technique and anisotropic dry etching technique, and then the inter-pixel separation region 15 is formed. It is formed by selectively embedding an insulating film in the separation groove. To embed the insulating film, for example, a silicon oxide film is formed on the entire surface of the sensor substrate 10 including the inside of the separation groove by the CVD (Chemical Vapor Deposition) method, and then on the first surface of the sensor substrate 10. This is performed by selectively removing the insulating film of the above by the etch back method or the CMP (Chemical Mechanical Polishing) method.
　次に、図１１に示すように、センサ基板１０の画素形成領域１０ａの上部表面から深さ方向に向かって延伸する凹部１６を形成する。凹部１６は、周知のフォトリソグラフィ技術及びセンサ基板の結晶軸に依存する結晶異方性エッチング技術を用いて形成することにより、センサ基板１０の凹部１６内における壁面をセンサ基板１０の厚さ方向（Ｚ方向）に対して傾斜させることができる。凹部１６は、センサ基板１０の画素形成領域１０ａの中央部が島領域となるように、平面視したときの平面パターンを方形の環状平面パターンで形成する。 Next, as shown in FIG. 11, a recess 16 extending from the upper surface of the pixel forming region 10a of the sensor substrate 10 in the depth direction is formed. The recess 16 is formed by using a well-known photolithography technique and a crystal anisotropic etching technique that depends on the crystal axis of the sensor substrate, so that the wall surface in the recess 16 of the sensor substrate 10 is formed in the thickness direction of the sensor substrate 10 ( It can be tilted with respect to (Z direction). The recess 16 is formed with a rectangular annular plane pattern when viewed in a plane so that the central portion of the pixel formation region 10a of the sensor substrate 10 is an island region.
　次に、図１２に示すように、凹部１６内を含むセンサ基板１０の第１の面上の全面に第１不純物イオン導入材として例えば多結晶シリコン膜１７をＣＶＤ法で形成する。多結晶シリコン膜１７は、堆積中又は堆積後にｐ型を呈する不純物イオンが注入される。ｐ型を呈する不純物としては、例えばボロンイオン又は二フッ化ボロンイオンを用いる。多結晶シリコン膜１７は、センサ基板１０の凹部１６内における壁面及び底面を含む内面に沿って形成される。 Next, as shown in FIG. 12, for example, a polycrystalline silicon film 17 as a first impurity iontophoresis material is formed on the entire surface of the sensor substrate 10 including the inside of the recess 16 by a CVD method. Impurity ions exhibiting p-type are injected into the polycrystalline silicon film 17 during or after deposition. As the impurities exhibiting the p-type, for example, boron ion or boron difluoride ion is used. The polycrystalline silicon film 17 is formed along the inner surface including the wall surface and the bottom surface in the recess 16 of the sensor substrate 10.
　次に、多結晶シリコン膜１７の不純物イオンをセンサ基板１０の凹部１６内からセンサ基板１０に拡散させる熱処理を施して、図１３に示すように、センサ基板１０の凹部１６内における壁面及び底面、並びにセンサ基板１０の第１の面にｐ型の半導体領域１８を形成する。ｐ型の半導体領域１８は、ｐ型の半導体領域１３と一体に接続され、ｐ型の第１電極領域１９の第２部分１９ｂを構成する。このｐ型の半導体領域１８は、多結晶シリコン膜１７からセンサ基板１０への不純物イオンの固相拡散（ドライブイン拡散）によって形成されるので、均一な厚さで形成される。ｐ型の半導体領域１８は、センサ基板１０の凹部１６内における壁面及び底面を含む内面に沿って形成される。この工程により、ｐ型の半導体領域１３からなる第１部分１９ａと、ｐ型の半導体領域１８からなる第２部分１９ｂとが一体化されたｐ型の第１電極領域１９が形成される。 Next, heat treatment is performed to diffuse the impurity ions of the polycrystalline silicon film 17 from the recess 16 of the sensor substrate 10 into the sensor substrate 10, and as shown in FIG. 13, the wall surface and the bottom surface in the recess 16 of the sensor substrate 10 are subjected to heat treatment. In addition, a p-type semiconductor region 18 is formed on the first surface of the sensor substrate 10. The p-type semiconductor region 18 is integrally connected to the p-type semiconductor region 13 to form a second portion 19b of the p-type first electrode region 19. Since the p-type semiconductor region 18 is formed by solid-phase diffusion (drive-in diffusion) of impurity ions from the polycrystalline silicon film 17 to the sensor substrate 10, it is formed with a uniform thickness. The p-type semiconductor region 18 is formed along the inner surface including the wall surface and the bottom surface in the recess 16 of the sensor substrate 10. By this step, the p-type first electrode region 19 in which the first portion 19a composed of the p-type semiconductor region 13 and the second portion 19b composed of the p-type semiconductor region 18 are integrated is formed.
　次に、図１４に示すように、多結晶シリコン膜１７を除去する。
　次に、図１５に示すように、凹部１６内を含むセンサ基板１０の第１の面上の全面に第２不純物イオン導入材として例えば多結晶シリコン膜２０をＣＶＤ法で形成する。多結晶シリコン膜２０は、堆積中又は堆積後にｎ型を呈する不純物イオン（例えばＰイオン又はＡｓイオン）が注入される。多結晶シリコン膜２０は、センサ基板１０の凹部１６内における壁面及び底面を含む内面に沿って形成される。 Next, as shown in FIG. 14, the polycrystalline silicon film 17 is removed.
Next, as shown in FIG. 15, for example, a polycrystalline silicon film 20 as a second impurity iontophoresis material is formed on the entire surface of the sensor substrate 10 including the inside of the recess 16 by a CVD method. The polycrystalline silicon film 20 is injected with impurity ions (for example, P ions or As ions) that exhibit n-type during or after deposition. The polycrystalline silicon film 20 is formed along the inner surface including the wall surface and the bottom surface in the recess 16 of the sensor substrate 10.
　次に、周知のフォトリソグラフィ技術及び指向性の高いドライエッチング技術を使用して、図１６に示すように、センサ基板１０の凹部１６内におけるｎ型の半導体領域１４側とは反対側の壁面及び上部表面を覆う多結晶シリコン膜２０を選択的に除去する。この工程において、多結晶シリコン膜２０は、センサ基板１０の凹部１６内における半導体領域１４側の壁面及び半導体領域１４を覆うとともに、凹部１６内の底面上で終端する。 Next, using a well-known photolithography technique and a highly directional dry etching technique, as shown in FIG. 16, the wall surface on the side opposite to the n-type semiconductor region 14 side in the recess 16 of the sensor substrate 10 and The polycrystalline silicon film 20 covering the upper surface is selectively removed. In this step, the polycrystalline silicon film 20 covers the wall surface on the semiconductor region 14 side and the semiconductor region 14 in the recess 16 of the sensor substrate 10 and terminates on the bottom surface in the recess 16.
　次に、多結晶シリコン膜２０の不純物イオンをセンサ基板１０の凹部１６内からセンサ基板１０に拡散させる熱処理を施して、図１７に示すように、センサ基板１０の凹部１６内における半導体領域１４側の壁面及び底面にｎ型の半導体領域２１を選択的に形成する。ｎ型の半導体領域２１は、ｎ型の半導体領域１４と一体に形成され、かつｐ型の半導体領域１８の上部側にｐｎ接合される。ｎ型の半導体領域２１は、ｎ型の第２電極領域２２の第２部分２２ｂを構成する。このｎ型の半導体領域２１は、多結晶シリコン膜２０からセンサ基板１０への不純物イオンの固相拡散（ドライブイン拡散）によって形成されるので、均一な厚さで形成される。この工程により、ｎ型の半導体領域１４からなる第１部分２２ａと、ｎ型の半導体領域２１からなる第２部分２２ｂとが一体化され、かつ第２部分２２ｂがｐ型の第１電極領域１９の第２部分１９ｂの上部側とｐｎ接合されたｎ型の第２電極領域２２が形成される。 Next, heat treatment is performed to diffuse the impurity ions of the polycrystalline silicon film 20 from the recess 16 of the sensor substrate 10 into the sensor substrate 10, and as shown in FIG. 17, the semiconductor region 14 side in the recess 16 of the sensor substrate 10 is subjected to heat treatment. The n-type semiconductor region 21 is selectively formed on the wall surface and the bottom surface of the surface. The n-type semiconductor region 21 is integrally formed with the n-type semiconductor region 14, and is pn-junctioned to the upper side of the p-type semiconductor region 18. The n-type semiconductor region 21 constitutes a second portion 22b of the n-type second electrode region 22. Since the n-type semiconductor region 21 is formed by solid-phase diffusion (drive-in diffusion) of impurity ions from the polycrystalline silicon film 20 to the sensor substrate 10, it is formed with a uniform thickness. By this step, the first portion 22a composed of the n-type semiconductor region 14 and the second portion 22b composed of the n-type semiconductor region 21 are integrated, and the second portion 22b is the p-type first electrode region 19. An n-type second electrode region 22 pn-junctioned with the upper side of the second portion 19b of the above is formed.
　次に、図１８に示すように、多結晶シリコン膜２０を除去する。
　次に、図１９に示すように、センサ基板１０の凹部１６内に絶縁体として絶縁膜２４を埋め込む。絶縁膜２４の埋め込みは、凹部１６内を含むセンサ基板１０の第１の面上の全面に例えば酸化シリコン膜からなる絶縁膜をＣＶＤ法で形成し、その後、センサ基板１０の第２の面上の絶縁膜をエッチバック法やＣＭＰ法で選択的に除去することによって行われる。この工程により、センサ基板１０の上部表面から窪む凹部１６と、この凹部１６内に設けられた絶縁体としての絶縁膜２４とを含む絶縁部２５が形成される。 Next, as shown in FIG. 18, the polycrystalline silicon film 20 is removed.
Next, as shown in FIG. 19, an insulating film 24 is embedded as an insulator in the recess 16 of the sensor substrate 10. To embed the insulating film 24, an insulating film made of, for example, a silicon oxide film is formed on the entire surface of the first surface of the sensor substrate 10 including the recess 16 by a CVD method, and then on the second surface of the sensor substrate 10. This is done by selectively removing the insulating film of the above by the etchback method or the CMP method. By this step, an insulating portion 25 including a recess 16 recessed from the upper surface of the sensor substrate 10 and an insulating film 24 as an insulator provided in the recess 16 is formed.
　次に、図２０に示すように、センサ基板１０の上部であって電荷蓄積領域１２上に電荷蓄積領域１２と接続するｐ型のコンタクト領域２６を形成するとともに、センサ基板１０の上部であってｎ型の第２電極領域２２の第１部分２２ａ（ｎ型の半導体領域１４）の上部にｎ型のコンタクト領域２７を形成する。ｐ型のコンタクト領域２６は、ｐ型を呈する不純物イオン（例えばＢイオン又はＢＦ２イオン）をセンサ基板１０の画素間分離領域１５と絶縁部２５との間の上部に選択的に注入し、その後、注入された不純物イオンを活性化させる熱処理を施すことによって形成される。同様に、ｎ型のコンタクト領域２７も、ｎ型を呈する不純物イオン（例えばＰイオン又はＡｓイオン）をｎ型の半導体領域１４の上部に選択的に注入し、その後、注入された不純物イオンを活性化させる熱処理を施すことによって形成される。この工程により、センサ基板１０の画素形成領域１０ａにＡＰＤ素子６が形成される。 Next, as shown in FIG. 20, a p-type contact region 26 is formed on the charge storage region 12 which is the upper portion of the sensor substrate 10 and is connected to the charge storage region 12, and is also the upper portion of the sensor substrate 10. An n-type contact region 27 is formed above the first portion 22a (n-type semiconductor region 14) of the n-type second electrode region 22. The p-type contact region 26 selectively injects p-type impurity ions (for example, B ions or BF2 ions) into the upper part between the inter-pixel separation region 15 and the insulating portion 25 of the sensor substrate 10, and then selectively injects them. It is formed by performing a heat treatment that activates the injected impurity ions. Similarly, in the n-type contact region 27, an impurity ion exhibiting n-type (for example, P ion or As ion) is selectively injected into the upper part of the n-type semiconductor region 14, and then the injected impurity ion is activated. It is formed by subjecting it to heat treatment. By this step, the APD element 6 is formed in the pixel forming region 10a of the sensor substrate 10.
　次に、センサ基板１０の第２の面にセンサ側配線層３０を設けるとともに、ロジック回路基板にロジック側配線層４０を設けた後、センサ側配線層３０及びロジック側配線層４０を接合面で接合する。そして、センサ基板１０の第２の面を画素間分離領域１５が露出するまでＣＭＰ等により研削してセンサ基板１０の厚さを薄くする。更に、センサ基板１０の第２の面にオンチップレンズ５０を設ける。これにより、図１から図６に示した第１実施形態に係る距離画像センサ１がほぼ完成する。 Next, the sensor-side wiring layer 30 is provided on the second surface of the sensor board 10, the logic-side wiring layer 40 is provided on the logic circuit board, and then the sensor-side wiring layer 30 and the logic-side wiring layer 40 are provided on the joint surface. Join. Then, the second surface of the sensor substrate 10 is ground by CMP or the like until the inter-pixel separation region 15 is exposed to reduce the thickness of the sensor substrate 10. Further, an on-chip lens 50 is provided on the second surface of the sensor substrate 10. As a result, the distance image sensor 1 according to the first embodiment shown in FIGS. 1 to 6 is almost completed.
　この第１実施形態に係る距離画像センサ１の製造方法によれば、ｎ型の第２電極領域２２とｐ型のコンタクト領域２６との間に絶縁部２５を形成するので、ｎ型の第２電極領域２２とｐ型のコンタクト領域２６との間のデバイス耐圧を確保しつつ、画素３の微細化を図った距離画像センサ１を製造することができる。 According to the manufacturing method of the distance image sensor 1 according to the first embodiment, the insulating portion 25 is formed between the n-type second electrode region 22 and the p-type contact region 26, so that the n-type second electrode region 22 is formed. It is possible to manufacture the distance image sensor 1 in which the pixel 3 is miniaturized while ensuring the device withstand voltage between the electrode region 22 and the p-type contact region 26.
　また、この第１実施形態に係る距離画像センサ１の製造方法によれば、ｐｎ接合をなすｐ型の第１電極領域１９及びｎ型の第２電極領域２２をセンサ基板１０の第１の面と平行な二次元平面及びセンサ基板１０の深さ方向に形成するので、ｐ型の第１電極領域１９とｎ型の第２電極領域２２とのｐｎ接合界面部に形成されるアバランシェ増倍領域２３の表面積（延べ面積）を確保しつつ、画素３の微細化を図った距離画像センサ１を製造することができる。 Further, according to the method for manufacturing the distance image sensor 1 according to the first embodiment, the p-type first electrode region 19 and the n-type second electrode region 22 forming a pn junction are formed on the first surface of the sensor substrate 10. Since it is formed in the two-dimensional plane parallel to and in the depth direction of the sensor substrate 10, the avalanche multiplication region formed at the pn junction interface between the p-type first electrode region 19 and the n-type second electrode region 22. It is possible to manufacture the distance image sensor 1 in which the pixels 3 are miniaturized while securing the surface area (total area) of 23.
　また、この第１実施形態に係る距離画像センサ１の製造方法によれば、ｐｎ接合をなすｐ型の第１電極領域１９及びｎ型の第２電極領域２２の各々の第２部分１９ａ，２２ｂを、不純物イオン導入材からの固相拡散によってセンサ基板１０の凹部１６内における壁面に形成するので、ｐｎ接合をなすｐ型の第１電極領域１９及びｎ型の第２電極領域２２の各々の第２部分１９ｂ，２２ｂを壁面から深さ方向に均一な厚さで形成することができる。 Further, according to the method for manufacturing the distance image sensor 1 according to the first embodiment, the second portions 19a and 22b of the p-type first electrode region 19 and the n-type second electrode region 22 forming a pn junction, respectively. Is formed on the wall surface in the recess 16 of the sensor substrate 10 by solid-phase diffusion from the impurity ion-introduced material, so that each of the p-type first electrode region 19 and the n-type second electrode region 22 forming a pn junction is formed. The second portions 19b and 22b can be formed with a uniform thickness in the depth direction from the wall surface.
　なお、上述の第１実施形態では、ｎ型の第２電極領域２２の第２部分２２ｂを絶縁部２５の下部直下で終端させた場合について説明した。しかしながら、本技術は第１実施形態に限定されない。例えば、ｎ型の第２電極領域２２の第２部分２２ｂを、絶縁部２５の下部の内側（ｎ型のコンタクト領域２７側）で終端させてもよく、また、ｐ型のコンタクト領域２６との間で接合リークが発生しない範囲であれば、絶縁部２５の下部の外側（ｐ型のコンタクト領域２６側）で終端させてもよい。ｐ型の第１電極領域１９とｎ型の第２電極領域２２とがなすｐｎ接合面積の増加、及びｎ型の第２電極領域２２とｐ型のコンタクト領域２６との間での接合リークを考慮すると、ｎ型の第２電極領域２２の第２部分２２ｂは、上述の第１実施形態のように、絶縁部２５の下部の直下で終端させることが好ましい。
　また、上述の第１実施形態では、絶縁部２５の凹部１６内に絶縁体として絶縁膜２４を用いた場合について説明した。しかしながら、本技術は絶縁膜２４に限定されるものてばない。例えば、凹部１６内に絶縁体として空気や不活性ガスなどを充填させてもよい。 In the first embodiment described above, a case where the second portion 22b of the n-type second electrode region 22 is terminated immediately below the lower portion of the insulating portion 25 has been described. However, the present technology is not limited to the first embodiment. For example, the second portion 22b of the n-type second electrode region 22 may be terminated inside the lower portion of the insulating portion 25 (n-type contact region 27 side), or may be terminated with the p-type contact region 26. As long as there is no joint leakage between them, it may be terminated on the outside of the lower part of the insulating portion 25 (on the side of the p-type contact region 26). An increase in the pn junction area formed by the p-type first electrode region 19 and the n-type second electrode region 22, and a junction leak between the n-type second electrode region 22 and the p-type contact region 26. In consideration, it is preferable that the second portion 22b of the n-type second electrode region 22 is terminated directly below the lower portion of the insulating portion 25 as in the first embodiment described above.
Further, in the above-described first embodiment, the case where the insulating film 24 is used as an insulator in the recess 16 of the insulating portion 25 has been described. However, the present technology is not limited to the insulating film 24. For example, the recess 16 may be filled with air, an inert gas, or the like as an insulator.
　（変 形 例）
　次に、絶縁部２５の変形例について説明する。
　上述の第１実施形態では、絶縁部２５の平面パターンを、方形の環状平面パターンで形成した場合について説明した。しかしながら、本技術は、この方形の環状パターンに限定されるものではない。例えば、第１変形例として、図２１に示すように、絶縁部２５の平面パターンを、円形の環状平面パターンにしてもよい。 (Transformation example)
Next, a modified example of the insulating portion 25 will be described.
In the above-described first embodiment, the case where the plane pattern of the insulating portion 25 is formed by a rectangular annular plane pattern has been described. However, the present technology is not limited to this rectangular cyclic pattern. For example, as a first modification, as shown in FIG. 21, the plane pattern of the insulating portion 25 may be a circular annular plane pattern.
　また、第２変形例として、図２２Ａ及び図２２Ｂに示すように、絶縁部２５の平面パターンを、方形の環状パターンの中に格子状パターンを有する複合平面パターンにしてもよい。この第２変形例の複合平面パターンの場合、上述の第１実施形態と比較して、ｐ型の第１電極領域１９とｎ型の第２電極領域２２とがなすｐｎ接合の接合面積を増加することができる。これにより、ｐ型の第１電極領域１９とｎ型の第２電極領域２２とのｐｎ接合界面部に形成されるアバランシェ増倍領域２３の表面積を増加することができる。 Further, as a second modification, as shown in FIGS. 22A and 22B, the plane pattern of the insulating portion 25 may be a composite plane pattern having a grid pattern in a rectangular annular pattern. In the case of the composite plane pattern of this second modification, the junction area of the pn junction formed by the p-type first electrode region 19 and the n-type second electrode region 22 is increased as compared with the first embodiment described above. can do. As a result, the surface area of the avalanche multiplication region 23 formed at the pn junction interface between the p-type first electrode region 19 and the n-type second electrode region 22 can be increased.
　また、第３変形例として、図２３に示すように、絶縁部２５の平面パターンを、円形の環状パターンの中に格子状パターンを有する複合平面パターンにしてもよい。この第３変形例の複合パターンにおいても、第２変形例の複合平面パターンと同様に、上述の第１実施形態と比較して、ｐ型の第１電極領域１９とｎ型の第２電極領域２２とがなすｐｎ接合の接合面積を増加することができる。これにより、ｐ型の第１電極領域１９とｎ型の第２電極領域２２とのｐｎ接合界面部に形成されるアバランシェ増倍領域２３の表面積を増加することができる。 Further, as a third modification, as shown in FIG. 23, the plane pattern of the insulating portion 25 may be a composite plane pattern having a grid pattern in a circular annular pattern. Also in the composite pattern of the third modification, as in the composite plane pattern of the second modification, the p-type first electrode region 19 and the n-type second electrode region are compared with the above-described first embodiment. The junction area of the pn junction formed by 22 can be increased. As a result, the surface area of the avalanche multiplication region 23 formed at the pn junction interface between the p-type first electrode region 19 and the n-type second electrode region 22 can be increased.
　ここで、第２及び第３変形例の場合、図２２Ａ、図２２Ｂ及び図２３に示すように、ｎ型の第２電極領域２２の第１部分２２ａ（ｎ型の半導体領域１４）は、１つの画素３内において絶縁部２５で囲まれた状態で個別に複数個点在するが、第２部分２２ｂを介して互に電気的に接続されている。したがって、ｎ型のコンタクト領域２７は、図２２Ａ、図２２Ｂ及び図２３に示すように、複数の第１部分２２ａのうちの少なくとも１つの第１部分２２ａに設けられていればよく、また、図示していないが、全ての第１部分２２ａに設けてもよい。 Here, in the case of the second and third modifications, as shown in FIGS. 22A, 22B, and 23, the first portion 22a (n-type semiconductor region 14) of the n-type second electrode region 22 is 1. A plurality of pixels are individually scattered in the pixel 3 while being surrounded by the insulating portions 25, but are electrically connected to each other via the second portion 22b. Therefore, the n-type contact region 27 may be provided in at least one first portion 22a of the plurality of first portions 22a, as shown in FIGS. 22A, 22B, and 23. Although not shown, it may be provided in all the first portions 22a.
　次に、ｐ型のコンタクト領域２６の変形例について説明する。
　上述の第１実施形態では、ｐ型のコンタクト領域２６の平面パターンを、方形の環状平面パターンで形成した場合について説明した。しかしながら、本技術は、この方形の環状平面パターンに限定されるものではない。例えば、第４変形例として、図２４に示すように、ｐ型のコンタクト領域２６の平面パターンを、１つの画素３内において絶縁部２５の周囲に個別に複数個点在するドット平面パターンにしてもよく、また、図示してないが、１つのドット平面パターンにしてもよい。 Next, a modified example of the p-type contact region 26 will be described.
In the first embodiment described above, a case where the plane pattern of the p-type contact region 26 is formed by a rectangular cyclic plane pattern has been described. However, the present technology is not limited to this rectangular annular plane pattern. For example, as a fourth modification, as shown in FIG. 24, the plane pattern of the p-type contact region 26 is made into a dot plane pattern individually scattered around the insulating portion 25 in one pixel 3. Also, although not shown, a single dot plane pattern may be used.
　ここで、１つの画素３では、アノードとして機能するｐ型のコンタクト領域２６の近傍で電界が集中する。したがって、ｐ型のコンタクト領域２６とｎ型の第２電極領域２２との間のデバイス耐圧を確保するためには、少なくともｐ型のコンタクト領域２６とｎ型の第２電極領域２２との間に絶縁部２５を設ければよい。したがって、上述の第１実施形態のように、ｐ型のコンタクト領域２６の平面パターンを方形の環状平面パターンとする場合は、ｐ型のコンタクト領域２６の平面パターンに合わせて絶縁部２５の平面パターンも方形又は円形の環状平面パターンとすることが好ましい。また、この第４変形例のように、ｐ型のコンタクト領域２６の平面パターンをドット平面パターンとする場合は、絶縁部２５の平面パターンを必ずしも環状平面パターンとする必要はない。要は、少なくとも電界が集中するｐ型のコンタクト領域２６とｎ型の第２電極領域２２との間に絶縁部２５が設けられていればよいので、ｐ型のコンタクト領域２６とｎ型の第２電極領域２２との間で接合リークが発生しない範囲であれば、１つの画素３内における絶縁部２５の平面パターンはどのような形状であってもよい。例えば、環状平面パターン及びドット平面パターンの他に、直線、Ｃ字状、Ｌ字状などの平面パターンとしてもよい。 Here, in one pixel 3, the electric field is concentrated in the vicinity of the p-type contact region 26 that functions as an anode. Therefore, in order to secure the device withstand voltage between the p-type contact region 26 and the n-type second electrode region 22, at least between the p-type contact region 26 and the n-type second electrode region 22. The insulating portion 25 may be provided. Therefore, when the plane pattern of the p-type contact region 26 is a rectangular annular plane pattern as in the first embodiment described above, the plane pattern of the insulating portion 25 is matched with the plane pattern of the p-type contact region 26. It is preferable to use a rectangular or circular annular plane pattern. Further, when the plane pattern of the p-type contact region 26 is a dot plane pattern as in the fourth modification, the plane pattern of the insulating portion 25 does not necessarily have to be an annular plane pattern. In short, since it is sufficient that the insulating portion 25 is provided between at least the p-type contact region 26 where the electric field is concentrated and the n-type second electrode region 22, the p-type contact region 26 and the n-type second electrode region 22 need to be provided. The plane pattern of the insulating portion 25 in one pixel 3 may have any shape as long as a bonding leak does not occur between the two electrode regions 22. For example, in addition to the annular plane pattern and the dot plane pattern, a plane pattern such as a straight line, a C-shape, or an L-shape may be used.
　（第２実施形態）
　本技術の第２実施形態に係る距離画像センサは、上述の第１実施形態に係る距離画像センサ１とほぼ同様の構成になっており、画素の構成が異なっている。 (Second Embodiment)
The distance image sensor according to the second embodiment of the present technology has substantially the same configuration as the distance image sensor 1 according to the first embodiment described above, and has a different pixel configuration.
　すなわち、第１実施形態の画素３は、センサ基板１０の画素形成領域１０ａの第１の面側である上部に、ｐ型の第１電極領域１９及びｎ型の第２電極領域２２と、ｐ型のコンタクト領域２６とが設けられた構造になっている。これに対し、第２実施形態の画素３Ａは、センサ基板１０の画素形成領域１０ａの上部にｐ型の第１電極領域１９及びｎ型の第２電極領域２２が設けられ、センサ基板１０の画素形成領域１０ａの下部にｐ型のコンタクト領域２６が設けられた構造になっている。その他の構成は第１実施形態と同様である。 That is, the pixel 3 of the first embodiment has a p-type first electrode region 19 and an n-type second electrode region 22 and p. The structure is provided with the contact region 26 of the mold. On the other hand, in the pixel 3A of the second embodiment, the p-type first electrode region 19 and the n-type second electrode region 22 are provided above the pixel forming region 10a of the sensor substrate 10, and the pixels of the sensor substrate 10 are provided. The structure is such that a p-type contact region 26 is provided below the formation region 10a. Other configurations are the same as those in the first embodiment.
　この第２実施形態に係る距離画像センサにおいても、上述の第１実施形態に係る距離画像センサ１と同様に、ｐ型のコンタクト領域２６とｎ型の第２電極領域２２との間のデバイス耐圧を確保しつつ、画素３Ａの微細化を図ることができる。また、ｐ型の第１電極領域１９とｎ型の第２電極領域２２とのｐｎ接合界面部に形成されるアバランシェ増倍領域２３の表面積（延べ面積）を確保しつつ、画素３Ａの微細化を図ることができる。 Also in the distance image sensor according to the second embodiment, the device withstand voltage between the p-type contact region 26 and the n-type second electrode region 22 is similar to the distance image sensor 1 according to the first embodiment described above. The pixel 3A can be miniaturized while ensuring the above. Further, the pixel 3A is miniaturized while ensuring the surface area (total area) of the avalanche multiplication region 23 formed at the pn junction interface between the p-type first electrode region 19 and the n-type second electrode region 22. Can be planned.
　（電子機器の構成例）
　図２６に示すように、電子機器としての距離画像機器２０１は、光学系２０２、センサチップ２、画像処理回路２０３、モニタ２０４、及びメモリ２０５を備えて構成される。距離画像機器２０１は、光源装置２１１から被写体に向かって投光され、被写体の表面で反射された光（変調光やパルス光）を受光することにより、被写体までの距離に応じた距離画像を取得することができる。 (Example of electronic device configuration)
As shown in FIG. 26, the distance image device 201 as an electronic device includes an optical system 202, a sensor chip 2, an image processing circuit 203, a monitor 204, and a memory 205. The distance image device 201 acquires a distance image according to the distance to the subject by receiving light (modulated light or pulsed light) that is projected from the light source device 211 toward the subject and reflected on the surface of the subject. can do.
　光学系２０２は、１枚または複数枚のレンズを有して構成され、被写体からの像光（入射光）をセンサチップ２に導き、センサチップ２の受光面（センサ部）に結像させる。 The optical system 202 is configured to have one or a plurality of lenses, guides the image light (incident light) from the subject to the sensor chip 2, and forms an image on the light receiving surface (sensor unit) of the sensor chip 2.
　センサチップ２としては、上述した各実施形態のセンサチップ２が適用され、センサチップ２から出力される受光信号（ＡＰＤ　ＯＵＴ）から求められる距離を示す距離信号が画像処理回路２０３に供給される。 As the sensor chip 2, the sensor chip 2 of each of the above-described embodiments is applied, and a distance signal indicating a distance obtained from a light receiving signal (APD OUT) output from the sensor chip 2 is supplied to the image processing circuit 203.
　画像処理回路２０３は、センサチップ２から供給された距離信号に基づいて距離画像を構築する画像処理を行い、その画像処理により得られた距離画像（画像データ）は、モニタ２０４に供給されて表示されたり、メモリ２０５に供給されて記憶（記録）されたりする。 The image processing circuit 203 performs image processing for constructing a distance image based on the distance signal supplied from the sensor chip 2, and the distance image (image data) obtained by the image processing is supplied to the monitor 204 and displayed. Or it is supplied to the memory 205 and stored (recorded).
　このように構成された距離画像機器２０１では、上述した実施形態のセンサチップ２を適用することで、安定性の高い画素３からの受光信号のみに基づいて被写体までの距離を演算し、精度の高い距離画像を生成することが可能となる。すなわち、距離画像機器２０１は、より正確な距離画像を取得することができる。 In the distance image device 201 configured in this way, by applying the sensor chip 2 of the above-described embodiment, the distance to the subject is calculated based only on the received signal from the highly stable pixel 3, and the accuracy is improved. It is possible to generate a high-distance image. That is, the distance image device 201 can acquire a more accurate distance image.
　（イメージセンサの使用例）
　上述したセンサチップ２（イメージセンサ）は、例えば、以下のように、可視光や、赤外光、紫外光、Ｘ線等の光をセンシングする様々なケースに使用することができる。
・ディジタルカメラや、カメラ機能付きの携帯機器等の、鑑賞の用に供される画像を撮影する装置
・自動停止等の安全運転や、運転者の状態の認識等のために、自動車の前方や後方、周囲、車内等を撮影する車載用センサ、走行車両や道路を監視する監視カメラ、車両間等の測距を行う測距センサ等の、交通の用に供される装置
・ユーザのジェスチャを撮影して、そのジェスチャに従った機器操作を行うために、テレビや、冷蔵庫、エアーコンディショナ等の家電に供される装置
・内視鏡や、赤外光の受光による血管撮影を行う装置等の、医療やヘルスケアの用に供される装置
・防犯用途の監視カメラや、人物認証用途のカメラ等の、セキュリティの用に供される装置
・肌を撮影する肌測定器や、頭皮を撮影するマイクロスコープ等の、美容の用に供される装置
・スポーツ用途等向けのアクションカメラやウェアラブルカメラ等の、スポーツの用に供される装置
・畑や作物の状態を監視するためのカメラ等の、農業の用に供される装置 (Example of using image sensor)
The sensor chip 2 (image sensor) described above can be used in various cases for sensing light such as visible light, infrared light, ultraviolet light, and X-ray, as described below.
・ Devices that capture images used for viewing, such as digital cameras and portable devices with camera functions. ・ For safe driving such as automatic stop, recognition of the driver's condition, etc. Devices and user gestures used for traffic, such as in-vehicle sensors that photograph the rear, surroundings, and interior of vehicles, surveillance cameras that monitor traveling vehicles and roads, and distance measurement sensors that measure distance between vehicles. Devices and endoscopes used in home appliances such as TVs, refrigerators, and air conditioners, and devices that take blood vessels by receiving infrared light, etc., in order to take pictures and operate the equipment according to the gesture. Equipment used for medical and healthcare, surveillance cameras for crime prevention, cameras for person authentication, etc., equipment used for security, skin measuring instruments for taking pictures of the skin, and taking pictures of the scalp Equipment used for beauty such as microscopes, action cameras and wearable cameras for sports applications, equipment used for sports, cameras for monitoring the condition of fields and crops, etc. , Equipment used for agriculture
　なお、本技術は、以下のような構成としてもよい。
（１）
　アバランシェフォトダイオード素子を有する画素が行列状に複数配置された画素アレイ部を備え、
　前記アバランシェフォトダイオード素子は、
　半導体層の画素形成領域の互に反対側に位置する第１の面及び第２の面のうちの前記第１の面側にｐｎ接合をなして設けられ、かつ前記ｐｎ接合の界面部にアバランシェ増倍領域が形成される第１導電型の第１電極領域及び第２導電型の第２電極領域と、
　前記画素形成領域の前記第１の面側に、前記第１電極領域と電気的に接続して設けられた第１導電型のコンタクト領域と、
　前記コンタクト領域と前記第２電極領域との間に設けられた絶縁部と、
　を有する半導体装置。
（２）
　前記絶縁部は、前記画素形成領域の前記第１の面から前記第２の面側に向かって延伸し、
　前記第１電極領域及び前記第２電極領域は、
　前記画素形成領域の前記第１の面側から前記第２の面側に向かって配置された第１部分と、
　前記第１部分から前記絶縁部に沿って延伸する第２部分と、
　を有する上記（１）に記載の半導体装置。
（３）
　前記第１電極領域の前記第２部分は、前記第１電極領域の前記第１部分から前記絶縁部の前記画素形成領域の前記第２の面側を越えて前記コンタクト領域に到達している、上記（２）に記載の半導体装置。
（４）
　前記第２電極領域の前記第２部分は、前記絶縁部の前記画素形成領域の前記第２の面側で終端している、上記（２）に記載の半導体装置。
（５）
　前記第２電極領域は、前記第１電極領域の上部側で前記第１電極領域とｐｎ接合をなしている、上記（１）から（４）の何れかに記載の半導体装置。
（６）
　前記絶縁部の前記第２電極領域と接する側壁は、前記半導体層の厚さ方向に対して傾斜している、上記（１）から（５）の何れかに記載の半導体装置。
（７）
　前記絶縁部は、前記画素形成領域の前記第１の面から窪む凹部と、前記凹部内に設けられた絶縁体とを含む、上記（１）から（６）の何れかに記載の半導体装置。
（８）
　前記絶縁部は、平面視の形状が環状になっている、上記（１）から（７）の何れかに記載の半導体装置。
（９）
　前記絶縁部は、平面視の形状が格子状になっている、上記（１）から（７）の何れかに記載の半導体装置。
（１０）
　前記コンタクト領域は、平面視の形状が環状になっている、上記（１）から（９）の何れかに記載の半導体装置。
（１１）
　前記コンタクト領域は、前記画素形成領域の周囲に点在している、上記（１）から（９）の何れかに記載の半導体装置。
（１２）
　前記画素形成領域は、前記半導体層の前記第１の面から深さ方向に延伸する画素間分離領域で区画されている、上記（１）から（１１）の何れかに記載の半導体装置。
（１３）
　前記画素間分領域に沿って延伸し、かつ前記コンタクト領域と電気的に接続された第１導電型の電荷蓄積領域を更に備えている、上記（１）から（１２）の何れかに記載の半導体装置。
（１４）
　半導体層の第１の面側に、第１導電型の第１電極領域を形成するとともに、前記第１電極領域とｐｎ接合をなす第２導電型の第２電極領域を形成する工程と、
　前記半導体層の前記第１の面側に、前記第１電極領域と電気的に接続する第１導電型のコンタクト領域を形成する工程と、
　前記第２電極領域と前記コンタクト領域との間に絶縁部を形成する工程と、
　を備える半導体装置の製造方法。
（１５）
　上記（１）から（１３）の何れかに記載の半導体装置と、前記画素形成領域の前記第２の面に被写体からの像光を結像させる光学系と、を備える電子機器。 The present technology may have the following configuration.
(1)
A pixel array unit in which a plurality of pixels having an avalanche photodiode element are arranged in a matrix is provided.
The avalanche photodiode element is
Avalanche is provided on the first surface side of the first surface and the second surface located on opposite sides of the pixel forming region of the semiconductor layer by forming a pn junction, and at the interface portion of the pn junction. A first conductive type first electrode region and a second conductive type second electrode region on which a multiplying region is formed,
A first conductive type contact region provided on the first surface side of the pixel forming region by being electrically connected to the first electrode region.
An insulating portion provided between the contact region and the second electrode region,
Semiconductor device with.
(2)
The insulating portion extends from the first surface of the pixel forming region toward the second surface side.
The first electrode region and the second electrode region are
A first portion of the pixel forming region arranged from the first surface side toward the second surface side, and
A second portion extending from the first portion along the insulating portion,
The semiconductor device according to (1) above.
(3)
The second portion of the first electrode region reaches the contact region from the first portion of the first electrode region beyond the second surface side of the pixel forming region of the insulating portion. The semiconductor device according to (2) above.
(4)
The semiconductor device according to (2) above, wherein the second portion of the second electrode region is terminated on the second surface side of the pixel forming region of the insulating portion.
(5)
The semiconductor device according to any one of (1) to (4) above, wherein the second electrode region has a pn junction with the first electrode region on the upper side of the first electrode region.
(6)
The semiconductor device according to any one of (1) to (5) above, wherein the side wall of the insulating portion in contact with the second electrode region is inclined with respect to the thickness direction of the semiconductor layer.
(7)
The semiconductor device according to any one of (1) to (6) above, wherein the insulating portion includes a recess recessed from the first surface of the pixel forming region and an insulator provided in the recess. ..
(8)
The semiconductor device according to any one of (1) to (7) above, wherein the insulating portion has an annular shape in a plan view.
(9)
The semiconductor device according to any one of (1) to (7) above, wherein the insulating portion has a grid-like shape in a plan view.
(10)
The semiconductor device according to any one of (1) to (9) above, wherein the contact region has an annular shape in a plan view.
(11)
The semiconductor device according to any one of (1) to (9) above, wherein the contact regions are scattered around the pixel forming region.
(12)
The semiconductor device according to any one of (1) to (11) above, wherein the pixel forming region is partitioned by an inter-pixel separation region extending in the depth direction from the first surface of the semiconductor layer.
(13)
The above-mentioned (1) to (12), further comprising a first conductive type charge storage region extending along the inter-pixel region and electrically connected to the contact region. Semiconductor device.
(14)
A step of forming a first conductive type first electrode region on the first surface side of the semiconductor layer and forming a second conductive type second electrode region forming a pn junction with the first electrode region.
A step of forming a first conductive type contact region electrically connected to the first electrode region on the first surface side of the semiconductor layer.
A step of forming an insulating portion between the second electrode region and the contact region,
A method for manufacturing a semiconductor device.
(15)
An electronic device comprising the semiconductor device according to any one of (1) to (13) above, and an optical system for forming an image light from a subject on the second surface of the pixel forming region.
　本技術の範囲は、図示され記載された例示的な実施形態に限定されるものではなく、本技術が目的とするものと均等な効果をもたらす全ての実施形態をも含む。さらに、本技術の範囲は、請求項により画される発明の特徴の組み合わせに限定されるものではなく、全ての開示されたそれぞれの特徴のうち特定の特徴のあらゆる所望する組み合わせによって画されうる。 The scope of the present technology is not limited to the exemplary embodiments illustrated and described, but also includes all embodiments that provide an effect equal to that of the present technology. Furthermore, the scope of the present invention is not limited to the combination of the features of the invention defined by the claims, but may be defined by any desired combination of the specific features of all the disclosed features.
　１…距離画像センサ（半導体装置）
　２…センサチップ
　２Ａ…画素アレイ部
　２Ｂ…周辺領域
　２Ｃ…パッド領域
　３…画素
　４…電極パッド
　５…バイアス電圧印加部
　６…ＡＰＤ素子
　７…クエンチング抵抗素子
　８…インバータ
　１０…センサ基板（半導体層）
　１１…ｎ型のウエル領域
　１２…ｐ型の電荷蓄積領域
　１２ａ…第１部分
　１２ｂ…第２部分
　１３…ｐ型の半導体領域（第１半導体領域）
　１４…ｎ型の半導体領域（第２半導体領域）
　１５…画素間分離領域
　１６…凹部
　１７…多結晶シリコン膜（第１不純物拡散材）
　１８…ｐ型の半導体領域（第３半導体領域）
　１９…ｐ型の第１電極領域
　１９ａ…第１部分
　１９ｂ…第２部分
　２０…多結晶シリコン膜（第２不純物拡散材）
　２１…ｎ型の半導体領域（第３半導体領域）
　２２…ｎ型の第２電極領域
　２２ａ…第１部分
　２２ｂ…第２部分
　２３…アバランシェ増倍領域
　２４…絶縁膜（絶縁体）
　２５…絶縁部
　２６…ｐ型のコンタクト領域
　２７…ｎ型のコンタクト領域
　３０…センサ側配線層
　３１，３２…コンタクト電極
　３３，３４…メタル配線
　３５，３６…コンタクト電極
　３７，３８…メタルパッド
　４０…ロジック側配線層
　４１，４２…電極パッド
　４３…絶縁層
　４４，４５…コンタクト電極
　４７，４８…メタルパッド
　５０…オンチップレンズ 1 ... Distance image sensor (semiconductor device)
2 ... Sensor chip 2A ... Pixel array part 2B ... Peripheral area 2C ... Pad area 3 ... Pixel 4 ... Electrode pad 5 ... Bias voltage application part 6 ... APD element 7 ... Quenching resistance element 8 ... Inverter 10 ... Sensor substrate (semiconductor layer) )
11 ... n-type well region 12 ... p-type charge storage region 12a ... first part 12b ... second part 13 ... p-type semiconductor region (first semiconductor region)
14 ... n-type semiconductor region (second semiconductor region)
15 ... Separation region between pixels 16 ... Recessed 17 ... Polycrystalline silicon film (first impurity diffusing material)
18 ... p-type semiconductor region (third semiconductor region)
19 ... p-type first electrode region 19a ... first part 19b ... second part 20 ... polycrystalline silicon film (second impurity diffusing material)
21 ... n-type semiconductor region (third semiconductor region)
22 ... n-type second electrode region 22a ... first part 22b ... second part 23 ... avalanche multiplication region 24 ... insulating film (insulator)
25 ... Insulation part 26 ... P-type contact area 27 ... n-type contact area 30 ... Sensor side wiring layer 31, 32 ... Contact electrode 33, 34 ... Metal wiring 35, 36 ... Contact electrode 37, 38 ... Metal pad 40 ... Logic side wiring layer 41, 42 ... Electrode pad 43 ... Insulation layer 44, 45 ... Contact electrode 47, 48 ... Metal pad 50 ... On-chip lens

Claims (15)

  1. 　アバランシェフォトダイオード素子を有する画素が行列状に複数配置された画素アレイ部を備え、
    　前記アバランシェフォトダイオード素子は、
    　半導体層の画素形成領域の互に反対側に位置する第１の面及び第２の面のうちの前記第１の面側にｐｎ接合をなして設けられ、かつ前記ｐｎ接合の界面部にアバランシェ増倍領域が形成される第１導電型の第１電極領域及び第２導電型の第２電極領域と、
    　前記画素形成領域の前記第１の面側に、前記第１電極領域と電気的に接続して設けられた第１導電型のコンタクト領域と、
    　前記コンタクト領域と前記第２電極領域との間に設けられた絶縁部と、
    　を有する半導体装置。     A pixel array unit in which a plurality of pixels having an avalanche photodiode element are arranged in a matrix is provided.
    The avalanche photodiode element is
    Avalanche is provided on the first surface side of the first surface and the second surface located on opposite sides of the pixel forming region of the semiconductor layer by forming a pn junction, and at the interface portion of the pn junction. A first conductive type first electrode region and a second conductive type second electrode region on which a multiplying region is formed,
    A first conductive type contact region provided on the first surface side of the pixel forming region by being electrically connected to the first electrode region.
    An insulating portion provided between the contact region and the second electrode region,
    Semiconductor device with.
  2. 　前記絶縁部は、前記画素形成領域の前記第１の面側から前記第２の面側に向かって延伸し、
    　前記第１電極領域及び前記第２電極領域は、
    　前記画素形成領域の前記第１の面側から前記第２の面側に向かって配置された第１部分と、
    　前記第１部分から前記絶縁部に沿って延伸する第２部分と、
    　を有する請求項１に記載の半導体装置。     The insulating portion extends from the first surface side of the pixel forming region toward the second surface side.
    The first electrode region and the second electrode region are
    A first portion of the pixel forming region arranged from the first surface side toward the second surface side, and
    A second portion extending from the first portion along the insulating portion,
    The semiconductor device according to claim 1.
  3. 　前記第１電極領域の前記第２部分は、前記第１電極領域の前記第１部分から前記絶縁部の前記画素形成領域の前記第２の面側を越えて前記コンタクト領域に到達している、請求項２に記載の半導体装置。 The second portion of the first electrode region reaches the contact region from the first portion of the first electrode region beyond the second surface side of the pixel forming region of the insulating portion. The semiconductor device according to claim 2.
  4. 　前記第２電極領域の前記第２部分は、前記絶縁部の前記画素形成領域の前記第２の面側で終端している、請求項２に記載の半導体装置。 The semiconductor device according to claim 2, wherein the second portion of the second electrode region is terminated on the second surface side of the pixel forming region of the insulating portion.
  5. 　前記第２電極領域は、前記第１電極領域の上部側で前記第１電極領域とｐｎ接合をなしている、請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the second electrode region has a pn junction with the first electrode region on the upper side of the first electrode region.
  6. 　前記絶縁部の前記第２電極領域と接する側壁は、前記半導体層の厚さ方向に対して傾斜している、請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the side wall of the insulating portion in contact with the second electrode region is inclined with respect to the thickness direction of the semiconductor layer.
  7. 　前記絶縁部は、前記画素形成領域の前記第１の面から窪む凹部と、前記凹部内に設けられた絶縁体とを含む、請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the insulating portion includes a recess recessed from the first surface of the pixel forming region and an insulator provided in the recess.
  8. 　前記絶縁部は、平面視の形状が環状になっている、請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the insulating portion has an annular shape in a plan view.
  9. 　前記絶縁部は、平面視の形状が格子状になっている、請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the insulating portion has a grid-like shape in a plan view.
  10. 　前記コンタクト領域は、平面視の形状が環状になっている、請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the contact region has an annular shape in a plan view.
  11. 　前記コンタクト領域は、前記画素形成領域の周囲に点在している、請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the contact regions are scattered around the pixel forming region.
  12. 　前記画素形成領域は、前記半導体層の前記第１の面から深さ方向に延伸する画素間分離領域で区画されている、請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the pixel forming region is partitioned by an inter-pixel separation region extending in the depth direction from the first surface of the semiconductor layer.
  13. 　前記画素間分領域に沿って延伸し、かつ前記コンタクト領域と電気的に接続された第１導電型の電荷蓄積領域を更に備えている、請求項１２に記載の半導体装置。 The semiconductor device according to claim 12, further comprising a first conductive type charge storage region extending along the inter-pixel division region and electrically connected to the contact region.
  14. 　半導体層の第１の面側に、第１導電型の第１電極領域を形成するとともに、前記第１電極領域とｐｎ接合をなす第２導電型の第２電極領域を形成する工程と、
    　前記半導体層の前記第１の面側に、前記第１電極領域と電気的に接続する第１導電型のコンタクト領域を形成する工程と、
    　前記第２電極領域と前記コンタクト領域との間に絶縁部を形成する工程と、
    　を備える半導体装置の製造方法。     A step of forming a first conductive type first electrode region on the first surface side of the semiconductor layer and forming a second conductive type second electrode region forming a pn junction with the first electrode region.
    A step of forming a first conductive type contact region electrically connected to the first electrode region on the first surface side of the semiconductor layer.
    A step of forming an insulating portion between the second electrode region and the contact region,
    A method for manufacturing a semiconductor device.
  15. 　アバランシェフォトダイオード素子を有する画素が行列状に複数配置された画素アレイ部を備え、前記アバランシェフォトダイオード素子は、半導体層の画素形成領域の互に反対側に位置する第１の面及び第２の面のうちの前記第１の面側にｐｎ接合をなして設けられ、かつ前記ｐｎ接合の界面部にアバランシェ増倍領域が形成される第１導電型の第１電極領域及び第２導電型の第２電極領域と、前記画素形成領域の前記第１の面側に、前記第１電極領域と電気的に接続して設けられた第１導電型のコンタクト領域と、前記コンタクト領域と前記第２電極領域との間に設けられた絶縁部と、を有する半導体装置と、
    　前記画素形成領域の前記第２の面に被写体からの像光を結像させる光学系と、
    　を備える電子機器。     A pixel array portion in which a plurality of pixels having an avalanche photodiode element are arranged in a matrix is provided, and the avalanche photodiode element has a first surface and a second surface located on opposite sides of the pixel forming region of the semiconductor layer. A first conductive type first electrode region and a second conductive type, which are provided with a pn junction on the first surface side of the surface and in which an avalanche multiplier region is formed at the interface portion of the pn junction. A second electrode region, a first conductive type contact region electrically connected to the first electrode region, provided on the first surface side of the pixel forming region, the contact region, and the second electrode region. A semiconductor device having an insulating portion provided between the electrode regions and
    An optical system that forms an image light from a subject on the second surface of the pixel forming region, and
    Electronic equipment equipped with.
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Publication number Priority date Publication date Assignee Title
WO2022219516A1 (en) * 2021-04-14 2022-10-20 Fondazione Bruno Kessler A diode radiation sensor
WO2023234070A1 (en) * 2022-06-01 2023-12-07 ソニーセミコンダクタソリューションズ株式会社 Optical detection device and distance measurement device

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