WO2021057302A1 - 数字预失真实现方法、系统、可读存储介质及dpd装置 - Google Patents

数字预失真实现方法、系统、可读存储介质及dpd装置 Download PDF

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WO2021057302A1
WO2021057302A1 PCT/CN2020/108689 CN2020108689W WO2021057302A1 WO 2021057302 A1 WO2021057302 A1 WO 2021057302A1 CN 2020108689 W CN2020108689 W CN 2020108689W WO 2021057302 A1 WO2021057302 A1 WO 2021057302A1
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data
dpd
fpga
core
function core
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PCT/CN2020/108689
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English (en)
French (fr)
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陈东泉
杨亮
周建光
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中兴通讯股份有限公司
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H03F1/3241—Modifications of amplifiers to reduce non-linear distortion using predistortion circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems

Definitions

  • the present invention relates to the field of communication technology, and in particular to a digital pre-distortion (Digital Pre-Distortion, DPD) implementation method, system, readable storage medium and DPD device.
  • DPD Digital Pre-Distortion
  • the power amplifier is an indispensable device that is widely used. After the input signal amplitude exceeds its linear region, the output of the device will inevitably produce non-linear distortion, which leads to in-band signal distortion and adjacent-band signal interference. Therefore, the nonlinear distortion must be quickly and effectively controlled within a certain range to solve this problem. How to quickly and effectively control the distortion of the power amplifier is a key issue facing the industry.
  • FPGA Field-Programmable Gate Array
  • DSP-FPGA DSP-FPGA architecture
  • the embodiments of the present invention provide a digital predistortion implementation method, system, readable storage medium, and device, which aim to solve one of the related technical problems at least to a certain extent, including: high resource consumption in FPGA implementation, The problem of high power consumption, and the problem of low transmission rate and low processing efficiency under the DSP-FPGA architecture.
  • the first embodiment of the present invention provides a method for implementing digital predistortion.
  • the method includes the following steps: after the system is powered on, a fixed digital predistortion DPD function core is allocated; system functions are initialized based on the DPD function core; After the system function is initialized, data communication with the field programmable gate array FPGA is performed based on the DPD function core.
  • the second embodiment of the present invention also provides a digital predistortion realization system, which is used to allocate a fixed digital predistortion DPD function core after power-on; perform system function initialization based on the DPD function core; After initialization, data communication with the field programmable gate array FPGA is performed based on the DPD function core.
  • a digital predistortion realization system which is used to allocate a fixed digital predistortion DPD function core after power-on; perform system function initialization based on the DPD function core; After initialization, data communication with the field programmable gate array FPGA is performed based on the DPD function core.
  • the third embodiment of the present invention also provides a computer-readable storage medium that stores a program for implementing information transfer, wherein the program is executed by a processor to implement the steps of the method described in the first embodiment.
  • An embodiment of the present invention also provides a DPD device, including: a memory, a processor, and a computer program that is stored on the memory and can run on the processor.
  • a computer program that is stored on the memory and can run on the processor.
  • Fig. 1 is a schematic flow chart of an embodiment of the present invention
  • FIG. 2 is a detailed schematic diagram of the process of an embodiment of the present invention.
  • FIG. 3 is a processing flowchart of a single-core completion of DPD according to an embodiment of the present invention
  • FIG. 4 is a flowchart of DPD processing for a single core and a high-speed link according to an embodiment of the present invention
  • FIG. 5 is a schematic structural diagram of an apparatus for implementing digital predistortion according to an embodiment of the present invention.
  • the first embodiment of the present invention proposes a method for implementing digital predistortion, as shown in FIG. 1 and FIG. 2.
  • the method includes the following steps:
  • the DPD function core refers to one of the physical cores of the processor, and the number of cores refers to the physical, that is, the processor has several cores on the hardware.
  • dual-core includes two relatively independent cores.
  • Unit group, quad-core contains 4 relatively independent core unit groups.
  • assigning DPD function core is to assign one of the 16 cores of the processor as a fixed DPD Functional core.
  • the method of the embodiments of the present invention overcomes the problems of large resource consumption and high power consumption in FPGA implementation, and at the same time solves the problems of low transmission rate and low processing efficiency under the DSP-FPGA architecture, and has achieved positive technical effects.
  • the method for implementing the DPD function under the multi-core SMP architecture is used to illustrate with an example.
  • the method in the embodiment of the present invention includes the following steps:
  • Data is sent and received under the multi-core SMP architecture, and memory is planned.
  • a fixed core is allocated for the realization of DPD functions, and the initialization of related functions is completed.
  • the system when the system is powered on, the system changes the function of the core 11 of the multi-core processor from the original load sharing mode to the DPD exclusive mode; the DPD module is bound Set to the core 11 of the multi-core processor to complete the initialization of the memory application and related tasks.
  • the system After the system completes the initialization of the memory application and related tasks, it performs data communication with the field programmable gate array FPGA based on the DPD function core.
  • the method before assigning a fixed digital predistortion DPD function core, the method further includes: configuring the DPD function of the system.
  • configure the processing of data receiving and sending under the multi-core SMP architecture including configuring the kernel, completing the data receiving and processing, and placing the data in the designated memory space; defining the data structure and transceiver interface required by the DPD function .
  • an independent core is configured to complete the DPD function under the multi-core SMP architecture, including the initialization of the DPD module, including the global scheduling task, the data collection task and the meter picking task.
  • Register read and write DPD form reading and writing Trapping table read and write DPD data read Data mining configuration RAM read and write
  • FPGA completes register reading and writing, data collection and return, and table configuration functions in turn.
  • the method further includes:
  • the configuration of the data transmission format between the DPD function core and the FPGA further includes a configuration of a serial port transceiver identifier, and the serial port transceiver identifier is used for data transmission between the DPD function core and the FPGA.
  • the DPD module and the FPGA are directly connected through a serial port to complete data communication.
  • the data between the DPD module and FPGA under the multi-core SMP architecture is defined as follows:
  • the initialization of system functions based on the DPD function core includes:
  • the DPD function core reads the communication data returned by the FPGA.
  • the system kernel (such as the Linux system kernel) adds the interrupt handler of the core 11 (Core11 in the figure) to the initialization process.
  • the DPD module DPD function core
  • the core 11 fetches the data from the cache.
  • the data communication with a field programmable gate array FPGA based on the DPD function core includes:
  • the DPD function core notifies the FPGA to report data based on the data transmission format
  • the data processing result is sent to the FPGA based on the data transmission format through the DPD function core.
  • the data transmission format is a serial port transmission format or an Ethernet data format
  • the configuring the data transmission format between the DPD function core and the FPGA further includes configuring a serial port transceiver identifier, and the serial port transceiver identifier is used for data transmission between the DPD function core and the FPGA;
  • the configuration of the data transmission format between the DPD function core and the FPGA further includes a configuration of a cooperative transmission identifier, and the cooperative transmission identifier is used for data transmission of the DPD function core within the processing chip.
  • a message is sent through the serial port to inform the FPGA to report the data. After that, trigger an interrupt to core 11.
  • the DPD function core starts a timed query task. After the required data has been received, the DPD function core starts a thread to complete the DPD algorithm calculation, and then sends the calculated data to the FPGA through the serial port.
  • the processing chip MSC0 and FPGA are directly connected through the serial port, as shown in Figure 2 and Figure 3.
  • the FPGA is notified through the serial port, and the FPGA reports the data through the serial port.
  • the system kernel triggers the interrupt handler and informs the core of the DPD function core11, the core of the DPD function core11 fetches the data from the buffer BUF, and core11 starts a regular query task, after the query has received the required data , Core11 starts a thread to run the calculation program to complete the DPD algorithm calculation.
  • the selected core 11 can simulate two logical cores. That is, dual threads.
  • a thread of core11 can be selected to complete the algorithm calculation.
  • the calculated data is sent to the FPGA through the serial port. See the XC data transmission in Figure 3.
  • FPGA completes data collection and uses a defined data structure to complete data transmission and reception through a common channel (serial port).
  • a core is used to receive data and complete DPD operations.
  • the method in this example reduces the demand for FPGA resources, saves hardware resources, and improves resource utilization.
  • the second embodiment of the present invention provides a method for implementing digital predistortion, as shown in FIG. 1 and FIG. 2.
  • the method includes the following steps:
  • the DPD function core refers to one of the physical cores of the processor, and the number of cores refers to the physical, that is, the processor has several cores on the hardware.
  • dual-core includes two relatively independent cores.
  • Unit group, quad-core contains 4 relatively independent core unit groups.
  • assigning DPD function core is to assign one of the 16 cores of the processor as a fixed DPD Functional core.
  • the method of the embodiment of the present invention overcomes the problems of large resource consumption and high power consumption in FPGA implementation, and at the same time solves the problems of low transmission rate and low processing efficiency under the DSP-FPGA architecture, and has achieved positive technical effects.
  • the method for realizing the DPD function under the multi-core SMP architecture is used to illustrate with an example.
  • the method in the embodiment of the present invention includes the following steps:
  • Data is sent and received under the multi-core SMP architecture, and memory is planned.
  • a fixed core is allocated for the realization of DPD functions, and the initialization of related functions is completed.
  • the function of the core 11 of the multi-core processor is modified to transform it from the original load sharing mode to the DPD exclusive mode; the DPD module is bound to On the core 11 of the multi-core processor, the initialization of the memory application and related tasks is completed.
  • the method before assigning a fixed digital predistortion DPD function core, the method further includes: configuring the DPD function of the system.
  • configure the processing of data receiving and sending under the multi-core SMP architecture including configuring the kernel, completing the data receiving and processing, and placing the data in the designated memory space; defining the data structure and transceiver interface required by the DPD function .
  • the initialization of the DPD module includes global scheduling tasks, data collection tasks and table picking tasks, and the main data of the interaction between DPD processing and FPGA are as follows:
  • Register read and write DPD form reading and writing Trapping table read and write DPD data read Data mining configuration RAM read and write
  • FPGA completes register reading and writing, data collection and return, and table configuration functions in turn.
  • the method further includes:
  • the configuration of the data transmission format between the DPD function core and the FPGA further includes configuring a cooperative transmission identifier, the cooperative transmission identifier Used for data transmission of the DPD function core inside the chip.
  • the DPD module and FPGA under the multi-core SMP architecture adopt a high-speed path.
  • a cooperative data transmission path is used inside the chip, and a high-speed Ethernet link is used outside. road.
  • IP data format and length for the communication between DPD module and FPGA are as follows:
  • the DPD module Define the cooperative data transmission key and Link ID used by the DPD module to receive data. At present, the first 4 bytes are used in the first 32 bytes of the above cooperative data transmission.
  • the first byte is the device type.
  • multi-core processors use 0x02.
  • the second byte is the subsystem number. Currently defined as 0x71.
  • the third and fourth bytes are customized according to the extension and are currently 0x01 0x00.
  • the key value of the cooperative data transmission header is: 0x02 0x71 0x01 0x00.
  • Link ID used by DPD From the Link ID table, plan an unused space for DPD use.
  • the Link ID used in this embodiment is 0xC000.
  • the key value of the cooperative data transmission header used by the FPGA to receive data is defined as follows according to the aforementioned rules:
  • the first 9 bytes in the Payload are the interactive control information between the DPD module and the FPGA, and the next X bytes are valid data.
  • the specific structure is defined as follows:
  • Length Data length, in bytes.
  • Valid data of this package For four types of operations such as single register reading and writing, DPD table reading and writing, Trapping table reading and writing, and data acquisition configuration RAM reading and writing, the effective data length is all within 1448Byte.
  • Register read and write 2Bytes DPD form reading and writing 64*8Bytes Trapping table reading and writing 32*2Bytes Data mining configuration RAM read and write 4Bytes
  • the data length read at one time is 8192*2 bytes, which is greater than 1448 bytes, in this embodiment, it is directly divided into 1024 bytes per packet, and 16 packets are transferred in total.
  • the initialization of system functions based on the DPD function core includes:
  • the DPD function core reads the communication data returned by the FPGA.
  • the system kernel adds the interrupt processing program of the core 11 in the initialization process.
  • the DPD module DPD function core
  • the high-speed link can be an Ethernet link to inform the FPGA to report data.
  • the system kernel triggers Interrupting the processing program, the core 11 fetches data from the cache.
  • the data communication with a field programmable gate array FPGA based on the DPD function core includes:
  • the DPD function core notifies the FPGA to report data based on the data transmission format
  • the data processing result is sent to the FPGA based on the data transmission format through the DPD function core.
  • the data transmission format is a serial port transmission format or an Ethernet data format
  • the configuring the data transmission format between the DPD function core and the FPGA further includes configuring a serial port transceiver identifier, and the serial port transceiver identifier is used for data transmission between the DPD function core and the FPGA;
  • the configuration of the data transmission format between the DPD function core and the FPGA further includes a configuration of a cooperative transmission identifier, and the cooperative transmission identifier is used for data transmission of the DPD function core within the processing chip.
  • the DPD module when the DPD module needs data, it sends a message through the high-speed link (Ethernet link) to inform the FPGA to report the data; after the data is returned, it triggers an interrupt to the core 11 to start A timing query task; after the query has received the required data, a thread is started to complete the DPD algorithm calculation, and the data is sent to the FPGA after completion.
  • the high-speed link Ethernet link
  • the processing chip MSC0 when the data transmission format is the Ethernet data format, the processing chip MSC0 internally uses the cooperative transmission identifier for data transmission, and externally uses the high-speed Ethernet link.
  • a hardware switching unit SW is also provided between the processing chip MSC0 and FPGA for high-speed link communication.
  • the core 11 of the DPD function needs data, it informs the FPGA through the Ethernet link, and the FPGA uses the Ethernet link.
  • the data is reported on the road and transmitted to the transceiver interface DXGE of the processing chip MSC0, and then the transceiver interface DXGE transmits the data to the accelerator RDM/XC, and the accelerator RDM/XC puts the data into the corresponding buffer BUF according to the key value of the data for coordinated transmission Identifies the high-speed data transmission between the DPD function core, transceiver interface DXGE, accelerator RDM/XC and other chip internal structures. Then, the system kernel triggers the interrupt handler and informs the DPD function core core11, and the DPD function core core11 is taken out of the buffer BUF At the same time, core11 starts a timed query task.
  • core11 After the query has received the required data, core11 starts a thread to run the calculation program to complete the DPD algorithm calculation.
  • the selected core 11 can simulate two logic cores, that is, dual threads.
  • one thread of core 11 can be selected to complete the algorithm calculation, and the calculated data will be sent to the processing chip after completion
  • the transceiver interface DXGE of MSC0 see XC data transmission in Figure 4, and finally the system sends the data to the FPGA through the hardware switching unit SW through the transceiver interface DXGE of the processing chip MSC0.
  • FPGA completes data collection and uses the defined key value to complete the data transmission and reception processing through the high-speed path; the core under the multi-core SMP architecture receives data and completes the DPD operation, and uses the defined data transmission and reception flag to pass through the high-speed path. Send data back to FPGA for control.
  • the transmission delay can be further reduced, and the processing efficiency of DPD is improved.
  • the third embodiment of the present invention provides a digital predistortion realization system, which is used to allocate a fixed digital predistortion DPD function core after power-on;
  • system is also used to set the interrupt handler of the DPD function core
  • the DPD function core reads the communication data returned by the FPGA.
  • system is further configured to configure the data transmission format between the DPD function core and the FPGA.
  • the data transmission format is a serial port transmission format or an Ethernet data format
  • the configuring the data transmission format between the DPD function core and the FPGA further includes configuring a serial port transceiver identifier, and the serial port transceiver identifier is used for data transmission between the DPD function core and the FPGA;
  • the configuration of the data transmission format between the DPD function core and the FPGA further includes a configuration of a cooperative transmission identifier, and the cooperative transmission identifier is used for data transmission of the DPD function core within the processing chip.
  • the fourth embodiment of the present invention provides a device for implementing digital predistortion, and the device includes:
  • the core distribution module is used to distribute a fixed digital predistortion DPD function core after the system is powered on;
  • the initialization module is used to initialize the system function based on the DPD function core; after the system function is initialized, perform data communication with the field programmable gate array FPGA based on the DPD function core.
  • the core distribution module and the initialization module can be integrated in the system level, so that the above functions can be realized by the system.
  • the system modifies the function of the core 11 of the multi-core processor to transform it from the original load sharing mode to the DPD exclusive mode, and the DPD module is bound to the core of the multi-core processor.
  • the system modifies the function of the core 11 of the multi-core processor to transform it from the original load sharing mode to the DPD exclusive mode, and the DPD module is bound to the core of the multi-core processor.
  • On 11, complete the initialization of memory application and related tasks.
  • the method of the embodiment of the present invention overcomes the problems of large resource consumption and high power consumption in FPGA implementation, and at the same time solves the problems of low transmission rate and low processing efficiency under the DSP-FPGA architecture, and has achieved positive technical effects.
  • the device further includes: a configuration module for configuring the DPD function of the system.
  • the configuration module is further configured to configure a data transmission format between the DPD function core and the FPGA.
  • the data transmission format is a serial port transmission format or an Ethernet data format
  • the data transmission format is a serial port transmission format.
  • the configuration module is also configured to configure a serial port transceiver identifier, and the serial port transceiver identifier is used for data transmission between the DPD function core and the FPGA.
  • serial port transceiver data format is defined between the DPD module and the FPGA under the multi-core SMP architecture for data transceiver transmission, and the configuration module can also be integrated in the system level.
  • the initialization module is further configured to set an interrupt handler based on the DPD function core;
  • the DPD function core reads the communication data returned by the FPGA.
  • the data communication with a field programmable gate array FPGA based on the DPD function core includes:
  • the DPD function core notifies the FPGA to report data based on the data transmission format
  • the data processing result is sent to the FPGA based on the data transmission format through the DPD function core.
  • the management module of the system adds the interrupt handler of the core 11 to the initialization process.
  • the DPD module needs data, it sends a message through the low-speed link (serial port) to inform the FPGA to report the data; after the data is returned, it triggers an interrupt to the core 11 to start a regular query task; after the query has received the required data After that, start a thread to complete the DPD algorithm calculation, and send the data to the FPGA after completion.
  • the core distribution module, the initialization module, and the configuration module can all be integrated in the system level, and the processing chip MSC0 and FPGA are directly connected through a serial port, as shown in Figure 2 and Figure 3, in the core 11
  • the FPGA is notified through the serial port.
  • the FPGA reports the data through the serial port and transmits it to the buffer BUF of the processing chip.
  • the system kernel triggers the interrupt handler and notifies the DPD function core core11.
  • the DPD function core core11 fetches the data from the buffer BUF, and at the same time core11 starts a timed query task. After the required data has been received, core11 starts a thread to run the calculation program to complete the DPD algorithm calculation.
  • a certain processor has 16 cores. 32 threads, the selected core 11 can simulate two logic cores, that is, dual threads. During operation, one thread of core 11 can be used to complete the algorithm calculation. After completion, the calculated data is sent to the FPGA through the serial port. See XC data transmission in Figure 3.
  • the fifth embodiment of the present invention provides a device for implementing digital predistortion, and the device includes:
  • the core distribution module is used to distribute a fixed digital predistortion DPD function core after the system is powered on;
  • the initialization module is used to initialize system functions based on the DPD function core
  • the core distribution module and the initialization module can be integrated into the system (for example, Linux system) level, so as to realize the above-mentioned functions through the system.
  • system for example, Linux system
  • the method of the embodiment of the present invention overcomes the problems of large resource consumption and high power consumption in FPGA implementation, and at the same time solves the problems of low transmission rate and low processing efficiency under the DSP-FPGA architecture, and has achieved positive technical effects.
  • the device further includes: a configuration module for configuring the DPD function of the system.
  • the configuration module is further configured to configure a data transmission format between the DPD function core and the FPGA.
  • the data transmission format is an Ethernet data format.
  • the configuration module is also configured to configure a cooperative transmission identifier, and the cooperative transmission identifier is used for data transmission of the DPD function core inside the chip.
  • a data format of the Ethernet standard is defined, and a cooperative data transmission field is added for data transmission and reception.
  • the initialization module is further configured to set an interrupt handler based on the DPD function core;
  • the DPD function core reads the communication data returned by the FPGA.
  • the data communication with a field programmable gate array FPGA based on the DPD function core includes:
  • the DPD function core notifies the FPGA to report data based on the data transmission format
  • the data processing result is sent to the FPGA based on the data transmission format through the DPD function core.
  • the core distribution module, the initialization module, and the configuration module can all be integrated into the system level, and the processing chip MSC0 performs data transmission through the cooperative transmission identifier.
  • the high-speed Ethernet link is used externally.
  • a hardware switching unit SW is also provided between the processing chip MSC0 and FPGA.
  • the Ethernet link Road informs the FPGA that the FPGA reports data through the Ethernet link and transmits it to the transceiver interface DXGE of the processing chip MSC0, and then the transceiver interface DXGE transmits the data to the accelerator RDM/XC, and the accelerator RDM/XC releases the data according to the key value of the data.
  • the cooperative transmission identifier is used for the high-speed data transmission between the DPD function core, the transceiver interface DXGE, the accelerator RDM/XC and other chip internal structures.
  • the system kernel triggers the interrupt program and informs the DPD function core core11, DPD
  • DPD DPD
  • the functional core core11 fetches data from the cache BUF, and core11 starts a timed query task. After the query has received the required data, core11 starts a thread to run the calculation program to complete the DPD algorithm calculation.
  • the selected core 11 can simulate two logical cores, that is, dual threads. In operation, one thread of core 11 can be used to complete the algorithm calculation.
  • transceiver interface DXGE accelerator RDM/XC and buffer BUF can also be integrated into the processing chip MCS0.
  • the data transmission format is an Ethernet data format
  • the function of the processor core 11 is modified to share the original load.
  • the mode is changed to DPD exclusive mode, and the external data communication with FPGA is realized through the hardware switching unit SW.
  • the management module of the system adds the interrupt handler of the core 11 to the initialization process.
  • the DPD module needs data, it sends a message through the high-speed link (Ethernet link) to inform the FPGA to report the data; after the data is returned, it triggers an interrupt to the core 11 to start a regular query task; After the data has been received, start a thread to complete the DPD algorithm calculation, and send the data to the FPGA after completion.
  • the high-speed link Ethernet link
  • the sixth embodiment of the present invention provides a computer-readable storage medium that stores a program for implementing information transfer, where the program is executed by a processor to implement the steps of the method of the first embodiment or the second embodiment.
  • the seventh embodiment of the present invention proposes a DPD device, including: a memory 51, a processor 52, and a computer program stored on the memory 51 and running on the processor 52, wherein the When the computer program is executed by the processor 52, the steps of the method of the first embodiment or the second embodiment are implemented.
  • the embodiment of the present invention allocates a fixed digital predistortion DPD function, and performs system function initialization based on the DPD function. After the system function is initialized, data communication with the field programmable gate array FPGA is performed based on the DPD function core.
  • the technical solution of the present invention can be embodied in the form of a software product in essence or a part that contributes to related technologies.
  • the computer software product is stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk). ) Includes several instructions to make a terminal (which can be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) execute the method described in each embodiment of the present invention.

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Abstract

一种数字预失真实现方法、系统、可读存储介质及DPD装置，所述方法包括如下步骤：在系统上电后，分配一固定数字预失真DPD功能核心；基于所述DPD功能核心进行系统功能初始化；在系统功能初始化后，基于所述DPD功能核心进行与现场可编程门阵列FPGA之间的数据通信。

Description

数字预失真实现方法、系统、可读存储介质及DPD装置
相关申请的交叉引用
本申请基于申请号为201910930125.7、申请日为2019年09月29日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本发明涉及通信技术领域，尤其涉及一种数字预失真(Digital Pre-Distortion，DPD)实现方法、系统、可读存储介质及DPD装置。
背景技术
在通信系统中，功率放大器是大量使用且不可或缺的一个器件。该器件在输入信号幅度超出其线性区后，其输出就不可避免地产生非线性失真，从而导致信号带内失真和邻带信号干扰。因此，必须把非线性失真快速有效地控制在一定的范围内，才能解决此问题。如何快速有效地控制功放的失真，是目前业界面临的一个关键性问题。
业界目前通用的系统方法，主要分为两类，一类是基于FPGA(Field-Programmable Gate Array，现场可编程门阵列)实现数据采集、DPD算法及控制输出；另一类是DSP-FPGA架构，FPGA实现数据采集，传输数据到DSP(Digital Signal Processing，数字信号处理)完成DPD算法处理，然后DSP再把数据回传给FPGA，控制输出。
但现有的硬件方案的缺陷如下：随着天线数增多，对资源需求越大，成本提高。
发明内容
有鉴于此，本发明实施例提供一种数字预失真实现方法、系统、可读存储介质及装置，旨在至少在一定程度上解决相关的技术问题之一，包括：FPGA实现中资源消耗大、功耗大的问题，以及DSP-FPGA架构下传输速率低、处理效率低的问题。
本发明第一实施例提出一种数字预失真实现方法，所述方法包括如下步骤：在系统上电后，分配一固定数字预失真DPD功能核心；基于所述DPD功能核心进行系统功能初始化；在系统功能初始化后，基于所述DPD功能核心进行与现场可编程门阵列FPGA之间的数据通信。
本发明第二实施例还提出一种数字预失真实现系统，所述系统用于在上电后，分配一固定数字预失真DPD功能核心；基于所述DPD功能核心进行系统功能初始化；在系统功能初始化后，基于所述DPD功能核心进行与现场可编程门阵列FPGA之间的数据通信。
本发明第三实施例还提出一种计算机可读存储介质，存储有信息传递的实现程序，其中，所述程序被处理器执行时实现如第一实施例所述的方法的步骤。
本发明实施例还提出一种DPD装置，包括：存储器、处理器及存储在所述存储器上并可在所述处理器上运行的计算机程序，其中，所述计算机程序被所述处理器执行时实现如第一实施例所述的方法的步骤。
附图说明
图1为本发明实施例流程示意图；
图2为本发明实施例流程细节示意图；
图3为本发明实施例单核完成DPD的处理流程图；
图4为本发明实施例单核与高速链路的DPD处理流程图；
图5为本发明实施例的数字预失真实现装置的结构示意图。
具体实施方式
下面将参照附图更详细地描述本发明的示例性实施例。虽然附图中显示了本发明的示例性实施例，然而应当理解，可以以各种形式实现本发明而不应被这里阐述的实施例所限制。相反，提供这些实施例是为了能够更透彻地理解本发明，并且能够将本发明的范围完整的传达给本领域的技术人员。
本发明第一实施例提出一种数字预失真实现方法，如图1、图2所示，所述方法包括如下步骤：
S101，在系统上电后，分配一固定数字预失真DPD功能核心；
S102，基于所述DPD功能核心进行系统功能初始化；
S103，在系统功能初始化后，基于所述DPD功能核心进行与现场可编程门阵列FPGA之间的数据通信。
在本实施例中，所述DPD功能核心是指处理器的物理核心之一，核心数是指物理上，也就是硬件上处理器存在几个核心，比如，双核就是包括2个相对独立的核心单元组，四核就包含4个相对独立的核心单元组，再例如，某处理器为16核32线程，则分配DPD功能核心也即将处理器的16个核心之一分配一个来作为固定的DPD功能核心。
通过上述技术方案本发明实施例的方法克服了FPGA实现中资源消耗大、功耗大问题，同时还解决了DSP-FPGA架构下传输速率低、处理效率低的问题，取得了积极的技术效果。
在本实施例中，通过多核SMP架构下实现DPD功能的方法，进行举例说明，本发明实施例方法包括如下步骤：
在多核SMP架构下进行数据的收发处理，并规划内存。
在多核SMP架构下分配一个固定的核用于DPD的功能实现，并完成相关功能的初始化。
规划FPGA数据处理流程。
具体的说，在本实施例中，如图2所示，系统上电中，系统通过修改多核处理器的核11的功能，使其从原有负荷分担模式转变为DPD独占模式；DPD模块绑定到多核处理器的核11上，完成内存申请及相关任务的初始化。
在系统完成内存申请及相关任务的初始化后，基于所述DPD功能核心进行与现场可编程门阵列FPGA之间的数据通信。
可选的，在本发明一个可选的实施例中，在分配一固定数字预失真DPD功能核心之前，所述方法还包括：配置系统的DPD功能。
具体的说，配置多核SMP架构下数据接收与发送的处理，包括，配置内核，完成该数据的接收处理，并把数据放到指定的内存空间中；定义DPD功能所需的数据结构及收发接口。
在配置完成之后，在多核SMP架构下配置一个独立核心完成DPD的功能，包括DPD模块的初始化，包括全局调度任务，采数任务与提表任务。
DPD处理与FPGA交互的主要数据如下：
寄存器读写
DPD表格读写
Trapping表格读写
DPD数据读
采数配置RAM读写
FPGA根据DPD模块的消息控制字，依次完成寄存器的读写，数据的采集回传与表格配置功能。
可选的，在所述基于所述DPD功能核心进行与现场可编程门阵列FPGA之间的数据通信之前，所述方法还包括：
配置所述DPD功能核心与所述FPGA之间的数据传输格式。
所述配置所述DPD功能核心与所述FPGA之间的数据传输格式，还包括配置串口收发标识，所述串口收发标识用于所述DPD功能核心与所述FPGA的数据传输。
具体的说，在本实施例中，如图3所示，多核SMP架构下，DPD模块与FPGA之间通过串口直连，完成数据通信。
在本实施例中，多核SMP架构下DPD模块与FPGA之间数据定义如下：
数据起始 读写控制 读写条目 负载 数据结束
0x5a5a 2Byte 2Byte 1448Byte 0xa5a5
可选的，在本发明一个可选的实施例中，所述基于所述DPD功能核心进行系统功能初始化，包括：
基于所述DPD功能核心设置中断处理程序；
在中断处理程序触发后，所述DPD功能核心读取所述FPGA回传的通信数据。
如图3所示，在本实施例中，系统内核(例如Linux系统内核)在初始化流程中增加核11(图中的Core11)的中断处理程序。DPD模块(DPD功能核心)在需要数据时，通过低速链路(串口)下发一个消息，告知FPGA上报数据，在中断处理程序触发后，核11从缓存中取出数据。
可选的，在本发明又一个可选的实施例中，所述基于所述DPD功能核心进行与现场可编程门阵列FPGA之间的数据通信包括：
DPD功能核心基于所述数据传输格式通知FPGA上报数据；
通过所述中断处理程序将所述FPGA回传的通信数据截取到所述DPD功能核心；
通过所述DPD功能核心根据所述通信数据进行数据处理；
通过所述DPD功能核心将数据处理结果基于所述数据传输格式发送至所述FPGA。
在某些实施例中，所述数据传输格式为串口传输格式或者以太网数据格式；
在所述数据传输格式为串口传输格式的情况下：
所述配置所述DPD功能核心与所述FPGA之间的数据传输格式，还包括配置串口收发标识，所述串口收发标识用于所述DPD功能核心与所述FPGA的数据传输；
在所述数据传输格式为以太网数据格式的情况下：
所述配置所述DPD功能核心与所述FPGA之间的数据传输格式，还包括配置协同传输标识，所述协同传输标识用于所述DPD功能核心在处理芯片内部的数据传输。
具体的说，在上述DPD功能核心与FPGA之间的数据传输格式配置完成后，在本实施例中，在DPD模块需要数据时，通过串口下发一个消息，告知FPGA上报数据，在数据回传后，触发中断到核11。DPD功能核心启动一个定时查询任务，在查询到所需数据已经收到后，DPD功能核心启动一个线程完成DPD算法计算，完成后把计算完成的数据通过串口发送给FPGA。
更进一步说，在本实施例中，处理芯片MSC0与FPGA之间通过串口直连，如图2、 图3所示，在DPD功能核心core11需要数据时，通过串口告知FPGA，FPGA通过串口上报数据，并传输到缓存BUF中，系统内核触发中断处理程序并通知DPD功能核心core11，DPD功能核心core11从缓存BUF中取出数据，同时core11启动一个定时查询任务，在查询到所需数据已经收到后，core11启动一个线程来运行计算程序从而完成DPD算法计算，在前述实施例的基础上，进一步说明，例如某处理器为16核32线程，则选定的核11可以模拟出两个逻辑核心，也即双线程，在运行中，可以选用core11的一个线程来完成算法计算，完成后把计算完成的数据通过串口发送给FPGA，参见图3中的XC数据发送。
在现有系统的基础上，本实施例中，FPGA完成数据采集，并使用定义的数据结构，通过普通通路(串口)完成数据收发处理，多核SMP架构下采用一个核接收数据，完成DPD的运算，使用定义的数据收发标志，通过低速通路回传数据到FPGA用于控制。
与一些情况相比，本实例方法降低了对FPGA资源的需求，节省了硬件资源，提高了资源利用率。
本发明第二实施例提出一种数字预失真实现方法，如图1、图2所示，所述方法包括如下步骤：
S101，在系统上电后，分配一固定数字预失真DPD功能核心；
S102，基于所述DPD功能核心进行系统功能初始化；
S103，在系统功能初始化后，基于所述DPD功能核心进行与现场可编程门阵列FPGA之间的数据通信。
在本实施例中，所述DPD功能核心是指处理器的物理核心之一，核心数是指物理上，也就是硬件上处理器存在几个核心，比如，双核就是包括2个相对独立的核心单元组，四核就包含4个相对独立的核心单元组，再例如，某处理器为16核32线程，则分配DPD功能核心也即将处理器的16个核心之一分配一个来作为固定的DPD功能核心。
通过上述技术方案本发明实施例方法克服了FPGA实现中资源消耗大、功耗大问题，同时还解决了DSP-FPGA架构下传输速率低、处理效率低的问题，取得了积极的技术效果。
在本实施例中，通过多核SMP架构下实现DPD功能的方法，进行举例说明，本发明实施例方法包括如下步骤：
在多核SMP架构下进行数据的收发处理，并规划内存。
在多核SMP架构下分配一个固定的核用于DPD的功能实现，并完成相关功能的初始化。
规划FPGA数据处理流程。
具体的说，在本实施例中，如图2所示，系统上电中，修改多核处理器的核11的功能， 使其从原有负荷分担模式转变为DPD独占模式；DPD模块绑定到多核处理器的核11上，完成内存申请及相关任务的初始化。
在完成内存申请及相关任务的初始化后，基于所述DPD功能核心进行与现场可编程门阵列FPGA之间的数据通信。
可选的，在本发明一个可选的实施例中，在分配一固定数字预失真DPD功能核心之前，所述方法还包括：配置系统的DPD功能。
具体的说，配置多核SMP架构下数据接收与发送的处理，包括，配置内核，完成该数据的接收处理，并把数据放到指定的内存空间中；定义DPD功能所需的数据结构及收发接口。
在配置完成之后，在多核SMP架构下配置一个独立核完成DPD的功能，DPD模块的初始化，包括全局调度任务，采数任务与提表任务，DPD处理与FPGA交互的主要数据如下：
寄存器读写
DPD表格读写
Trapping表格读写
DPD数据读
采数配置RAM读写
FPGA根据DPD模块的消息控制字，依次完成寄存器的读写，数据的采集回传与表格配置功能。
可选的，在所述基于所述DPD功能核心进行与现场可编程门阵列FPGA之间的数据通信之前，所述方法还包括：
配置所述DPD功能核心与所述FPGA之间的数据传输格式。
在本实施例中，所述数据传输格式为以太网数据格式的情况，所述配置所述DPD功能核心与所述FPGA之间的数据传输格式，还包括配置协同传输标识，所述协同传输标识用于所述DPD功能核心在芯片内部的数据传输。
具体的说，在本实施例中，多核SMP架构下DPD模块与FPGA采用高速通路，如图4所示，多核DPD模块与FPGA之间，芯片内部使用协同数据传输通路，外部使用高速以太网链路。
FPGA与多核SMP架构DPD功能之间数据定义如下。
DPD模块与FPGA通信的一个IP数据格式及长度如下：
MAC Header IP Header Key Header Payload
14Byte 20Byte 32Byte 1448Byte
定义DPD模块接收数据使用的协同数据传输键值及Link ID。目前在上面协同数据传输头32个字节中使用了前面4个字节。
第一个字节为设备类型。目前多核处理器通一使用0x02。
第二个字节为子系统号。目前定义为0x71。
第三与第四个字节，根据扩展，自定义，目前为0x01 0x00。
所以协同数据传输头键值是：0x02 0x71 0x01 0x00。
DPD使用的Link ID。从Link ID表中，规划一个未使用的空间，供DPD使用，例如在本实施例中使用的Link ID为0xC000。
FPGA接收数据使用的协同数据传输头键值，根据前述规则定义为：
0x02 0x72 0x01 0x00
Payload中前9个字节为DPD模块和FPGA之间的交互控制信息，后面X个字节为有效数据。具体结构定义如下：
Figure PCTCN2020108689-appb-000001
Command：0表示读，1表示写。
Address：寄存器或RAM访问首地址。
Length：数据长度，以字节为单位。
该包有效数据：对于单个寄存器读写、DPD表格读写、Trapping表格读写、采数配置RAM读写四类操作，有效数据长度均在1448Byte之内。
寄存器读、写 2Bytes
DPD表格读、写 64*8Bytes
Trapping表格读、写 32*2Bytes
采数配置RAM读、写 4Bytes
DPD数据读的操作，由于一次读取的数据长度为8192*2字节，大于1448字节，因此本实施例中直接均分成每包1024字节，共传递16包完成。
需求 数据长度
DPD数据读 1024Bytes*16包
可选的，所述基于所述DPD功能核心进行系统功能初始化，包括：
基于所述DPD功能核心设置中断处理程序；
在中断处理程序触发后，所述DPD功能核心读取所述FPGA回传的通信数据。
如图4所示，在本实施例中，系统内核在初始化流程中增加核11的中断处理程序。DPD模块(DPD功能核心)在需要数据时，通过高速链路下发一个消息，在本实施例中高速链路可以是以太网链路，告知FPGA上报数据，在数据回传后，系统内核触发中断处理程序，核11从缓存中取出数据。
可选的，在本发明一个可选的实施例中，所述基于所述DPD功能核心进行与现场可编程门阵列FPGA之间的数据通信包括：
DPD功能核心基于所述数据传输格式通知FPGA上报数据；
通过所述中断处理程序将所述FPGA回传的通信数据截取到所述DPD功能核心；
通过所述DPD功能核心根据所述通信数据进行数据处理；
通过所述DPD功能核心将数据处理结果基于所述数据传输格式发送至所述FPGA。
在某些实施例中，所述数据传输格式为串口传输格式或者以太网数据格式；
在所述数据传输格式为串口传输格式的情况下：
所述配置所述DPD功能核心与所述FPGA之间的数据传输格式，还包括配置串口收发标识，所述串口收发标识用于所述DPD功能核心与所述FPGA的数据传输；
在所述数据传输格式为以太网数据格式的情况下：
所述配置所述DPD功能核心与所述FPGA之间的数据传输格式，还包括配置协同传输标识，所述协同传输标识用于所述DPD功能核心在处理芯片内部的数据传输。
具体的说，在本实施例中，DPD模块在需要数据时，通过高速链路(以太网链路)下发一个消息，告知FPGA上报数据；在数据回传后，触发中断到核11，启动一个定时查询任务；在查询到所需数据已经收到后，启动一个线程完成DPD算法计算，完成后把数据发送给FPGA。
更进一步说，在本实施例中，数据传输格式为以太网数据格式的情况，处理芯片MSC0内部通过协同传输标识进行数据传输，外部通过使用高速以太网链路，在本实施例中，如图2、图4所示，处理芯片MSC0与FPGA之间还设置有硬件交换单元SW用于高速链路通信，在DPD功能核心core11需要数据时，通过以太网链路告知FPGA，FPGA通过以太网链路上报数据，并传输到处理芯片MSC0的收发接口DXGE，然后收发接口DXGE将数据传输至加速器RDM/XC中，加速器RDM/XC根据数据的key值将数据放到对应的缓存 BUF中，协同传输标识用于DPD功能核心、收发接口DXGE、加速器RDM/XC等芯片内部结构之间的数据高速传输，然后，系统内核触发中断处理程序并通知DPD功能核心core11，DPD功能核心core11从缓存BUF中取出数据，同时core11启动一个定时查询任务，在查询到所需数据已经收到后，core11启动一个线程来运行计算程序从而完成DPD算法计算，在前述实施例的基础上，进一步说明，例如某处理器为16核32线程，则选定的核11可以模拟出两个逻辑核心，也即双线程，在运行中，可以选用core11的一个线程来完成算法计算，完成后把计算完成的数据发送处理芯片MSC0的收发接口DXGE，参见图4中的XC数据发送，最后系统通过处理芯片MSC0的收发接口DXGE将数据通过硬件交换单元SW发送给FPGA。
在本实施例中，FPGA完成数据采集，并使用定义的键值，通过高速通路完成数据收发处理；多核SMP架构下一个核接收数据，完成DPD的运算，使用定义的数据收发标志，通过高速通路回传数据到FPGA用于控制。与第一实施例相比，可以进一步减少传输时延，提供了DPD的处理效率。
本发明第三实施例提出了一种数字预失真实现系统，所述系统用于在上电后，分配一固定数字预失真DPD功能核心；
基于所述DPD功能核心进行系统功能初始化；
在系统功能初始化后，基于所述DPD功能核心进行与现场可编程门阵列FPGA之间的数据通信。
在某些实施例中，所述系统，还用于设置所述DPD功能核心的中断处理程序；
在中断处理程序触发后，所述DPD功能核心读取所述FPGA回传的通信数据。
在某些实施例中，所述系统，还用于配置所述DPD功能核心与所述FPGA之间的数据传输格式。
在某些实施例中，所述数据传输格式为串口传输格式或者以太网数据格式；
在所述数据传输格式为串口传输格式的情况下：
所述配置所述DPD功能核心与所述FPGA之间的数据传输格式，还包括配置串口收发标识，所述串口收发标识用于所述DPD功能核心与所述FPGA的数据传输；
在所述数据传输格式为以太网数据格式的情况下：
所述配置所述DPD功能核心与所述FPGA之间的数据传输格式，还包括配置协同传输标识，所述协同传输标识用于所述DPD功能核心在处理芯片内部的数据传输。
本发明第四实施例提出一种数字预失真实现装置，所述装置包括：
核心分配模块，用于在系统上电后，分配一固定数字预失真DPD功能核心；
初始化模块，用于基于所述DPD功能核心进行系统功能初始化；在系统功能初始化后，基于所述DPD功能核心进行与现场可编程门阵列FPGA之间的数据通信。
在本实施例中，参见图3，核心分配模块与初始化模块可以整合在系统层级中，从而通过系统来实现上述功能。
具体的说，如图2所示，系统上电中，系统修改多核处理器的核11的功能，使其从原有负荷分担模式转变为DPD独占模式，DPD模块绑定到多核处理器的核11上，完成内存申请及相关任务的初始化。
通过上述技术方案本发明实施例方法克服了FPGA实现中资源消耗大、功耗大问题，同时还解决了DSP-FPGA架构下传输速率低、处理效率低的问题，取得了积极的技术效果。
可选的，所述装置还包括：配置模块，用于配置系统的DPD功能。
可选的，所述配置模块还用于，配置所述DPD功能核心与所述FPGA之间的数据传输格式。
其中，可选的，所述数据传输格式为串口传输格式或者以太网数据格式；
在本发明一个可选的实施例中，所述数据传输格式为串口传输格式。
所述配置模块，还用于配置串口收发标识，所述串口收发标识用于所述DPD功能核心与所述FPGA的数据传输。
具体的说，在本实施例中，在多核SMP架构下DPD模块与FPGA之间，定义串口收发数据格式，用于数据收发传输，配置模块也可以整合在系统层级中。
可选的，所述初始化模块，还用于基于所述DPD功能核心设置中断处理程序；
在中断处理程序触发后，所述DPD功能核心读取所述FPGA回传的通信数据。
可选的，所述基于所述DPD功能核心进行与现场可编程门阵列FPGA之间的数据通信包括：
DPD功能核心基于所述数据传输格式通知FPGA上报数据；
在中断处理程序触发后，通过DPD功能核心读取所述FPGA回传的通信数据；
通过所述DPD功能核心根据所述通信数据进行数据处理；
通过所述DPD功能核心将数据处理结果基于所述数据传输格式发送至所述FPGA。
具体的说，系统的管理模块在初始化流程中增加核11的中断处理程序。DPD模块在需要数据时，通过低速链路(串口)下发一个消息，告知FPGA上报数据；在数据回传后，触发中断到核11，启动一个定时查询任务；在查询到所需数据已经收到后，启动一个线程完成DPD算法计算，完成后把数据发送给FPGA。
更进一步说，在本实施例中，核心分配模块、初始化模块和配置模块均可以整合系统层级内，处理芯片MSC0与FPGA之间通过串口直连，如图2、图3所示，在核11需要数据时，通过串口告知FPGA，FPGA通过串口上报数据，并传输到处理芯片的缓存BUF中，系统内核触发中断处理程序并通知DPD功能核心core11，DPD功能核心core11从缓存BUF中取出数据，同时core11启动一个定时查询任务，在查询到所需数据已经收到后，core11启动一个线程来运行计算程序从而完成DPD算法计算，在前述实施例的基础上，进一步说明，例如某处理器为16核32线程，则选定的核11可以模拟出两个逻辑核心，也即双线程，在运行中，可以选用core11的一个线程来完成算法计算，完成后把计算完成的数据通过串口发送给FPGA，参见图3中的XC数据发送。
本发明第五实施例提出一种数字预失真实现装置，所述装置包括：
核心分配模块，用于在系统上电后，分配一固定数字预失真DPD功能核心；
初始化模块，用于基于所述DPD功能核心进行系统功能初始化；
在系统功能初始化后，基于所述DPD功能核心进行与现场可编程门阵列FPGA之间的数据通信。
在本实施例中，参见图4，核心分配模块与初始化模块可以整合到系统(例如Linux系统)层级内，从而通过系统来实现上述功能。
具体的说，如图2所示，系统上电中，修改多核处理器的核11的功能，使其从原有负荷分担模式转变为DPD独占模式，DPD模块绑定到多核处理器的核11上，完成内存申请及相关任务的初始化。
通过上述技术方案本发明实施例方法克服了FPGA实现中资源消耗大、功耗大问题，同时还解决了DSP-FPGA架构下传输速率低、处理效率低的问题，取得了积极的技术效果。
可选的，所述装置还包括：配置模块，用于配置系统的DPD功能。
可选的，所述配置模块还用于，配置所述DPD功能核心与所述FPGA之间的数据传输格式。
在本发明一个可选的实施例中，所述数据传输格式为以太网数据格式。
所述配置模块，还用于配置协同传输标识，所述协同传输标识用于所述DPD功能核心在芯片内部的数据传输。
在本实施例中，在多核SMP架构下DPD模块与FPGA之间，定义以太网标准的数据格式，增加协同数据传输字段，用于数据的收发传输。
可选的，所述初始化模块，还用于基于所述DPD功能核心设置中断处理程序；
在中断处理程序触发后，所述DPD功能核心读取所述FPGA回传的通信数据。
可选的，所述基于所述DPD功能核心进行与现场可编程门阵列FPGA之间的数据通信包括：
DPD功能核心基于所述数据传输格式通知FPGA上报数据；
在中断处理程序触发后，通过DPD功能核心读取所述FPGA回传的通信数据；
通过所述DPD功能核心根据所述通信数据进行数据处理；
通过所述DPD功能核心将数据处理结果基于所述数据传输格式发送至所述FPGA。
更进一步说，数据传输格式为以太网数据格式的情况，在本实施例中，核心分配模块、初始化模块和配置模块均可以整合到系统层级内，处理芯片MSC0内部通过协同传输标识进行数据传输，外部通过使用高速以太网链路，在本实施例中，如图2、图4所示，处理芯片MSC0与FPGA之间还设置有硬件交换单元SW，在核11需要数据时，通过以太网链路告知FPGA，FPGA通过以太网链路上报数据，并传输到处理芯片MSC0的收发接口DXGE，然后收发接口DXGE将数据传输至加速器RDM/XC中，加速器RDM/XC根据数据的key值将数据放到对应的缓存BUF中，协同传输标识用于DPD功能核心、收发接口DXGE、加速器RDM/XC等芯片内部结构之间的数据高速传输，然后，系统内核触发中断程序并通知DPD功能核心core11，DPD功能核心core11从缓存BUF中取出数据，同时core11启动一个定时查询任务，在查询到所需数据已经收到后，core11启动一个线程来运行计算程序从而完成DPD算法计算，在前述实施例的基础上，进一步说明，例如某处理器为16核32线程，则选定的核11可以模拟出两个逻辑核心，也即双线程，在运行中，可以选用core11的一个线程来完成算法计算，完成后把计算完成的数据发送处理芯片MSC0的收发接口DXGE，参见图4中的XC数据发送，最后处理芯片MSC0的收发接口DXGE将数据通过硬件交换单元SW发送给FPGA。
上述收发接口DXGE，加速器RDM/XC及缓存BUF也可以整合到处理芯片MCS0内，在数据传输格式为以太网数据格式的情况，通过修改处理器的核11的功能，使其从原有负荷分担模式转变为DPD独占模式，外部通过硬件交换单元SW实现与FPGA之间的数据通信。
在本实施例中，系统的管理模块在初始化流程中增加核11的中断处理程序。DPD模块在需要数据时，通过高速链路(以太网链路)下发一个消息，告知FPGA上报数据；在数据回传后，触发中断到核11，启动一个定时查询任务；在查询到所需数据已经收到后，启动一个线程完成DPD算法计算，完成后把数据发送给FPGA。
本发明第六实施例提出一种计算机可读存储介质，存储有信息传递的实现程序，其中，所述程序被处理器执行时实现第一实施例或第二实施例的方法的步骤。
参见图5，本发明第七实施例提出一种DPD装置，包括：存储器51、处理器52及存储在所述存储器51上并可在所述处理器52上运行的计算机程序，其中，所述计算机程序被所述处理器52执行时实现第一实施例或第二实施例的方法的步骤。
本发明实施例通过分配一固定数字预失真DPD功能，并基于所述DPD功能进行系统功能初始化，在系统功能初始化后，基于所述DPD功能核心进行与现场可编程门阵列FPGA之间的数据通信，克服FPGA实现中资源消耗大、功耗大问题，同时还解决了DSP-FPGA架构下传输速率低、处理效率低的问题，取得了积极的技术效果。
需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。
上述本发明实施例序号仅仅为了描述，不代表实施例的优劣。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到上述实施例方法可借助软件加必需的通用硬件平台的方式来实现，当然也可以通过硬件，但很多情况下前者是更佳的实施方式。基于这样的理解，本发明的技术方案本质上或者说对相关技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质(如ROM/RAM、磁碟、光盘)中，包括若干指令用以使得一台终端(可以是手机，计算机，服务器，空调器，或者网络设备等)执行本发明各个实施例所述的方法。
上面结合附图对本发明的实施例进行了描述，但是本发明并不局限于上述的具体实施方式，上述的具体实施方式仅仅是示意性的，而不是限制性的，本领域的普通技术人员在本发明的启示下，在不脱离本发明宗旨和权利要求所保护的范围情况下，还可做出很多形式，这些均属于本发明的保护之内。

Claims (12)

  1. 一种数字预失真实现方法，包括如下步骤：
    在系统上电后，分配一固定数字预失真DPD功能核心；
    基于所述DPD功能核心进行系统功能初始化；
    在系统功能初始化后，基于所述DPD功能核心进行与现场可编程门阵列FPGA之间的数据通信。
  2. 根据权利要求1所述的方法，在分配一固定数字预失真DPD功能核心之前，还包括：配置系统的DPD功能。
  3. 根据权利要求1所述的方法，其中，所述基于所述DPD功能核心进行系统功能初始化，包括：
    设置所述DPD功能核心的中断处理程序；
    在中断处理程序触发后，所述DPD功能核心读取所述FPGA回传的通信数据。
  4. 根据权利要求3所述的方法，在所述基于所述DPD功能核心进行与现场可编程门阵列FPGA之间的数据通信之前，还包括：
    配置所述DPD功能核心与所述FPGA之间的数据传输格式。
  5. 根据权利要求4所述的方法，其中，所述基于所述DPD功能核心进行与现场可编程门阵列FPGA之间的数据通信包括：
    DPD功能核心基于所述数据传输格式通知FPGA上报数据；
    在中断处理程序触发后，通过所述DPD功能核心读取所述FPGA回传的通信数据；
    通过所述DPD功能核心根据所述通信数据进行数据处理；
    通过所述DPD功能核心将数据处理结果基于所述数据传输格式发送至所述FPGA。
  6. 根据权利要求4所述的方法，其中，所述数据传输格式为串口传输格式或者以太网数据格式；
    在所述数据传输格式为串口传输格式的情况下：
    所述配置所述DPD功能核心与所述FPGA之间的数据传输格式，还包括配置串口收发标识，所述串口收发标识用于所述DPD功能核心与所述FPGA的数据传输；
    在所述数据传输格式为以太网数据格式的情况下：
    所述配置所述DPD功能核心与所述FPGA之间的数据传输格式，还包括配置协同传输标识，所述协同传输标识用于所述DPD功能核心在处理芯片内部的数据传输。
  7. 一种数字预失真实现系统，用于在上电后，分配一固定数字预失真DPD功能核心；
    基于所述DPD功能核心进行系统功能初始化；
    在系统功能初始化后，基于所述DPD功能核心进行与现场可编程门阵列FPGA之间 的数据通信。
  8. 如权利要求7所述的系统，还用于设置所述DPD功能核心的中断处理程序；
    在中断处理程序触发后，所述DPD功能核心读取所述FPGA回传的通信数据。
  9. 如权利要求7所述的系统，还用于配置所述DPD功能核心与所述FPGA之间的数据传输格式。
  10. 如权利要求9所述的系统，其中，所述数据传输格式为串口传输格式或者以太网数据格式；
    在所述数据传输格式为串口传输格式的情况下：
    所述配置所述DPD功能核心与所述FPGA之间的数据传输格式，还包括配置串口收发标识，所述串口收发标识用于所述DPD功能核心与所述FPGA的数据传输；
    在所述数据传输格式为以太网数据格式的情况下：
    所述配置所述DPD功能核心与所述FPGA之间的数据传输格式，还包括配置协同传输标识，所述协同传输标识用于所述DPD功能核心在处理芯片内部的数据传输。
  11. 一种计算机可读存储介质，存储有信息传递的实现程序，其中，所述程序被处理器执行时实现如权利要求1至6中任一项所述的方法的步骤。
  12. 一种DPD装置，包括：存储器、处理器及存储在所述存储器上并可在所述处理器上运行的计算机程序，其中，所述计算机程序被所述处理器执行时实现如权利要求1至6中任一项所述的方法的步骤。
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