WO2021057273A1 - Procédé et appareil pour réaliser un appel de contrat efficace sur un fpga - Google Patents

Procédé et appareil pour réaliser un appel de contrat efficace sur un fpga Download PDF

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WO2021057273A1
WO2021057273A1 PCT/CN2020/107162 CN2020107162W WO2021057273A1 WO 2021057273 A1 WO2021057273 A1 WO 2021057273A1 CN 2020107162 W CN2020107162 W CN 2020107162W WO 2021057273 A1 WO2021057273 A1 WO 2021057273A1
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chip
fpga
cache
code program
external storage
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PCT/CN2020/107162
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Chinese (zh)
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潘国振
魏长征
闫莺
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支付宝(杭州)信息技术有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G06F15/781—On-chip cache; Off-chip memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
    • G06F21/52—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity ; Preventing unwanted data erasure; Buffer overflow
    • G06F21/53—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity ; Preventing unwanted data erasure; Buffer overflow by executing in a restricted environment, e.g. sandbox or secure virtual machine
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/60—Protecting data
    • G06F21/602—Providing cryptographic facilities or services
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/60—Protecting data
    • G06F21/62—Protecting access to data via a platform, e.g. using keys or access control rules
    • G06F21/6218—Protecting access to data via a platform, e.g. using keys or access control rules to a system of files or objects, e.g. local or distributed file system or database
    • G06F21/6245—Protecting personal data, e.g. for financial or medical purposes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information

Definitions

  • One or more embodiments of this specification relate to the field of blockchain technology, and in particular to a method and device for implementing efficient contract invocation on FPGA.
  • Blockchain technology is built on a transmission network (such as a peer-to-peer network).
  • the network nodes in the transmission network use chained data structures to verify and store data, and use distributed node consensus algorithms to generate and update data.
  • TEE Trusted Execution Environment
  • TEE can play the role of a black box in the hardware. Neither the code executed in the TEE nor the data operating system layer can be peeped, and only the pre-defined interface in the code can operate on it.
  • plaintext data is calculated in TEE instead of complex cryptographic operations in homomorphic encryption. There is no loss of efficiency in the calculation process. Therefore, the combination with TEE can achieve less performance loss. Under the premise, the security and privacy of the blockchain are greatly improved. At present, the industry is very concerned about the TEE solution.
  • TEE solutions including TPM (Trusted Platform Module) in software and Intel SGX (Software Guard Extensions) in hardware. , Software Protection Extension), ARM Trustzone (trust zone) and AMD PSP (Platform Security Processor, platform security processor).
  • one or more embodiments of this specification provide a method and device for implementing efficient contract invocation on FPGA.
  • a method for implementing efficient contract invocation on FPGA includes: FPGA structure loads the deployed circuit logic configuration file to the FPGA chip contained in itself, so that the An on-chip processor and an on-chip cache are respectively formed on the FPGA chip; wherein the FPGA structure further includes an external storage connected to the FPGA chip; the FPGA structure determines the smart contract of the transaction call received by the belonging blockchain node; The FPGA structure reads the code program of the smart contract from the on-chip cache for the on-chip processor to run, and the code program is obtained by the FPGA structure from the external storage and cached in the on-chip cache.
  • an apparatus for implementing efficient contract invocation on FPGA including: a loading unit, which enables the FPGA structure to load the deployed circuit logic configuration file to the FPGA chip contained in itself , To respectively form an on-chip processor and an on-chip cache on the FPGA chip; wherein the FPGA structure further includes an external storage connected to the FPGA chip; the determining unit enables the FPGA structure to determine the blockchain node to which it belongs The smart contract invoked by the transaction; the reading unit causes the FPGA structure to read the code program of the smart contract from the on-chip cache for the on-chip processor to run, the code program from the FPGA structure The external storage acquires and caches to the on-chip cache.
  • an electronic device including: a processor; a memory for storing executable instructions of the processor; wherein the processor runs the executable instructions In order to realize the method as described in the first aspect.
  • a computer-readable storage medium on which computer instructions are stored, and when the instructions are executed by a processor, the steps of the method described in the first aspect are implemented.
  • Fig. 1 is a flowchart of a method for implementing efficient contract invocation on FPGA provided by an exemplary embodiment.
  • Fig. 2 is a schematic structural diagram of a blockchain node provided by an exemplary embodiment.
  • Fig. 3 is a schematic diagram of forming a functional module on an FPGA chip provided by an exemplary embodiment.
  • Fig. 4 is a schematic structural diagram of an on-chip cache module provided by an exemplary embodiment.
  • Fig. 5 is a schematic diagram of implementing preloading in an on-chip cache module according to an exemplary embodiment.
  • Fig. 6 is a block diagram of a device for implementing efficient contract invocation on FPGA provided by an exemplary embodiment.
  • the steps of the corresponding method are not necessarily executed in the order shown and described in this specification.
  • the method may include more or fewer steps than described in this specification.
  • a single step described in this specification may be decomposed into multiple steps for description in other embodiments; and multiple steps described in this specification may also be combined into a single step in other embodiments. description.
  • Block chains are generally divided into three types: Public Blockchain, Private Blockchain and Consortium Blockchain.
  • the public chain is represented by Bitcoin and Ethereum. Participants who join the public chain can read the data records on the chain, participate in transactions, and compete for the accounting rights of new blocks. Moreover, each participant (ie, node) can freely join and exit the network, and perform related operations.
  • the private chain is the opposite.
  • the write permission of the network is controlled by an organization or institution, and the data read permission is regulated by the organization.
  • the private chain can be a weakly centralized system with strict restrictions and few participating nodes.
  • This type of blockchain is more suitable for internal use by specific institutions.
  • Consortium chain is a block chain between public chain and private chain, which can realize "partial decentralization".
  • Each node in the alliance chain usually has a corresponding entity or organization; participants are authorized to join the network and form a stakeholder alliance to jointly maintain the operation of the blockchain.
  • the nodes in the blockchain network may use a solution that combines the blockchain and the TEE (Trusted Execution Environment).
  • TEE Trusted Execution Environment
  • TEE is a secure extension based on CPU hardware and a trusted execution environment that is completely isolated from the outside.
  • TEE was first proposed by Global Platform to solve the security isolation of resources on mobile devices, and parallel to the operating system to provide a trusted and secure execution environment for applications.
  • ARM's Trust Zone technology is the first to realize the real commercial TEE technology. With the rapid development of the Internet, security requirements are getting higher and higher. Not only mobile devices, cloud devices, and data centers have put forward more demands on TEE.
  • TEE has also been rapidly developed and expanded.
  • the TEE now referred to is a more generalized TEE compared to the original concept.
  • server chip manufacturers Intel and AMD have successively introduced hardware-assisted TEE and enriched the concepts and features of TEE, which has been widely recognized in the industry.
  • SGX provides an enclave (also known as an enclave), which is an encrypted trusted execution area in the memory, and the CPU protects data from being stolen.
  • enclave also known as an enclave
  • the CPU protects data from being stolen.
  • a part of the area EPC Enclave Page Cache, enclave page cache or enclave page cache
  • the encryption engine MEE Memory Encryption Engine
  • the first step in using TEE is to confirm the authenticity of TEE.
  • the related technology provides a remote certification mechanism for the above-mentioned SGX technology to prove that the SGX platform on the target device and the challenger have deployed the same configuration file.
  • the TEE technology in the related technology is implemented by software or a combination of software and hardware, even if the remote attestation method can indicate to a certain extent that the configuration file deployed in the TEE has not been tampered with, the TEE itself depends on the operation The environment cannot be verified.
  • a virtual machine for executing smart contracts needs to be configured in the TEE.
  • the instructions executed by the virtual machine are not directly executed, but actually executed corresponding X86 instructions (Assuming that the target device adopts the X86 architecture), which poses a certain degree of security risk.
  • this specification proposes a hardware TEE technology based on FPGA implementation.
  • FPGA implements hardware TEE by loading circuit logic configuration files. Because the content of the circuit logic configuration file can be checked and verified in advance, and the FPGA is configured and operated completely based on the logic recorded in the circuit logic configuration file, it can be ensured that the hardware TEE implemented by the FPGA has relatively higher security.
  • the code programs of the smart contracts in related technologies are all deployed at the blockchain nodes, which makes the FPGA need to frequently obtain the code programs from the blockchain nodes, which consumes a lot of resources.
  • Fig. 1 is a flowchart of a method for implementing efficient contract invocation on FPGA provided by an exemplary embodiment. As shown in Figure 1, the method is applied to the FPGA structure and may include steps 102-106.
  • Step 102 The FPGA structure loads the deployed circuit logic configuration file to the FPGA chip contained in itself, so as to form an on-chip processor and an on-chip cache on the FPGA chip; wherein, the FPGA structure also includes a connection to the FPGA chip External storage.
  • the FPGA chip contains a number of editable hardware logic units. After these hardware logic units are configured via a circuit logic configuration file, they can be implemented as corresponding functional modules to implement corresponding logic functions. Specifically, the circuit logic configuration file can be burned to the FPGA structure based on the form of a bit stream.
  • the above-mentioned on-chip processor is formed by the deployed circuit logic configuration file, and by further deploying other related functional modules, the FPGA structure can be configured as a hardware TEE on the blockchain node. Since these functional modules are completely configured by the circuit logic configuration file, it is possible to determine the logic and other aspects of the information realized by the functional module configured by checking the circuit logic configuration file to ensure that the functional module can be configured according to the complete user’s requirements. Needs to be formed and run.
  • the above-mentioned on-chip processor is used to implement virtual machine logic.
  • the virtual machine logic may include the execution logic of the Ethereum virtual machine or the execution logic of the WASM virtual machine, etc. This specification does not limit this.
  • the circuit logic configuration file can be deployed locally to the FPGA structure.
  • the deployment operation can be implemented in an offline environment to ensure safety.
  • the user can remotely deploy the circuit logic configuration file to the FPGA structure.
  • Step 104 The FPGA structure determines the smart contract called by the transaction received by the blockchain node to which it belongs.
  • the FPGA structure can obtain the contract address of the smart contract called by the exchange by parsing the to field of the transaction, and obtain the code program of the corresponding smart contract based on the contract address. If the transaction is encrypted and submitted to the blockchain by the transaction initiator, the FPGA structure needs to decrypt the transaction to read the information in the to field. Wherein, by loading the above-mentioned deployed circuit logic configuration file, a decryption module can be formed on the FPGA chip, so that the transaction can be decrypted by the decryption module.
  • the FPGA structure can maintain a node private key, and the node public key corresponding to the node private key is disclosed. Then, on the one hand, the transaction initiator can obtain the above-mentioned node public key, on the other hand, it can generate a symmetric key by itself, and implement a digital envelope encryption operation on the plaintext transaction content based on the node’s public key and symmetric key: The key encrypts the plaintext transaction content to obtain the ciphertext transaction content, encrypts the symmetric key with the node public key to obtain the ciphertext symmetric key, and the above transaction includes the ciphertext transaction content and the ciphertext symmetric key.
  • the aforementioned decryption module can decrypt the ciphertext symmetric key contained in the exchange based on the node private key to obtain the symmetric key, and then the decryption module can decrypt the ciphertext transaction content based on the symmetric key to obtain the plaintext transaction content , So as to read the information in the to field in the plaintext transaction content, and determine the contract address of the smart contract called by the exchange.
  • Step 106 The FPGA structure reads the code program of the smart contract from the on-chip cache for the on-chip processor to run, and the code program is obtained by the FPGA structure from the external storage and cached in the On-chip cache.
  • the on-chip processor reads data from the on-chip cache relatively faster, but the storage space of the on-chip cache is usually relatively small and has poor scalability, which cannot meet the deployment requirements of a large number of code programs.
  • the on-chip processor is relatively slow to read data from external storage, but the storage space of external storage is usually relatively large and has good scalability, which can meet the deployment requirements of a large number of code programs. Therefore, by deploying the code program in external storage, and caching the code program from the external storage to the on-chip cache when in use, and reading the code program from the on-chip cache by the on-chip processor to run, it can satisfy the need to perform a large number of code programs.
  • the deployment requirements can also enable the on-chip processor to quickly read and run code programs to improve transaction execution efficiency.
  • the read speed that the external storage can achieve is relatively lower than the on-chip cache, compared to deploying the code program on the blockchain node, the on-chip processor reads the code program from the external storage much faster than Read from the blockchain node.
  • the above-mentioned on-chip buffer is located inside the FPGA chip and is formed by the storage device on the FPGA chip.
  • the external storage is located outside the FPGA chip and can be plugged into the interface of the FPGA structure.
  • the external storage may include an external DDR. Since the inside of the FPGA chip is considered to be in the security range and the outside of the FPGA chip is considered to be a security risk, when the code program is in the on-chip cache, it can be cached directly in plaintext, and when the code program is stored in external storage, it needs to pass through the FPGA chip.
  • the encryption module above encrypts the code program and realizes storage.
  • the encryption module is formed by loading the aforementioned deployed circuit logic configuration file on the FPGA chip.
  • the key used can be the business root key maintained by the FPGA structure or its derived secret. key.
  • the FPGA structure decrypts the code program through the decryption module described above on the FPGA chip, so as to cache the decrypted code program to the on-chip cache, so that the on-chip processor
  • the decrypted code program can be read directly from the on-chip cache.
  • a preprocessing module can be formed on the FPGA chip, and the FPGA structure can preprocess the obtained code program through the preprocessing module, and cache the preprocessed code program on the chip Cache to be read and run by the on-chip processor.
  • the preprocessing here refers to the processing operations that must be implemented in advance before executing the original code program (that is, the code program that has not been preprocessed).
  • the preprocessing is performed before being stored in the on-chip cache, so that the on-chip processor executes the code in the subsequent During the program, the computing resources and processing time required for temporary execution of preprocessing can be saved, which helps to speed up the execution of the code program.
  • the aforementioned preprocessing may include at least one of the following: parsing and converting each field contained in the code program into a preset data structure, and adjusting the offset of the jump instruction (jump instruction) in the code program.
  • the on-chip processor does not read and execute all the operating instructions contained in the code program at one time, but reads and executes the operating instructions contained in the code program one by one. Therefore, the on-chip processor can first try to read the required operation instructions from the on-chip cache; if the required operation instructions exist in the on-chip cache, the on-chip processor can read the corresponding operation instructions from the on-chip cache and execute them Compared with reading the operation instruction from external storage or blockchain nodes, it has relatively higher efficiency; and, when the required operation instruction does not exist in the on-chip cache, the FPGA structure can obtain the operation instruction from the external storage. Operation instructions are cached to the on-chip cache for the on-chip processor to read and execute.
  • the storage addresses corresponding to each operation instruction of the same code program are usually arranged in sequence. Therefore, in the case that the on-chip processor wishes to read a certain operation instruction, the on-chip processor will usually continue to read and execute other nearby operation instructions until the contract code to which these operation instructions belong is executed.
  • the FPGA structure can only obtain an operation instruction required by the on-chip processor from the external storage, in fact the FPGA structure can also obtain the code program segment containing the operation instruction from the external storage, that is, the code program segment also contains the on-chip
  • the on-chip processor can subsequently directly read the above-mentioned other operation instructions from the on-chip cache without temporarily reading from external storage. Help improve efficiency.
  • the FPGA structure can determine the initial storage address in the external storage of the above-mentioned operation instructions required by the on-chip processor, and obtain the preset address segment containing the initial storage address from the external storage, and ensure that the above-mentioned code program segment is located in the external storage. The preset address segment. Then, by reading the data corresponding to the preset address segment from the external storage, the above-mentioned code program segment can be obtained.
  • the aforementioned preset address segment may include the aforementioned initial storage address and an address located after the initial storage address, so that other operation instructions contained in the aforementioned code program segment are arranged after the aforementioned operation instructions; taking into account the on-chip
  • the processor executes the processing logic of each operation instruction from front to back in the process of executing the code program, as well as the storage logic in which the storage address of the operation instruction in the external storage is arranged in sequence.
  • the above scheme enables the operation instructions cached in the on-chip cache to be on-chip
  • the processor has a relatively higher probability of reading and executing, avoiding other operation instructions that are arranged before the above operation instructions and have a relatively lower probability of being read and executed by the on-chip processor to be stored in the on-chip cache, which helps to optimize the on-chip Reasonable use of cache.
  • the cache space in the on-chip cache can be divided into several cache blocks, and these cache blocks are respectively used to store corresponding data. Therefore, when the FPGA structure reads the code program segment corresponding to the preset address segment from the external storage, the length of the preset address segment used can be the cache length of a single cache block in the on-chip cache, that is, each time it is stored in the on-chip cache All data occupies a cache block to facilitate effective management of the on-chip cache space.
  • the read ratio of the code program segment in the on-chip cache of the FPGA structure reaches the preset ratio
  • other code program segments after the code program segment can be automatically pre-fetched from the external storage and cached in the on-chip cache without the need
  • the on-chip processor temporarily initiates a request, so that when the on-chip processor executes the contract code of the same smart contract, it only needs to request the FPGA structure to obtain it from the external storage and store it in the on-chip cache when reading the first operation instruction.
  • Other operation instructions can be efficiently read from the on-chip cache directly, which helps to improve the execution efficiency of smart contracts.
  • the FPGA structure can read the code segment corresponding to a cache block from the external storage every time and store it in the on-chip cache; when it is monitored that the read ratio of the code segment stored in the on-chip cache reaches 50% , FPGA structure can automatically read the subsequent code program segments from the external storage according to the corresponding storage address in the external storage of the previously read code program segment.
  • each cache block can be provided with a corresponding weight, and the value of the weight is negatively related to the probability that the data in the corresponding cache block is eliminated, that is, the more the weight is The smaller the probability of a large cache block being eliminated (the data contained in the cache block is eliminated) and the smaller the weight of the cache block, the greater the probability of being eliminated.
  • the cache block containing the first operation instruction in the smart contract can be stored in the on-chip cache for a relatively longer time, so that the on-chip processor has a greater probability and can directly Read the first operation instruction of a certain contract code from the on-chip cache, without the need for the FPGA structure to temporarily read from the external storage, and cooperate with the above-mentioned automatic loading scheme for subsequent operation instructions, so that the on-chip processor can always be from the on-chip cache Read the required operation instructions in the middle, so as to achieve higher operation instruction reading and execution efficiency.
  • Fig. 2 is a schematic structural diagram of a blockchain node provided by an exemplary embodiment.
  • an FPGA structure can be added to the blockchain node to implement hardware TEE.
  • the FPGA structure can be an FPGA board as shown in FIG. 2.
  • the FPGA board can be connected to the blockchain node through the PCIE interface to realize the data interaction between the FPGA board and the blockchain node.
  • FPGA boards can include FPGA chips, Flash chips, secret tube chips, and external DDR structures; of course, in some embodiments, in addition to FPGA chips and external DDRs, they may only include the remaining Flash chips and secret tube chips, etc. Part of the structure of, or may contain more structures, here are just examples.
  • no user-defined logic is programmed on the FPGA chip, which is equivalent to the FPGA chip in a blank state.
  • Users can burn circuit logic configuration files on the FPGA chip to form corresponding functions or logic on the FPGA chip.
  • the FPGA board does not have the capability of security protection, so it usually needs to provide an external security environment.
  • users can implement the programming of the circuit logic configuration file in an offline environment to achieve physical security isolation. Instead of implementing remote programming online.
  • the corresponding logic code can be formed through FPGA hardware language, and then the logic code can be mirrored to obtain the above-mentioned circuit logic configuration file.
  • the user can check the above-mentioned logic code. Especially, when multiple users are involved at the same time, multiple users can check the above logic code separately to ensure that the FPGA board can finally meet the needs of all users and prevent security risks, logic errors, fraud and other abnormalities. problem.
  • the user can burn the circuit logic configuration file to the FPGA board in the above-mentioned offline environment.
  • the circuit logic configuration file is transferred from the blockchain node to the FPGA board, and then deployed to the Flash chip as shown in Figure 2, so that even if the FPGA board is powered off, the Flash chip can still save the above-mentioned circuit logic. Configuration file.
  • Fig. 3 is a schematic diagram of forming a functional module on an FPGA chip provided by an exemplary embodiment.
  • the hardware logic unit contained in the FPGA chip can be configured to form corresponding functional modules on the FPGA chip, such as the formed functional modules It may include an on-chip cache module, a preprocessing module, a plaintext calculation module, a key agreement module, a decryption verification module, an encryption and decryption module, etc. as shown in FIG. 3.
  • the circuit logic configuration file can also be used to transmit the information that needs to be stored to the FPGA board.
  • the preset certificate can be stored on the FPGA chip, and the authentication root key can be stored in the secret tube chip (the authentication root key can also be Stored on the FPGA chip) and so on.
  • the FPGA board can realize remote key agreement with the user.
  • the key agreement process can use related technologies. Any algorithm or standard can be implemented, and this specification does not limit it.
  • the key agreement process can include: the user can generate a key Ka-1 at the local client, the key agreement module can generate a key Kb-1 locally, and the client can generate a key Kb-1 based on the key Ka- 1 Calculate the key agreement information Ka-2, the key agreement module can calculate the key agreement information Kb-2 based on the key Kb-1, and then the client sends the key agreement information Ka-2 to the key agreement module, The key agreement module sends the key agreement information Kb-2 to the client, so that the client can generate a secret value based on the key Ka-1 and the key agreement information Kb-2, and the key agreement module can be based on the key Kb -1 generates the same secret value as the key agreement information Ka-2, and finally the client and the key agreement module respectively derive the same
  • the key agreement information Ka-2 and key agreement information Kb-2 are transmitted between the client and the key agreement module via the blockchain node
  • the key Ka-1 is controlled by the client
  • the key Kb-1 is controlled by the key agreement module, so it can ensure that the blockchain node cannot know the final secret value and the configuration file deployment key, so as to avoid possible security risks.
  • the secret value is also used to derive the business secret deployment key; for example, the secret value can be derived as a 32-bit value, the first 16 bits can be used as the configuration file deployment key, and the last 16 bits can be used as the business secret deployment Key.
  • the user can deploy the service key to the FPGA board through the service secret deployment key.
  • the service key may include the node private key and the service root key.
  • the user can use the business secret deployment key on the client to sign, encrypt the node private key or the business root key, and send it to the FPGA board, so that after the FPGA board is decrypted and verified through the decryption verification module, Deploy the obtained node private key or service root key.
  • the FPGA board can be implemented as a TEE on the blockchain node to meet privacy requirements. For example, when a blockchain node receives a transaction, if the transaction is a plaintext transaction, the blockchain node can directly process the plaintext transaction, if the transaction is a private transaction, the blockchain node transmits the private transaction to the FPGA The board is processed.
  • the transaction content of a plaintext transaction is in plaintext form, and the contract status generated after the transaction is executed is also stored in plaintext form.
  • the transaction content of a private transaction is in the form of cipher text, which is obtained by encrypting the content of the transaction in plain text by the transaction initiator, and the contract state generated after the transaction is executed needs to be stored in the form of cipher text to ensure the protection of transaction privacy.
  • the transaction initiator can generate a symmetric key randomly or based on other methods.
  • the business public key corresponding to the above-mentioned business private key is disclosed, then the transaction initiator can perform transaction content in plaintext based on the symmetric key and the business public key.
  • the transaction initiator encrypts the plaintext transaction content with a symmetric key, and encrypts the symmetric key with the business public key.
  • the two parts obtained are included in the above-mentioned private transaction; in other words, the private transaction includes Two parts of content: the content of the transaction in plaintext encrypted with a symmetric key, and the symmetric key encrypted with the business public key.
  • the encryption and decryption module can use the business private key to decrypt the symmetric key encrypted with the business public key to obtain the symmetric key, and then the encryption and decryption module
  • the symmetric key is used to decrypt the plaintext transaction content encrypted with the symmetric key to obtain the plaintext transaction content.
  • Private transactions can be used to deploy smart contracts, then the data field of the plaintext transaction content can contain the contract code of the smart contract to be deployed; or, the privacy transaction can be used to call the smart contract, then the to field of the plaintext transaction content can contain the called The contract address of the smart contract, and the FPGA board can retrieve the corresponding contract code based on the contract address.
  • the FPGA board is equipped with an on-chip cache module and an external DDR at the same time.
  • the storage space of the external DDR is often larger or even much larger than the storage space of the on-chip cache module, and has a high degree of scalability, so that the external DDR can store more data. Therefore, when private transactions are used to deploy smart contracts, the FPGA board can deploy the contract code contained in the data field of the plaintext transaction content to the external DDR. Then, when the FPGA board subsequently receives a private transaction for invoking the smart contract, the FPGA board can find the corresponding contract code from the external DDR based on the contract address contained in the to field of the clear text transaction content to pass The plaintext calculation module executes the contract code.
  • the plaintext calculation module formed on the FPGA chip is used to implement virtual machine logic in related technologies, that is, the plaintext calculation module is equivalent to the "hardware virtual machine" on the FPGA board. Therefore, after the contract code is determined based on the foregoing plaintext transaction content, the contract code can be passed into the plaintext calculation module, so that the plaintext calculation module executes the contract code.
  • the plaintext calculation module is equivalent to the on-chip processor formed on the FPGA chip in this specification.
  • the FPGA board For private transactions used to deploy smart contracts, after the FPGA board obtains the contract code to be deployed, it can be directly stored in the external DDR, or it can be preprocessed through the preprocessing module, and then the preprocessed contract code can be stored in the external DDR. If it is not preprocessed by the preprocessing module before storing in the external DDR, the plaintext calculation module needs to temporarily perform preprocessing operations through the preprocessing module before it is used to execute the contract code, and then the plaintext calculation module performs preprocessing operations on the preprocessed Contract code for processing.
  • preprocessing of contract code can include several dimensions, and the preprocessing dimensions involved may be different for contract codes written in different languages or rules.
  • preprocessing can include the following two aspects:
  • Adjust the offset of the jump instruction may cause the offset of the jump instruction to be updated: by parsing the jump instruction in the contract code, the symbol identifier corresponding to the jump instruction is converted into address information that can be recognized by the on-chip processor, so that the length of the contract code changes ; Decode the encoded operands in the contract code, so that the length of the contract code changes.
  • the encoding method here may include LEB (Little-Endian Base) encoding or other encodings, for example.
  • the FPGA board can read the contract address from the to field of the privacy transaction, and obtain the corresponding code program from the external DDR based on the contract address for plaintext calculations Module execution.
  • the plaintext calculation module needs to read and execute each operation instruction contained in the code program from front to back:
  • the plaintext calculation module first accesses the on-chip cache module to read the first operation instruction from the on-chip cache module; if the read fails, that is, the first operation instruction of the corresponding code program is not cached in the on-chip cache module, the FPGA board needs Read the first operation instruction from the external DDR. After determining the storage address of the first operation instruction in the external DDR, the FPGA board does not only read the first operation instruction, but reads a code segment corresponding to the storage address and subsequent addresses, and stores it on the chip Cache module.
  • FIG. 4 is a schematic structural diagram of an on-chip cache module provided by an exemplary embodiment.
  • the on-chip cache module contains cache blocks such as B1, B2, B3, B4, B5, and B6, and these cache blocks are initially empty.
  • the FPGA board can read the above-mentioned code program segment from the external DDR according to the size of a single cache block.
  • the code program segment can be stored in the B1 cache block shown in FIG. 4. Therefore, in addition to the above-mentioned first operation instruction, that is, instruction 1, the B1 cache block also contains other instructions after instruction 1.
  • the plaintext calculation module can read instruction 1, that is, the above-mentioned first operation instruction, from the cache block B1 of the on-chip cache module and execute it. After completing the execution operation of instruction 1, the plaintext calculation module needs to execute subsequent operation instructions in sequence. In the previous steps, the FPGA board has read instruction 1 and several subsequent instructions together and stored them in the cache block B1, so the plaintext calculation module can directly read the subsequent instructions from the cache block B1 of the on-chip cache module. Operation instructions, without the need for the FPGA board to temporarily read from the external DDR, saves the waiting time of the plaintext calculation module, and can speed up the execution of the smart contract.
  • FIG. 5 is a schematic diagram of implementing preloading in an on-chip cache module according to an exemplary embodiment. As shown in Figure 5, if it is detected that the data previously stored in the buffer block B1 has been read by the plaintext calculation module to reach or exceed 50% (or other proportions), then the FPGA board can automatically read the operation instructions from the external DDR And stored in the on-chip cache module.
  • the FPGA board can read the corresponding end address in the external DDR according to the code segment previously stored in the buffer block B1, and read a code segment backward from the memory address after the end address, and store it in the on-chip cache In the module, such as cache block B2, for the plaintext calculation module to continue reading.
  • the plaintext calculation module can always read the operation instructions directly from the on-chip cache module without waiting for the FPGA board to temporarily read from the external DDR.
  • the storage space of the on-chip cache module is limited. Therefore, the on-chip cache module eliminates the stored infrequently used data through the elimination mechanism to improve the efficiency of the storage space. For example, a weight can be set for each cache block, so that a cache block with a relatively larger weight is relatively less likely to be eliminated, and a cache block with a relatively smaller weight is relatively easy to be eliminated.
  • a relatively larger weight can be set for the cache block containing the first operation instruction of the contract code of the smart contract, so that the cache block containing the first operation instruction is relatively less likely to be eliminated, so for some smart contracts that are often executed Contract, the plaintext calculation module can directly read its first operation instruction from the on-chip cache module, and then cooperate with the preload operation of the subsequent operation instructions in the above scheme, so that the plaintext calculation module can read the corresponding from the on-chip cache module without delay All contract codes of smart contracts have extremely high execution efficiency.
  • the user may want to update the version of the circuit logic configuration file deployed on the FPGA board.
  • the authentication root key contained in the circuit logic configuration file may be known by risky users, or the user wants to update the version on the FPGA board.
  • the deployed functional modules are upgraded, etc. This manual does not limit this.
  • the circuit logic configuration file that has been deployed in the above process can be referred to as the old version of the circuit logic configuration file, and the circuit logic configuration file that needs to be deployed is referred to as the new version of the circuit logic configuration file.
  • the user can generate a new version of the circuit logic configuration file through the process of writing code and mirroring. Further, the user can sign the new version of the circuit logic configuration file with his own private key, and then encrypt the signed new version of the circuit logic configuration file with the configuration file deployment key negotiated above to obtain the encrypted new version of the circuit Logical configuration file. In some cases, there may be multiple users at the same time, so the old version of the circuit logic configuration file needs to deploy the preset certificates corresponding to these users to the FPGA board, and these users need to use their own private keys to pair the new version of the circuit. Sign the logical configuration file.
  • the user can remotely send the encrypted new version of the circuit logic configuration file to the blockchain node through the client, and the blockchain node will further transfer it to the FPGA board.
  • the decryption verification module formed on the FPGA chip in the foregoing process is located on the transmission path between the PCIE interface and the Flash chip, so that the encrypted new version of the circuit logic configuration file must first be successfully processed by the decryption verification module before it can be
  • the Flash chip is passed in to achieve a credible update, and the Flash chip cannot be updated directly without bypassing the process of decryption and verification.
  • the decryption verification module After the decryption verification module receives the encrypted new version of the circuit logic configuration file, it first decrypts it with the configuration file deployment key deployed on the FPGA board. If the decryption is successful, the decryption verification module is further based on the preset certificate deployed on the FPGA chip , To perform signature verification on the decrypted new version of the circuit logic configuration file.
  • the decryption and signature verification module will trigger the termination of the update operation; and if the decryption is successful and the signature verification is passed, you can It is determined that the obtained new version of the circuit logic configuration file is from the aforementioned user and has not been tampered with during the transmission process.
  • the new version of the circuit logic configuration file can be further transmitted to the Flash chip to update and deploy the old version of the circuit logic configuration file in the Flash chip.
  • the above-mentioned plaintext calculation module, on-chip cache module, key agreement module, encryption and decryption module, decryption verification module, and storage in the FPGA chip can also be formed on the FPGA chip. Enter the preset certificate, and store the authentication root key to the secret management chip and other information.
  • the formed plaintext calculation module, on-chip cache module, key agreement module, encryption/decryption module, decryption and signature verification module, etc., the implemented functional logic can be changed and upgraded, and stored in the deployed preset certificate, authentication root Information such as keys may also be different from the information before the update.
  • the FPGA board can remotely negotiate with the user to obtain a new configuration file deployment key based on the updated key agreement module, authentication root key, etc., and the configuration file deployment key can be used for the next renewal Update process. Similarly, a reliable update operation for FPGA boards can be continuously implemented accordingly.
  • the FPGA board can generate certification results for the new version of the circuit logic configuration file.
  • the above-mentioned key agreement module can calculate the hash value of the new version of the circuit logic configuration file and the hash value of the configuration file deployment key negotiated based on the new version of the circuit logic configuration file through an algorithm such as sm3 or other algorithms.
  • the calculation result can be used as the above-mentioned authentication result, and the key agreement module sends the authentication result to the user.
  • the user can verify the authentication result on the client based on the maintained new version of the circuit logic configuration file and the configuration file deployment key negotiated accordingly. If the verification is successful, it indicates that the new version of the circuit logic configuration file is successful on the FPGA board. Deployed, and the user and the FPGA board successfully negotiated accordingly to obtain a consistent configuration file deployment key, thereby confirming the successful completion of the circuit logic configuration file update deployment.
  • Fig. 6 is a schematic structural diagram of an apparatus for implementing efficient contract invocation on FPGA provided by an exemplary embodiment.
  • the device may include: a loading unit 601, which causes the FPGA structure to load the deployed circuit logic configuration file to the FPGA chip contained in itself, so as to form an on-chip processor on the FPGA chip.
  • the FPGA structure also includes an external storage connected to the FPGA chip; a determining unit 602, enabling the FPGA structure to determine the smart contract of the transaction call received by the blockchain node to which it belongs; reading unit 603 , Enabling the FPGA structure to read the code program of the smart contract from the on-chip cache for the on-chip processor to run, and the code program is obtained by the FPGA structure from the external storage and cached on the chip Cache.
  • it further includes: an instruction determining unit 604 to enable the FPGA structure to determine the operation instructions that the on-chip processor needs to read from the code program; an instruction cache unit 605 to enable the FPGA structure to be on the chip If the operation instruction does not exist in the cache, the operation instruction is obtained from the external storage and cached in the on-chip cache, so as to be further provided to the on-chip processor.
  • the instruction cache unit 605 is specifically configured to: enable the FPGA structure to obtain the code program segment containing the operation instruction from the external storage, and cache it in the on-chip cache.
  • the instruction cache unit 605 is specifically configured to: enable the FPGA structure to determine the initial storage address of the operation instruction in the external storage; and enable the FPGA structure to obtain from the external storage including the The preset address segment of the initial storage address, and the code program segment is located in the preset address segment.
  • the preset address segment includes the initial storage address and an address located after the initial storage address.
  • the length of the preset address segment is the cache length of a single cache block in the on-chip cache.
  • the instruction cache unit 605 is specifically configured to: in the case where the read ratio of the code program segments in the on-chip cache of the FPGA structure reaches a preset ratio, store the preset ratio from the outside. Obtain other code program segments after the code program segment and cache them in the on-chip cache.
  • the code program is encrypted and stored in the external storage; the device further includes: a decryption unit 606, which enables the FPGA structure to decrypt the code program through a decryption module on the FPGA chip , To cache the decrypted code program to the on-chip cache; wherein, the decryption module is formed by loading the deployed circuit logic configuration file by the FPGA chip.
  • a decryption unit 606 which enables the FPGA structure to decrypt the code program through a decryption module on the FPGA chip , To cache the decrypted code program to the on-chip cache; wherein, the decryption module is formed by loading the deployed circuit logic configuration file by the FPGA chip.
  • a preprocessing unit 607 which enables the FPGA structure to preprocess the code program through the preprocessing module on the FPGA chip, so as to cache the preprocessed code program in the on-chip cache ;
  • the preprocessing module is formed by loading the deployed circuit logic configuration file by the FPGA chip.
  • the preprocessing includes at least one of the following: parsing and converting each field contained in the code program into a preset data structure; adjusting the offset of the jump instruction in the code program.
  • the on-chip cache includes several cache blocks; wherein, the cache block containing the first operation instruction in the smart contract corresponds to a relatively larger weight, so that the on-chip cache has a relatively longer duration .
  • a typical implementation device is a computer.
  • the specific form of the computer can be a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email receiving and sending device, and a game control A console, a tablet computer, a wearable device, or a combination of any of these devices.
  • the computer includes one or more processors (CPU), input/output interfaces, network interfaces, and memory.
  • processors CPU
  • input/output interfaces network interfaces
  • memory volatile and non-volatile memory
  • the memory may include non-permanent memory in a computer readable medium, random access memory (RAM) and/or non-volatile memory, such as read-only memory (ROM) or flash memory (flash RAM). Memory is an example of computer readable media.
  • RAM random access memory
  • ROM read-only memory
  • flash RAM flash memory
  • Computer-readable media include permanent and non-permanent, removable and non-removable media, and information storage can be realized by any method or technology.
  • the information can be computer-readable instructions, data structures, program modules, or other data.
  • Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, CD-ROM, digital versatile disc (DVD) or other optical storage, Magnetic cassettes, disk storage, quantum memory, graphene-based storage media or other magnetic storage devices or any other non-transmission media can be used to store information that can be accessed by computing devices. According to the definition in this article, computer-readable media does not include transitory media, such as modulated data signals and carrier waves.
  • first, second, third, etc. may be used to describe various information in one or more embodiments of this specification, the information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other.
  • first information may also be referred to as second information, and similarly, the second information may also be referred to as first information.
  • word “if” as used herein can be interpreted as "when” or “when” or "in response to determination”.

Abstract

L'invention concerne un procédé et un appareil pour réaliser un appel de contrat efficace sur un FPGA. Le procédé peut comprendre les étapes suivantes : une structure FPGA charge un fichier de configuration logique de circuit déployé sur une puce FPGA incluse dans la structure FPGA, de sorte qu'un processeur intégré et une mémoire cache intégrée sont respectivement formés sur la puce FPGA, la structure FPGA comprenant en outre une mémoire externe connectée à la puce FPGA ; la structure FPGA détermine un contrat intelligent appelé par une transaction qui est reçue par un nœud de chaîne de blocs auquel appartient la structure FPGA ; et la structure FPGA lit un programme de code du contrat intelligent à partir de la mémoire cache intégrée, de sorte que le processeur intégré exécute le programme de code, le programme de code étant acquis à partir du stockage externe par la structure FPGA et étant mis en cache dans la mémoire cache intégrée.
PCT/CN2020/107162 2019-09-25 2020-08-05 Procédé et appareil pour réaliser un appel de contrat efficace sur un fpga WO2021057273A1 (fr)

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