WO2021057272A1 - 基于fpga实现合约调用的方法及装置 - Google Patents

基于fpga实现合约调用的方法及装置 Download PDF

Info

Publication number
WO2021057272A1
WO2021057272A1 PCT/CN2020/107119 CN2020107119W WO2021057272A1 WO 2021057272 A1 WO2021057272 A1 WO 2021057272A1 CN 2020107119 W CN2020107119 W CN 2020107119W WO 2021057272 A1 WO2021057272 A1 WO 2021057272A1
Authority
WO
WIPO (PCT)
Prior art keywords
fpga
chip
transaction
code program
fpga structure
Prior art date
Application number
PCT/CN2020/107119
Other languages
English (en)
French (fr)
Inventor
潘国振
魏长征
闫莺
Original Assignee
支付宝(杭州)信息技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 支付宝(杭州)信息技术有限公司 filed Critical 支付宝(杭州)信息技术有限公司
Publication of WO2021057272A1 publication Critical patent/WO2021057272A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06Q—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
    • G06Q40/00—Finance; Insurance; Tax strategies; Processing of corporate or income taxes
    • G06Q40/04—Trading; Exchange, e.g. stocks, commodities, derivatives or currency exchange
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45533—Hypervisors; Virtual machine monitors
    • G06F9/45558—Hypervisor-specific management and integration aspects
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45533—Hypervisors; Virtual machine monitors
    • G06F9/45558—Hypervisor-specific management and integration aspects
    • G06F2009/45583—Memory management, e.g. access or allocation

Definitions

  • One or more embodiments of this specification relate to the field of blockchain technology, and in particular to a method and device for implementing contract invocation based on FPGA.
  • Blockchain technology is built on a transmission network (such as a peer-to-peer network).
  • the network nodes in the transmission network use chained data structures to verify and store data, and use distributed node consensus algorithms to generate and update data.
  • TEE Trusted Execution Environment
  • TEE can play the role of a black box in the hardware. Neither the code executed in the TEE nor the data operating system layer can be peeped, and only the pre-defined interface in the code can operate on it.
  • plaintext data is calculated in TEE instead of complex cryptographic operations in homomorphic encryption. There is no loss of efficiency in the calculation process. Therefore, the combination with TEE can achieve less performance loss. Under the premise, the security and privacy of the blockchain are greatly improved. At present, the industry is very concerned about the TEE solution.
  • TEE solutions including TPM (Trusted Platform Module) in software and Intel SGX (Software Guard Extensions) in hardware. , Software Protection Extension), ARM Trustzone (trust zone) and AMD PSP (Platform Security Processor, platform security processor).
  • one or more embodiments of this specification provide a method and device for implementing contract invocation based on FPGA.
  • a method for implementing contract invocation based on FPGA includes: FPGA structure obtains the transaction received by the blockchain node to which it belongs; and the FPGA structure determines the The contract address of the smart contract called by the transaction; the FPGA structure obtains the code program corresponding to the contract address from the local space, so as to run the code program on the FPGA structure.
  • a device for implementing contract calls based on FPGA which includes: a transaction acquisition unit that enables the FPGA structure to acquire transactions received by its own blockchain node; address determination Unit to enable the FPGA structure to determine the contract address of the smart contract called by the transaction; program acquisition unit to enable the FPGA structure to acquire the code program corresponding to the contract address from the local space to run on the FPGA structure The code program.
  • an electronic device including: a processor; a memory for storing executable instructions of the processor; wherein the processor runs the executable instructions In order to realize the method as described in the first aspect.
  • a computer-readable storage medium on which computer instructions are stored, and when the instructions are executed by a processor, the steps of the method described in the first aspect are implemented.
  • Fig. 1 is a flowchart of a method for implementing contract invocation based on FPGA provided by an exemplary embodiment.
  • Fig. 2 is a schematic structural diagram of a blockchain node provided by an exemplary embodiment.
  • Fig. 3 is a schematic diagram of forming a functional module on an FPGA chip provided by an exemplary embodiment.
  • Fig. 4 is a schematic structural diagram of another blockchain node provided by an exemplary embodiment.
  • Fig. 5 is a block diagram of a device for implementing contract invocation based on FPGA provided by an exemplary embodiment.
  • the steps of the corresponding method may not be executed in the order shown and described in this specification.
  • the method may include more or fewer steps than described in this specification.
  • a single step described in this specification may be decomposed into multiple steps for description in other embodiments; and multiple steps described in this specification may also be combined into a single step in other embodiments. description.
  • Block chains are generally divided into three types: Public Blockchain, Private Blockchain and Consortium Blockchain.
  • the public chain is represented by Bitcoin and Ethereum. Participants who join the public chain can read the data records on the chain, participate in transactions, and compete for the accounting rights of new blocks. Moreover, each participant (ie, node) can freely join and exit the network, and perform related operations.
  • the private chain is the opposite.
  • the write permission of the network is controlled by an organization or institution, and the data read permission is regulated by the organization.
  • the private chain can be a weakly centralized system with strict restrictions and few participating nodes.
  • This type of blockchain is more suitable for internal use by specific institutions.
  • Consortium chain is a block chain between public chain and private chain, which can realize "partial decentralization".
  • Each node in the alliance chain usually has a corresponding entity or organization; participants are authorized to join the network and form a stakeholder alliance to jointly maintain the operation of the blockchain.
  • the nodes in the blockchain network may use a solution that combines the blockchain and the TEE (Trusted Execution Environment).
  • TEE Trusted Execution Environment
  • TEE is a secure extension based on CPU hardware and a trusted execution environment that is completely isolated from the outside.
  • TEE was first proposed by Global Platform to solve the security isolation of resources on mobile devices, and parallel to the operating system to provide a trusted and secure execution environment for applications.
  • ARM's Trust Zone technology is the first to realize the real commercial TEE technology. With the rapid development of the Internet, security requirements are getting higher and higher. Not only mobile devices, cloud devices, and data centers have put forward more demands on TEE.
  • TEE has also been rapidly developed and expanded. Compared with the originally proposed concept, the TEE referred to now is a more generalized TEE.
  • server chip manufacturers Intel and AMD have successively introduced hardware-assisted TEE and enriched the concepts and features of TEE, which has been widely recognized in the industry.
  • the TEE mentioned now usually refers more to this kind of hardware-assisted TEE technology.
  • SGX provides an enclave (also known as an enclave), which is an encrypted trusted execution area in the memory, and the CPU protects data from being stolen.
  • enclave also known as an enclave
  • the CPU protects data from being stolen.
  • a part of the area EPC Enclave Page Cache, enclave page cache or enclave page cache
  • the encryption engine MEE Memory Encryption Engine
  • the first step in using TEE is to confirm the authenticity of TEE.
  • the related technology provides a remote certification mechanism for the above-mentioned SGX technology to prove that the SGX platform on the target device and the challenger have deployed the same configuration file.
  • the TEE technology in the related technology is implemented by software or a combination of software and hardware, even if the remote attestation method can indicate to a certain extent that the configuration file deployed in the TEE has not been tampered with, the TEE itself depends on the operation The environment cannot be verified.
  • a virtual machine for executing smart contracts needs to be configured in the TEE.
  • the instructions executed by the virtual machine are not directly executed, but actually executed corresponding X86 instructions (Assuming that the target device adopts the X86 architecture), which poses a certain degree of security risk.
  • this specification proposes a hardware TEE technology based on FPGA implementation.
  • FPGA implements hardware TEE by loading circuit logic configuration files. Because the content of the circuit logic configuration file can be checked and verified in advance, and the FPGA is configured and operated completely based on the logic recorded in the circuit logic configuration file, it can be ensured that the hardware TEE implemented by the FPGA has relatively higher security.
  • the code programs of the smart contracts in related technologies are all deployed at the blockchain nodes, which makes the FPGA need to frequently obtain the code programs from the blockchain nodes, which consumes a lot of resources.
  • Fig. 1 is a flowchart of a method for implementing contract invocation based on FPGA provided by an exemplary embodiment. As shown in Figure 1, the method is applied to the FPGA structure and may include steps 102-106.
  • Step 102 The FPGA structure obtains the transaction received by the blockchain node to which it belongs.
  • Blockchain nodes include node hosts.
  • the FPGA structure is connected to the node host, so that the FPGA structure can realize data interaction with the node host, and can also be described as the FPGA structure and the blockchain node to realize data interaction.
  • the blockchain node can transmit the received transaction to the FPGA structure, so that the FPGA structure executes the smart contract involved in the transaction.
  • the FPGA structure can be plugged into the PCIE interface on the node host of the blockchain node to realize the above-mentioned connection relationship; or, other types of interfaces can also be used, and the connection may even be established wirelessly, which is not discussed in this manual. limit.
  • the transaction initiator can submit the above-mentioned transaction at the above-mentioned blockchain node.
  • the transaction initiator may submit the above-mentioned transaction at other blockchain nodes, and the other blockchain nodes can transmit the transaction to the above-mentioned blockchain node.
  • the above-mentioned blockchain node may obtain the above-mentioned transaction in other ways, and this specification does not limit this.
  • Step 104 The FPGA structure determines the contract address of the smart contract called by the transaction.
  • the above transaction can be in an encrypted state.
  • the blockchain node can identify whether the received transaction is encrypted, and transmit the encrypted transaction to the FPGA structure for processing, and process the unencrypted transaction locally on the blockchain node.
  • the FPGA structure includes an FPGA chip, and by loading the circuit logic configuration file deployed on the FPGA structure onto the FPGA chip, a decryption module can be formed on the FPGA chip. Then, when the above transaction is in an encrypted state, the FPGA structure can pass the transaction to the above decryption module, and extract the contract address of the smart contract called by the transaction from the decrypted transaction content output by the decryption module, such as the contract address It is usually located in the to field of the decrypted transaction content.
  • Step 106 The FPGA structure obtains the code program corresponding to the contract address from the local space, so as to run the code program on the FPGA structure.
  • the FPGA structure includes a local space, which can be used to maintain at least a part of the code program of the deployed smart contract. Therefore, the FPGA structure can directly obtain the required code program from the local space in at least part of the scene without interacting with the blockchain node, which can save the resource consumption caused by the interaction, speed up the acquisition of the code program, Improve transaction execution efficiency.
  • the FPGA structure may encounter the inability to obtain the code corresponding to the contract address in the local space In the case of the program, the FPGA structure can then request the blockchain node to obtain the code program corresponding to the contract address.
  • the local space may include: the on-chip storage space of the FPGA chip contained in the FPGA structure, or the external storage space of the FPGA chip, or include both on-chip storage space and external storage space.
  • the on-chip storage space is located inside the FPGA chip and is formed by storage devices on the FPGA chip.
  • the external storage space is located outside the FPGA chip and can be plugged into the interface of the FPGA structure.
  • the external storage space may include an external DDR.
  • the code program is stored in the on-chip storage space, it can be stored directly in plain text, and when the code program is stored in the external storage space, it is required
  • the code program is encrypted and stored by the encryption module on the FPGA chip, where the encryption module is formed by the FPGA chip loading the aforementioned deployed circuit logic configuration file. Therefore, in the aforementioned process of obtaining the code program from the local space, if the code program is cached in the on-chip cache space, the code program can be directly read from the on-chip cache space and read into the on-chip processor. If the code program is cached in the external For storage space, it is necessary to decrypt the code program read from the external storage space through the aforementioned decryption module on the FPGA chip, and read the decrypted code program into the on-chip processor.
  • the original code program can be directly stored, for example, the original code program may be a bytecode program.
  • the FPGA structure can preprocess the original code program and store the preprocessed code program in the local space.
  • the preprocessing here refers to the processing operations that must be implemented in advance before the original code program is executed. By performing preprocessing before storing in the local space, the FPGA structure can save the need for temporary preprocessing when the code program is subsequently executed. Consumption of computing resources and processing time helps to speed up the execution of code programs.
  • the aforementioned preprocessing may include at least one of the following: parsing and converting each field contained in the code program into a preset data structure, and adjusting the offset of the jump instruction (jump instruction) in the code program.
  • the FPGA structure can transfer the code program to its own FPGA chip to form an on-chip processor for realizing the logic of the virtual machine, such as
  • the virtual machine logic may include the execution logic of the Ethereum virtual machine or the execution logic of the WASM virtual machine, etc. This specification does not limit this; wherein, the on-chip processor loads the deployed circuit logic configuration file on the FPGA structure from the FPGA chip And formed.
  • the FPGA chip contains a number of editable hardware logic units. After these hardware logic units are configured via a circuit logic configuration file, they can be implemented as corresponding functional modules to implement corresponding logic functions. Specifically, the circuit logic configuration file can be burned to the FPGA structure based on the form of a bit stream. For example, the above-mentioned decryption module, encryption module, and on-chip processor are formed by the deployed circuit logic configuration file, and by further deploying other related functional modules, the FPGA structure can be configured as a hardware TEE on the blockchain node .
  • the circuit logic configuration file can be deployed locally to the FPGA structure.
  • the deployment operation can be implemented in an offline environment to ensure safety.
  • the user can remotely deploy the circuit logic configuration file to the FPGA structure.
  • Fig. 2 is a schematic structural diagram of a blockchain node provided by an exemplary embodiment.
  • an FPGA structure can be added to the blockchain node to implement hardware TEE.
  • the FPGA structure can be an FPGA board as shown in FIG. 2.
  • the FPGA board can be connected to the blockchain node through the PCIE interface to realize the data interaction between the FPGA board and the blockchain node.
  • FPGA boards can include FPGA chips, Flash (flash memory) chips, and dense tube chips; of course, in addition to FPGA chips in some embodiments, they may only include parts of the remaining Flash chips and dense tube chips. , Or may contain more structures, here are just examples.
  • no user-defined logic is programmed on the FPGA chip, which is equivalent to the FPGA chip in a blank state.
  • Users can burn circuit logic configuration files on the FPGA chip to form corresponding functions or logic on the FPGA chip.
  • the FPGA board does not have the capability of security protection, so it usually needs to provide an external security environment.
  • users can implement the programming of the circuit logic configuration file in an offline environment to achieve physical security isolation. Instead of implementing remote programming online.
  • the corresponding logic code can be formed through FPGA hardware language, and then the logic code can be mirrored to obtain the above-mentioned circuit logic configuration file.
  • the user can check the above-mentioned logic code. Especially, when multiple users are involved at the same time, multiple users can check the above logic code separately to ensure that the FPGA board can finally meet the needs of all users and prevent security risks, logic errors, fraud and other abnormalities. problem.
  • the user can burn the circuit logic configuration file to the FPGA board in the above-mentioned offline environment.
  • the circuit logic configuration file is transferred from the blockchain node to the FPGA board, and then deployed to the Flash chip as shown in Figure 2, so that even if the FPGA board is powered off, the Flash chip can still save the above-mentioned circuit logic. Configuration file.
  • Fig. 3 is a schematic diagram of forming a functional module on an FPGA chip provided by an exemplary embodiment.
  • the hardware logic unit contained in the FPGA chip can be configured to form corresponding functional modules on the FPGA chip.
  • the formed functional modules can include such The on-chip cache module, preprocessing module, plaintext calculation module, key agreement module, decryption verification module, encryption and decryption module, etc. shown in FIG.
  • the circuit logic configuration file can also be used to transmit the information that needs to be stored to the FPGA board.
  • the preset certificate can be stored on the FPGA chip, and the authentication root key can be stored in the secret tube chip (the authentication root key can also be Stored on the FPGA chip) and so on.
  • the FPGA board can realize remote key agreement with the user.
  • the key agreement process can use related technologies. Any algorithm or standard can be implemented, and this specification does not limit it.
  • the key agreement process can include: the user can generate a key Ka-1 at the local client, the key agreement module can generate a key Kb-1 locally, and the client can generate a key Kb-1 based on the key Ka- 1 Calculate the key agreement information Ka-2, the key agreement module can calculate the key agreement information Kb-2 based on the key Kb-1, and then the client sends the key agreement information Ka-2 to the key agreement module, The key agreement module sends the key agreement information Kb-2 to the client, so that the client can generate a secret value based on the key Ka-1 and the key agreement information Kb-2, and the key agreement module can be based on the key Kb -1 generates the same secret value as the key agreement information Ka-2, and finally the client and the key agreement module respectively derive the same
  • the key agreement information Ka-2 and key agreement information Kb-2 are transmitted between the client and the key agreement module via the blockchain node
  • the key Ka-1 is controlled by the client
  • the key Kb-1 is controlled by the key agreement module, so it can ensure that the blockchain node cannot know the final secret value and the configuration file deployment key, so as to avoid possible security risks.
  • the secret value is also used to derive the business secret deployment key; for example, the secret value can be derived as a 32-bit value, the first 16 bits can be used as the configuration file deployment key, and the last 16 bits can be used as the business secret deployment Key.
  • the user can deploy the service key to the FPGA board through the service secret deployment key.
  • the service key may include the node private key and the service root key.
  • the user can use the business secret deployment key on the client to sign, encrypt the node private key or the business root key, and send it to the FPGA board, so that after the FPGA board is decrypted and verified through the decryption verification module, Deploy the obtained node private key or service root key.
  • the FPGA board can be implemented as a TEE on the blockchain node to meet privacy requirements. For example, when a blockchain node receives a transaction, if the transaction is a plaintext transaction, the blockchain node can directly process the plaintext transaction, if the transaction is a private transaction, the blockchain node transmits the private transaction to the FPGA The board is processed.
  • the transaction content of a plaintext transaction is in plaintext form, and the contract status generated after the transaction is executed is also stored in plaintext form.
  • the transaction content of a private transaction is in the form of cipher text, which is obtained by encrypting the content of the transaction in plain text by the transaction initiator, and the contract state generated after the transaction is executed needs to be stored in the form of cipher text to ensure the protection of transaction privacy.
  • the transaction initiator can generate a symmetric key randomly or based on other methods.
  • the business public key corresponding to the above-mentioned business private key is disclosed, then the transaction initiator can perform transaction content in plaintext based on the symmetric key and the business public key.
  • the transaction initiator encrypts the plaintext transaction content with a symmetric key, and encrypts the symmetric key with the business public key.
  • the two parts obtained are included in the above-mentioned private transaction; in other words, the private transaction includes Two parts of content: the content of the transaction in plaintext encrypted with a symmetric key, and the symmetric key encrypted with the business public key.
  • the encryption and decryption module can use the business private key to decrypt the symmetric key encrypted with the business public key to obtain the symmetric key, and then the encryption and decryption module
  • the symmetric key is used to decrypt the plaintext transaction content encrypted with the symmetric key to obtain the plaintext transaction content.
  • Private transactions can be used to deploy smart contracts, then the data field of the plaintext transaction content can contain the contract code of the smart contract to be deployed; or, the privacy transaction can be used to call the smart contract, then the to field of the plaintext transaction content can contain the called The contract address of the smart contract, and the FPGA board can retrieve the corresponding contract code based on the contract address.
  • the FPGA board can deploy the contract code contained in the data field of the plaintext transaction content to the on-chip cache module. Then, when the FPGA board subsequently receives a private transaction for invoking the smart contract, the FPGA board can find the corresponding contract code from the on-chip cache module based on the contract address contained in the to field of the plaintext transaction content, to The contract code is executed through the plaintext calculation module.
  • the plaintext calculation module formed on the FPGA chip is used to implement virtual machine logic in related technologies, that is, the plaintext calculation module is equivalent to the "hardware virtual machine" on the FPGA board.
  • the contract code can be passed into the plaintext calculation module, so that the plaintext calculation module executes the contract code.
  • the plaintext calculation module is equivalent to the on-chip processor formed on the FPGA chip in this specification.
  • the FPGA board For private transactions used to deploy smart contracts, after the FPGA board obtains the contract code to be deployed, it can be directly stored in the on-chip cache module, or it can be preprocessed through the preprocessing module, and then the preprocessed contract code is stored in On-chip cache module. If it is not preprocessed by the preprocessing module before being stored in the on-chip cache module, the plaintext calculation module needs to temporarily perform preprocessing operations through the preprocessing module before it is used to execute the contract code, and then the plaintext calculation module will perform the preprocessing operation Contract code for processing.
  • the plaintext calculation module can directly obtain the preprocessed contract code from the on-chip cache module, and can directly execute the contract code without temporary Implement preprocessing operations to speed up transaction execution and reduce latency.
  • preprocessing of contract code can include several dimensions, and the preprocessing dimensions involved may be different for contract codes written in different languages or rules.
  • preprocessing can include the following two aspects:
  • Adjust the offset of the jump instruction may cause the offset of the jump instruction to be updated: by parsing the jump instruction in the contract code, the symbol identifier corresponding to the jump instruction is converted into address information that can be recognized by the on-chip processor, so that the length of the contract code changes ; Decode the encoded operands in the contract code, so that the length of the contract code changes.
  • the encoding method here may include LEB (Little-Endian Base) encoding or other encodings, for example.
  • FIG. 4 is a schematic structural diagram of a blockchain node provided by an exemplary embodiment.
  • the FPGA board may further include an external DDR, and the external DDR can implement data interaction with the FPGA chip. Then, the external DDR can realize the above-mentioned related functions of the on-chip cache module, such as caching the contract code.
  • the external DDR is not on the FPGA chip
  • the data on the FPGA chip needs to be encrypted by the encryption and decryption module before being transmitted to the external DDR to ensure that only ciphertext data exists on the external DDR
  • the data on the external DDR also needs
  • the obtained plaintext data can be applied to processing operations such as on-chip processors.
  • the external DDR involves data encryption and decryption and the data transmission efficiency is relatively lower, but it is relatively better than the data transmission efficiency between the FPGA board and the blockchain node.
  • the storage space of the external DDR is often larger or even much larger than the storage space of the on-chip cache module, so the external DDR can help to achieve more data cache.
  • the FPGA board can contain both on-chip cache module and external DDR.
  • the relatively more popular contract code can be cached in the on-chip cache module, and the relatively less popular contract code can be maintained in the external DDR.
  • the user may want to update the version of the circuit logic configuration file deployed on the FPGA board.
  • the authentication root key contained in the circuit logic configuration file may be known by risky users, or the user wants to update the version on the FPGA board.
  • the deployed functional modules are upgraded, etc. This manual does not limit this.
  • the circuit logic configuration file that has been deployed in the above process can be referred to as the old version of the circuit logic configuration file, and the circuit logic configuration file that needs to be deployed is referred to as the new version of the circuit logic configuration file.
  • the user can generate a new version of the circuit logic configuration file through the process of writing code and mirroring. Further, the user can sign the new version of the circuit logic configuration file with his own private key, and then encrypt the signed new version of the circuit logic configuration file with the configuration file deployment key negotiated above to obtain the encrypted new version of the circuit Logical configuration file. In some cases, there may be multiple users at the same time, so the old version of the circuit logic configuration file needs to deploy the preset certificates corresponding to these users to the FPGA board, and these users need to use their own private keys to pair the new version of the circuit. Sign the logical configuration file.
  • the user can remotely send the encrypted new version of the circuit logic configuration file to the blockchain node through the client, and the blockchain node will further transfer it to the FPGA board.
  • the decryption verification module formed on the FPGA chip in the foregoing process is located on the transmission path between the PCIE interface and the Flash chip, so that the encrypted new version of the circuit logic configuration file must first be successfully processed by the decryption verification module before it can be
  • the Flash chip is passed in to achieve a credible update, and the Flash chip cannot be updated directly without bypassing the process of decryption and verification.
  • the decryption verification module After the decryption verification module receives the encrypted new version of the circuit logic configuration file, it first decrypts it with the configuration file deployment key deployed on the FPGA board. If the decryption is successful, the decryption verification module is further based on the preset certificate deployed on the FPGA chip , To perform signature verification on the decrypted new version of the circuit logic configuration file.
  • the decryption and signature verification module will trigger the termination of the update operation; and if the decryption is successful and the signature verification is passed, you can It is determined that the obtained new version of the circuit logic configuration file is from the aforementioned user and has not been tampered with during the transmission process.
  • the new version of the circuit logic configuration file can be further transmitted to the Flash chip to update and deploy the old version of the circuit logic configuration file in the Flash chip.
  • the above-mentioned plaintext calculation module, on-chip cache module, key agreement module, encryption and decryption module, decryption verification module, and storage in the FPGA chip can also be formed on the FPGA chip. Enter the preset certificate, and store the authentication root key to the secret management chip and other information.
  • the formed plaintext calculation module, on-chip cache module, key agreement module, encryption/decryption module, decryption and signature verification module, etc., the implemented functional logic can be changed and upgraded, and stored in the deployed preset certificate, authentication root Information such as keys may also be different from the information before the update.
  • the FPGA board can remotely negotiate with the user to obtain a new configuration file deployment key based on the updated key agreement module, authentication root key, etc., and the configuration file deployment key can be used for the next renewal Update process. Similarly, a reliable update operation for FPGA boards can be continuously implemented accordingly.
  • the FPGA board can generate certification results for the new version of the circuit logic configuration file.
  • the above-mentioned key agreement module can calculate the hash value of the new version of the circuit logic configuration file and the hash value of the configuration file deployment key negotiated based on the new version of the circuit logic configuration file through an algorithm such as sm3 or other algorithms.
  • the calculation result can be used as the above-mentioned authentication result, and the key agreement module sends the authentication result to the user.
  • the user can verify the authentication result on the client based on the maintained new version of the circuit logic configuration file and the configuration file deployment key negotiated accordingly. If the verification is successful, it indicates that the new version of the circuit logic configuration file is successful on the FPGA board. Deployed, and the user and the FPGA board successfully negotiated accordingly to obtain a consistent configuration file deployment key, thereby confirming the successful completion of the circuit logic configuration file update deployment.
  • Fig. 5 is a schematic structural diagram of a device for implementing contract invocation based on FPGA provided by an exemplary embodiment.
  • the device for implementing contract calls based on FPGA may include: a transaction acquisition unit 501, which enables the FPGA structure to acquire transactions received by the blockchain node to which it belongs; and an address determination unit 502, which enables all The FPGA structure determines the contract address of the smart contract called by the transaction; the program obtaining unit 503 enables the FPGA structure to obtain the code program corresponding to the contract address from the local space, so as to run the code on the FPGA structure program.
  • the local space includes: on-chip storage space of the FPGA chip included in the FPGA structure, and/or external storage space of the FPGA chip.
  • the code program in the on-chip storage space is stored in plain text.
  • the code program in the external storage space is stored in ciphertext; the program obtaining unit 503 is specifically configured to: enable the FPGA structure to obtain the encryption corresponding to the contract address from the external storage space After the code program; enable the FPGA structure to decrypt the encrypted code program through the decryption module on the FPGA chip to obtain the code program; wherein the decryption module is loaded by the FPGA chip into the FPGA structure It is formed on the logic configuration file of the deployed circuit.
  • the code program in the local space is obtained after preprocessing the original code program.
  • the preprocessing includes at least one of the following: parsing and converting each field contained in the code program into a preset data structure; adjusting the offset of the jump instruction in the code program.
  • the address determining unit 502 is specifically configured to: when the transaction is in an encrypted state, cause the FPGA structure to transfer the transaction to the decryption module on the FPGA chip contained in the FPGA structure, and the decryption The module is formed by loading the FPGA chip with a circuit logic configuration file deployed on the FPGA structure; enabling the FPGA structure to extract the contract address from the decrypted transaction content output by the decryption module.
  • a program transfer unit 504 which causes the FPGA structure to transfer the code program to the FPGA chip contained in itself to form an on-chip processor for realizing virtual machine logic; wherein, the on-chip processor It is formed by the FPGA chip loading the circuit logic configuration file that has been deployed on the FPGA structure.
  • a typical implementation device is a computer.
  • the specific form of the computer can be a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email receiving and sending device, and a game control A console, a tablet computer, a wearable device, or a combination of any of these devices.
  • a computer includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.
  • processors CPUs
  • input/output interfaces network interfaces
  • memory volatile and non-volatile memory
  • the memory may include non-permanent memory in a computer readable medium, random access memory (RAM) and/or non-volatile memory, such as read-only memory (ROM) or flash memory (flash RAM). Memory is an example of computer readable media.
  • RAM random access memory
  • ROM read-only memory
  • flash RAM flash memory
  • Computer-readable media include permanent and non-permanent, removable and non-removable media, and information storage can be realized by any method or technology.
  • the information can be computer-readable instructions, data structures, program modules, or other data.
  • Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, CD-ROM, digital versatile disc (DVD) or other optical storage, Magnetic cassettes, disk storage, quantum memory, graphene-based storage media or other magnetic storage devices or any other non-transmission media can be used to store information that can be accessed by computing devices. According to the definition in this article, computer-readable media does not include transitory media, such as modulated data signals and carrier waves.
  • first, second, third, etc. may be used to describe various information in one or more embodiments of this specification, the information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other.
  • first information may also be referred to as second information, and similarly, the second information may also be referred to as first information.
  • word “if” as used herein can be interpreted as "when” or “when” or "in response to determination”.

Abstract

一种基于FPGA实现合约调用的方法及装置，该方法可以包括：FPGA结构获取自身所属的区块链节点接收到的交易（102）；所述FPGA结构确定所述交易调用的智能合约的合约地址（104）；所述FPGA结构从本地空间中获取所述合约地址对应的代码程序，以在所述FPGA结构上运行所述代码程序（106）。

Description

基于FPGA实现合约调用的方法及装置 技术领域
本说明书一个或多个实施例涉及区块链技术领域，尤其涉及一种基于FPGA实现合约调用的方法及装置。
背景技术
区块链技术构建在传输网络(例如点对点网络)之上。传输网络中的网络节点利用链式数据结构来验证与存储数据，并采用分布式节点共识算法来生成和更新数据。
目前企业级的区块链平台技术上最大的两个挑战就是隐私和性能，往往这两个挑战很难同时解决。大多解决方案都是通过损失性能换取隐私，或者不大考虑隐私去追求性能。常见的解决隐私问题的加密技术，如同态加密(Homomorphic encryption)和零知识证明(Zero-knowledge proof)等复杂度高，通用性差，而且还可能带来严重的性能损失。
可信执行环境(Trusted Execution Environment,TEE)是另一种解决隐私问题的方式。TEE可以起到硬件中的黑箱作用，在TEE中执行的代码和数据操作系统层都无法偷窥，只有代码中预先定义的接口才能对其进行操作。在效率方面，由于TEE的黑箱性质，在TEE中进行运算的是明文数据，而不是同态加密中的复杂密码学运算，计算过程效率没有损失，因此与TEE相结合可以在性能损失较小的前提下很大程度上提升区块链的安全性和隐私性。目前工业界十分关注TEE的方案，几乎所有主流的芯片和软件联盟都有自己的TEE解决方案，包括软件方面的TPM(Trusted Platform Module，可信赖平台模块)以及硬件方面的Intel SGX(Software Guard Extensions,软件保护扩展)、ARM Trustzone(信任区)和AMD PSP(Platform Security Processor，平台安全处理器)。
发明内容
有鉴于此，本说明书一个或多个实施例提供一种基于FPGA实现合约调用的方法及装置。
为实现上述目的，本说明书一个或多个实施例提供技术方案如下。
根据本说明书一个或多个实施例的第一方面，提出了一种基于FPGA实现合约调 用的方法，包括：FPGA结构获取自身所属的区块链节点接收到的交易；所述FPGA结构确定所述交易调用的智能合约的合约地址；所述FPGA结构从本地空间中获取所述合约地址对应的代码程序，以在所述FPGA结构上运行所述代码程序。
根据本说明书一个或多个实施例的第二方面，提出了一种基于FPGA实现合约调用的装置，包括：交易获取单元，使FPGA结构获取自身所属的区块链节点接收到的交易；地址确定单元，使所述FPGA结构确定所述交易调用的智能合约的合约地址；程序获取单元，使所述FPGA结构从本地空间中获取所述合约地址对应的代码程序，以在所述FPGA结构上运行所述代码程序。
根据本说明书一个或多个实施例的第三方面，提出了一种电子设备，包括：处理器；用于存储处理器可执行指令的存储器；其中，所述处理器通过运行所述可执行指令以实现如第一方面所述的方法。
根据本说明书一个或多个实施例的第四方面，提出了一种计算机可读存储介质，其上存储有计算机指令，该指令被处理器执行时实现如第一方面所述方法的步骤。
附图说明
图1是一示例性实施例提供的一种基于FPGA实现合约调用的方法的流程图。
图2是一示例性实施例提供的一种区块链节点的结构示意图。
图3是一示例性实施例提供的一种在FPGA芯片上形成功能模块的示意图。
图4是一示例性实施例提供的另一种区块链节点的结构示意图。
图5是一示例性实施例提供的一种基于FPGA实现合约调用的装置的框图。
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本说明书一个或多个实施例相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本说明书一个或多个实施例的一些方面相一致的装置和方法的例子。
需要说明的是：在其他实施例中并不一定按照本说明书示出和描述的顺序来执行 相应方法的步骤。在一些其他实施例中，其方法所包括的步骤可以比本说明书所描述的更多或更少。此外，本说明书中所描述的单个步骤，在其他实施例中可能被分解为多个步骤进行描述；而本说明书中所描述的多个步骤，在其他实施例中也可能被合并为单个步骤进行描述。
区块链一般被划分为三种类型：公有链(Public Blockchain)，私有链(Private Blockchain)和联盟链(Consortium Blockchain)。此外，还有多种类型的结合，比如私有链+联盟链、联盟链+公有链等不同组合形式。其中去中心化程度最高的是公有链。公有链以比特币、以太坊为代表，加入公有链的参与者可以读取链上的数据记录、参与交易以及竞争新区块的记账权等。而且，各参与者(即节点)可自由加入以及退出网络，并进行相关操作。私有链则相反，该网络的写入权限由某个组织或者机构控制，数据读取权限受组织规定。简单来说，私有链可以为一个弱中心化系统，参与节点具有严格限制且少。这种类型的区块链更适合于特定机构内部使用。联盟链则是介于公有链以及私有链之间的区块链，可实现“部分去中心化”。联盟链中各个节点通常有与之相对应的实体机构或者组织；参与者通过授权加入网络并组成利益相关联盟，共同维护区块链运行。
不论是公有链、私有链还是联盟链，区块链网络中的节点出于隐私保护的目的，均可能通过区块链与TEE(Trusted Execution Environment，可信执行环境)相结合的解决方案，在TEE内执行收到的交易。TEE是基于CPU硬件的安全扩展，且与外部完全隔离的可信执行环境。TEE最早是由Global Platform提出的概念，用于解决移动设备上资源的安全隔离，平行于操作系统为应用程序提供可信安全的执行环境。ARM的Trust Zone技术最早实现了真正商用的TEE技术。伴随着互联网的高速发展，安全的需求越来越高，不仅限于移动设备，云端设备，数据中心都对TEE提出了更多的需求。TEE的概念也得到了高速的发展和扩充。现在所说的TEE相比与最初提出的概念已经是更加广义的TEE。例如，服务器芯片厂商Intel，AMD等都先后推出了硬件辅助的TEE并丰富了TEE的概念和特性，在工业界得到了广泛的认可。现在提起的TEE通常更多指这类硬件辅助的TEE技术。
以Intel SGX技术为例，SGX提供了围圈(enclave，也称为飞地)，即内存中一个加密的可信执行区域，由CPU保护数据不被窃取。以第一区块链节点采用支持SGX的CPU为例，利用新增的处理器指令，在内存中可以分配一部分区域EPC(Enclave Page Cache，围圈页面缓存或飞地页面缓存)，通过CPU内的加密引擎MEE(Memory  Encryption Engine)对其中的数据进行加密。EPC中加密的内容只有进入CPU后才会被解密成明文。因此，在SGX中，用户可以不信任操作系统、VMM(Virtual Machine Monitor，虚拟机监控器)、甚至BIOS(Basic Input Output System，基本输入输出系统)，只需要信任CPU便能确保隐私数据不会泄漏。因此，围圈就相当于SGX技术下产生的TEE。
不同于移动端，云端访问需要远程访问，终端用户对硬件平台不可见，因此使用TEE的第一步就是要确认TEE的真实可信。例如，相关技术中提供了针对上述SGX技术的远程证明机制，以用于证明目标设备上的SGX平台与挑战方部署了相同的配置文件。但是，由于相关技术中的TEE技术是以软件或软硬件结合的方式实现，使得即便通过远程证明方式可以在一定程度上表明TEE内所部署的配置文件未经篡改，但是TEE本身所依托的运行环境却无法被验证。例如，在需要实现隐私功能的区块链节点上，TEE内需要配置用于执行智能合约的虚拟机，该虚拟机所执行的指令并非直接执行，而是实际上执行了对应的若干条X86指令(假定目标设备采用X86架构)，从而造成了一定程度上的安全性风险。
为此，本说明书提出了一种基于FPGA实现的硬件TEE技术，FPGA通过加载电路逻辑配置文件而实现硬件TEE。由于电路逻辑配置文件的内容可以被预先查看与检验，并且FPGA完全基于电路逻辑配置文件中记载的逻辑而配置运行，因而可以确保FPGA所实现的硬件TEE具有相对更高的安全性。但是，相关技术中智能合约的代码程序都部署于区块链节点处，使得FPGA需要频繁从区块链节点获取代码程序，导致消耗大量资源。
以下结合实施例说明本说明书提供的一种基于FPGA实现合约调用的方法，以减少数据交互次数。
图1是一示例性实施例提供的一种基于FPGA实现合约调用的方法的流程图。如图1所示，该方法应用于FPGA结构，可以包括步骤102～106。
步骤102，FPGA结构获取自身所属的区块链节点接收到的交易。
区块链节点包括节点主机。FPGA结构与节点主机相连，使得该FPGA结构可以与节点主机之间实现数据交互，也可以描述为FPGA结构与区块链节点之间实现数据交互。譬如，区块链节点可以将接收到的交易传输至FPGA结构，以由FPGA结构执行该交易所涉及的智能合约。FPGA结构可以插接于区块链节点的节点主机上的PCIE接口上， 以实现上述的连接关系；或者，还可以采用其他类型的接口，甚至可能采用无线方式建立连接，本说明书并不对此进行限制。
交易发起方可以在上述的区块链节点处提交上述交易。或者，交易发起方可以在其他区块链节点处提交上述交易，并由其他区块链节点将该交易传输至上述区块链节点。或者，上述区块链节点可以通过其他方式获得上述交易，本说明书并不对此进行限制。
步骤104，所述FPGA结构确定所述交易调用的智能合约的合约地址。
上述交易可以处于加密状态。例如，区块链节点可以识别所收到的交易是否被加密，并将处于加密状态的交易传输至FPGA结构予以处理，而在区块链节点本地处理未加密的交易。
FPGA结构上包含FPGA芯片，通过将该FPGA结构上已部署的电路逻辑配置文件加载至FPGA芯片上，可使该FPGA芯片上形成解密模块。那么，在上述交易处于加密状态的情况下，FPGA结构可以将该交易传入上述的解密模块，并在解密模块输出的解密后交易内容中提取交易调用的智能合约的合约地址，譬如该合约地址通常位于解密后交易内容的to字段。
步骤106，所述FPGA结构从本地空间中获取所述合约地址对应的代码程序，以在所述FPGA结构上运行所述代码程序。
FPGA结构包含本地空间，该本地空间可以用于维护至少一部分已部署的智能合约的代码程序。因此，FPGA结构可以在至少一部分场景下直接从本地空间中获得所需的代码程序，而无需与区块链节点进行交互，可以节省该交互所带来的资源消耗、加快代码程序的获取速度、提升交易执行效率。在一些场景中，如果本地空间仅存储了部分智能合约的代码程序，而其余智能合约的代码程序被部署于区块链节点处，那么FPGA结构可能遇到无法在本地空间获取合约地址对应的代码程序的情况，FPGA结构可以进而向区块链节点请求获取该合约地址对应的代码程序。
上述的本地空间可以存在多种情况。例如，该本地空间可以包括：FPGA结构所含的FPGA芯片的片上存储空间，或该FPGA芯片的外接存储空间，或者同时包含片上存储空间和外接存储空间。片上存储空间位于FPGA芯片内部，由该FPGA芯片上的存储器件形成。外接存储空间位于FPGA芯片外部，可以插接至FPGA结构的接口上，譬如该外接存储空间可以包括外接DDR等。
由于FPGA芯片内部被认为处于安全范围、FPGA芯片外部被认为存在安全风险， 因而当代码程序存储于片上存储空间时，可以直接以明文形式进行存储，而当代码程序存储于外接存储空间时，需要通过FPGA芯片上的加密模块对代码程序进行加密后实现存储，其中加密模块由FPGA芯片加载前述已部署的电路逻辑配置文件而形成。因此，在前述从本地空间获取代码程序的过程中，如果代码程序被缓存在片上缓存空间，则可以直接从该片上缓存空间读取代码程序并读入片上处理器，如果代码程序被缓存在外接存储空间，则需要通过FPGA芯片上的前述解密模块对从外接存储空间读取的代码程序进行解密，并将解密得到的代码程序读入片上处理器。
FPGA结构将智能合约的代码程序存储至本地空间时，可以直接存储原始代码程序，譬如该原始代码程序可以为字节码程序。或者，FPGA结构可以对原始代码程序进行预处理，并将预处理后的代码程序存入本地空间。这里的预处理是指在执行原始代码程序之前必须预先实施的处理操作，通过在存入本地空间之前实施预处理，使得FPGA结构在后续执行该代码程序时，可以省去临时执行预处理所需消耗的运算资源和处理时间，有助于加快代码程序的执行速度。其中，上述预处理可以包括以下至少之一：将代码程序所含的各个字段解析并转换为预设数据结构，调整代码程序中的跳转指令(jump指令)的偏移量(offset)。
在执行交易的过程中，针对从本地空间或区块链节点处获得的代码程序，FPGA结构可将该代码程序传入自身包含的FPGA芯片上形成用于实现虚拟机逻辑的片上处理器，譬如该虚拟机逻辑可以包括以太坊虚拟机的执行逻辑或者WASM虚拟机的执行逻辑等，本说明书并不对此进行限制；其中，该片上处理器由FPGA芯片加载FPGA结构上已部署的电路逻辑配置文件而形成。
FPGA芯片上包含若干可编辑的硬件逻辑单元，这些硬件逻辑单元经由电路逻辑配置文件进行配置后，可以实现为相应的功能模块，以用于实现相应的逻辑功能。具体的，该电路逻辑配置文件可以基于比特流的形式被烧录至FPGA结构。例如，上述的解密模块、加密模块、片上处理器即为通过已部署的电路逻辑配置文件而形成，而通过进一步部署相关的其他功能模块，可以将FPGA结构配置为区块链节点上的硬件TEE。由于这些功能模块完全由电路逻辑配置文件进行配置而形成，因而通过检查电路逻辑配置文件即可确定由此配置得到的功能模块所实现的逻辑等各方面的信息，确保功能模块能够按照完全用户的需求而形成和运行。
用户生成电路逻辑配置文件后，如果位于FPGA结构所在地点处，则可以在本地将该电路逻辑配置文件部署至FPGA结构，譬如可以在离线环境下实施部署操作，以确 保安全性。或者，在FPGA结构处于线上环境的情况下，用户可以将电路逻辑配置文件远程部署至FPGA结构。
图2是一示例性实施例提供的一种区块链节点的结构示意图。基于本说明书的技术方案，可以在区块链节点上添加FPGA结构以实现硬件TEE，譬如该FPGA结构可以为如图2所示的FPGA板卡。FPGA板卡可以通过PCIE接口连接至区块链节点上，以实现FPGA板卡与区块链节点之间的数据交互。FPGA板卡可以包括FPGA芯片、Flash(闪存)芯片和密管芯片等结构；当然，在一些实施例中除了包含FPGA芯片之外，可能仅包含剩余的Flash芯片和密管芯片等中的部分结构，或者可能包含更多结构，此处仅用于举例。
在初始阶段，FPGA芯片上并未烧录用户定义的任何逻辑，相当于FPGA芯片处于空白状态。用户可以通过向FPGA芯片上烧录电路逻辑配置文件，以在FPGA芯片上形成相应的功能或逻辑。在首次烧录电路逻辑配置文件时，FPGA板卡不具有安全防护的能力，因而通常需要外部提供安全环境，比如用户可以在离线环境下实施对电路逻辑配置文件的烧录以实现物理安全隔离，而非在线上实施远程烧录。
针对用户所需实现的功能或逻辑，可以通过FPGA硬件语言形成相应的逻辑代码，并进而对该逻辑代码进行镜像化处理，即可得到上述的电路逻辑配置文件。在烧录至FPGA板卡之前，用户可以针对上述的逻辑代码进行检查。尤其是，当同时涉及到多个用户时，多个用户可以分别对上述的逻辑代码进行检查，以确保FPGA板卡最终能够满足所有用户的需求，防止出现安全性风险、逻辑错误、欺诈等异常问题。
在确定代码无误后，用户可以在上述的离线环境下，将电路逻辑配置文件烧录至FPGA板卡上。具体的，电路逻辑配置文件被从区块链节点传入FPGA板卡，进而部署至如图2所示的Flash芯片中，使得即便FPGA板卡发生掉电，Flash芯片仍然能够保存上述的电路逻辑配置文件。
图3是一示例性实施例提供的一种在FPGA芯片上形成功能模块的示意图。通过将Flash芯片中所部署的电路逻辑配置文件加载至FPGA芯片，可以对FPGA芯片所含的硬件逻辑单元进行配置，从而在FPGA芯片上形成相应的功能模块，譬如所形成的功能模块可以包括如图3所示的片上缓存模块、预处理模块、明文计算模块、密钥协商模块、解密验签模块、加解密模块等。同时，电路逻辑配置文件还可以用于向FPGA板卡传输需要存储的信息，比如可以将预置证书存储于FPGA芯片上、将认证根密钥存储于密管芯片中(认证根密钥也可以存储于FPGA芯片上)等。
基于FPGA芯片上所形成的密钥协商模块，以及部署于FPGA板卡上的认证根密钥，使得FPGA板卡可以与用户实现远程的密钥协商，该密钥协商过程可以采用相关技术中的任意算法或标准来实现，本说明书并不对此进行限制。举例而言，密钥协商过程可以包括：用户可以在本地的客户端生成一密钥Ka-1、密钥协商模块可以在本地生成一密钥Kb-1，且客户端可以基于密钥Ka-1计算得到密钥协商信息Ka-2、密钥协商模块可以基于密钥Kb-1计算得到密钥协商信息Kb-2，然后客户端将密钥协商信息Ka-2发送至密钥协商模块、密钥协商模块将密钥协商信息Kb-2发送至客户端，使得客户端可以基于密钥Ka-1与密钥协商信息Kb-2生成一秘密值，而密钥协商模块可以基于密钥Kb-1与密钥协商信息Ka-2生成相同的秘密值，最后由客户端、密钥协商模块分别基于密钥导出函数从该相同的秘密值导出相同的配置文件部署密钥，该配置文件部署密钥可以存在FPGA芯片或密管芯片。在上述过程中，虽然密钥协商信息Ka-2、密钥协商信息Kb-2是经由区块链节点在客户端与密钥协商模块之间传输，但是由于密钥Ka-1由客户端掌握、密钥Kb-1由密钥协商模块掌握，因而可以确保区块链节点无法获知最终得到的秘密值和配置文件部署密钥，避免可能造成的安全性风险。
除了配置文件部署密钥之外，秘密值还用于导出业务秘密部署密钥；例如，秘密值可以导出32位数值，可以将前16位作为配置文件部署密钥、后16位作为业务秘密部署密钥。用户可以通过业务秘密部署密钥向FPGA板卡部署业务密钥，譬如该业务密钥可以包括节点私钥和业务根密钥。例如，用户可以在客户端上采用业务秘密部署密钥对节点私钥或业务根密钥进行签名、加密并发送至FPGA板卡，使得FPGA板卡通过解密验签模块进行解密、验签后，对得到的节点私钥或业务根密钥进行部署。
基于部署的节点密钥、业务根密钥和FPGA芯片上的加解密模块、明文计算模块，使得FPGA板卡可以实现为区块链节点上的TEE，以满足隐私需求。例如，当区块链节点收到一笔交易时，如果该交易为明文交易，区块链节点可以直接处理该明文交易，如果该交易为隐私交易，区块链节点将该隐私交易传入FPGA板卡进行处理。
明文交易的交易内容为明文形式，并且交易执行后所产生的合约状态等同样采用明文形式进行存储。隐私交易的交易内容为密文形式，由交易发起方对明文交易内容进行加密而得到，且交易执行后产生的合约状态等需要采用密文形式进行存储，从而确保交易隐私保护。例如，交易发起方可以随机或基于其他方式生成一对称密钥，同样上述的业务私钥对应的业务公钥被公开，那么交易发起方可以基于该对称密钥和业务公钥对明文交易内容进行数字信封加密：交易发起方通过对称密钥加密明文交易内容，并通过 业务公钥对该对称密钥进行加密，得到的两部分内容均被包含于上述的隐私交易中；换言之，隐私交易中包含两部分内容：采用对称密钥加密的明文交易内容、采用业务公钥加密的对称密钥。
因此，FPGA板卡在收到区块链节点传入的隐私交易后，可由加解密模块通过业务私钥对采用业务公钥加密的对称密钥进行解密、得到对称密钥，然后由加解密模块通过对称密钥对采用对称密钥加密的明文交易内容进行解密、得到明文交易内容。隐私交易可以用于部署智能合约，那么明文交易内容的data字段可以包含待部署的智能合约的合约代码；或者，隐私交易可以用于调用智能合约，那么明文交易内容的to字段可以包含被调用的智能合约的合约地址，而FPGA板卡可以基于该合约地址调取相应的合约代码。
当隐私交易用于部署智能合约时，FPGA板卡可以将明文交易内容的data字段所含的合约代码部署至片上缓存模块中。那么，当FPGA板卡后续收到用于调用该智能合约的隐私交易时，FPGA板卡可以基于明文交易内容的to字段所含的合约地址，从片上缓存模块中查找到相应的合约代码，以通过明文计算模块执行该合约代码。其中，FPGA芯片上形成的明文计算模块用于实现相关技术中的虚拟机逻辑，即明文计算模块相当于FPGA板卡上的“硬件虚拟机”。因此，基于上述明文交易内容确定出合约代码后，可以将该合约代码传入明文计算模块中，以由该明文计算模块执行该合约代码。该明文计算模块相当于本说明书中在FPGA芯片上形成的片上处理器。
针对用于部署智能合约的隐私交易，FPGA板卡在获得待部署的合约代码后，可以直接存入片上缓存模块，或者可以通过预处理模块进行预处理，然后将预处理后的合约代码存入片上缓存模块。如果在存入片上缓存模块之前未通过预处理模块进行预处理，那么明文计算模块在用于执行该合约代码之前，需要临时通过预处理模块实施预处理操作，然后由明文计算模块对预处理后的合约代码进行处理。可见，如果将经过预处理模块实施预处理之后的合约代码存入片上缓存模块，则明文计算模块可以直接从片上缓存模块获得已经过预处理的合约代码，并且可以直接执行该合约代码而无需临时实施预处理操作，从而加快交易执行速度、降低延迟。
针对合约代码的预处理可以包括若干维度，并且针对不同语言或规则所编写的合约代码，所涉及的预处理维度可能存在差异。以wasm智能合约的合约代码为例，预处理可以包括以下两个方面：
1)数据格式转换。对合约代码进行数据结构解析，并转换为所需的预设格式的数据结构，以便于后续执行。
2)调整jump指令的偏移量。下述两个方面可能导致jump指令的偏移量产生更新：通过解析合约代码中的jump指令，将jump指令对应的symbol标识转换为片上处理器能够识别的地址信息，使得合约代码的长度发生变化；对合约代码中经过编码的操作数进行解码，使得合约代码的长度发生变化，这里的编码方式譬如可以包括LEB(Little-Endian Base)编码或其他编码。
除了在FPGA芯片上配置片上缓存模块之外，还可以为FPGA芯片配置外接存储空间。例如，图4是一示例性实施例提供的一种区块链节点的结构示意图。如图4所示，在图2所示实施例的基础上，FPGA板卡上可以进一步包含外接DDR，该外接DDR可与FPGA芯片之间实现数据交互。那么，该外接DDR可以实现上述的片上缓存模块的相关功能，譬如针对合约代码进行缓存等。但由于外接DDR并未处于FPGA芯片上，因而FPGA芯片上的数据传输至外接DDR之前需要经过加解密模块的加密处理，以确保外接DDR上仅存在密文数据，而外接DDR上的数据同样需要经过加解密模块的解密处理后，得到的明文数据才能够被应用于诸如片上处理器的处理操作。虽然相比于片上缓存模块而言，外接DDR涉及到数据加解密且数据传输效率相对更低，但相对优于FPGA板卡与区块链节点之间的数据传输效率。
相对而言，外接DDR的存储空间往往大于甚至远大于片上缓存模块的存储空间，因而外接DDR可以有助于实现更多数据的缓存。当然，FPGA板卡上可以同时包含片上缓存模块和外接DDR，例如可以将热度相对更高的合约代码缓存于片上缓存模块，而将热度相对更低的合约代码维护于外接DDR中。
基于一些原因，用户可能希望对FPGA板卡上部署的电路逻辑配置文件进行版本更新，比如该电路逻辑配置文件所含的认证根密钥可能被风险用户获知、再比如用户希望对FPGA板卡上部署的功能模块进行升级等，本说明书并不对此进行限制。为了便于区分，可以将上述过程中已部署的电路逻辑配置文件称之为旧版电路逻辑配置文件，而将需要部署的电路逻辑配置文件称之为新版电路逻辑配置文件。
与旧版电路逻辑配置文件相类似的，用户可以通过编写代码、镜像化等过程生成新版电路逻辑配置文件。进一步的，用户可以通过自身持有的私钥对新版电路逻辑配置文件进行签名，然后通过上文协商出的配置文件部署密钥对签名后的新版电路逻辑配置文件进行加密，得到加密后新版电路逻辑配置文件。在一些情况下，可能同时存在多名用户，那么旧版电路逻辑配置文件需要将这些用户对应的预置证书均部署至FPGA板卡中，且这些用户需要分别采用自身持有的私钥对新版电路逻辑配置文件进行签名。
用户可以通过客户端远程将加密后新版电路逻辑配置文件发送至区块链节点，并由区块链节点进一步将其传入FPGA板卡。前述过程中在FPGA芯片上形成的解密验签模块位于PCIE接口与Flash芯片之间的传输通路上，使得加密后新版电路逻辑配置文件必然需要优先经过解密验签模块的成功处理后，才能够被传入Flash芯片以实现可信更新，无法绕过解密验签的过程而直接对Flash芯片进行更新。
解密验签模块在收到加密后新版电路逻辑配置文件后，首先通过FPGA板卡上部署的配置文件部署密钥进行解密，如果解密成功则解密验签模块进一步基于FPGA芯片上部署的预置证书，对解密后的新版电路逻辑配置文件进行签名验证。如果解密失败或者签名验证未通过，则说明收到的文件并非来自上述用户或者遭到篡改，解密验签模块将触发终止本次的更新操作；而在解密成功且验签通过的情况下，可以确定得到的新版电路逻辑配置文件来自上述用户且传输过程中未遭到篡改，可以将该新版电路逻辑配置文件进一步传输至Flash芯片，以针对Flash芯片中的旧版电路逻辑配置文件进行更新部署。
新版电路逻辑配置文件被加载至FPGA芯片后，同样可以在该FPGA芯片上形成诸如上述的明文计算模块、片上缓存模块、密钥协商模块、加解密模块、解密验签模块，以及向FPGA芯片存入预置证书、向密管芯片存入认证根密钥等信息。其中，所形成的明文计算模块、片上缓存模块、密钥协商模块、加解密模块、解密验签模块等，所实现的功能逻辑可以发生变化和升级，所存入部署的预置证书、认证根密钥等信息也可能区别于更新前的信息。那么，FPGA板卡可以基于更新后的密钥协商模块、认证根密钥等，与用户进行远程协商得到新的配置文件部署密钥，该配置文件部署密钥可以被用于下一次的可新更新过程。类似地，可以据此不断实现针对FPGA板卡的可信更新操作。
在完成更新部署后，FPGA板卡可以针对新版电路逻辑配置文件生成认证结果。例如，上述的密钥协商模块可以通过诸如sm3算法或其他算法对新版电路逻辑配置文件的哈希值、基于新版电路逻辑配置文件协商得到的配置文件部署密钥的哈希值进行计算，得到的计算结果可以被作为上述的认证结果，并由密钥协商模块将该认证结果发送至用户。相应地，用户可以在客户端上基于所维护的新版电路逻辑配置文件和据此协商的配置文件部署密钥对认证结果进行验证，如果验证成功则表明新版电路逻辑配置文件在FPGA板卡上成功部署，且用户与FPGA板卡之间据此成功协商得到了一致的配置文件部署密钥，从而确认成功完成了针对电路逻辑配置文件的更新部署。
图5是一示例性实施例提供的一种基于FPGA实现合约调用的装置的示意结构图。 请参考图5，在软件实施方式中，该基于FPGA实现合约调用的装置可以包括：交易获取单元501，使FPGA结构获取自身所属的区块链节点接收到的交易；地址确定单元502，使所述FPGA结构确定所述交易调用的智能合约的合约地址；程序获取单元503，使所述FPGA结构从本地空间中获取所述合约地址对应的代码程序，以在所述FPGA结构上运行所述代码程序。
可选的，所述本地空间包括：所述FPGA结构所含的FPGA芯片的片上存储空间，和/或所述FPGA芯片的外接存储空间。
可选的，所述片上存储空间内的代码程序以明文形式进行存储。
可选的，所述外接存储空间内的代码程序以密文形式进行存储；所述程序获取单元503具体用于：使所述FPGA结构从所述外接存储空间内获取所述合约地址对应的加密后代码程序；使所述FPGA结构通过所述FPGA芯片上的解密模块对所述加密后代码程序进行解密，得到所述代码程序；其中，所述解密模块由所述FPGA芯片加载所述FPGA结构上已部署的电路逻辑配置文件而形成。
可选的，所述本地空间内的代码程序由原始代码程序经过预处理后得到。
可选的，所述预处理包括以下至少之一：将代码程序所含的各个字段解析并转换为预设数据结构；调整所述代码程序中的跳转指令的偏移量。
可选的，所述地址确定单元502具体用于：在所述交易处于加密状态的情况下，使所述FPGA结构将所述交易传入自身所含的FPGA芯片上的解密模块，所述解密模块由所述FPGA芯片加载所述FPGA结构上已部署的电路逻辑配置文件而形成；使所述FPGA结构在所述解密模块输出的解密后交易内容中提取所述合约地址。
可选的，还包括：程序传入单元504，使所述FPGA结构将所述代码程序传入自身包含的FPGA芯片上形成用于实现虚拟机逻辑的片上处理器；其中，所述片上处理器由所述FPGA芯片加载所述FPGA结构上已部署的电路逻辑配置文件而形成。
上述实施例阐明的系统、装置、模块或单元，具体可以由计算机芯片或实体实现，或者由具有某种功能的产品来实现。一种典型的实现设备为计算机，计算机的具体形式可以是个人计算机、膝上型计算机、蜂窝电话、相机电话、智能电话、个人数字助理、媒体播放器、导航设备、电子邮件收发设备、游戏控制台、平板计算机、可穿戴设备或者这些设备中的任意几种设备的组合。
在一个典型的配置中，计算机包括一个或多个处理器(CPU)、输入/输出接口、 网络接口和内存。
内存可能包括计算机可读介质中的非永久性存储器，随机存取存储器(RAM)和/或非易失性内存等形式，如只读存储器(ROM)或闪存(flash RAM)。内存是计算机可读介质的示例。
计算机可读介质包括永久性和非永久性、可移动和非可移动媒体可以由任何方法或技术来实现信息存储。信息可以是计算机可读指令、数据结构、程序的模块或其他数据。计算机的存储介质的例子包括，但不限于相变内存(PRAM)、静态随机存取存储器(SRAM)、动态随机存取存储器(DRAM)、其他类型的随机存取存储器(RAM)、只读存储器(ROM)、电可擦除可编程只读存储器(EEPROM)、快闪记忆体或其他内存技术、只读光盘只读存储器(CD-ROM)、数字多功能光盘(DVD)或其他光学存储、磁盒式磁带、磁盘存储、量子存储器、基于石墨烯的存储介质或其他磁性存储设备或任何其他非传输介质，可用于存储可以被计算设备访问的信息。按照本文中的界定，计算机可读介质不包括暂存电脑可读媒体(transitory media)，如调制的数据信号和载波。
还需要说明的是，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、商品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、商品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、商品或者设备中还存在另外的相同要素。
上述对本说明书特定实施例进行了描述。其它实施例在所附权利要求书的范围内。在一些情况下，在权利要求书中记载的动作或步骤可以按照不同于实施例中的顺序来执行并且仍然可以实现期望的结果。另外，在附图中描绘的过程不一定要求示出的特定顺序或者连续顺序才能实现期望的结果。在某些实施方式中，多任务处理和并行处理也是可以的或者可能是有利的。
在本说明书一个或多个实施例使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本说明书一个或多个实施例。在本说明书一个或多个实施例和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。还应当理解，本文中使用的术语“和/或”是指并包含一个或多个相关联的列出项目的任何或所有可能组合。
应当理解，尽管在本说明书一个或多个实施例可能采用术语第一、第二、第三等来描述各种信息，但这些信息不应限于这些术语。这些术语仅用来将同一类型的信息彼此区分开。例如，在不脱离本说明书一个或多个实施例范围的情况下，第一信息也可以被称为第二信息，类似地，第二信息也可以被称为第一信息。取决于语境，如在此所使用的词语“如果”可以被解释成为“在……时”或“当……时”或“响应于确定”。
以上所述仅为本说明书一个或多个实施例的较佳实施例而已，并不用以限制本说明书一个或多个实施例，凡在本说明书一个或多个实施例的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本说明书一个或多个实施例保护的范围之内。

Claims (11)

  1. 一种基于FPGA实现合约调用的方法，包括：
    FPGA结构获取自身所属的区块链节点接收到的交易；
    所述FPGA结构确定所述交易调用的智能合约的合约地址；
    所述FPGA结构从本地空间中获取所述合约地址对应的代码程序，以在所述FPGA结构上运行所述代码程序。
  2. 根据权利要求1所述的方法，所述本地空间包括：所述FPGA结构所含的FPGA芯片的片上存储空间，和/或所述FPGA芯片的外接存储空间。
  3. 根据权利要求2所述的方法，所述片上存储空间内的代码程序以明文形式进行存储。
  4. 根据权利要求2所述的方法，所述外接存储空间内的代码程序以密文形式进行存储；所述FPGA结构从本地空间中获取所述合约地址对应的代码程序，包括：
    所述FPGA结构从所述外接存储空间内获取所述合约地址对应的加密后代码程序；
    所述FPGA结构通过所述FPGA芯片上的解密模块对所述加密后代码程序进行解密，得到所述代码程序；其中，所述解密模块由所述FPGA芯片加载所述FPGA结构上已部署的电路逻辑配置文件而形成。
  5. 根据权利要求1所述的方法，所述本地空间内的代码程序由原始代码程序经过预处理后得到。
  6. 根据权利要求5所述的方法，所述预处理包括以下至少之一：将代码程序所含的各个字段解析并转换为预设数据结构；调整所述代码程序中的跳转指令的偏移量。
  7. 根据权利要求1所述的方法，所述FPGA结构确定所述交易调用的智能合约的合约地址，包括：
    在所述交易处于加密状态的情况下，所述FPGA结构将所述交易传入自身所含的FPGA芯片上的解密模块，所述解密模块由所述FPGA芯片加载所述FPGA结构上已部署的电路逻辑配置文件而形成；
    所述FPGA结构在所述解密模块输出的解密后交易内容中提取所述合约地址。
  8. 根据权利要求1所述的方法，还包括：
    所述FPGA结构将所述代码程序传入自身包含的FPGA芯片上形成用于实现虚拟机逻辑的片上处理器；
    其中，所述片上处理器由所述FPGA芯片加载所述FPGA结构上已部署的电路逻辑配置文件而形成。
  9. 一种基于FPGA实现合约调用的装置，包括：
    交易获取单元，使FPGA结构获取自身所属的区块链节点接收到的交易；
    地址确定单元，使所述FPGA结构确定所述交易调用的智能合约的合约地址；
    程序获取单元，使所述FPGA结构从本地空间中获取所述合约地址对应的代码程序，以在所述FPGA结构上运行所述代码程序。
  10. 一种电子设备，包括：
    处理器；
    用于存储处理器可执行指令的存储器；
    其中，所述处理器通过运行所述可执行指令以实现如权利要求1-8中任一项所述的方法。
  11. 一种计算机可读存储介质，其上存储有计算机指令，该指令被处理器执行时实现如权利要求1-8中任一项所述方法的步骤。
PCT/CN2020/107119 2019-09-25 2020-08-05 基于fpga实现合约调用的方法及装置 WO2021057272A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910913486.0 2019-09-25
CN201910913486.0A CN110751555B (zh) 2019-09-25 2019-09-25 基于fpga实现合约调用的方法及装置

Publications (1)

Publication Number Publication Date
WO2021057272A1 true WO2021057272A1 (zh) 2021-04-01

Family

ID=69277097

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/107119 WO2021057272A1 (zh) 2019-09-25 2020-08-05 基于fpga实现合约调用的方法及装置

Country Status (2)

Country Link
CN (2) CN112927077B (zh)
WO (1) WO2021057272A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115987513A (zh) * 2023-03-17 2023-04-18 山东浪潮科学研究院有限公司 分布式数据库分片加密、解密方法、装置、设备及介质

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112927077B (zh) * 2019-09-25 2022-05-24 支付宝(杭州)信息技术有限公司 基于fpga实现合约调用的方法及装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107103472A (zh) * 2017-04-26 2017-08-29 北京计算机技术及应用研究所 一种用于区块链的算法处理模块
CN109831298A (zh) * 2019-01-31 2019-05-31 阿里巴巴集团控股有限公司 区块链中安全更新密钥的方法及节点、存储介质
CN109886682A (zh) * 2019-01-31 2019-06-14 阿里巴巴集团控股有限公司 区块链中实现合约调用的方法及节点、存储介质
WO2019120315A2 (en) * 2019-03-26 2019-06-27 Alibaba Group Holding Limited Field-programmable gate array based trusted execution environment for use in a blockchain network
CN110751555A (zh) * 2019-09-25 2020-02-04 支付宝(杭州)信息技术有限公司 基于fpga实现合约调用的方法及装置

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017011601A1 (en) * 2015-07-14 2017-01-19 Fmr Llc Computationally efficient transfer processing, auditing, and search apparatuses, methods and systems
US10546156B2 (en) * 2017-01-19 2020-01-28 Intel Corporation MRC training in FPGA-in-memory-controller
US11488121B2 (en) * 2017-05-11 2022-11-01 Microsoft Technology Licensing, Llc Cryptlet smart contract
US10681033B2 (en) * 2017-10-16 2020-06-09 Microsoft Technology Licensing, Llc Selecting and securing proof delgates for cryptographic functions
US10880071B2 (en) * 2018-02-23 2020-12-29 Samsung Electronics Co., Ltd. Programmable blockchain solid state drive and switch
CN108833398B (zh) * 2018-06-08 2020-12-15 深圳智链未来科技有限公司 一种区块链智能合约更新方法、装置及设备
US11836721B2 (en) * 2018-06-29 2023-12-05 Intel Corporation Protection of information in an information exchange
CN109376541A (zh) * 2018-09-21 2019-02-22 上海点融信息科技有限责任公司 用于运行智能合约的方法、装置以及计算机存储介质
CN109358859B (zh) * 2018-09-27 2021-07-30 上海点融信息科技有限责任公司 在区块链网络中安装智能合约的方法、装置及存储介质
CN109670335A (zh) * 2018-12-20 2019-04-23 众安信息技术服务有限公司 用于在区块链与链外数据之间进行交互的方法及装置
CN110008735B (zh) * 2019-01-31 2020-05-19 阿里巴巴集团控股有限公司 区块链中实现合约调用的方法及节点、存储介质

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107103472A (zh) * 2017-04-26 2017-08-29 北京计算机技术及应用研究所 一种用于区块链的算法处理模块
CN109831298A (zh) * 2019-01-31 2019-05-31 阿里巴巴集团控股有限公司 区块链中安全更新密钥的方法及节点、存储介质
CN109886682A (zh) * 2019-01-31 2019-06-14 阿里巴巴集团控股有限公司 区块链中实现合约调用的方法及节点、存储介质
WO2019120315A2 (en) * 2019-03-26 2019-06-27 Alibaba Group Holding Limited Field-programmable gate array based trusted execution environment for use in a blockchain network
CN110751555A (zh) * 2019-09-25 2020-02-04 支付宝(杭州)信息技术有限公司 基于fpga实现合约调用的方法及装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115987513A (zh) * 2023-03-17 2023-04-18 山东浪潮科学研究院有限公司 分布式数据库分片加密、解密方法、装置、设备及介质

Also Published As

Publication number Publication date
CN110751555A (zh) 2020-02-04
CN112927077A (zh) 2021-06-08
CN112927077B (zh) 2022-05-24
CN110751555B (zh) 2021-01-12

Similar Documents

Publication Publication Date Title
WO2021103794A1 (zh) 在区块链中实现隐私保护的高效交易方法及装置
WO2021057181A1 (zh) 基于fpga的密钥协商方法及装置
WO2020233623A1 (zh) 结合交易类型和判断条件的收据存储方法和节点
WO2020233626A1 (zh) 结合交易与用户类型的条件限制的收据存储方法和节点
WO2020233635A1 (zh) 结合多类型维度的条件限制的收据存储方法和节点
WO2020233631A1 (zh) 基于交易类型的收据存储方法和节点
WO2020233625A1 (zh) 结合用户类型和判断条件的收据存储方法和节点
WO2021057182A1 (zh) Fpga逻辑的可信更新方法及装置
WO2021057166A1 (zh) 在fpga中实现外部调用的方法及装置
WO2021057168A1 (zh) 基于fpga实现虚拟机运算的方法及装置
WO2021057180A1 (zh) 基于fpga实现隐私区块链的方法及装置
WO2020233624A1 (zh) 结合交易类型和事件函数类型的收据存储方法和节点
WO2020233619A1 (zh) 结合用户类型与交易类型的收据存储方法和节点
WO2020233627A1 (zh) 多类型维度的收据存储方法和节点
WO2020238955A1 (zh) 基于交易偏移量实现动态加密的方法及装置
WO2021057184A1 (zh) 基于fpga的安全智能合约处理器的高效运算方法及装置
WO2020233634A1 (zh) 结合交易与事件类型的条件限制的收据存储方法和节点
WO2021057167A1 (zh) 基于fpga的安全智能合约处理器的交易处理方法及装置
WO2021057124A1 (zh) 基于fpga实现隐私区块链的方法及装置
WO2021057272A1 (zh) 基于fpga实现合约调用的方法及装置
WO2021057273A1 (zh) 在fpga上实现高效合约调用的方法及装置
WO2021057221A1 (zh) 基于fpga实现状态更新的方法及装置
WO2021057141A1 (zh) 基于fpga的流水线式指令读取方法及装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20870340

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20870340

Country of ref document: EP

Kind code of ref document: A1