WO2021057141A1

WO2021057141A1 - Pipelined instruction reading method and apparatus based on fpga

Info

Publication number: WO2021057141A1
Application number: PCT/CN2020/098522
Authority: WO
Inventors: 潘国振; 魏长征; 闫莺
Original assignee: 支付宝(杭州)信息技术有限公司
Priority date: 2019-09-25
Filing date: 2020-06-28
Publication date: 2021-04-01
Also published as: CN110750303A; CN110750303B

Abstract

A pipelined instruction reading method and apparatus based on an FPGA. The method may comprise: an on-chip processor on an FPGA chip determining a code program to be executed, wherein the on-chip processor is formed by the FPGA chip loading a circuit logic configuration file that has been deployed on an FPGA structure to which the FPGA chip belongs, and the code program corresponds to a smart contract called by a transaction and received by a blockchain node to which the FPGA structure belongs (102); and during a process in which the on-chip processor sequentially reads, according to a preset length, data contained in the code program, parsing the end bit of a non-fixed-length operation instruction contained in a data segment read each time, so that a data segment read next time is adjacent to the end bit (104).

Description

FPGA-based pipelined instruction reading method and device

Technical field

One or more embodiments of this specification relate to the field of blockchain technology, and in particular to an FPGA-based pipelined instruction reading method and device.

Background technique

Blockchain technology is built on a transmission network (such as a peer-to-peer network). The network nodes in the transmission network use chained data structures to verify and store data, and use distributed node consensus algorithms to generate and update data.

At present, the two biggest challenges in enterprise-level blockchain platform technology are privacy and performance. It is often difficult to solve these two challenges at the same time. Most of the solutions are to lose performance in exchange for privacy, or do not consider privacy to pursue performance. Common encryption technologies that solve privacy problems, such as Homomorphic encryption and Zero-knowledge proof, are highly complex, have poor versatility, and may also cause serious performance losses.

Trusted Execution Environment (TEE) is another way to solve privacy issues. TEE can play the role of a black box in the hardware. Neither the code executed in the TEE nor the data operating system layer can be peeped, and only the pre-defined interface in the code can operate on it. In terms of efficiency, due to the black box nature of TEE, plaintext data is calculated in TEE instead of complex cryptographic operations in homomorphic encryption. There is no loss of efficiency in the calculation process. Therefore, the combination with TEE can achieve less performance loss. Under the premise, the security and privacy of the blockchain are greatly improved. At present, the industry is very concerned about the TEE solution. Almost all mainstream chip and software alliances have their own TEE solutions, including TPM (Trusted Platform Module) in software and Intel SGX (Software Guard Extensions) in hardware. , Software Protection Extension), ARM Trustzone (trust zone) and AMD PSP (Platform Security Processor, platform security processor).

Summary of the invention

In view of this, one or more embodiments of this specification provide a pipelined instruction reading method and device based on FPGA.

In order to achieve the foregoing objectives, one or more embodiments of this specification provide technical solutions as follows: According to the first aspect of one or more embodiments of this specification, an FPGA-based pipelined instruction reading method is proposed, including: FPGA chip The on-chip processor determines the code program to be executed. The on-chip processor is formed by the FPGA chip loading the deployed circuit logic configuration file on the FPGA structure to which it belongs, and the code program corresponds to the area to which the FPGA structure belongs. The smart contract called by the transaction received by the blockchain node; the on-chip processor reads the data contained in the code program according to the preset length and parses out the non-deterministic data contained in the data segment read each time. The end bit of the operation instruction is long, so that the data segment read next time is adjacent to the end bit.

According to the second aspect of one or more embodiments of this specification, an FPGA-based pipelined instruction reading device is proposed, which includes: a determining unit that enables an on-chip processor on the FPGA chip to determine the code program to be executed, and The on-chip processor is formed by the FPGA chip loading the deployed circuit logic configuration file on the FPGA structure to which the FPGA structure belongs, and the code program corresponds to the smart contract of the transaction call received by the blockchain node to which the FPGA structure belongs; parsing unit , So that the on-chip processor in the process of sequentially reading the data contained in the code program according to the preset length, parses out the end bit of the non-fixed-length operation instruction contained in the data segment read each time, so that the next The data segment read this time is adjacent to the end bit.

According to a third aspect of one or more embodiments of this specification, an electronic device is proposed, including: a processor; a memory for storing executable instructions of the processor; wherein the processor runs the executable instructions In order to realize the method as described in the first aspect.

According to the fourth aspect of one or more embodiments of the present specification, a computer-readable storage medium is provided, on which computer instructions are stored, and when the instructions are executed by a processor, the steps of the method described in the first aspect are implemented.

Description of the drawings

Fig. 1 is a flowchart of an FPGA-based pipelined instruction reading method provided by an exemplary embodiment.

Fig. 2 is a schematic structural diagram of a blockchain node provided by an exemplary embodiment.

Fig. 3 is a schematic diagram of forming a functional module on an FPGA chip provided by an exemplary embodiment.

Fig. 4 is a schematic diagram of reading operation instructions in a pipeline manner according to an exemplary embodiment.

Fig. 5 is a block diagram of an FPGA-based pipelined instruction reading device provided by an exemplary embodiment.

detailed description

The exemplary embodiments will be described in detail here, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings indicate the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with one or more embodiments of this specification. Rather, they are merely examples of devices and methods consistent with some aspects of one or more embodiments of this specification as detailed in the appended claims.

It should be noted that in other embodiments, the steps of the corresponding method are not necessarily executed in the order shown and described in this specification. In some other embodiments, the method may include more or fewer steps than described in this specification. In addition, a single step described in this specification may be decomposed into multiple steps for description in other embodiments; and multiple steps described in this specification may also be combined into a single step in other embodiments. description.

Block chains are generally divided into three types: Public Blockchain, Private Blockchain and Consortium Blockchain. In addition, there are many types of combinations, such as private chain + alliance chain, alliance chain + public chain and other different combinations. Among them, the most decentralized one is the public chain. The public chain is represented by Bitcoin and Ethereum. Participants who join the public chain can read the data records on the chain, participate in transactions, and compete for the accounting rights of new blocks. Moreover, each participant (ie, node) can freely join and exit the network, and perform related operations. The private chain is the opposite. The write permission of the network is controlled by an organization or institution, and the data read permission is regulated by the organization. In simple terms, the private chain can be a weakly centralized system with strict restrictions and few participating nodes. This type of blockchain is more suitable for internal use by specific institutions. Consortium chain is a block chain between public chain and private chain, which can realize "partial decentralization". Each node in the alliance chain usually has a corresponding entity or organization; participants are authorized to join the network and form a stakeholder alliance to jointly maintain the operation of the blockchain.

Regardless of whether it is a public chain, a private chain or a consortium chain, for the purpose of privacy protection, the nodes in the blockchain network may use a solution that combines the blockchain and the TEE (Trusted Execution Environment). Execute received transactions within TEE. TEE is a secure extension based on CPU hardware and a trusted execution environment that is completely isolated from the outside. TEE was first proposed by Global Platform to solve the security isolation of resources on mobile devices, and parallel to the operating system to provide a trusted and secure execution environment for applications. ARM's Trust Zone technology is the first to realize the real commercial TEE technology. With the rapid development of the Internet, security requirements are getting higher and higher. Not only mobile devices, cloud devices, and data centers have put forward more demands on TEE. The concept of TEE has also been rapidly developed and expanded. Compared with the originally proposed concept, the TEE referred to now is a more generalized TEE. For example, server chip manufacturers Intel and AMD have successively introduced hardware-assisted TEE and enriched the concepts and features of TEE, which has been widely recognized in the industry. The TEE mentioned now usually refers more to this kind of hardware-assisted TEE technology.

Taking Intel SGX technology as an example, SGX provides an enclave (also called an enclave), which is an encrypted trusted execution area in the memory, and the CPU protects data from being stolen. Taking the first blockchain node using a CPU that supports SGX as an example, using the newly added processor instructions, a part of the area EPC (Enclave Page Cache, enclave page cache or enclave page cache) can be allocated in the memory, and through the CPU The encryption engine MEE (Memory Encryption Engine) encrypts the data in it. The encrypted content in EPC will be decrypted into plain text only after entering the CPU. Therefore, in SGX, users can distrust the operating system, VMM (Virtual Machine Monitor), and even BIOS (Basic Input Output System). They only need to trust the CPU to ensure that private data will not leakage. Therefore, the enclosure is equivalent to the TEE produced under SGX technology.

Different from the mobile terminal, cloud access requires remote access, and the end user is invisible to the hardware platform. Therefore, the first step in using TEE is to confirm the authenticity of TEE. For example, the related technology provides a remote certification mechanism for the above-mentioned SGX technology to prove that the SGX platform on the target device and the challenger have deployed the same configuration file. However, because the TEE technology in the related technology is implemented by software or a combination of software and hardware, even if the remote attestation method can indicate to a certain extent that the configuration file deployed in the TEE has not been tampered with, the TEE itself depends on the operation The environment cannot be verified. For example, on a blockchain node that needs to implement privacy functions, a virtual machine for executing smart contracts needs to be configured in the TEE. The instructions executed by the virtual machine are not directly executed, but actually executed corresponding X86 instructions (Assuming that the target device adopts the X86 architecture), which poses a certain degree of security risk.

To this end, this specification proposes a hardware TEE technology based on FPGA implementation. FPGA implements hardware TEE by loading circuit logic configuration files. Because the content of the circuit logic configuration file can be checked and verified in advance, and the FPGA is configured and operated completely based on the logic recorded in the circuit logic configuration file, it can be ensured that the hardware TEE implemented by the FPGA has relatively higher security. At the same time, by improving the instruction reading method of the code program in this specification, the execution efficiency of the code program can be improved.

The following describes an FPGA-based pipelined instruction reading method provided in this specification with reference to embodiments, so as to improve the execution efficiency of the code program.

Fig. 1 is a flowchart of an FPGA-based pipelined instruction reading method provided by an exemplary embodiment. As shown in FIG. 1, the method is applied to the FPGA structure and may include the following steps 102 to 104.

Step 102: The on-chip processor on the FPGA chip determines the code program to be executed. The on-chip processor is formed by the FPGA chip loading the circuit logic configuration file deployed on the FPGA structure to which it belongs, and the code program corresponds to the The smart contract called by the transaction received by the blockchain node to which the FPGA structure belongs.

The FPGA chip contains a number of editable hardware logic units. After these hardware logic units are configured via a circuit logic configuration file, they can be implemented as corresponding functional modules to implement corresponding logic functions. Specifically, the circuit logic configuration file can be burned to the FPGA structure based on the form of a bit stream. For example, the above-mentioned on-chip processor is formed by the deployed circuit logic configuration file, and by further deploying other related functional modules, the FPGA structure can be configured as a hardware TEE on the blockchain node. Since these functional modules are completely configured by the circuit logic configuration file, it is possible to determine the logic and other aspects of the information realized by the functional module configured by checking the circuit logic configuration file to ensure that the functional module can be configured according to the complete user’s requirements. Needs to be formed and run. The above-mentioned on-chip processor is used to implement virtual machine logic. For example, the virtual machine logic may include the execution logic of the Ethereum virtual machine or the execution logic of the WASM virtual machine, etc. This specification does not limit this.

After the user generates the circuit logic configuration file, if it is located at the location of the FPGA structure, the circuit logic configuration file can be deployed locally to the FPGA structure. For example, the deployment operation can be implemented in an offline environment to ensure safety. Or, when the FPGA structure is in an online environment, the user can remotely deploy the circuit logic configuration file to the FPGA structure.

The FPGA structure can obtain the contract address of the smart contract called by the exchange by parsing the to field of the transaction, and obtain the code program of the corresponding smart contract based on the contract address. If the transaction is encrypted and submitted to the blockchain by the transaction initiator, the FPGA structure needs to decrypt the transaction to read the information in the to field. Wherein, by loading the above-mentioned deployed circuit logic configuration file, a decryption module can be formed on the FPGA chip, so that the transaction can be decrypted by the decryption module.

For example, the FPGA structure can maintain a node private key, and the node public key corresponding to the node private key is disclosed. Then, on the one hand, the transaction initiator can obtain the above-mentioned node public key, on the other hand, it can generate a symmetric key by itself, and implement a digital envelope encryption operation on the plaintext transaction content based on the node’s public key and symmetric key: The key encrypts the plaintext transaction content to obtain the ciphertext transaction content, encrypts the symmetric key with the node public key to obtain the ciphertext symmetric key, and the above transaction includes the ciphertext transaction content and the ciphertext symmetric key. Correspondingly, the aforementioned decryption module can decrypt the ciphertext symmetric key contained in the exchange based on the node private key to obtain the symmetric key, and then the decryption module can decrypt the ciphertext transaction content based on the symmetric key to obtain the plaintext transaction content , So as to read the information in the to field in the plaintext transaction content, and determine the contract address of the smart contract called by the exchange.

If the code program corresponding to the contract address can be deployed at the blockchain node, the FPGA structure needs to interact with the blockchain node, such as sending the contract address to the blockchain node and receiving the code program returned by the blockchain node. If the code program corresponding to the contract address is deployed in the local space of the FPGA structure, compared to interacting with the blockchain node, the FPGA structure can obtain the code program from the local space to save resource efficiency and shorten the waiting time. The local space may include on-chip storage space formed on the FPGA chip, or external storage space outside the FPGA chip. For example, the external storage space may include an external DDR plugged into the FPGA structure.

Step 104: In the process of sequentially reading the data contained in the code program according to the preset length, the on-chip processor parses out the end bit of the non-fixed-length operation instruction contained in the data segment read each time, so that The data segment read next time is adjacent to the end bit.

Each time the on-chip processor performs a reading operation on the code program, it always reads data segments of the same length (that is, the aforementioned preset length), so that the on-chip processor can improve the efficiency of data reading. For example, the on-chip processor can read a data segment in each clock cycle, and implement pipelined processing operations for the operation instructions contained in the read data segment, so as to execute a data segment in each clock cycle as much as possible Contains an operation instruction.

Since the operation instructions contained in the code program are not of fixed length (ie, non-fixed length), the on-chip processor cannot read the data segment based on the above-mentioned preset length alone, otherwise the operation instructions may be truncated. For example, the length of the first operation instruction is 3B, the length of the second operation instruction is B, and the length of the third operation instruction is 2B. If the above-mentioned preset length is 2B, the first operation instruction cannot be completely intercepted. Therefore, the above-mentioned preset length should not be less than the maximum length of a single operation instruction in the code program to ensure that the data segment read each time must contain an operation instruction completely; and, assuming that the maximum length of a single operation instruction is 5B, follow When the preset length is 5B to read the data segment, the data segment read for the first time contains not only the first operation instruction, but also the second operation instruction and part of the third operation instruction. If the second data segment read operation is performed after the data segment read the second time, the second operation instruction cannot be read, and the third operation instruction cannot be read completely, so that the code program cannot be executed correctly.

Therefore, the on-chip processor analyzes the data segment read each time to determine the end bit of the contained operation instruction, so that the data segment read next time is adjacent to the end bit instead of the last read. The data segments are adjacent. For example, in the above example, although the data segment with a length of 5B is read for the first time, it can be analyzed to determine that the length of the first operation instruction is 3B. Then, when the data segment is read for the second time, it can be ensured from the first operation instruction. Read the data segment with a length of 5B at the beginning and back to ensure that the read data segment contains the second operation instruction; similarly, the second operation instruction is determined by analyzing the data segment read the second time The length of is B. When reading the data segment for the third time, you can ensure that the data segment of length 5B is read from the second operation instruction and backward to ensure that the read data segment contains the third operation instruction. And so on. It can be seen that, based on the above solution, it is possible to ensure that the on-chip processor can correctly read the data segment according to the fixed preset length every time when the operation instruction has a non-fixed length, so as to improve the efficiency of reading the operation instruction and speed up the operation. The execution efficiency of the code program.

Each operation instruction contained in the code program contains an operation code, which indicates the type of operation to be performed. Further, some operation instructions may include operands, that is, these operation instructions include associated operation codes and operands, and the operands are used as parameters when the corresponding operation codes are executed; among them, the operands contained in the operation instructions can be one or more One, usually one or two. It can be seen that because the operation instructions may or may not include operands, and the number of operands contained is not fixed, the length of different operation instructions is not fixed, thus forming the above-mentioned non-fixed-length operation instructions. In addition, there are other factors that may cause the length of the operation instruction to be non-fixed. For example, in the bytecode used by smart contracts, the length of each operand is usually fixed, for example, it can be 4B or 8B based on different numeric types. However, if the operand is an encoded operand, such as LEB (Little-Endian Base) encoding is usually used in the wasm bytecode program, the length of the operand after encoding will change, usually 2B or 4B. The maximum possible is 5B.

The length of the operation code contained in each operation instruction is fixed, for example, the length of each operation code in the byte code is 1B. When the on-chip processor reads the data segment, the first data segment must start from the start address of the first operation instruction, and because the length of the opcode is fixed, the on-chip processor can parse out the non-indication contained in the data segment read for the first time. The operation code of the fixed-length operation instruction, and determine whether the operation code has a corresponding operand and the number of corresponding operands according to the analysis result; among them, the on-chip processor determines that the non-fixed-length operation instruction contains an operand based on the operation code. In this case, according to the number of operands contained and the length of each operand, the last bit of the last operand is determined as the end bit of the non-fixed-length operation instruction; and the on-chip processor determines the non-fixed bit based on the opcode. When the long operation instruction does not include an operand, the last bit of the opcode is used as the end bit of the non-fixed length operation instruction. Then, the on-chip processor can determine the end bit based on the above method to ensure that the data segment read next time must start from the start address of the second operation instruction to ensure that the on-chip processor can successfully parse the second operation instruction. Operation code, and determine whether the operation code has a corresponding operand and the number of corresponding operands according to the analysis result, and then determine the end bit of the second operation instruction; and so on.

Fig. 2 is a schematic structural diagram of a blockchain node provided by an exemplary embodiment. Based on the technical solution in this specification, an FPGA structure can be added to the blockchain node to implement hardware TEE. For example, the FPGA structure can be an FPGA board as shown in FIG. 2. The FPGA board can be connected to the blockchain node through the PCIE interface to realize the data interaction between the FPGA board and the blockchain node. FPGA boards can include FPGA chips, Flash (flash memory) chips, and dense tube chips; of course, in addition to FPGA chips in some embodiments, they may only include parts of the remaining Flash chips and dense tube chips. , Or may contain more structures, here are just examples.

In the initial stage, no user-defined logic is programmed on the FPGA chip, which is equivalent to the FPGA chip in a blank state. Users can burn circuit logic configuration files on the FPGA chip to form corresponding functions or logic on the FPGA chip. When programming the circuit logic configuration file for the first time, the FPGA board does not have the capability of security protection, so it usually needs to provide an external security environment. For example, users can implement the programming of the circuit logic configuration file in an offline environment to achieve physical security isolation. Instead of implementing remote programming online.

For the function or logic that the user needs to implement, the corresponding logic code can be formed through FPGA hardware language, and then the logic code can be mirrored to obtain the above-mentioned circuit logic configuration file. Before programming to the FPGA board, the user can check the above-mentioned logic code. Especially, when multiple users are involved at the same time, multiple users can check the above logic code separately to ensure that the FPGA board can finally meet the needs of all users and prevent security risks, logic errors, fraud and other abnormalities. problem.

After confirming that the code is correct, the user can burn the circuit logic configuration file to the FPGA board in the above-mentioned offline environment. Specifically, the circuit logic configuration file is transferred from the blockchain node to the FPGA board, and then deployed to the Flash chip as shown in Figure 2, so that even if the FPGA board is powered off, the Flash chip can still save the above-mentioned circuit logic. Configuration file.

Fig. 3 is a schematic diagram of forming a functional module on an FPGA chip provided by an exemplary embodiment. By loading the circuit logic configuration file deployed in the Flash chip to the FPGA chip, the hardware logic unit contained in the FPGA chip can be configured to form corresponding functional modules on the FPGA chip. For example, the formed functional modules can include such Figure 3 shows the on-chip cache module, plaintext calculation module, key agreement module, decryption verification module, encryption and decryption module, etc. At the same time, the circuit logic configuration file can also be used to transmit the information that needs to be stored to the FPGA board. For example, the preset certificate can be stored on the FPGA chip, and the authentication root key can be stored in the secret tube chip (the authentication root key can also be Stored on the FPGA chip) and so on.

Based on the key agreement module formed on the FPGA chip and the authentication root key deployed on the FPGA board, the FPGA board can realize remote key agreement with the user. The key agreement process can use related technologies. Any algorithm or standard can be implemented, and this specification does not limit it. For example, the key agreement process can include: the user can generate a key Ka-1 at the local client, the key agreement module can generate a key Kb-1 locally, and the client can generate a key Kb-1 based on the key Ka- 1 Calculate the key agreement information Ka-2, the key agreement module can calculate the key agreement information Kb-2 based on the key Kb-1, and then the client sends the key agreement information Ka-2 to the key agreement module, The key agreement module sends the key agreement information Kb-2 to the client, so that the client can generate a secret value based on the key Ka-1 and the key agreement information Kb-2, and the key agreement module can be based on the key Kb -1 generates the same secret value as the key agreement information Ka-2, and finally the client and the key agreement module respectively derive the same configuration file deployment key from the same secret value based on the key derivation function, and the configuration file deployment The key can be stored in the FPGA chip or the secret management chip. In the above process, although the key agreement information Ka-2 and key agreement information Kb-2 are transmitted between the client and the key agreement module via the blockchain node, the key Ka-1 is controlled by the client , The key Kb-1 is controlled by the key agreement module, so it can ensure that the blockchain node cannot know the final secret value and the configuration file deployment key, so as to avoid possible security risks.

In addition to the configuration file deployment key, the secret value is also used to derive the business secret deployment key; for example, the secret value can be derived as a 32-bit value, the first 16 bits can be used as the configuration file deployment key, and the last 16 bits can be used as the business secret deployment Key. The user can deploy the service key to the FPGA board through the service secret deployment key. For example, the service key may include the node private key and the service root key. For example, the user can use the business secret deployment key on the client to sign, encrypt the node private key or the business root key, and send it to the FPGA board, so that after the FPGA board is decrypted and verified through the decryption verification module, Deploy the obtained node private key or service root key.

Based on the deployed node key, service root key, encryption and decryption module and plaintext calculation module on the FPGA chip, the FPGA board can be implemented as a TEE on the blockchain node to meet privacy requirements. For example, when a blockchain node receives a transaction, if the transaction is a plaintext transaction, the blockchain node can directly process the plaintext transaction, if the transaction is a private transaction, the blockchain node transmits the private transaction to the FPGA The board is processed.

The transaction content of a plaintext transaction is in plaintext form, and the contract status generated after the transaction is executed is also stored in plaintext form. The transaction content of a private transaction is in the form of cipher text, which is obtained by encrypting the content of the transaction in plain text by the transaction initiator, and the contract state generated after the transaction is executed needs to be stored in the form of cipher text to ensure the protection of transaction privacy. For example, the transaction initiator can generate a symmetric key randomly or based on other methods. Similarly, the business public key corresponding to the above-mentioned business private key is disclosed, then the transaction initiator can perform transaction content in plaintext based on the symmetric key and the business public key. Digital Envelope Encryption: The transaction initiator encrypts the plaintext transaction content with a symmetric key, and encrypts the symmetric key with the business public key. The two parts obtained are included in the above-mentioned private transaction; in other words, the private transaction includes Two parts of content: the content of the transaction in plaintext encrypted with a symmetric key, and the symmetric key encrypted with the business public key.

Therefore, after the FPGA board receives the private transaction from the blockchain node, the encryption and decryption module can use the business private key to decrypt the symmetric key encrypted with the business public key to obtain the symmetric key, and then the encryption and decryption module The symmetric key is used to decrypt the plaintext transaction content encrypted with the symmetric key to obtain the plaintext transaction content. Private transactions can be used to deploy smart contracts, then the data field of the plaintext transaction content can contain the contract code of the smart contract to be deployed; or, the privacy transaction can be used to call the smart contract, then the to field of the plaintext transaction content can contain the called The contract address of the smart contract, and the FPGA board can retrieve the corresponding contract code based on the contract address.

The on-chip cache module can be used to cache the contract code and/or the contract state involved in the contract code. In some cases, the FPGA board may have an external DDR, and the contract code and/or contract state involved in the contract code can be stored in the external DDR. Of course, the contract code and/or the contract state involved in the contract code can also be stored at the blockchain node. In contrast, the storage space of the external DDR is often larger or even much larger than the storage space of the on-chip cache module, so the external DDR can help to achieve more data cache. Of course, the FPGA board can contain both on-chip cache module and external DDR. For example, the relatively more popular contract code can be cached in the on-chip cache module, and the relatively less popular contract code can be maintained in the external DDR. And, compared to blockchain nodes, the on-chip cache module and external DDR can be considered as the local space of the FPGA board, and the amount of resources and time consumed for data interaction with the local space is much less than that between the blockchain nodes The data interaction process helps to improve the execution efficiency of smart contracts.

The plaintext calculation module formed on the FPGA chip is used to implement virtual machine logic in related technologies, that is, the plaintext calculation module is equivalent to the "hardware virtual machine" on the FPGA board. Therefore, after the contract code is determined based on the foregoing plaintext transaction content, the contract code can be passed into the plaintext calculation module, so that the plaintext calculation module executes the contract code. The plaintext calculation module is equivalent to the on-chip processor formed on the FPGA chip in this specification.

The process of executing the contract code by the plaintext calculation module can be broken down into the process of reading and executing each operation instruction contained in the contract code. For example, FIG. 4 is a schematic diagram of reading operation instructions in a pipeline manner according to an exemplary embodiment. As shown in Figure 4, assuming that the code program of the contract code includes several operation instructions, the first operation instruction includes operation code P1 and operand Q1, the second operation instruction includes operation code P2 and operands Q21, Q22, and the third operation instruction includes operation code P2 and operands Q21 and Q22. One operation instruction includes operation code P3 and operands Q31, Q32, the fourth operation instruction includes operation code P4, and the fifth operation instruction includes operation code P5 and so on. Assuming that the code program is a wasm bytecode program, the length of each opcode is 1B, and each operand is coded in LEB. The length is usually 2B or 4B and the maximum is not more than 5B. At the same time, each operation instruction contains at most 2 Operand. Based on this, it can be determined that each operation instruction in this embodiment includes at most one operation code and two operands, and the maximum length of each operation instruction is 1+2×5=11B, that is, 88b.

Therefore, in the process of reading the operation instruction, the plaintext calculation module can be set to perform a reading operation in each clock cycle, and each time a data segment with a length of 88b is read. For example, as shown in Figure 4, the plaintext calculation module reads a data segment with a length of 88b in the first clock cycle C1. Since this data segment is the first data segment, the data segment must start with an opcode, making the plaintext calculation module You can directly read the data of the first Byte of the data segment, that is, the operation code P1, and analyze and determine the operand corresponding to the operation code P1. The plaintext calculation module can determine based on the analysis result: there is one operand in the opcode P1, that is, the above-mentioned Q1, and the length of the operand is 2B; and the plaintext calculation module can determine the location of the data segment read by the clock cycle C1 based on this In the second clock cycle C2, the plaintext calculation module can read a data segment with a length of 88b starting from the next bit of the end bit.

Since the end bit in the data segment read in the clock cycle C1 is accurately analyzed, the data segment read by the plaintext calculation module in the clock cycle C2 must start with the opcode of the second operation instruction. Therefore, the plaintext calculation module can analyze the data segment read by clock cycle C2 in a similar manner to the above, and determine that the opcode P2 contained in the data segment has two operands with a length of 2B, that is, the aforementioned operand Q21. , Q22, which determines the end bit of the operation instruction contained in the data segment read in clock cycle C2, and then in the third clock cycle C3, the plaintext calculation module can read the length from the next bit of the end bit The data segment of 88b.

It can be seen that because the plaintext calculation module can accurately analyze the end bit of the operation instruction contained in the read data segment, the data segment in the code program can be sequentially intercepted according to a fixed length in each clock cycle, which is helpful to improve the code The read efficiency of the program speeds up the execution of the smart contract.

For some reasons, the user may want to update the version of the circuit logic configuration file deployed on the FPGA board. For example, the authentication root key contained in the circuit logic configuration file may be known by risky users, or the user wants to update the version on the FPGA board. The deployed functional modules are upgraded, etc. This manual does not limit this. In order to facilitate the distinction, the circuit logic configuration file that has been deployed in the above process can be referred to as the old version of the circuit logic configuration file, and the circuit logic configuration file that needs to be deployed is referred to as the new version of the circuit logic configuration file.

Similar to the old version of the circuit logic configuration file, the user can generate a new version of the circuit logic configuration file through the process of writing code and mirroring. Further, the user can sign the new version of the circuit logic configuration file with his own private key, and then encrypt the signed new version of the circuit logic configuration file with the configuration file deployment key negotiated above to obtain the encrypted new version of the circuit Logical configuration file. In some cases, there may be multiple users at the same time, so the old version of the circuit logic configuration file needs to deploy the preset certificates corresponding to these users to the FPGA board, and these users need to use their own private keys to pair the new version of the circuit. Sign the logical configuration file.

The user can remotely send the encrypted new version of the circuit logic configuration file to the blockchain node through the client, and the blockchain node will further transfer it to the FPGA board. The decryption verification module formed on the FPGA chip in the foregoing process is located on the transmission path between the PCIE interface and the Flash chip, so that the encrypted new version of the circuit logic configuration file must first be successfully processed by the decryption verification module before it can be The Flash chip is passed in to achieve a credible update, and the Flash chip cannot be updated directly without bypassing the process of decryption and verification.

After the decryption verification module receives the encrypted new version of the circuit logic configuration file, it first decrypts it with the configuration file deployment key deployed on the FPGA board. If the decryption is successful, the decryption verification module is further based on the preset certificate deployed on the FPGA chip , To perform signature verification on the decrypted new version of the circuit logic configuration file. If the decryption fails or the signature verification fails, it means that the received file is not from the above-mentioned user or has been tampered with, and the decryption and signature verification module will trigger the termination of the update operation; and if the decryption is successful and the signature verification is passed, you can It is determined that the obtained new version of the circuit logic configuration file is from the aforementioned user and has not been tampered with during the transmission process. The new version of the circuit logic configuration file can be further transmitted to the Flash chip to update and deploy the old version of the circuit logic configuration file in the Flash chip.

After the new version of the circuit logic configuration file is loaded into the FPGA chip, the above-mentioned plaintext calculation module, on-chip cache module, key agreement module, encryption and decryption module, decryption verification module, and storage in the FPGA chip can also be formed on the FPGA chip. Enter the preset certificate, and store the authentication root key to the secret management chip and other information. Among them, the formed plaintext calculation module, on-chip cache module, key agreement module, encryption/decryption module, decryption and signature verification module, etc., the implemented functional logic can be changed and upgraded, and stored in the deployed preset certificate, authentication root Information such as keys may also be different from the information before the update. Then, the FPGA board can remotely negotiate with the user to obtain a new configuration file deployment key based on the updated key agreement module, authentication root key, etc., and the configuration file deployment key can be used for the next renewal Update process. Similarly, a reliable update operation for FPGA boards can be continuously implemented accordingly.

After completing the update deployment, the FPGA board can generate certification results for the new version of the circuit logic configuration file. For example, the above-mentioned key agreement module can calculate the hash value of the new version of the circuit logic configuration file and the hash value of the configuration file deployment key negotiated based on the new version of the circuit logic configuration file through an algorithm such as sm3 or other algorithms. The calculation result can be used as the above-mentioned authentication result, and the key agreement module sends the authentication result to the user. Correspondingly, the user can verify the authentication result on the client based on the maintained new version of the circuit logic configuration file and the configuration file deployment key negotiated accordingly. If the verification is successful, it indicates that the new version of the circuit logic configuration file is successful on the FPGA board. Deployed, and the user and the FPGA board successfully negotiated accordingly to obtain a consistent configuration file deployment key, thereby confirming the successful completion of the circuit logic configuration file update deployment.

Fig. 5 is a schematic structural diagram of an FPGA-based pipelined instruction reading device provided by an exemplary embodiment. Referring to FIG. 5, in a software implementation, the terminal interaction device may include: a determining unit 501, which enables the on-chip processor on the FPGA chip to determine the code program to be executed, and the on-chip processor is loaded by the FPGA chip to the FPGA. The circuit logic configuration file that has been deployed structurally is formed, and the code program corresponds to the smart contract called by the transaction received by the blockchain node to which the FPGA structure belongs; the parsing unit 502 enables the on-chip processor to execute In the process of reading the data contained in the code program by length, the end bit of the non-fixed-length operation instruction contained in the data segment read each time is parsed, so that the data segment read next time is adjacent to the end Bit.

Optionally, the preset length is not less than the maximum length of a single operation instruction in the code program.

Optionally, the parsing unit 502 is specifically configured to: make the on-chip processor parse out the operation code of the non-fixed-length operation instruction contained in the data segment read each time; make the on-chip processor be based on the When the operation code determines that the non-fixed-length operation instruction contains operands, the last bit of the last operand is determined according to the number of operands contained and the length of each operand as the non-fixed-length operation instruction The end bit of the operation code; if the on-chip processor determines that the non-fixed-length operation instruction does not contain an operand based on the operation code, use the last bit of the operation code as the end of the non-fixed-length operation instruction Bit.

Optionally, the operand is a post-encoded operand after LEB encoding.

Optionally, the reading of the data contained in the code program by the on-chip processor includes: the on-chip processor sequentially reads the data contained in the code program at a frequency of reading once per clock cycle.

Optionally, the code program includes a bytecode program.

Optionally, the bytecode program includes a wasm bytecode program.

The systems, devices, modules, or units explained in the above embodiments may be implemented by computer chips or entities, or implemented by products with certain functions. A typical implementation device is a computer. The specific form of the computer can be a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email receiving and sending device, and a game control A console, a tablet computer, a wearable device, or a combination of any of these devices.

In a typical configuration, the computer includes one or more processors (CPU), input/output interfaces, network interfaces, and memory.

The memory may include non-permanent memory in a computer readable medium, random access memory (RAM) and/or non-volatile memory, such as read-only memory (ROM) or flash memory (flash RAM). Memory is an example of computer readable media.

Computer-readable media include permanent and non-permanent, removable and non-removable media, and information storage can be realized by any method or technology. The information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, CD-ROM, digital versatile disc (DVD) or other optical storage, Magnetic cassettes, disk storage, quantum memory, graphene-based storage media or other magnetic storage devices or any other non-transmission media can be used to store information that can be accessed by computing devices. According to the definition in this article, computer-readable media does not include transitory media, such as modulated data signals and carrier waves.

It should also be noted that the terms "include", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or equipment including a series of elements not only includes those elements, but also includes Other elements that are not explicitly listed, or they also include elements inherent to such processes, methods, commodities, or equipment. If there are no more restrictions, the element defined by the sentence "including a..." does not exclude the existence of other identical elements in the process, method, commodity, or equipment that includes the element.

The foregoing describes specific embodiments of this specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps described in the claims may be performed in a different order than in the embodiments and still achieve desired results. In addition, the processes depicted in the drawings do not necessarily require the specific order or sequential order shown in order to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

The terms used in one or more embodiments of this specification are only for the purpose of describing specific embodiments, and are not intended to limit one or more embodiments of this specification. The singular forms "a", "said" and "the" used in one or more embodiments of this specification and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings. It should also be understood that the term "and/or" as used herein refers to and includes any or all possible combinations of one or more associated listed items.

It should be understood that, although the terms first, second, third, etc. may be used to describe various information in one or more embodiments of this specification, the information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of one or more embodiments of this specification, the first information may also be referred to as second information, and similarly, the second information may also be referred to as first information. Depending on the context, the word "if" as used herein can be interpreted as "when" or "when" or "in response to determination".

The foregoing descriptions are only preferred embodiments of one or more embodiments of this specification, and are not intended to limit one or more embodiments of this specification. All within the spirit and principle of one or more embodiments of this specification, Any modification, equivalent replacement, improvement, etc. made should be included in the protection scope of one or more embodiments of this specification.

Claims

A pipelined instruction reading method based on FPGA, including:

The on-chip processor on the FPGA chip determines the code program to be executed. The on-chip processor is formed by the FPGA chip loading the deployed circuit logic configuration file on the FPGA structure to which it belongs, and the code program corresponds to the FPGA structure to which the FPGA structure belongs. The smart contract called by the transaction received by the blockchain node;

In the process of sequentially reading the data contained in the code program according to the preset length, the on-chip processor parses out the end bit of the non-fixed-length operation instruction contained in the data segment read each time, so that the next read The fetched data segment is adjacent to the end bit.
The method according to claim 1, wherein the preset length is not less than the maximum length of a single operation instruction in the code program.
The method according to claim 1, wherein the on-chip processor parses out the end bit of the non-fixed-length operation instruction contained in the data segment read each time, comprising:

The on-chip processor parses out the operation code of the non-fixed-length operation instruction contained in the data segment read each time;

When the on-chip processor determines that the non-fixed-length operation instruction includes an operand based on the opcode, it determines the last bit of the last operand according to the number of operands contained and the length of each operand, As the end bit of the non-fixed length operation instruction;

In the case that the on-chip processor determines based on the operation code that the non-fixed-length operation instruction does not include an operand, the last bit of the operation code is used as the end bit of the non-fixed-length operation instruction.
The method according to claim 3, wherein the operand is an encoded operand after LEB encoding.
The method according to claim 1, wherein the on-chip processor reading the data contained in the code program comprises:

The on-chip processor sequentially reads the data contained in the code program according to the frequency of reading once per clock cycle.
The method according to claim 1, wherein the code program includes a bytecode program.
The method according to claim 6, wherein the bytecode program comprises a wasm bytecode program.
A pipelined instruction reading device based on FPGA, including:

The determining unit enables the on-chip processor on the FPGA chip to determine the code program to be executed. The on-chip processor is formed by the FPGA chip loading the circuit logic configuration file deployed on the FPGA structure to which the code program corresponds The smart contract called by the transaction received by the blockchain node to which the FPGA structure belongs;

The parsing unit enables the on-chip processor to parse out the end bit of the non-fixed-length operation instruction contained in the data segment read each time during the process of sequentially reading the data contained in the code program according to the preset length, and Make the data segment read next time adjacent to the end bit.
An electronic device including:

processor;

A memory for storing processor executable instructions;

Wherein, the processor implements the method according to any one of claims 1-7 by running the executable instruction.
A computer-readable storage medium having computer instructions stored thereon, which, when executed by a processor, implement the steps of the method according to any one of claims 1-7.