WO2021054387A1 - Power packet transmitting device, power packet transmitting system, and power packet transmission control method - Google Patents

Power packet transmitting device, power packet transmitting system, and power packet transmission control method Download PDF

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Publication number
WO2021054387A1
WO2021054387A1 PCT/JP2020/035202 JP2020035202W WO2021054387A1 WO 2021054387 A1 WO2021054387 A1 WO 2021054387A1 JP 2020035202 W JP2020035202 W JP 2020035202W WO 2021054387 A1 WO2021054387 A1 WO 2021054387A1
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Prior art keywords
power
power packet
output
packet
input
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PCT/JP2020/035202
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French (fr)
Japanese (ja)
Inventor
▲隆▼士 引原
翔太 稲垣
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国立大学法人京都大学
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Priority to JP2021546944A priority Critical patent/JPWO2021054387A1/ja
Publication of WO2021054387A1 publication Critical patent/WO2021054387A1/en

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J1/00—Circuit arrangements for dc mains or dc distribution networks
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J1/00—Circuit arrangements for dc mains or dc distribution networks
    • H02J1/10—Parallel operation of dc sources
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J13/00—Circuit arrangements for providing remote indication of network conditions, e.g. an instantaneous record of the open or closed condition of each circuitbreaker in the network; Circuit arrangements for providing remote control of switching means in a power distribution network, e.g. switching in and out of current consumers by using a pulse code signal carried by the network

Definitions

  • the present disclosure relates to a power packet transmission device, a power packet transmission system, and a power packet transmission control method.
  • This application claims priority based on Japanese Patent Application No. 2019-168161 filed on September 17, 2019, and incorporates all the contents described in the Japanese patent application.
  • the power packet is for transmitting pulsed power.
  • the power packet includes a payload having pulsed power and information tags such as headers and footers.
  • Patent Document 1 and Patent Document 2 disclose a power packet transmission system in which a power packet is transmitted.
  • a power packet is generated from the power supplied from a distributed power source.
  • the power packet is transmitted to the load via a router that relays and routes the power packet.
  • the power transmission system since the power is separated by the power packet, the amount of power required by the load can be considered by the number of power packets. That is, the power transmission system can supply the power required by the load to the load by transmitting the number of power packets required by the load to the load.
  • each router included in the power packet transmission system In order to supply power packets to the load in response to the load request, it is desired that each router included in the power packet transmission system appropriately controls the relay of the power packet.
  • the load may not get the power it needs. That is, there may be a difference between the power required by the load and the power actually obtained by the load.
  • the fluctuation of the power of the power packet is caused by, for example, the fluctuation of the power energy stored in the router.
  • Power packets may be generated from the power energy stored in the router. Therefore, fluctuations in the power energy stored in the router affect the power of the power packet.
  • Fluctuations in the power energy stored in the router may occur due to an imbalance between the number of power packets input to the router and the number of power packets output from the router. For example, when there is a power packet input to the router and the router outputs the power packet, the power energy stored in the router itself does not fluctuate so much. On the other hand, when there is no power packet input to the router, in order for the router to output the power packet, it is necessary to release the power energy stored in the router itself. Therefore, the power energy stored in the router itself is reduced.
  • the first aspect of the present disclosure is a power packet transmission device.
  • the power packet transmission device of the embodiment is the difference between the ideal output power determined by the power packet request from the output side of the power packet transmission device and the actual output power determined by the output power packet output from the power packet transmission device.
  • a controller for executing a transmission control process for setting the power of the output power packet so that the output power packet becomes smaller is provided.
  • the second aspect of the present disclosure is a power packet transmission system.
  • the system comprises a power packet transmission device.
  • the third aspect of the present disclosure is a power packet transmission control method.
  • the output is such that the difference between the ideal output power determined by the power packet request and the actual output power determined by the output power packet output based on the power packet request is small. It is provided to set the power possessed by the power packet.
  • FIG. 1 is a configuration diagram of a power packet transmission system.
  • FIG. 2 is a configuration diagram of a power packet.
  • FIG. 3 is a configuration diagram of a power packet transmission device having one input and one output.
  • FIG. 4 is a configuration diagram of a power packet transmission device having a plurality of inputs and a plurality of outputs.
  • FIG. 5 is an explanatory diagram of a time frame and a logical operation for the time frame.
  • FIG. 6 is an explanation of a power packet request and a power packet input / output.
  • FIG. 7 is a diagram showing a power packet request, an input power packet voltage, and an output power packet voltage.
  • FIG. 8 is a diagram showing an output power packet modified from the power packet request.
  • FIG. 1 is a configuration diagram of a power packet transmission system.
  • FIG. 2 is a configuration diagram of a power packet.
  • FIG. 3 is a configuration diagram of a power packet transmission device having one input and one output.
  • FIG. 4
  • FIG. 9 is a flowchart of the transmission control process of the embodiment.
  • FIG. 10 is an explanatory diagram of the dynamic quantizer.
  • FIG. 11 is a circuit diagram of the power packet transmission system according to the embodiment.
  • FIG. 12 is a diagram showing an equation relating to the state ⁇ .
  • FIG. 13 is a correspondence diagram of step S11 of FIG.
  • FIG. 14 is a diagram showing a power packet request, an input power packet, and an output power packet.
  • FIG. 15 is a diagram showing a change in the load voltage V 2.
  • FIG. 16 is a diagram showing an actual voltage error V 2e with respect to an ideal voltage.
  • FIG. 17 is a diagram showing the relationship between the transmission probability and the difference between the average errors.
  • FIG. 18 is a configuration diagram of a power transmission system.
  • FIG. 10 is an explanatory diagram of the dynamic quantizer.
  • FIG. 11 is a circuit diagram of the power packet transmission system according to the embodiment.
  • FIG. 12 is a diagram showing an equation
  • FIG. 19A is a circuit diagram of the router.
  • FIG. 19B is a switch circuit diagram of the router.
  • FIG. 20 is a processing circuit diagram.
  • FIG. 21A is a processing circuit diagram in a non-calculation state.
  • FIG. 21B is a processing circuit diagram of an input state.
  • FIG. 21C is a processing circuit diagram of an input / output state.
  • FIG. 21D is a processing circuit diagram of an output state.
  • FIG. 22 is a data structure diagram of a power packet.
  • FIG. 23 is an explanatory diagram of processing by the controller.
  • FIG. 24A is an explanatory diagram of an input power packet.
  • FIG. 24B is a truth table of AND.
  • FIG. 25A is a diagram showing an input voltage.
  • FIG. 25B is a diagram showing an output voltage.
  • FIG. 26A is a diagram showing an output current.
  • FIG. 26B is a diagram showing a voltage change of the power storage unit.
  • FIG. 27A is a diagram showing an input voltage and an output voltage of the AND operation.
  • FIG. 27B is a diagram showing the output current of the AND operation.
  • FIG. 28 is a diagram showing a truth table of OR, NOT, EXOR, NOR, and NAND.
  • FIG. 29A is a diagram showing an input voltage.
  • FIG. 29B is a diagram showing an output voltage.
  • FIG. 30A is a diagram showing an output current.
  • FIG. 30B is a diagram showing a voltage change of the power storage unit.
  • FIG. 31A is a diagram showing an input voltage and an output voltage of NAND operation.
  • FIG. 31B is a diagram showing the output current of the NAND operation.
  • FIG. 32 is an explanatory diagram of processing by the controller.
  • FIG. 33A is a state transition diagram of the voltage of the power storage unit.
  • FIG. 33B is a table showing inputs, operation types, outputs and states.
  • FIG. 33C is a state transition diagram in the control example.
  • FIG. 34 is a diagram showing a voltage change of the power storage unit.
  • the power packet transmission device is an ideal output power determined by a power packet request from the output side of the power packet transmission device and an actual output power determined by an output power packet output from the power packet transmission device.
  • a controller that executes transmission control processing including setting the power possessed by the output power packet so that the difference between the power and the power is small is provided.
  • the transmission control process reduces the difference between the ideal output power and the actual output power.
  • the power packet transmission device may further include a power processing circuit that generates the output power packet having the power set by the transmission control process.
  • Setting the power of the output power packet can include selecting a logical operation that minimizes the difference from a plurality of logical operations.
  • the power of the output power packet is set according to the calculation result obtained by applying the selected logical operation to the logical value indicated by the power of the input power packet input to the power packet transmission device. It is preferable to be done.
  • the plurality of logical operations may include, for example, a NOT operation that inverts the logical value indicated by the power indicated by the input power packet, and a Through operation that maintains the logical value indicated by the power indicated by the input power packet. it can.
  • the transmission control process can include calculating the difference for each of a plurality of candidate values for the power of the output power packet.
  • the power contained in the output power packet may be set to a candidate value that minimizes the difference among the plurality of candidate values.
  • the output power packet may not be transmitted, or the output transmission packet having 0 power may be transmitted.
  • each of the plurality of candidate values is a logical value.
  • the power of the output power packet may be set to a value different from the power packet request.
  • the difference is preferably calculated based on the value of the power possessed by the input power packet input to the power packet transmission device.
  • the difference is preferably calculated based on the circuit model on the output side.
  • the power packet transmission device further includes a power storage unit that stores the power of the input power packet input to the power packet transmission device.
  • the difference is preferably calculated based on the energy value stored in the power storage unit.
  • the power packet transmission device preferably further includes a measuring unit for measuring the energy value.
  • the power packet request is preferably a request generated in a load device that is a power supply destination.
  • the power packet request may be generated from another power packet transmission device connected to the output side of the power packet transmission device.
  • the power packet transmission system according to the embodiment may include the power packet transmission device. Further, the power packet transmission system according to the embodiment can include a network to which a plurality of power packet transmission devices are connected. It is preferable that at least one or more power packet transmission devices among the plurality of power packet transmission devices are the power packet transmission devices according to any one of items (1) to (11).
  • the difference between the ideal output power determined by the power packet request and the actual output power determined by the output power packet output based on the power packet request is reduced. Can be provided with setting the power contained in the output power packet.
  • FIG. 1 shows a power packet transmission system 10.
  • the system 10 constitutes a network in which electric power is transmitted from the power source 20 to the load 50 by the electric power packet 60.
  • the power source 20 is, for example, a power generation facility or a battery.
  • a plurality of power supplies 20 are distributed and arranged.
  • the power supply 20 is, for example, a DC power supply.
  • System 10 includes a mixer 30.
  • the mixer 30 generates a power packet 60 from the power supplied from the power source 20.
  • the power packet 60 is for transmitting pulsed power.
  • the power packet 60 includes a payload 62 having pulsed power and an information tag including a header 61 and a footer 63.
  • the power packet 60 generated by the mixer 30 is transmitted to the router 40 in the system 10.
  • the information tag is for information transmission, not for power transmission.
  • the header 61 has a destination address of the power packet 60 and the like.
  • the footer 63 has end information of the power packet 60 and the like.
  • the payload 62 is accompanied by an electric current and is for power transmission. Since the electric power is packetized, the electric power is discretized. Therefore, the amount of power transmission is determined by the number or density of power packets 60.
  • the voltage value of the header 61 does not have to be equal to the voltage of the payload 62, and may be the minimum voltage value at which information transmission can be ensured.
  • the system 10 includes a router 40.
  • the power packet 60 is forwarded in the network via the router 40 and reaches the load 50.
  • the router 40 relays the power packet 60 in the network.
  • the router 40 of the embodiment operates as a power packet transmission device that executes a transmission control process of the power packet 60.
  • the router 40 executes a process related to input / output of a power packet as a transmission control process.
  • the router 40 includes a controller 41 and a power processing circuit 45.
  • the controller 41 is composed of a computer having a CPU and a memory.
  • the controller 41 executes the transmission control process. In the transmission control process, the controller 41 controls the power processing circuit 45.
  • the controller 41 acquires the power value (input power value) of the input power packet and the power packet request for the calculation of the error V 2e described later.
  • the controller 41 may send a power packet request to another router 40.
  • the power processing circuit 45 calculates the power of the input power packet 60, and outputs the output power packet 60 having the power corresponding to the calculation result in the payload 62.
  • the power processing circuit 45 includes a power storage unit 46 for storing the power of the input power packet 60. That is, the router 40 can store the electric power transmitted as the electric power packet 60 in the power storage unit 46. The router 40 can regenerate the output power packet from the power stored in the power storage unit 46 and the power of the input power packet 60. Therefore, the router 40 can output the input power packet 60 as the output power packet 60 at an arbitrary timing.
  • the power processing circuit 45 since the power processing circuit 45 performs the power calculation, the power value of the payload 62 of the input power packet 60 and the power value of the payload 62 of the output power packet 60 are the same. It does not have to be. That is, the power value of the output power packet 60 corresponds to the power calculation result with respect to the power value of the input power packet 60.
  • the number of inputs and outputs of the power packet 60 is one input and one output. That is, the number of input ports 45A of the power packet 60 is one.
  • the number of output ports 45B of the power packet 60 is one.
  • the router 40 may include a plurality of input ports 45A and a plurality of output ports 45B. By including the plurality of input ports 45A, the router 40 can receive the power packet 60 from a plurality of transmission sources (router 40 or mixer 30). Further, the router 40 includes a plurality of output ports 45B, so that the router 40 can perform routing for determining a route for forwarding the power packet 60.
  • the router 40 shown in FIG. 4 includes a plurality of power processing circuits 45. Further, the router 40 shown in FIG. 4 includes switch circuits 47 and 48.
  • the switch circuit 47 supplies the power packet 60 input from any one of the plurality of input ports 45A to any one of the plurality of power processing circuits 45.
  • the switch circuit 48 causes the power packet 60 output from any one of the plurality of power processing circuits 45 to be output from any one of the plurality of output ports 45B.
  • the controller 41 can perform routing for determining a route (output port 45B) for forwarding the power packet 60.
  • the router 40 with one input and one output shown in FIG. 3 will be described below. However, the following description also applies to the router 40 having a plurality of inputs and a plurality of outputs shown in FIG.
  • the power packet 60 is represented by the “timelot t” shown in FIG.
  • the time frame t includes only the payload 62, omitting the header 61 and the footer 63 in the power packet 60.
  • the time length of each time frame t is constant.
  • the calculation for the power of the power packet 60 will be described as the calculation for the power value within the time frame t.
  • the operation is a logical operation as an example, and the logical value (for example, binary logical value) of the power in the time frame t (power packet 60) is defined by the magnitude of the power in the time frame t.
  • the logical value "1" indicates that the power in the time frame t is larger than the threshold value
  • the logical value "0" indicates that the power in the time frame t is equal to or less than the threshold value.
  • the threshold value is set to 0
  • "1” is set if the power exists in the time frame t
  • "0” is set if there is no power in the time frame t.
  • the logical value represents the presence / absence of the voltage in the time frame t, that is, the presence / absence of the power packet 60.
  • the logical value "0" may indicate that the power packet 60 itself exists, but the power stored in the payload 62 is almost 0, or the power packet 60 itself does not exist. May be indicated.
  • the operation may be an arithmetic operation.
  • a plurality of logical operations including NOT operation and Through operation are defined as logical operations (Logic Operation).
  • the NOT operation is an inversion operation for the input. As shown in FIG. 5, in the NOT operation, if “0" is input, “1” is output. If “1” is input, “0” is output.
  • the Throw operation is a non-inverted operation on the input. As shown in FIG. 5, in the Throw operation, if "1" is input, “1” is output. If “0” is input, “0” is output.
  • the plurality of logical operations may be other logical operations other than NOT operation and Through operation. Further, the plurality of logical operations may include other logical operations other than the NOT operation and the Through operation.
  • logical operations are, for example, at least one of AND operation (logical product), NAND operation (negative logical product), OR operation (logical sum), NOR operation (negative OR), and XOR operation (exclusive OR). More than one. Other logical operations are also described in the second disclosure below.
  • the router 40 may be configured to be able to perform the logical operations described in the second disclosure.
  • FIG. 6 shows a case where the router 40 executes a Through operation and a case where the router 40 executes a NOT operation.
  • the power supply 20 supplies the power packet 60 (power in the time frame t) to the router 40, and the router 40 supplies the power packet to the load 50.
  • the load 50 gives a logical value of the amount of power required by the load 50 to the power supply 20 and the router 40 as a power packet request.
  • the power packet request may be given to the router 40 by another router instead of the load 50.
  • the load 50 transmits a logical value “1” or a logical value “0” as a power packet request to the power supply 20 and the router 40.
  • "1" as a power packet request is a power packet transmission request having a logical value of "1”.
  • "0" as a power packet request is a power packet transmission request (or a power packet non-transmission request) having a logical value of "0".
  • the power supply 20 may not always be able to output the power packet 60 as requested by the power packet. Therefore, the router 40 may not always be able to receive the input power packet as requested by the power packet.
  • the case where the router 40 cannot receive the input power packet as requested by the power packet is a case where the power generation amount of the power source 20 is not sufficient or a case where the power should be preferentially transmitted to another router 40.
  • the router 40 when the device connected to the input side of the router 40 is another router 40, the router 40 also uses the power packet even when the other router 40 does not transmit the output power packet as requested by the power packet. The input power packet as requested cannot be received.
  • the power supply 20 When the power packet request is "1" and the power supply 20 can output the power packet 60 of "1", the power supply 20 outputs "1" (the "Reference operation” shown in FIG. 6 and the time frame of FIG. 7). t see 1). In this case, the logical value of the power packet 60 input to the router 40 is "1". Therefore, the router 40 can output the power packet having the logical value "1" in accordance with the power packet request from the load 50. In this way, the operation in which the router 40 operates so as to output a power packet having the same value as the input is the Throw operation.
  • the power supply 20 Even if the power packet request is "1", if the power supply 20 cannot output the power packet 60 of "1", the power supply 20 outputs "0"("NOToperation” shown in FIG. 6 and FIG. 7). reference time frame t 3). In this case, the logical value of the power packet 60 input to the router 40 is "0". However, the router 40 outputs a power packet having a logical value of "1" in accordance with the power packet request from the load 50. In this way, the operation in which the router 40 operates so as to output a power packet having a value different from the input is the NOT operation.
  • the router 40 As shown in the time frame t 3 in FIG. 7, when the input to the router 40 is "0", the router 40 outputs "1", the power accumulated in the power storage unit 46 of the router 40, Since it is released to the load 50, it decreases. Therefore, even in "1" as the output logical value of the router 40 in the time frame t 3, the analog voltage at time frame t 3 is reduced.
  • Such voltage when reduction is no voltage (e.g., 20V) and, when an ideal output voltage corresponding to a logical value "1", the analog voltage at time frame t 3 is, as was reduced from the ideal output voltage Become.
  • the theoretical output power is the power when the power packet is output according to the power packet request given to the router 40, and is calculated based on the value (logical value) indicated by the power packet request.
  • the electric power when the electric power is packetized, the electric power can be handled by the number or density of the electric power packets, which is convenient.
  • the analog value of the individual electric power packet electric power may fluctuate. There is a difference between the theoretical power value when dealing with the number or density and the actual power value. Hereinafter, this difference is referred to as an "error". Therefore, even if the load 50 receives the required power as a logical value, the load 50 obtains a power different from the required power as an analog value.
  • the controller 41 of the router 40 of the embodiment considers such an error and executes the transmission control process of the power packet 60 so that the error becomes small.
  • the transmission control process of the embodiment includes selection of a logic operation.
  • FIG. 8 shows an input / output sequence of the router 40 when the logical operation for reducing the error is not performed, and an input / output sequence of the router 40 when the logical operation for reducing the error is performed.
  • the ideal input given to the router 40 is "101010” which is the same as the power packet request. In this case, the router 40 does not need to perform any special calculation on the input.
  • the router 40 can output the power according to the power packet request by outputting the ideal input “101010” as it is.
  • the actual input may be different from the power packet request, for example, as shown in FIG. 8 “010010”.
  • the router 40 when the router 40 outputs "101010" as requested by the power packet, the power obtained by the load 50 is different from the power expected by the load 50, and an error occurs. This error is accumulated with each output of the power packet 60. Therefore, the router 40 of the embodiment selects and executes a logical operation for the input so that the accumulated error becomes small. As a result, for example, the modified "101" 1 "10" is output from the power packet request of "101" 0 "10". As described above, the router 40 of the embodiment determines the corrected output from the power packet request by considering the error and selecting an appropriate operation.
  • FIG. 9 shows a transmission control process for determining the modified output.
  • This transmission control process is executed by the controller 41.
  • step S11 of the transmission control process the power contained in the output power packet is set so that the error V 2e becomes small. More specifically, in step S11 of the transmission control process, an operation applied to the logical value indicated by the power of the input power packet 60 is selected for setting the power of the output power packet.
  • the operation applied to the logical value indicated by the power of the input power packet 60 the operation of the NOT operation and the Through operation, whichever has the smaller error V 2e, is selected. The above error is calculated for the choice of operation.
  • the error here is the difference V 2e between the ideal output voltage to the load 50 (ideal load voltage V 2l ) and the actual output voltage to the load 50 (actual load voltage V 2r ).
  • the error V 2e that occurs in a certain time frame t is determined by the input / output values in that time frame t in addition to the error accumulated from the past. Therefore, the error V 2e that occurs in a certain time frame t can be regarded as the output power packet 60 if the logical value of the input power packet 60 in the time frame t, that is, the power value (input power value) of the input power packet is known. It depends on whether to output "1" or "0".
  • the analog value of the input power packet 60 is constant and does not fluctuate with respect to the same logical value.
  • step S10 the controller 41 receives the power packet request in the time frame t from the load 50.
  • the power packet request here indicates "0" or "1".
  • the power packet request is given from the load 50 in each time frame t by synchronizing the router 40 and the load 50. That is, the transmission control process shown in FIG. 9 is executed in each time frame t. However, the power packet request does not have to be given in each time frame t.
  • the controller 41 can start the execution of the transmission control process by using the power packet request received from the load 50 as a trigger.
  • step S111 included in the following step S11 it is determined whether the input power value of the input power packet 60 is "0" or "1".
  • the input power value is "1”
  • step S112 assuming that the input power value is "1”, it is a candidate value (output power candidate value) for the power possessed by the output power packet.
  • the error V 2E10 when outputting the the error V 2E10 when outputs" 1 "which is another output power candidate value, but are calculated respectively.
  • the error V 2e10 is the difference V 2e between the ideal output voltage to the load 50 (ideal load voltage V 2l ) and the actual output voltage to the load 50 (actual load voltage V 2r). ..
  • the ideal output voltage (ideal load voltage V 2l ) is an ideal voltage output according to the power packet request received in step S10, and is obtained based on the value indicated by the received power packet request.
  • the actual output voltage (actual load voltage V 2r ) is obtained based on the input voltage value and the output power value candidate value.
  • step S116 If the input power value is "0", the error V 2e00 when the output power candidate value "0" is output on the premise that the input power value is "0" in step S116. And the error V 2e11 when the other output power candidate value "1" is output, respectively, are calculated. The calculation of the error V 2e11 is performed in the same manner as in step S122.
  • the operation of the NOT operation and the Through operation whichever has the smaller error V 2e, is selected. Specifically, in steps S113 and S117, it is determined whether the output power candidate value that minimizes the error V 2e is 0 or 1. If the error V 2e can be reduced by outputting 0 when the input power value is "1", the NOT operation is selected in step S114 (selection D 10 ). On the other hand, if the error V 2e can be reduced by outputting 1, the Throw operation is selected in step S115 (selection D 11 ).
  • step S118 selection D 01
  • the Throw operation is selected in step S119 (selection D 11 ).
  • the output power of the output power packet is set to a value corresponding to the calculation result obtained by applying the selected logical operation to the logical value indicated by the power of the input power packet 60. For example, if the NOT operation is selected when the input power value is "1”, the logical value of the output power is set to "0". If the Through operation is selected when the input power value is "1", the logical value of the output power is set to "1".
  • step S11 has been described here as the selection of the operation that reduces the error, the process of step S11 may be regarded as the selection of the output power candidate value that reduces the error.
  • step S12 When the calculation is selected, the calculation is executed in step S12.
  • the controller 41 controls the power processing circuit 45 so that the selected operation is performed on the input power packet 60.
  • the power processing circuit 45 executes an operation on the input power packet 60 and generates an output power packet corresponding to the operation result.
  • the process of step S13 may be regarded as the generation of an output power packet in which the power of the selected output power candidate value is set. That is, the power processing circuit 45 generates an output power packet having an analog value output power corresponding to the logical value of the output power set by the transmission control process in step S11.
  • a plurality of routers 40 capable of executing the transmission control process according to the embodiment can be provided.
  • the router 40 which is close to the power supply 20 side and away from the load 50, does not need to output the power packet in a strict response to the power packet request, and can roughly respond to the power packet request. It is permissible to output power packets within a range. Even if the router 40 close to the power source 20 outputs a power packet different from the power packet request, the router 40 close to the load 50 can supply power to the load 50 so as to reduce the error from the power packet request. it can.
  • the operation of the dynamic quantizer is applied for the selection of the above-mentioned calculation.
  • Dynamic quantizers are used in control system designs where the input is limited to discrete values.
  • the dynamic quantizer operates to minimize the accumulation error between the output value in the case of continuous value input and the output value in the case of discretized input.
  • FIG. 10 shows an open-loop system composed of a plant P and a dynamic quantizer Q.
  • the dynamic quantizer Q is given a continuous value input u (k) and produces a discrete value output v (k).
  • the discrete value output v (k) of the dynamic quantizer Q is given as an input (discrete value input), and the output y (k) is generated.
  • the dynamic quantizer Q discretizes the input u (k) so that the quantization error has a small effect on the output y (k) of the plant P.
  • Plant P is defined by equations (1-1) and (1-2) of FIG.
  • the dynamic quantizer Q is defined by the equations (2-1) and (2-2) of FIG.
  • the parameters of the dynamic quantizer Q are set so as to minimize the accumulation error of the output y (k) of the plant P caused by the quantization error due to the quantization of the continuous value input u (k), the figure shows. It becomes like the formula (3-1) and the formula (3-2) of 10.
  • equation (3-1) the state ⁇ and output v (k) of the dynamic quantizer Q are affected by the parameters A, B, C of the plant P.
  • the circuit shown in FIG. 11 is assumed as the power packet transmission system 10 to which the operation of the dynamic quantizer is applied.
  • the load 50 includes a capacitor C 2 and a resistor R 2 .
  • the capacitor C 2 stores the power transmitted by the power packet 60.
  • the resistor R 2 consumes power.
  • a power router 40 that supplies a power packet 60 to the load 50 is connected to the stage before the load 50.
  • a power supply 20 (V in ) is connected to the front stage of the power router 40.
  • the power router 40 has one input and one output, and includes a power processing circuit 45.
  • the power processing circuit 45 includes a capacitor C 1 that operates as a power storage unit 46.
  • the input side of the capacitor C 1 power supply 20 side
  • the first switch SW 1 is provided, than a capacitor C 1, to the output side (load 50 side), a second switch SW 2 is provided .
  • the first switch SW1 and the second switch SW2 are each composed of MOSFETs.
  • the ON resistance of each MOSFET is represented by r.
  • the first input side of the switch SW 1 is provided with measuring resistor R 1.
  • Equation (4-1-1) shows the storage voltage V 1 in the case where “1” is output when the input is “1” at time t (Through calculation).
  • Equation (4-1-2) shows the load voltage V 2 when "1” is output when the input is “1” at time t (Through calculation).
  • P 11 the operations of equations (4-1-1) and equations (4-1-2) are referred to as P 11 .
  • Equation (4-2-1) shows the power storage voltage V 1 when “0” is output when the input is “1” at time t (NOT calculation).
  • Equation (4-2-2) shows the load voltage V 2 when "0” is output when the input is “1” at time t (NOT calculation).
  • P 10 the operation of Equation (4-2-1) and (4-2-2), represented as P 10.
  • Equation (5-1-1) shows the power storage voltage V 1 when “0” is output when the input is “0” at time t (Through calculation).
  • Equation (5-1-2) shows the load voltage V 2 when "0” is output when the input is “0” at time t (Through calculation).
  • P 00 the operations of equations (5-1-1) and equations (5-1-2) are referred to as P 00 .
  • Equation (5-2-1) shows the power storage voltage V 1 when “1” is output when the input is “0” at time t (NOT calculation).
  • Equation (5-2-2) shows the load voltage V 2 when "1” is output when the input is “0” at time t (NOT calculation).
  • the operations of equations (5-1-1) and equations (5-2-2) are referred to as P 01 .
  • i indicates the logical value of the input
  • j indicates the logical value of the output.
  • the state error ⁇ e is calculated according to the equation shown in FIG.
  • ⁇ l (t) be the ideal state
  • ⁇ r be the actual state
  • the state error ⁇ e is represented by the difference between the actual state ⁇ r and the ideal state ⁇ l.
  • the error when the input i is “1” is calculated according to the equations (6-1), (6-2), and (6-3) shown in FIG. Equations (6-1), (6-2), and (6-3) are applied when the output j is "0" and “1", respectively. That is, the error xi] e10 when output j when the input i is “1” is “0”, error in the output j when the input i is “1” is “1” xi] e11 And are calculated.
  • Equation 7-1), (7-2), and (7-3 The error when the input i is “0” is calculated according to the equations (7-1), (7-2), and (7-3). Equations (7-1), (7-2), and (7-3) are applied when the output j is "0" and “1", respectively. That is, the error xi] e00 when output j when the input i is “0” is “0”, error in the output j when the input i is "0” is "1” xi] e01 And are calculated.
  • the calculation is selected so that the output error at the next time t + 1 (here, the error V 2e of the load voltage V 2) is minimized.
  • the selection of this operation corresponds to the process of step S11 shown in FIG.
  • the controller 41 selects an operation that reduces the error according to FIG.
  • V 2e10 in FIG. 13 indicates a load voltage error when the output j is “0” when the input i is “1”.
  • V 2e 11 indicates a load voltage error when the output j is “1” when the input i is “1”.
  • V 2e01 indicates a load voltage error when the output j is “1” when the input i is “0”.
  • V 2e00 indicates a load voltage error when the output j is “0” when the input i is “0”.
  • D 10 in FIG. 13 corresponds to selection D 10 in step S114 of FIG. D 11 in FIG. 13 corresponds to selection D 11 in step S115 of FIG. D 01 in FIG. 13 corresponds to the selection D 01 in step S118 of FIG. D 00 in FIG. 13 corresponds to the selection D 00 in step S119 of FIG.
  • the controller has parameters of the circuit model 43 on the router output side (load 50) and parameters of the circuit model 42 of the power processing circuit 45 of the router 40 in order to calculate the state error ⁇ e (see FIG. 3). ).
  • the ideal state ⁇ l and the actual state ⁇ r when there is a power packet request of a certain value are the values of the input power given to the router 40 (input power packet 60) if the circuit models 42 and 43 are known. It can be calculated based on the value of the electric power that the router has.
  • the value of the input given to the router 40 may be given as a logical value or as an analog value.
  • the router 40 may acquire the value of the input power given to the router 40 from the input side device (for example, the power supply 20) of the router 40, or may acquire the value by measuring at the router 40.
  • the error ⁇ electricity storage unit voltage (energy value stored in the power storage unit) used in the calculation of e V 1 is, knowing the value of the input power supplied to the router 40 can be obtained by calculation.
  • the controller 41 acquires the voltage V 1 from the measuring unit 46A (see FIG. 3) that measures the power storage unit voltage (energy value stored in the power storage unit) V 1, and sets the acquired voltage V 1 as an error ⁇ e. It may be used for the calculation of. In this case, by measuring the voltages V 1, as compared with the case of obtaining the voltages V 1 in the calculation, it is possible to suppress the calculation error of the voltages V 1.
  • the circuit shown in FIG. 11 was used, the time length of the time frame t was 400 ⁇ s, and the power supply voltage E was 20 V. Further, in the circuit shown in FIG. 11, the ON resistance r of the MOSFET is 22 m ⁇ , the measurement resistance R 1 is 1.5 k ⁇ , the capacitor C 1 in the router 40 is 4700 ⁇ F, the load capacitor C 2 is 4700 ⁇ F, and the load resistance R 2 was set to 10 ⁇ .
  • the initial state ⁇ (0) [18 15] T of the state ⁇ was set.
  • the input to the router 40 is randomly given regardless of the request from the load 50, and the probability (transmission probability) that the input to the router 40 becomes "1" is defined as p. To do. In the evaluation, p was changed to 1/2, 1/3, 1/4.
  • “demand” indicates a power packet sequence (request packet sequence) requested by the load 50 to the router 40.
  • “1" and “0" are alternately generated.
  • “input” indicates a power packet sequence (input packet sequence) input to the router 40.
  • the input packet sequence shown in FIG. 14 does not match the request packet sequence, and "1" and "0" are randomly generated.
  • modified output indicates an output power packet sequence determined by the transmission control process according to the embodiment.
  • the output power packet sequence shown in FIG. 14 is partially modified from the request packet sequence.
  • the Through operation is selected for the portion that matches the request packet sequence, and in the output power packet sequence shown in FIG. 14, the NOT operation is selected for the portion that does not match the request packet sequence. Indicates that it has been done.
  • FIG. 15 shows a change in the load voltage (output voltage of the router 40) V 2.
  • “Ideal” indicates a change in the ideal voltage V 2l.
  • the “Without algorithm” shows a method of determining the output of the router 40 according to the required logical value of the load 50.
  • “With algorithm” indicates a method of determining the output of the router 40 according to the transmission control process (see FIG. 9) according to the embodiment. According to FIG. 15, it can be seen that the “With algorithm” is closer to the ideal.
  • FIG. 16 shows the error V 2e of the actual voltage with respect to the ideal voltage. According to FIG. 16, it can be seen that the error V 2e is smaller in the “With algorithm”.
  • FIG. 17 shows the relationship between the transmission probability and the difference in the average error.
  • the difference in the average error depending on whether or not the transmission control process according to the embodiment is applied is set as shown in FIG.
  • FIG. 17 shows the difference in the average error calculated at 0.2 s when the transmission probability p is set to 1/2, 1/3, 1/4, respectively. According to FIG. 17, it can be seen that the lower the transmission probability of the power packet, that is, the probability that "1" is input, the more effective the transmission control process according to the embodiment.
  • the second disclosure relates to power calculation.
  • the second disclosure relates to, for example, power arithmetic units, power transmission systems, and data structures of power packets.
  • the second disclosure incorporates all the statements contained in Japanese Application No. 2018-092668 filed May 14, 2018 and International Application PCT / JP2019 / 018829 filed May 10, 2019.
  • Patent Document 1 and Patent Document 2 disclose a power transmission system in which a power packet is transmitted.
  • the power packet includes a payload in which the transmitted power is pulsed and an information tag such as a header.
  • pulsed power like a power packet
  • power can be discreteized and transmitted. Since the power is discretized, the amount of power transmitted can be considered as the number or density of packets or pulses.
  • the second disclosure presents the concept of calculating discretized power in order to take advantage of the above-mentioned feature of discretized power transmission.
  • the first aspect of the second disclosure is the power arithmetic unit.
  • the power arithmetic unit performs an operation on the pulsed input power.
  • the power calculation device includes a power storage unit that stores input power, and a processing circuit that executes calculation processing that outputs output power corresponding to a calculation result for the input power from the power storage unit.
  • the power transmission system includes the power arithmetic unit.
  • the data structure includes a payload having electric power to be transmitted and arithmetic information used for controlling the arithmetic processing.
  • the calculation information is used in the power calculation device.
  • the power calculation device calculates the pulsed first input power.
  • the power arithmetic unit includes a power storage unit that stores the first input power.
  • the power storage unit is, for example, a capacitor.
  • the power calculation device includes a processing circuit that executes a calculation process for outputting an output power corresponding to a calculation result for the first input power from the power storage unit. Since the output power of the processing circuit is the calculation result for the input power, the power calculation is realized.
  • the power calculation here reflects the calculation result as a physical electric energy, and is different from the general signal calculation in which the calculation result is only a logical value.
  • the power storage unit functions as an element corresponding to a memory for storing signals in signal calculation.
  • the power arithmetic unit may be incorporated in the power router described in Patent Document 1 or 2, or may be provided in the power transmission system as a device separate from the power router.
  • the power arithmetic unit When the power arithmetic unit is incorporated in the power router, the power of the power packet can be changed by the arithmetic processing inside the router.
  • the processing circuit may be configured as a switch circuit capable of executing a plurality of types of arithmetic processing. Being able to execute multiple types of arithmetic processing enhances versatility. Further, by integrating a large number of processing circuits, a power calculation integrated circuit can be realized.
  • the power arithmetic unit can further include a controller that controls the processing circuit so that the arithmetic processing of the selected type is executed.
  • the controller can cause the same processing circuit to execute various types of arithmetic processing. That is, a rewritable processing circuit is realized.
  • the pulsed power may be included in the power packet. That is, the first input power may be included in the first input power packet.
  • the power packet can have power in the payload, for example.
  • the first input power packet can include arithmetic information used for controlling the arithmetic processing in the controller.
  • the arithmetic processing can be controlled by the arithmetic information of the power packet.
  • the calculation information may include calculation type information indicating the type of the calculation process.
  • the controller can select the arithmetic processing indicated by the arithmetic type information as the arithmetic processing executed by the processing circuit. In this case, the type of arithmetic processing executed in the processing circuit can be controlled by the arithmetic type information.
  • the calculation information may include identification information of a second input power packet having a second input power.
  • the output power may be power corresponding to a calculation result for the first input power and the second input power of the second input power packet identified by the identification information. That is, the controller outputs an output power corresponding to a calculation result for the first input power and the second input power of the second input power packet identified by the identification information from the power storage unit. The process can be executed.
  • the controller may be configured to determine whether or not the arithmetic processing can be executed. In this case, the controller can select whether or not the power arithmetic unit accepts the power packet and executes the arithmetic processing.
  • the determination as to whether or not the calculation process can be executed is performed based on the voltage of the power storage unit and the input power of the input power packet to be calculated.
  • the determination as to whether or not the arithmetic processing can be executed is further performed based on the type of the arithmetic processing.
  • the determination as to whether or not the arithmetic processing can be executed is performed in order to make the voltage of the power storage unit a desired voltage.
  • the processing circuit is configured to be switchable to a plurality of states including an input state for storing electric power in the power storage unit and an output state for outputting the output power from the power storage unit.
  • the plurality of states may further include an input / output state in which the input power is stored in the power storage unit and the output power is output from the power storage unit at the same time.
  • the plurality of states may further include a non-calculation state in which the input power is neither stored in the power storage unit nor the output power is output from the power storage unit.
  • a packet generation unit that generates an output power packet having the output power can be further provided.
  • a power packet having output power can be generated, and output power can be transmitted.
  • the power transmission system according to the embodiment may include the power calculation device according to any one of (1) to (10).
  • the data structure of the power packet according to the embodiment is such that the power calculation device that executes the calculation process for outputting the payload having the power to be transmitted and the power corresponding to the calculation result for the power included in the payload performs the calculation process. It is provided with arithmetic information used for controlling the above.
  • the calculation information can have calculation type information indicating the type of the calculation process.
  • the calculation type information is used by the power calculation device to select the type of the calculation process.
  • the calculation information can include identification information of a power packet to be calculated.
  • the identification information is used by the power arithmetic unit to identify a power packet to be subjected to the arithmetic processing.
  • FIG. 18 shows the power transmission system 10.
  • the system 10 is a network that transmits electric power from the power source 20 to the load 50 by the electric power packet 60.
  • the power source 20 is, for example, a power generation facility or a battery.
  • the power supply 20 is a DC power supply.
  • System 10 includes a mixer 30.
  • the mixer 30 generates a power packet 60 from the power supplied from the power source 20.
  • the power packet 60 shown in FIG. 18 includes a payload 62 having pulsed power and an information tag including a header 61 and a footer 63.
  • the power packet 60 generated by the mixer 30 is transmitted to the router 40 in the system 10.
  • the mixer 30 includes a controller 31, a gate driver 32, and a switch circuit 33.
  • the switch circuit 33 shown is a 2-input 1-output circuit. Power supplies 20 and 20 are connected to the two inputs of the switch circuit 33, respectively.
  • the switch circuit 33 can generate and output a power packet 60 from any one of the two power supplies 20 and 20.
  • the switch circuit 33 includes switch elements 301 and 305 provided between the input and the output.
  • the power packet 60 shown in FIG. 18 is generated by switching ON / OFF of the switch elements 301 and 305.
  • Diodes 303 and 307 are provided between the switch elements 301 and 305 and the output. The diodes 303 and 307 allow a current in the direction from the input side to the output side and block the current in the opposite direction.
  • the other ends of the resistors 302 and 306, one end of which is connected to the ground, are connected between the switch elements 301 and 305 and the diodes 303 and 307.
  • the controller 31 gives a control signal for switching control of the switch elements 301 and 305 to the gate driver 32.
  • the gate driver 32 outputs a gate voltage that controls ON / OFF of the switch elements 301 and 305 according to the control signal.
  • a power packet is generated and output by the power from the power source 20 connected to the switch element 301.
  • the switch element 305 is ON / OFF controlled, a power packet is generated and output by the power from the power source 20 connected to the switch element 305.
  • the system 10 includes a router 40.
  • the power packet 60 is forwarded in the network via the router 40 to reach the load.
  • the router 40 relays the power packet 60 in the network.
  • the router 40 performs routing that determines a route for forwarding the power packet 60.
  • the router 40 of the embodiment functions as a power arithmetic unit.
  • the router 40 can perform an operation on the power of the input power packet and output a power packet having a power corresponding to the operation result.
  • the router 40 includes a controller 41, a gate driver 42, a switch circuit 43, and an isolator 44.
  • the switch circuit 43 shown is a 2-input 2-output circuit. The switch circuit 43 can select from which output the input power packet is transmitted. The output selection routes the power packets.
  • the illustrated switch circuit 43 includes two power calculation units 450A and 450B.
  • the power calculation units 450A and 450B each include a processing circuit 451 and a power storage unit 452, respectively.
  • the power storage unit 452 of the embodiment is composed of a capacitor.
  • the power storage unit may be a storage element having a quick response.
  • Two switch elements are connected to each input of the switch circuit 43.
  • the switch element 401 and the switch element 402 are connected in parallel to the first input.
  • the switch element 401 When the switch element 401 is turned on, the first input is connected to the power calculation unit 450B.
  • the switch element 402 is turned on, the first input is connected to the power calculation unit 450A.
  • the switch element 403 and the switch element 404 are connected in parallel to the second input.
  • the switch element 403 is turned on, the second input is connected to the power calculation unit 450B.
  • the switch element 404 is turned on, the second input is connected to the power calculation unit 450A.
  • Diodes 405, 406, 407, and 408 are provided between the switch elements 401, 402, 403, and 404 and the power calculation units 450A and 450B.
  • the diodes 405, 406, 407, and 408 allow the current in the direction from the input side toward the power calculation units 450A and 450B, and block the current in the opposite direction.
  • Two switch elements are connected to the outputs of the power calculation units 450A and 450B, respectively.
  • the switch element 411 and the switch element 412 are connected in parallel to the output of the power calculation unit 450A.
  • the switch element 411 When the switch element 411 is turned on, the output of the power calculation unit 450A is connected to the second output.
  • the switch element 412 When the switch element 412 is turned on, the output of the power calculation unit 450A is connected to the first output.
  • a switch element 413 and a switch element 414 are connected in parallel to the output of the power calculation unit 450B.
  • the switch element 413 is turned on, the output of the power calculation unit 450B is connected to the second output.
  • the switch element 404 When the switch element 404 is turned on, the output of the power calculation unit 450B is connected to the first output.
  • Diodes 415, 416, 417, 418 are provided between each switch element 411, 421, 413, 414 and the output.
  • the diodes 415, 416, 417, 418 allow the current in the direction from the power calculation units 450A, 450B to the output, and block the current in the opposite direction.
  • FIG. 20 is a circuit diagram of the power calculation units 450A and 450B.
  • the processing circuit 451 is a switch circuit that controls charging / discharging to the power storage unit 452.
  • the processing circuit 451 of FIG. 20 includes three switch elements 501, 502, and 503. Further, the processing circuit 451 is provided with diodes 511, 512, 513, 514 for allowing current to flow only in an intended direction. Further, the other end of the resistor 505, one end of which is connected to the ground, is connected between the input of the processing circuit 451 (the left end of the processing circuit 451 of FIG. 20) and the diode 511.
  • FIG. 21A shows a state in which all three switch elements 501, 502, and 503 are OFF. In the state of FIG. 21A, even if a power packet is given to the input of the processing circuit 451, the processing circuit 451 does not accept the power packet.
  • the state of FIG. 21A is a non-calculation state. In the non-calculation state, the input power is not stored in the power storage unit 452, and the power is not output from the processing circuit 451.
  • FIG. 21B shows a state in which the switch element 501 is ON and the switch elements 502 and 503 are OFF.
  • the state of FIG. 21B is a power input state (storage state). In the input state, the electric power given to the input of the processing circuit 451 is stored in the power storage unit 452.
  • FIG. 21C shows a state in which the switch elements 501, 502, and 503 are all ON.
  • the state of FIG. 21C is a power input / output state (storage / discharge state).
  • the electric power given to the processing circuit 451 is stored in the power storage unit 452, and the electric power stored in the power storage unit 452 can be output from the processing circuit 451.
  • FIG. 21D shows a state in which the switch elements 502 and 503 are ON and the switch element 501 is OFF.
  • the state of FIG. 21D is a power output state (discharge state). In the output state, the electric power stored in the power storage unit 452 can be output from the processing circuit 451.
  • the controller 41 gives the gate driver 42 a control signal for switching control of the switch element included in the switch circuit 43.
  • the gate driver 42 outputs a gate voltage that controls ON / OFF of the switch element included in the switch circuit 43 according to the control signal.
  • the controller 41 controls ON / OFF of the switch elements 401, 402, 403, 404, it is selected which of the plurality of power calculation units 450A and 450B is given the power of the input power packet. Further, by ON / OFF control of the switch elements 411, 421, 413 and 414, the power packet generated from the power output from any of the power calculation units 450A and 450B is sent to the two outputs of the switch circuit 43 (router 40). Which of them is output is selected.
  • the switch elements 411, 421, 413, 414 constitute a packet generation unit that generates a power packet 60 having a header 61 and a footer 63 from the power output from the power calculation units 450A and 450B. By turning ON / OFF the switch elements 411, 421, 413 and 414, the pulses constituting the header 61 and the footer 63 are generated.
  • the controller 41 controls ON / OFF of the switch elements 501, 502, and 503, so that the state of the processing circuit 451 is selected as one of a non-calculation state, an input state, an input / output state, and an output state. Can be switched.
  • the desired arithmetic processing is executed by switching the state of the processing circuit 451. The details of the arithmetic processing will be described later.
  • FIG. 22 shows the header 61 of the packet 60 according to the embodiment.
  • the header 61 is read by the controller 41 via the isolator 44.
  • the header 61 has an area in which the packet ID 601 is stored.
  • the packet ID 601 is an identifier of the packet.
  • the header 61 has an area in which the calculation information 602 is stored.
  • the calculation information 602 is used in the controller 41 for controlling the power calculation processing.
  • the calculation information 602 has the calculation type information 611.
  • the calculation type information 611 indicates the type of calculation processing performed by the power calculation units 450A and 450B.
  • the arithmetic processing may be a logical operation or a four arithmetic operation.
  • Logical operations include, for example, AND operations, OR operations, NOT operations, XOR operations, NOR operations, and NAND operations.
  • the four arithmetic operations include, for example, addition (ADD) and subtraction (SUB).
  • the operation type information 611 indicates which type of operation among these operations is performed on the power packet.
  • the calculation information 602 has the calculation target identification information 612.
  • the calculation target identification information 612 indicates the ID 601 of the power packet to be calculated by the calculation process.
  • the calculation target identification information 612 indicates the ID 601 of the other power packet 60.
  • the calculation target identification information 612 may indicate the ID 601 of the own packet 60.
  • the calculation target identification information 612 can include ID 601 of a plurality of packets 60.
  • the header 61 has an area in which the address information 603 is stored.
  • the address information 603 is used for routing in the router 40.
  • the address information 603 has a source address 621 and a destination address 622.
  • FIG. 23 shows the process executed by the controller 41.
  • the process executed by the controller 41 includes the operation type identification process 701.
  • the calculation type identification process 701 the calculation type information 611 included in the power packet 60 is read, and the calculation type for the power packet 60 is identified.
  • the calculation type information 611 of the power packet 60 in which the ID 601 is A and the power packet 60 in which the ID 601 is B indicates “AND” as the calculation type. Therefore, in the operation type identification process 701, "AND" is identified as the operation type.
  • the process executed by the controller 41 includes the calculation target identification process 702.
  • the calculation target identification information 612 included in the power packet 60 is read, and the power packet 60 to be calculated is identified.
  • the calculation target identification information 612 of the power packet 60 whose ID 601 is A indicates B as the calculation target ID.
  • the calculation target identification information 612 of the power packet 60 in which the ID 601 is B indicates A as the calculation target ID. Therefore, the controller 41 identifies the power packet 60 having the ID A and the power packet 60 having the ID B as the calculation target of the calculation type “AND”.
  • the process executed by the controller 41 includes the process 703 for detecting the power to be calculated.
  • the electric energy to be calculated or the logical value indicated by the electric energy is detected.
  • the electric energy to be calculated is detected, for example, by the controller 41 measuring the time length of the payload 62 or the voltage value via the isolator 44.
  • the electric energy to be calculated may be detected by reading the electric power information (not shown) stored in the header 61.
  • the logical value indicated by the electric energy to be calculated is detected, for example, by identifying the voltage value of the payload 62.
  • the logical value indicated by the electric energy may be detected by reading the electric power information (not shown) stored in the header 61.
  • the process executed by the controller 41 includes the arithmetic control process 704.
  • the processing circuit 451 is controlled so that the processing circuit 451 executes an arithmetic processing for outputting the electric power corresponding to the arithmetic result with respect to the electric power of the electric power packet 60 to be calculated from the processing circuit 451.
  • the processing circuit 451 executes an arithmetic processing for outputting the electric power corresponding to the arithmetic result with respect to the electric power of the electric power packet 60 to be calculated from the processing circuit 451.
  • the process executed by the controller 41 includes the packet generation process 705.
  • the packet generation process 705 the switch elements 411, 421, 413, 414 are controlled, and the power packet 60 having the power output from the processing circuit 451 (power corresponding to the calculation result) in the payload 62 (ID 601 in FIG. 23). Power packet that is C) is generated.
  • the generated power packet 60 is output from the router 40.
  • the time length of the power packet is constant.
  • the length of the power packet is t, and the length t is called the time frame of each power packet.
  • the logic is defined as "1” if the voltage in a certain time frame is at the High level and "0" if it is at the Low level.
  • the method of assigning “1” and “0” is shown in FIG. 24A.
  • two consecutive power packets f and b are regarded as one pair.
  • the logical operation here is defined by taking these two consecutive power packets f and b as inputs. In the example of FIG. 24A, "11" is input after "10" is input. It is assumed that the calculation result for the input is output in the time frame of the power packet b.
  • the information tag consisting of the header 61 and the footer 63 has 0 bits, and only the payload 62 exists.
  • the length t of each of the power packets f and b is set to 0.05 seconds, and the clock period T for performing the logical operation is set to 0.1 seconds.
  • the voltage applied to the input of the processing circuit 451 was a DC voltage of 10 V, and the initial voltage of the power storage unit 452 was 8.0 V.
  • the logical value of the input power packet in each time frame is selected from 0 or 1 with a probability of 1/2.
  • FIG. 24B shows the truth table of AND.
  • the AND operation as shown in FIG. 24B, when the input power packets f and b are "11", 1 is output in the time frame of b, and 0 is output in other cases.
  • the arithmetic processing algorithm for AND arithmetic is as follows.
  • the switch element 501 of the processing circuit 451 closes. Then, the power of the power packet b is stored in the power storage unit 452 (see FIG. 21B).
  • FIG. 25A, 25B, 26A and 26B show the simulation results of executing the above AND arithmetic processing algorithm in the power arithmetic unit of FIG.
  • FIG. 25A shows 10 pairs of input power packets f and b.
  • FIG. 25B shows the voltage of the output power packet and
  • FIG. 26A shows the output current. It can be said that the output of FIG. 25B is a correct result because it shows a voltage corresponding to the calculation result according to the truth table of FIG. 24B.
  • FIG. 26B shows the voltage of the power storage unit 452.
  • the power of the power packet f is stored in the power storage unit 452, so that the voltage of the power storage unit 452 rises.
  • the power of the power packet f is stored in the power storage unit 452, the voltage of the power storage unit 452 rises, and the power of the power packet b is used for storage in the power storage unit 452 and power output. Be done.
  • the power of the power packet b is stored in the power storage unit 452, and the voltage of the power storage unit 452 rises. From the above, it can be seen that the AND operation is executed correctly.
  • 27A and 27B show the experimental results of the AND operation.
  • the packet 60 in which the header 61 is added to the payload 62 was used as the calculation target.
  • the header 61 has calculation type information 611.
  • the calculation type information 611 indicates the type of calculation.
  • the payload 61 has a first payload section f and a second payload section b.
  • the calculation indicated by the calculation type information 611 is performed on the first payload section f and the second payload section b.
  • the operation type information 611 indicates an AND operation. Therefore, the arithmetic processing algorithm executed by the power arithmetic unit of FIG. 20 is set to the AND operation.
  • the packet ID 601 shown in FIG. 22, the calculation target information 612, and the address information 603 were omitted.
  • FIG. 27A four pairs of the first payload section f and the second payload section b of the packet input to the power calculation section are shown, and the first payload section f and the packet output from the power calculation section are shown. Four pairs of second payload parts b are also shown.
  • FIG. 27B shows the output current Iout.
  • the outputs (OUTPUTs) of FIGS. 27A and 27B also show the voltage and current corresponding to the calculation results according to the truth table of FIG. 24B as well as the simulation results.
  • FIG. 28 shows a truth table T1 for OR operation, a truth table T2 for NOT operation, a truth table T3 for EXOR operation, a truth table T4 for NOR operation, and a truth table T5 for NAND operation.
  • the operation processing algorithm of NOT operation is as follows. Since the NOT operation is an operation on the power of one power packet, the algorithm of the NOT operation on the power packet b will be described here.
  • the logical value of the power packet b is identified.
  • the switch elements 502 and 503 of the processing circuit 451 are closed, and the power of the power storage unit 452 is output. It is in the output state (see FIG. 21D).
  • the switch element 501 of the processing circuit 451 When it is detected that the logical value of the power packet f is "1" in the time frame of the power packet b, the switch element 501 of the processing circuit 451 is closed, and the power of the power packet f is stored in the power storage unit 452. It is in the input state (see FIG. 21B).
  • the arithmetic processing algorithm of the EXOR operation is as follows.
  • the switch element 501 of the processing circuit 451 closes. Then, the power of the power packet f is stored in the power storage unit 452 (see FIG. 21B).
  • the switch element 501 of the processing circuit 451 When it is detected that the logical value of the power packet b is "1" in the time frame of the power packet b, the switch element 501 of the processing circuit 451 is closed, and the power of the power packet f is stored in the power storage unit 452. It becomes a state (see FIG. 21B).
  • the switch element 501 of the processing circuit 451 closes. Then, the power of the power packet f is stored in the power storage unit 452 (see FIG. 21B).
  • the arithmetic processing algorithm for NAND arithmetic is as follows.
  • the switch element 501 of the processing circuit 451 closes. Then, the power of the power packet f is stored in the power storage unit 452 (see FIG. 21B).
  • FIG. 29A, 29B, 30A and 30B show the simulation results of executing the NAND arithmetic processing algorithm in the power arithmetic unit of FIG.
  • FIG. 29A shows 10 pairs of input power packets f and b.
  • FIG. 29B shows the voltage of the output power packet and
  • FIG. 30A shows the output current. Since the output of FIG. 30B shows the voltage corresponding to the calculation result according to the NAND truth table T5 in FIG. 28, it can be said that the result is correct.
  • FIG. 30B shows the voltage of the power storage unit 452 when the NAND calculation is executed.
  • the voltage of the power storage unit 452 increases in the time frame of the power packet f, and the voltage of the power storage unit 452 decreases in the time frame of the power packet b.
  • the power of the power packet b is used for storage in the power storage unit 452 and power output.
  • the power of the power packet f and the power packet b is stored in the power storage unit 452, and the voltage of the power storage unit 452 rises.
  • the output power packet is generated in the time frame of the power packet b, so that the voltage of the power storage unit 452 decreases. From the above, it can be seen that the NAND operation is executed correctly.
  • FIGS. 31A and 31B show the experimental results of the NAND operation.
  • the operation type information 611 indicates a NAND operation. Therefore, the arithmetic processing algorithm executed by the power arithmetic unit of FIG. 3 is set to the AND operation.
  • FIG. 31A four pairs of the first payload section f and the second payload section b of the packet input to the power calculation section are shown, and the first payload section f and the packet output from the power calculation section are shown.
  • Four pairs of second payload parts b are also shown.
  • FIG. 31B shows the output current Iout.
  • the outputs (OUTPUTs) of FIGS. 31A and 31B also show the voltage and current corresponding to the calculation results according to the NAND truth table in FIG. 28, as in the simulation results.
  • FIG. 32 shows another example of processing executed by the controller 41.
  • the controller 41 of FIG. 32 controls the voltage of the power storage unit 452 to a desired voltage by causing the processing circuit 451 to execute arithmetic processing.
  • the voltage of the power storage unit 452 changes by calculation. For example, when the AND operation is performed on the "10" input, the voltage of the power storage unit 452 rises. Further, when the NAND operation is performed on the "00" input, the voltage of the power storage unit 452 decreases. Therefore, it is possible to control the voltage of the power storage unit 452 to be increased or decreased by appropriately selecting the operation to be executed.
  • the voltage of the power packet 60 can be set to a desired voltage. For example, the voltage of the power packet 60 can be maintained at a specified voltage, or the voltage can be stepped up or down in order to adjust the transmission power.
  • the router 40 can entrust the arithmetic processing to another router 40 capable of executing the arithmetic processing.
  • the controller 41 shown in FIG. 32 executes the voltage detection process 711 of the power storage unit 452 in order to determine whether or not the arithmetic processing can be executed.
  • the voltage detection process 711 allows the controller 41 to monitor the voltage of the power storage unit 452.
  • the controller 41 shown in FIG. 32 executes the calculation possibility determination process 712.
  • the calculation possibility determination process 712 can be performed based on the voltage of the power storage unit 452 detected by the voltage detection process 711 and the voltage of the power packet 60 to be calculated. For example, when the processing circuit 451 executes only a single arithmetic processing, the voltage of the storage unit 452 after the arithmetic processing is executed is the voltage of the storage unit 452 before the arithmetic processing is executed and the power packet 60 to be calculated. Determined by the voltage of.
  • the calculation possibility determination process 712 whether or not the voltage of the power packet 60 to be calculated can bring the voltage of the power storage unit 452 into a desired power state in view of the voltage of the power storage unit 452 before the calculation process is executed.
  • the determination 713 may be performed.
  • the arithmetic control process 704 is executed. On the other hand, when it is determined that the power state deviates from the desired power state, the switch control 715 is performed so as not to accept the power packet.
  • the processing circuit 451 performs the arithmetic processing and outputs the electric power corresponding to the arithmetic result.
  • the controller 41 executes the process 704 that generates a power packet from the power output from the process circuit 451.
  • the processing circuit 451 can execute a plurality of arithmetic processes, the voltage of the power storage unit 452 after the arithmetic processing is executed further depends on the type of arithmetic. Therefore, in the calculation possibility determination process 712 shown in FIG. 32, the type of the calculation process identified by the calculation type identification process 701 and the voltage of the power packet 60 to be calculated are the voltages of the power storage unit 452 before the calculation process is executed. In view of the above, determination 713 is performed as to whether or not the voltage of the power storage unit 452 can be set to a desired power state.
  • 33A, 33B, 33C and 34 show an example of controlling the voltage of the power storage unit 452.
  • the voltage of the power storage unit 452, S -2, S -1 expressed in five states S 0, S 1, S 2 .
  • S- 2 indicates 8.51V or more and less than 8.86V.
  • S -1 indicates 8.17V or more and less than 8.51V.
  • S 0 indicates 7.74 V or more and less than 8.17 V.
  • S 1 indicates 7.56 V or more and less than 7.74.
  • S 2 indicates 7.09 V or more and less than 7.34 V.
  • Figure 33A shows a state transition diagram of around state S 0.
  • a two-digit number indicates the logical value of a pair of two input power packets, and A or N above the logical value indicates an AND or NAND operation performed on that logical value.
  • the state. S 0 when the AND operation for the “00” input, the NAND operation for the "01” input, the AND operation for the "11” input is performed, and the NAND operation for the "10” input is performed, the state. S 0 is maintained. However, depending on the voltage of the power storage unit 452, when the NAND operation for the “10” input is performed, the state S 0 may transition to the state S -1.
  • FIG. 33B shows examples of input power packets f, b, selected operations, outputs, and states.
  • the types of arithmetic processing selected are AND and NAND.
  • the initial voltage of the power storage unit 452 is 8 V (state S 0 ).
  • (10,10,11,00,10,11,11,00,11) is input in the calculation cycle (T1, T2, T3, T4, T5, T6, T7, T8, T9). ..
  • T1, T2, T3, T5, and T6, NAND is selected as the type of calculation processing.
  • T4, T7, T8, and T9 AND is selected as the type of calculation processing.
  • the state drops to S-1 , but in the calculation cycle T3, the voltage of the power storage unit 452 is increased (NAND for the “11” input). ) by the execution, it is possible to return to the state S 0.
  • the state S 0 could be maintained in other calculation cycles.
  • [Clause 1] It is a power calculation device that calculates the pulsed first input power.
  • the power storage unit that stores the first input power and A processing circuit that executes arithmetic processing to output output power corresponding to the arithmetic result for the first input electric power from the power storage unit, and A power arithmetic unit equipped with.
  • [Clause 2] The power arithmetic unit according to Clause 1, wherein the processing circuit is a switch circuit capable of executing a plurality of types of arithmetic processing.
  • the first input power is included in the first input power packet.
  • the power arithmetic unit according to Clause 3 wherein the first input power packet includes arithmetic information used for controlling the arithmetic processing in the controller.
  • the calculation information includes calculation type information indicating the type of the calculation process.
  • the calculation information includes identification information of a second input power packet having a second input power.
  • the output power is the power corresponding to the calculation result for the first input power and the second input power of the second input power packet identified by the identification information, as described in Clause 4 or Clause 5.
  • Power computing device [Clause 7] The power arithmetic unit according to any one of Articles 3 to 6, wherein the controller is configured to determine whether or not the arithmetic processing can be executed.
  • the processing circuit is configured to be switchable to a plurality of states including an input state for storing electric power in the power storage unit and an output state for outputting the output power from the power storage unit.
  • a power transmission system comprising the power arithmetic unit according to any one of Articles 1 to 10.

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Abstract

According to the present invention, power packets are output in such a way as to reduce errors with respect to the required power. The disclosed power packet transmitting device is provided with a controller which executes transmission control processing that includes setting the power of a power packet in such a way as to reduce the difference between an ideal output power determined in accordance with a power packet request from the output side of the power packet transmitting device, and the actual output power determined from an output power packet that is output from the power packet transmitting device.

Description

電力パケット伝送装置、電力パケット伝送システム、及び電力パケット伝送制御方法Power packet transmission device, power packet transmission system, and power packet transmission control method
　本開示は、電力パケット伝送装置、電力パケット伝送システム、及び電力パケット伝送制御方法に関する。本出願は、２０１９年９月１７日に出願された日本特許出願第２０１９－１６８１６１号に基づく優先権を主張し、前記日本特許出願に記載された全ての記載内容を援用する。 The present disclosure relates to a power packet transmission device, a power packet transmission system, and a power packet transmission control method. This application claims priority based on Japanese Patent Application No. 2019-168161 filed on September 17, 2019, and incorporates all the contents described in the Japanese patent application.
　電力パケットは、パルス化された電力を伝送するためのものである。電力パケットは、パルス化された電力を有するペイロードと、ヘッダ及びフッタなどの情報タグと、を備えている。特許文献１及び特許文献２は、電力パケットが伝送される電力パケット伝送システムを開示している。電力パケット伝送システムでは、分散配置された電源から供給される電力から電力パケットが生成される。電力パケットは、電力パケットの中継及びルーティングを行うルータを介して、負荷へ伝送される。 The power packet is for transmitting pulsed power. The power packet includes a payload having pulsed power and information tags such as headers and footers. Patent Document 1 and Patent Document 2 disclose a power packet transmission system in which a power packet is transmitted. In a power packet transmission system, a power packet is generated from the power supplied from a distributed power source. The power packet is transmitted to the load via a router that relays and routes the power packet.
国際公開第２０１４／１８９０５１号International Publication No. 2014/189051 国際公開第２０１４／０７７１９１号International Publication No. 2014/077191
　電力パケット伝送システムでは、電力パケットによって電力が離散化されているため、負荷が必要とする電力量を電力パケットの数で考えることができる。すなわち、電力伝送システムは、負荷が要求する数の電力パケットを負荷へ伝送することで、負荷が必要とする電力を負荷に供給することができる。 In the power packet transmission system, since the power is separated by the power packet, the amount of power required by the load can be considered by the number of power packets. That is, the power transmission system can supply the power required by the load to the load by transmitting the number of power packets required by the load to the load.
　負荷の要求に応じて電力パケットが負荷へ供給されるようにするため、電力パケット伝送システムに含まれる各ルータは、電力パケットの中継を適切に制御することが望まれる。しかし、負荷が要求するとおりに電力パケットが負荷へ伝送されても、負荷は、必要とする電力が得られないことがある。つまり、負荷が必要とする電力と、負荷が実際に得られる電力と、には、差が生じることがある。 In order to supply power packets to the load in response to the load request, it is desired that each router included in the power packet transmission system appropriately controls the relay of the power packet. However, even if power packets are transmitted to the load as the load requires, the load may not get the power it needs. That is, there may be a difference between the power required by the load and the power actually obtained by the load.
　このような差は、ルータから出力される個々の電力パケットの電力の変動によって生じる。ルータから出力される個々の電力パケットの電圧が変動すると、負荷が要求する数の電力パケットが負荷に供給された場合であっても、負荷が必要とする電力が得られるとは限らず、上記の差が生じる。 Such a difference is caused by the fluctuation of the power of each power packet output from the router. When the voltage of each power packet output from the router fluctuates, even if the load requires the number of power packets, the power required by the load is not always obtained. Difference occurs.
　電力パケットの電力の変動は、例えば、ルータに蓄積されている電力エネルギーの変動によって生じる。電力パケットは、ルータに蓄積されている電力エネルギーから生成されることがある。このため、ルータに蓄積されている電力エネルギーの変動は、電力パケットの電力に影響を及ぼす。 The fluctuation of the power of the power packet is caused by, for example, the fluctuation of the power energy stored in the router. Power packets may be generated from the power energy stored in the router. Therefore, fluctuations in the power energy stored in the router affect the power of the power packet.
　ルータに蓄積される電力エネルギーの変動は、ルータに入力される電力パケット数とルータから出力される電力パケット数の不均衡により生じることがある。例えば、ルータへ入力される電力パケットがあるときに、ルータが電力パケットを出力しても、ルータ自身が蓄積している電力エネルギーはさほど変動しない。一方、ルータへ入力される電力パケットがないときに、ルータが電力パケットを出力するには、ルータ自身が蓄積している電力エネルギーを放出する必要がある。したがって、ルータ自身が蓄積している電力エネルギーが低下する。 Fluctuations in the power energy stored in the router may occur due to an imbalance between the number of power packets input to the router and the number of power packets output from the router. For example, when there is a power packet input to the router and the router outputs the power packet, the power energy stored in the router itself does not fluctuate so much. On the other hand, when there is no power packet input to the router, in order for the router to output the power packet, it is necessary to release the power energy stored in the router itself. Therefore, the power energy stored in the router itself is reduced.
　以上のように、ルータ等の電力パケット伝送装置が、要求に従って電力パケットを出力しても、実際に電力パケットとして出力される電力が、必要な電力に一致するとは限らない。したがって、必要な電力からの差が少なくなるように、電力パケットを出力することが望まれる。 As described above, even if a power packet transmission device such as a router outputs a power packet according to a request, the power actually output as a power packet does not always match the required power. Therefore, it is desirable to output power packets so that the difference from the required power is small.
　本開示の第１の側面は、電力パケット伝送装置である。実施形態の電力パケット伝送装置は、前記電力パケット伝送装置の出力側からの電力パケット要求によって決まる理想出力電力と、前記電力パケット伝送装置から出力される出力電力パケットから決まる実出力電力と、の差が小さくなるように前記出力電力パケットが有する電力を設定する伝送制御処理を実行するコントローラを備える。 The first aspect of the present disclosure is a power packet transmission device. The power packet transmission device of the embodiment is the difference between the ideal output power determined by the power packet request from the output side of the power packet transmission device and the actual output power determined by the output power packet output from the power packet transmission device. A controller for executing a transmission control process for setting the power of the output power packet so that the output power packet becomes smaller is provided.
　本開示の第２の側面は、電力パケット伝送システムである。システムは、電力パケット伝送装置を備える。 The second aspect of the present disclosure is a power packet transmission system. The system comprises a power packet transmission device.
　本開示の第３の側面は、電力パケット伝送制御方法である。実施形態に係る電力パケット伝送制御方法は、電力パケット要求によって決まる理想出力電力と、前記電力パケット要求に基づいて出力される出力電力パケットから決まる実出力電力と、の差が小さくなるように前記出力電力パケットが有する電力を設定することを備える。 The third aspect of the present disclosure is a power packet transmission control method. In the power packet transmission control method according to the embodiment, the output is such that the difference between the ideal output power determined by the power packet request and the actual output power determined by the output power packet output based on the power packet request is small. It is provided to set the power possessed by the power packet.
　　更なる詳細は、後述の実施形態として説明される。 Further details will be described as an embodiment described later.
図１は、電力パケット伝送システムの構成図である。FIG. 1 is a configuration diagram of a power packet transmission system. 図２は、電力パケットの構成図である。FIG. 2 is a configuration diagram of a power packet. 図３は、１入力１出力の電力パケット伝送装置の構成図である。FIG. 3 is a configuration diagram of a power packet transmission device having one input and one output. 図４は、複数入力複数出力の電力パケット伝送装置の構成図である。FIG. 4 is a configuration diagram of a power packet transmission device having a plurality of inputs and a plurality of outputs. 図５は、時間枠と時間枠に対する論理演算の説明図である。FIG. 5 is an explanatory diagram of a time frame and a logical operation for the time frame. 図６は、電力パケット要求と電力パケット入出力との説明である。FIG. 6 is an explanation of a power packet request and a power packet input / output. 図７は、電力パケット要求、入力電力パケット電圧、出力電力パケット電圧を示す図である。FIG. 7 is a diagram showing a power packet request, an input power packet voltage, and an output power packet voltage. 図８は、電力パケット要求から修正された出力電力パケットを示す図である。FIG. 8 is a diagram showing an output power packet modified from the power packet request. 図９は、実施形態の伝送制御処理のフローチャートである。FIG. 9 is a flowchart of the transmission control process of the embodiment. 図１０は、動的量子化器の説明図である。FIG. 10 is an explanatory diagram of the dynamic quantizer. 図１１は、実施形態に係る電力パケット伝送システムの回路図である。FIG. 11 is a circuit diagram of the power packet transmission system according to the embodiment. 図１２は、状態ξに関する式を示す図である。FIG. 12 is a diagram showing an equation relating to the state ξ. 図１３は、図９のステップＳ１１の対応図である。FIG. 13 is a correspondence diagram of step S11 of FIG. 図１４は、電力パケット要求、入力電力パケット、出力電力パケットを示す図である。FIG. 14 is a diagram showing a power packet request, an input power packet, and an output power packet. 図１５は、負荷電圧Ｖ２の変化を示す図である。FIG. 15 is a diagram showing a change in the load voltage V 2. 図１６は、理想的な電圧に対する実際の電圧の誤差Ｖ２eを示す図である。FIG. 16 is a diagram showing an actual voltage error V 2e with respect to an ideal voltage. 図１７は、伝送確率と平均誤差の差との関係を示す図である。FIG. 17 is a diagram showing the relationship between the transmission probability and the difference between the average errors. 図１８は、電力伝送システムの構成図である。FIG. 18 is a configuration diagram of a power transmission system. 図１９Ａは、ルータの回路図である。図１９Ｂは、ルータのスイッチ回路図である。FIG. 19A is a circuit diagram of the router. FIG. 19B is a switch circuit diagram of the router. 図２０は、処理回路図である。FIG. 20 is a processing circuit diagram. 図２１Ａは、非演算状態の処理回路図である。図２１Ｂは、入力状態の処理回路図である。図２１Ｃは、入出力状態の処理回路図である。図２１Ｄは、出力状態の処理回路図である。FIG. 21A is a processing circuit diagram in a non-calculation state. FIG. 21B is a processing circuit diagram of an input state. FIG. 21C is a processing circuit diagram of an input / output state. FIG. 21D is a processing circuit diagram of an output state. 図２２は、電力パケットのデータ構造図である。FIG. 22 is a data structure diagram of a power packet. 図２３は、コントローラによる処理の説明図である。FIG. 23 is an explanatory diagram of processing by the controller. 図２４Ａは、入力電力パケットの説明図である。図２４Ｂは、ＡＮＤの真理値表である。FIG. 24A is an explanatory diagram of an input power packet. FIG. 24B is a truth table of AND. 図２５Ａは、入力電圧を示す図である。図２５Ｂは、出力電圧を示す図である。FIG. 25A is a diagram showing an input voltage. FIG. 25B is a diagram showing an output voltage. 図２６Ａは、出力電流を示す図である。図２６Ｂは、蓄電部の電圧変化を示す図である。FIG. 26A is a diagram showing an output current. FIG. 26B is a diagram showing a voltage change of the power storage unit. 図２７Ａは、ＡＮＤ演算の入力電圧及び出力電圧を示す図である。図２７Ｂは、ＡＮＤ演算の出力電流を示す図である。FIG. 27A is a diagram showing an input voltage and an output voltage of the AND operation. FIG. 27B is a diagram showing the output current of the AND operation. 図２８は、ＯＲ，ＮＯＴ，ＥＸＯＲ，ＮＯＲ，ＮＡＮＤの真理値表を示す図である。FIG. 28 is a diagram showing a truth table of OR, NOT, EXOR, NOR, and NAND. 図２９Ａは、入力電圧を示す図である。図２９Ｂは、出力電圧を示す図である。FIG. 29A is a diagram showing an input voltage. FIG. 29B is a diagram showing an output voltage. 図３０Ａは、出力電流を示す図である。図３０Ｂは、蓄電部の電圧変化を示す図である。FIG. 30A is a diagram showing an output current. FIG. 30B is a diagram showing a voltage change of the power storage unit. 図３１Ａは、ＮＡＮＤ演算の入力電圧及び出力電圧を示す図である。図３１Ｂは、ＮＡＮＤ演算の出力電流を示す図である。FIG. 31A is a diagram showing an input voltage and an output voltage of NAND operation. FIG. 31B is a diagram showing the output current of the NAND operation. 図３２は、コントローラによる処理の説明図である。FIG. 32 is an explanatory diagram of processing by the controller. 図３３Ａは、蓄電部の電圧の状態遷移図である。図３３Ｂは、入力、演算種別、出力および状態を示す表である。図３３Ｃは、制御例における状態遷移図である。FIG. 33A is a state transition diagram of the voltage of the power storage unit. FIG. 33B is a table showing inputs, operation types, outputs and states. FIG. 33C is a state transition diagram in the control example. 図３４は、蓄電部の電圧変化を示す図である。FIG. 34 is a diagram showing a voltage change of the power storage unit.
＜１．第１の開示＞ <1. First disclosure>
＜１．１　電力パケット伝送装置、電力パケット伝送システム、及び電力パケット伝送制御方法の概要＞ <1.1 Outline of power packet transmission device, power packet transmission system, and power packet transmission control method>
（１）実施形態に係る電力パケット伝送装置は、前記電力パケット伝送装置の出力側からの電力パケット要求によって決まる理想出力電力と、前記電力パケット伝送装置から出力される出力電力パケットから決まる実出力電力と、の差が小さくなるように前記出力電力パケットが有する電力を設定することを含む伝送制御処理を実行するコントローラを備える。伝送制御処理により、理想出力電力と実出力電力との差が小さくされる。実施形態に係る電力パケット伝送装置は、前記伝送制御処理によって設定された前記電力を有する前記出力電力パケットを生成するパワープロセッシング回路を更に備えることができる。 (1) The power packet transmission device according to the embodiment is an ideal output power determined by a power packet request from the output side of the power packet transmission device and an actual output power determined by an output power packet output from the power packet transmission device. A controller that executes transmission control processing including setting the power possessed by the output power packet so that the difference between the power and the power is small is provided. The transmission control process reduces the difference between the ideal output power and the actual output power. The power packet transmission device according to the embodiment may further include a power processing circuit that generates the output power packet having the power set by the transmission control process.
　　前記出力電力パケットが有する電力を設定することは、複数の論理演算のうちから、前記差を最小にする論理演算を選択することを含むことができる。前記出力電力パケットが有する電力は、前記電力パケット伝送装置へ入力される入力電力パケットが有する電力が示す論理値に対して、選択された前記論理演算を適用して得られる演算結果に応じて設定されるのが好ましい。前記複数の論理演算は、例えば、前記入力電力パケットが有する電力が示す論理値を反転させるＮＯＴ演算と、及び前記入力電力パケットが有する電力が示す論理値を維持するＴｈｒｏｕｇｈ演算と、を含むことができる。 Setting the power of the output power packet can include selecting a logical operation that minimizes the difference from a plurality of logical operations. The power of the output power packet is set according to the calculation result obtained by applying the selected logical operation to the logical value indicated by the power of the input power packet input to the power packet transmission device. It is preferable to be done. The plurality of logical operations may include, for example, a NOT operation that inverts the logical value indicated by the power indicated by the input power packet, and a Through operation that maintains the logical value indicated by the power indicated by the input power packet. it can.
（３）前記伝送制御処理は、前記出力電力パケットが有する電力についての複数の候補値毎に前記差を演算することを含むことができる。前記出力電力パケットが有する電力は、前記複数の候補値のうち前記差を最小にする候補値に設定されてもよい。なお、出力電力パケットに含まれる電力が０に設定される場合、出力電力パケットは伝送されなくてもよいし、電力が０である出力伝送パケットが伝送されてもよい。 (3) The transmission control process can include calculating the difference for each of a plurality of candidate values for the power of the output power packet. The power contained in the output power packet may be set to a candidate value that minimizes the difference among the plurality of candidate values. When the power included in the output power packet is set to 0, the output power packet may not be transmitted, or the output transmission packet having 0 power may be transmitted.
（４）前記複数の候補値それぞれは、論理値であるのが好ましい。 (4) It is preferable that each of the plurality of candidate values is a logical value.
（５）前記出力電力パケットが有する電力は、前記電力パケット要求とは異なる値に設定されることがあるのが好ましい。 (5) It is preferable that the power of the output power packet may be set to a value different from the power packet request.
（６）前記差は、前記電力パケット伝送装置へ入力される入力電力パケットが有する電力の値に基づいて計算されるのが好ましい。 (6) The difference is preferably calculated based on the value of the power possessed by the input power packet input to the power packet transmission device.
（７）前記差は、前記出力側の回路モデルに基づいて計算されるのが好ましい。 (7) The difference is preferably calculated based on the circuit model on the output side.
（８）電力パケット伝送装置は、前記電力パケット伝送装置へ入力される入力電力パケットが有する電力を蓄える蓄電部を更に備えるのが好ましい。 (8) It is preferable that the power packet transmission device further includes a power storage unit that stores the power of the input power packet input to the power packet transmission device.
（９）前記差は、前記蓄電部に蓄えられたエネルギー値に基づいて計算されるのが好ましい。 (9) The difference is preferably calculated based on the energy value stored in the power storage unit.
（１０）電力パケット伝送装置は、前記エネルギー値を計測する計測部を更に備えるのが好ましい。 (10) The power packet transmission device preferably further includes a measuring unit for measuring the energy value.
（１１）前記電力パケット要求は、電力供給先である負荷装置において生成された要求であるのが好ましい。なお、電力パケット要求は、電力パケット伝送装置の出力側に接続された他の電力パケット伝送装置から生成されてもよい。 (11) The power packet request is preferably a request generated in a load device that is a power supply destination. The power packet request may be generated from another power packet transmission device connected to the output side of the power packet transmission device.
（１２）実施形態に係る電力パケット伝送システムは、前記電力パケット伝送装置を備えることができる。また、実施形態に係る電力パケット伝送システムは、複数の電力パケット伝送装置が接続されたネットワークを備えることができる。前記複数の電力パケット伝送装置のうちの少なくとも１以上の電力パケット伝送装置は、（１）項から（１１）項のいずれか１項に記載の電力パケット伝送装置であるのが好ましい。 (12) The power packet transmission system according to the embodiment may include the power packet transmission device. Further, the power packet transmission system according to the embodiment can include a network to which a plurality of power packet transmission devices are connected. It is preferable that at least one or more power packet transmission devices among the plurality of power packet transmission devices are the power packet transmission devices according to any one of items (1) to (11).
（１３）実施形態に係る電力パケット伝送制御方法は、電力パケット要求によって決まる理想出力電力と、前記電力パケット要求に基づいて出力される出力電力パケットから決まる実出力電力と、の差が小さくなるように前記出力電力パケットが有する電力を設定することを備えることができる。 (13) In the power packet transmission control method according to the embodiment, the difference between the ideal output power determined by the power packet request and the actual output power determined by the output power packet output based on the power packet request is reduced. Can be provided with setting the power contained in the output power packet.
＜１．２　電力パケット伝送装置、電力パケット伝送システム、及び電力パケット伝送制御方法の例＞ <1.2 Example of power packet transmission device, power packet transmission system, and power packet transmission control method>
　図１は、電力パケット伝送システム１０を示している。システム１０は、電源２０から負荷５０へ電力を電力パケット６０によって伝送するネットワークを構成する。電源２０は、例えば、発電設備又は電池である。システム１０においては、複数の電源２０が、分散配置されている。電源２０は、例えば、直流電源である。 FIG. 1 shows a power packet transmission system 10. The system 10 constitutes a network in which electric power is transmitted from the power source 20 to the load 50 by the electric power packet 60. The power source 20 is, for example, a power generation facility or a battery. In the system 10, a plurality of power supplies 20 are distributed and arranged. The power supply 20 is, for example, a DC power supply.
　システム１０は、ミキサ３０を備える。ミキサ３０は、電源２０から供給される電力から、電力パケット６０を生成する。電力パケット６０は、パルス化された電力を伝送するためのものである。図２に示すように、電力パケット６０は、パルス化された電力を有するペイロード６２と、ヘッダ６１及びフッタ６３からなる情報タグと、を備えている。ミキサ３０が生成した電力パケット６０は、システム１０内のルータ４０へ送信される。 System 10 includes a mixer 30. The mixer 30 generates a power packet 60 from the power supplied from the power source 20. The power packet 60 is for transmitting pulsed power. As shown in FIG. 2, the power packet 60 includes a payload 62 having pulsed power and an information tag including a header 61 and a footer 63. The power packet 60 generated by the mixer 30 is transmitted to the router 40 in the system 10.
　実施形態において、情報タグは、情報伝送用であり、電力伝送用ではない。ヘッダ６１は、電力パケット６０の宛先アドレスなどを有する。フッタ６３は、電力パケット６０の終了情報などを有する。ペイロード６２は、電流を伴い、電力伝送用である。電力がパケット化されていることにより、電力の離散化が図られている。したがって、電力伝送量は、電力パケット６０の個数又は密度で決定される。なお、ヘッダ６１の電圧値は、ペイロード６２の電圧と等しくなくてもよく、情報伝送が確保できる最低限の電圧値であってもよい。 In the embodiment, the information tag is for information transmission, not for power transmission. The header 61 has a destination address of the power packet 60 and the like. The footer 63 has end information of the power packet 60 and the like. The payload 62 is accompanied by an electric current and is for power transmission. Since the electric power is packetized, the electric power is discretized. Therefore, the amount of power transmission is determined by the number or density of power packets 60. The voltage value of the header 61 does not have to be equal to the voltage of the payload 62, and may be the minimum voltage value at which information transmission can be ensured.
　システム１０は、ルータ４０を備える。電力パケット６０は、ルータ４０を介して、ネットワーク内で転送され、負荷５０へ到達する。ルータ４０は、ネットワーク内で、電力パケット６０を中継する。実施形態のルータ４０は、電力パケット６０の伝送制御処理を実行する電力パケット伝送装置として動作する。ルータ４０は、伝送制御処理として、電力パケットの入出力に関する処理を実行する。 The system 10 includes a router 40. The power packet 60 is forwarded in the network via the router 40 and reaches the load 50. The router 40 relays the power packet 60 in the network. The router 40 of the embodiment operates as a power packet transmission device that executes a transmission control process of the power packet 60. The router 40 executes a process related to input / output of a power packet as a transmission control process.
　図３に示すように、ルータ４０は、コントローラ４１とパワープロセッシング回路４５とを備える。コントローラ４１は、ＣＰＵ及びメモリを有するコンピュータによって構成される。コントローラ４１は、伝送制御処理を実行する。伝送制御処理では、コントローラ４１は、パワープロセッシング回路４５を制御する。コントローラ４１は、後述の誤差Ｖ2eの演算のため、入力電力パケットが有する電力の値（入力電力値）及び電力パケット要求を取得する。コントローラ４１は、他のルータ４０に対して電力パケット要求を送信してもよい。パワープロセッシング回路４５は、入力電力パケット６０の電力に対する演算を行い、演算結果に相当する電力をペイロード６２に有する出力電力パケット６０を出力する。 As shown in FIG. 3, the router 40 includes a controller 41 and a power processing circuit 45. The controller 41 is composed of a computer having a CPU and a memory. The controller 41 executes the transmission control process. In the transmission control process, the controller 41 controls the power processing circuit 45. The controller 41 acquires the power value (input power value) of the input power packet and the power packet request for the calculation of the error V 2e described later. The controller 41 may send a power packet request to another router 40. The power processing circuit 45 calculates the power of the input power packet 60, and outputs the output power packet 60 having the power corresponding to the calculation result in the payload 62.
　パワープロセッシング回路４５は、入力電力パケット６０の電力を蓄えるための蓄電部４６を備える。つまり、ルータ４０は、電力パケット６０として伝送される電力を、蓄電部４６に蓄積することができる。ルータ４０は、蓄電部４６に蓄積された電力及び入力電力パケット６０の電力から、出力電力パケットを再生成することができる。したがって、ルータ４０は、入力電力パケット６０を、任意のタイミングで、出力電力パケット６０として出力することができる。 The power processing circuit 45 includes a power storage unit 46 for storing the power of the input power packet 60. That is, the router 40 can store the electric power transmitted as the electric power packet 60 in the power storage unit 46. The router 40 can regenerate the output power packet from the power stored in the power storage unit 46 and the power of the input power packet 60. Therefore, the router 40 can output the input power packet 60 as the output power packet 60 at an arbitrary timing.
　本実施形態においては、パワープロセッシング回路４５において、電力演算が行われるため、入力電力パケット６０のペイロード６２が有する電力の値と、出力電力パケット６０のペイロード６２が有する電力の値とは、同じでなくてもよい。すなわち、出力電力パケット６０の電力値は、入力電力パケット６０の電力値に対する電力演算結果に相当する。 In the present embodiment, since the power processing circuit 45 performs the power calculation, the power value of the payload 62 of the input power packet 60 and the power value of the payload 62 of the output power packet 60 are the same. It does not have to be. That is, the power value of the output power packet 60 corresponds to the power calculation result with respect to the power value of the input power packet 60.
　ここで、図３に示すルータ４０は、電力パケット６０の入出力数が１入力１出力である。つまり、電力パケット６０の入力ポート４５Ａの数は１つである。電力パケット６０の出力ポート４５Ｂの数は１つである。ただし、図４に示すように、ルータ４０は、複数の入力ポート４５Ａ及び複数の出力ポート４５Ｂを備えてもよい。ルータ４０は、複数の入力ポート４５Ａを備えることで、複数の伝送元（ルータ４０又はミキサ３０）から、電力パケット６０を受信できる。また、ルータ４０は、複数の出力ポート４５Ｂを備えることで、電力パケット６０を転送するルートを決定するルーティングを行うことができる。 Here, in the router 40 shown in FIG. 3, the number of inputs and outputs of the power packet 60 is one input and one output. That is, the number of input ports 45A of the power packet 60 is one. The number of output ports 45B of the power packet 60 is one. However, as shown in FIG. 4, the router 40 may include a plurality of input ports 45A and a plurality of output ports 45B. By including the plurality of input ports 45A, the router 40 can receive the power packet 60 from a plurality of transmission sources (router 40 or mixer 30). Further, the router 40 includes a plurality of output ports 45B, so that the router 40 can perform routing for determining a route for forwarding the power packet 60.
　図４に示すルータ４０は、複数のパワープロセッシング回路４５を備える。また、図４に示すルータ４０は、スイッチ回路４７，４８を備える。スイッチ回路４７は、複数の入力ポート４５Ａのいずれか一方から入力された電力パケット６０を、複数のパワープロセッシング回路４５のいずれかに与える。スイッチ回路４８は、複数のパワープロセッシング回路４５のいずれか一方から出力された電力パケット６０を、複数の出力ポート４５Ｂのいずれかから出力させる。コントローラ４１は、スイッチ回路４８を制御することにより、電力パケット６０を転送するルート（出力ポート４５Ｂ）を決定するルーティングを行うことができる。 The router 40 shown in FIG. 4 includes a plurality of power processing circuits 45. Further, the router 40 shown in FIG. 4 includes switch circuits 47 and 48. The switch circuit 47 supplies the power packet 60 input from any one of the plurality of input ports 45A to any one of the plurality of power processing circuits 45. The switch circuit 48 causes the power packet 60 output from any one of the plurality of power processing circuits 45 to be output from any one of the plurality of output ports 45B. By controlling the switch circuit 48, the controller 41 can perform routing for determining a route (output port 45B) for forwarding the power packet 60.
　以下では、ルータ４０のルーティング機能を考慮することなく、ルータ４０の伝送制御機能について説明するため、図３に示す１入力１出力のルータ４０を前提に説明する。ただし、以下の説明は、図４に示す複数入力複数出力のルータ４０にも当てはまる。 In the following, in order to explain the transmission control function of the router 40 without considering the routing function of the router 40, the router 40 with one input and one output shown in FIG. 3 will be described below. However, the following description also applies to the router 40 having a plurality of inputs and a plurality of outputs shown in FIG.
　また、以下では、電力パケット６０を、図５に示す「時間枠（timeslot）ｔ」にて表す。時間枠ｔは、電力パケット６０におけるヘッダ６１及びフッタ６３が省略され、ペイロード６２のみからなる。ここで、個々の時間枠ｔの時間長は一定とする。以下では、電力パケット６０の電力に対する演算は、時間枠ｔ内の電力値に対する演算として説明される。演算は、一例として、論理演算であり、時間枠ｔ（電力パケット６０）における電力の論理値（例えば、２値論理値）は、時間枠ｔにおける電力の大小によって定義される。すなわち、論理値「１」は、時間枠ｔにおける電力が閾値よりも大きいことを示し、論理値「０」は、時間枠ｔにおける電力が閾値以下であることを示す。以下では、簡単化のため、閾値を０とし、時間枠ｔ内に電力が存在すれば「１」とし、時間枠ｔ内に電力が存在しなければ「０」とする。これにより、論理値は、時間枠ｔにおける電圧の有無、すなわち、電力パケット６０の有無を表すものとなる。なお、実際には、論理値「０」は、電力パケット６０自体は存在するが、ペイロード６２に格納された電力がほぼ０であることを示してもよいし、電力パケット６０自体が存在しないことを示してもよい。また、演算は、算術演算であってもよい。 Further, in the following, the power packet 60 is represented by the “timelot t” shown in FIG. The time frame t includes only the payload 62, omitting the header 61 and the footer 63 in the power packet 60. Here, the time length of each time frame t is constant. In the following, the calculation for the power of the power packet 60 will be described as the calculation for the power value within the time frame t. The operation is a logical operation as an example, and the logical value (for example, binary logical value) of the power in the time frame t (power packet 60) is defined by the magnitude of the power in the time frame t. That is, the logical value "1" indicates that the power in the time frame t is larger than the threshold value, and the logical value "0" indicates that the power in the time frame t is equal to or less than the threshold value. In the following, for the sake of simplicity, the threshold value is set to 0, "1" is set if the power exists in the time frame t, and "0" is set if there is no power in the time frame t. As a result, the logical value represents the presence / absence of the voltage in the time frame t, that is, the presence / absence of the power packet 60. In reality, the logical value "0" may indicate that the power packet 60 itself exists, but the power stored in the payload 62 is almost 0, or the power packet 60 itself does not exist. May be indicated. Moreover, the operation may be an arithmetic operation.
　実施形態では、論理演算（Logic Operation）として、ＮＯＴ演算及びＴｈｒｏｕｇｈ演算を含む複数の論理演算が定義される。ＮＯＴ演算は、入力に対する反転演算である。図５に示すように、ＮＯＴ演算では、「０」が入力されれば、「１」が出力される。また、「１」が入力されれば、「０」が出力される。Ｔｈｒｏｕｇｈ演算は、入力に対する非反転演算である。図５に示すように、Ｔｈｒｏｕｇｈ演算では、「１」が入力されれば、「１」が出力される。また、「０」が入力されれば、「０」が出力される。複数の論理演算は、ＮＯＴ演算及びＴｈｒｏｕｇｈ演算以外の他の論理演算であってもよい。また、複数の論理演算は、ＮＯＴ演算及びＴｈｒｏｕｇｈ演算以外の他の論理演算を含んでもよい。他の論理演算は、例えば、ＡＮＤ演算（論理積）、ＮＡＮＤ演算（否定論理積）、ＯＲ演算（論理和）、ＮＯＲ演算（否定論理和）、及びＸＯＲ演算（排他的論理和）の少なくとも１つ以上である。他の論理演算は、後述の第２の開示においても説明される。ルータ４０は、第２の開示において説明される論理演算を実行可能に構成されていてもよい。 In the embodiment, a plurality of logical operations including NOT operation and Through operation are defined as logical operations (Logic Operation). The NOT operation is an inversion operation for the input. As shown in FIG. 5, in the NOT operation, if "0" is input, "1" is output. If "1" is input, "0" is output. The Throw operation is a non-inverted operation on the input. As shown in FIG. 5, in the Throw operation, if "1" is input, "1" is output. If "0" is input, "0" is output. The plurality of logical operations may be other logical operations other than NOT operation and Through operation. Further, the plurality of logical operations may include other logical operations other than the NOT operation and the Through operation. Other logical operations are, for example, at least one of AND operation (logical product), NAND operation (negative logical product), OR operation (logical sum), NOR operation (negative OR), and XOR operation (exclusive OR). More than one. Other logical operations are also described in the second disclosure below. The router 40 may be configured to be able to perform the logical operations described in the second disclosure.
　図６は、ルータ４０がＴｈｒｏｕｇｈ演算を実行する場合と、ＮＯＴ演算を実行する場合と、を示している。なお、図６では、電源２０が電力パケット６０（時間枠ｔの電力）をルータ４０に与え、ルータ４０が電力パケットを負荷５０に与える。また、図６では、負荷５０は、負荷５０が必要とする電力量の論理値を、電力パケット要求として、電源２０及びルータ４０に与える。なお、電力パケット要求は、負荷５０ではなく、他のルータからルータ４０に与えられてもよい。 FIG. 6 shows a case where the router 40 executes a Through operation and a case where the router 40 executes a NOT operation. In FIG. 6, the power supply 20 supplies the power packet 60 (power in the time frame t) to the router 40, and the router 40 supplies the power packet to the load 50. Further, in FIG. 6, the load 50 gives a logical value of the amount of power required by the load 50 to the power supply 20 and the router 40 as a power packet request. The power packet request may be given to the router 40 by another router instead of the load 50.
　図６では、負荷５０が、電力パケット要求として論理値「１」又は論理値「０」を、電源２０及びルータ４０に送信する。電力パケット要求としての「１」は、論理値「１」の電力パケットの送信要求である。また、電力パケット要求としての「０」は、論理値「０」の電力パケットの送信要求（又は電力パケットの非送信要求）である。 In FIG. 6, the load 50 transmits a logical value “1” or a logical value “0” as a power packet request to the power supply 20 and the router 40. "1" as a power packet request is a power packet transmission request having a logical value of "1". Further, "0" as a power packet request is a power packet transmission request (or a power packet non-transmission request) having a logical value of "0".
　ここで、電源２０は、電力パケット要求とおりに、電力パケット６０を出力できるとは限らない。したがって、ルータ４０は、電力パケット要求とおりの入力電力パケットを受信できるとは限らない。なお、ルータ４０が、電力パケット要求とおりの入力電力パケットを受信できないケースとしては、電源２０の発電量が十分でない場合又は他のルータ４０へ電力を優先して送信すべき場合などである。また、ルータ４０の入力側に接続された装置が他のルータ４０である場合には、他のルータ４０が、電力パケット要求とおりの出力電力パケットを送信しない場合にも、ルータ４０は、電力パケット要求とおりの入力電力パケットを受信できなくなる。 Here, the power supply 20 may not always be able to output the power packet 60 as requested by the power packet. Therefore, the router 40 may not always be able to receive the input power packet as requested by the power packet. The case where the router 40 cannot receive the input power packet as requested by the power packet is a case where the power generation amount of the power source 20 is not sufficient or a case where the power should be preferentially transmitted to another router 40. Further, when the device connected to the input side of the router 40 is another router 40, the router 40 also uses the power packet even when the other router 40 does not transmit the output power packet as requested by the power packet. The input power packet as requested cannot be received.
　電力パケット要求が「１」であり、電源２０が「１」の電力パケット６０を出力できる場合、電源２０は「１」を出力する（図６に示される「Ｔｈｒｏｕｇｈ演算」及び図７の時間枠ｔ１参照）。この場合、ルータ４０に入力される電力パケット６０の論理値は「１」である。したがって、ルータ４０は、負荷５０からの電力パケット要求に従い、論理値「１」の電力パケットを出力することができる。このように、ルータ４０が入力と同じ値の電力パケットを出力するように動作する演算がＴｈｒｏｕｇｈ演算である。 When the power packet request is "1" and the power supply 20 can output the power packet 60 of "1", the power supply 20 outputs "1" (the "Reference operation" shown in FIG. 6 and the time frame of FIG. 7). t see 1). In this case, the logical value of the power packet 60 input to the router 40 is "1". Therefore, the router 40 can output the power packet having the logical value "1" in accordance with the power packet request from the load 50. In this way, the operation in which the router 40 operates so as to output a power packet having the same value as the input is the Throw operation.
　電力パケット要求が「１」であっても、電源２０が「１」の電力パケット６０を出力できない場合、電源２０は「０」を出力する（図６に示される「ＮＯＴ演算」及び図７の時間枠ｔ３参照）。この場合、ルータ４０に入力される電力パケット６０の論理値は「０」である。しかし、ルータ４０は、負荷５０からの電力パケット要求に従い、論理値「１」の電力パケットを出力する。このように、ルータ４０が入力とは異なる値の電力パケットを出力するように動作する演算がＮＯＴ演算である。 Even if the power packet request is "1", if the power supply 20 cannot output the power packet 60 of "1", the power supply 20 outputs "0"("NOToperation" shown in FIG. 6 and FIG. 7). reference time frame t 3). In this case, the logical value of the power packet 60 input to the router 40 is "0". However, the router 40 outputs a power packet having a logical value of "1" in accordance with the power packet request from the load 50. In this way, the operation in which the router 40 operates so as to output a power packet having a value different from the input is the NOT operation.
　図７の時間枠ｔ３に示すように、ルータ４０への入力が「０」であるときに、ルータ４０が「１」を出力すると、ルータ４０の蓄電部４６に蓄積されていた電力は、負荷５０へ放出されるため、減少する。このため、時間枠ｔ３におけるルータ４０の出力が論理値として「１」であっても、時間枠ｔ３におけるアナログ電圧は減少する。そのような電圧減少がない場合の電圧（例えば、２０Ｖ）を、論理値「１」に対応した理想出力電圧であるとすると、時間枠ｔ３におけるアナログ電圧は、理想出力電圧から減少したものとなる。したがって、時間枠ｔ３において、ルータ４０が実際に出力した電力は、負荷５０が要求した電力値（論理値「１」＝２０Ｖに相当する電力＝理想出力電力）とは異なる。つまり、時間枠ｔ３において、負荷５０が受け取った電力は、論理値としてみると負荷５０の要求とおりであるが、アナログ値としてみると負荷５０の要求とは異なるものとなっている。なお、理論出力電力は、ルータ４０に与えられた電力パケット要求に従って電力パケットが出力された場合の電力であり、電力パケット要求が示す値（論理値）に基づいて演算される。 As shown in the time frame t 3 in FIG. 7, when the input to the router 40 is "0", the router 40 outputs "1", the power accumulated in the power storage unit 46 of the router 40, Since it is released to the load 50, it decreases. Therefore, even in "1" as the output logical value of the router 40 in the time frame t 3, the analog voltage at time frame t 3 is reduced. Such voltage when reduction is no voltage (e.g., 20V) and, when an ideal output voltage corresponding to a logical value "1", the analog voltage at time frame t 3 is, as was reduced from the ideal output voltage Become. Accordingly, the time frame t 3, power router 40 is actually output is different from the power value load 50 requests (power = ideal output power corresponding to a logic value "1" = 20V). That is, in the time frame t 3, power load 50 has received is, but as a request to the load 50 viewed as a logical value, which is different from the viewed as an analog value and the required load 50. The theoretical output power is the power when the power packet is output according to the power packet request given to the router 40, and is calculated based on the value (logical value) indicated by the power packet request.
　このように、電力をパケット化すると、電力を電力パケットの個数又は密度で取り扱うことができ簡便になる一方、個々の電力パケット電力のアナログ値は変動する可能性があるため、電力を電力パケットの個数又は密度で取り扱った場合の理論的な電力値と、実際の電力値と、の間に差が生じる。以下では、この差を「誤差」という。このため、負荷５０は、論理値としては要求とおりの電力を受け取っていても、アナログ値としては要求とは異なる電力を得ることになる。 In this way, when the electric power is packetized, the electric power can be handled by the number or density of the electric power packets, which is convenient. On the other hand, the analog value of the individual electric power packet electric power may fluctuate. There is a difference between the theoretical power value when dealing with the number or density and the actual power value. Hereinafter, this difference is referred to as an "error". Therefore, even if the load 50 receives the required power as a logical value, the load 50 obtains a power different from the required power as an analog value.
　そこで、実施形態のルータ４０のコントローラ４１は、かかる誤差を考慮して、かかる誤差が小さくなるように、電力パケット６０の伝送制御処理を実行する。実施形態の伝送制御処理は、論理演算（logic Operation）の選択を含む。 Therefore, the controller 41 of the router 40 of the embodiment considers such an error and executes the transmission control process of the power packet 60 so that the error becomes small. The transmission control process of the embodiment includes selection of a logic operation.
　図８は、誤差を小さくするための論理演算が行われない場合のルータ４０の入出力系列と、誤差を小さくするための論理演算が行われる場合のルータ４０の入出力系列と、を示している。ルータ４０へ与えられる電力パケット要求が「１０１０１０」である場合、ルータ４０に与えられる理想的な入力（Ideal Input）は、電力パケット要求と同じ「１０１０１０」である。この場合、ルータ４０は、入力に対する特別な演算をする必要はない。ルータ４０は、理想的な入力「１０１０１０」をそのまま出力することで、電力パケット要求に応じた電力を出力することができる。 FIG. 8 shows an input / output sequence of the router 40 when the logical operation for reducing the error is not performed, and an input / output sequence of the router 40 when the logical operation for reducing the error is performed. There is. When the power packet request given to the router 40 is "101010", the ideal input given to the router 40 is "101010" which is the same as the power packet request. In this case, the router 40 does not need to perform any special calculation on the input. The router 40 can output the power according to the power packet request by outputting the ideal input “101010” as it is.
　しかし、実際の入力（Real Input）は、例えば、図８に示す「０１００１０」のように、電力パケット要求とは異なることがある。この場合に、ルータ４０が、電力パケット要求とおりに「１０１０１０」を出力すると、負荷５０が得られる電力は、負荷５０が期待した電力とは異なるものとなり誤差が生じる。この誤差は、電力パケット６０の出力のたびに蓄積される。そこで、実施形態のルータ４０は、蓄積される誤差が小さくなるように、入力に対する論理演算の選択及び実行をする。この結果、例えば、「１０１『０』１０」の電力パケット要求から、修正された「１０１『１』１０」が出力される。このように、実施形態のルータ４０は、誤差を考慮し、適切な演算を選択することで、電力パケット要求から修正された出力を決定する。 However, the actual input (Real Input) may be different from the power packet request, for example, as shown in FIG. 8 “010010”. In this case, when the router 40 outputs "101010" as requested by the power packet, the power obtained by the load 50 is different from the power expected by the load 50, and an error occurs. This error is accumulated with each output of the power packet 60. Therefore, the router 40 of the embodiment selects and executes a logical operation for the input so that the accumulated error becomes small. As a result, for example, the modified "101" 1 "10" is output from the power packet request of "101" 0 "10". As described above, the router 40 of the embodiment determines the corrected output from the power packet request by considering the error and selecting an appropriate operation.
　図９は、修正された出力を決定するための伝送制御処理を示している。この伝送制御処理は、コントローラ４１により実行される。伝送制御処理のステップＳ１１では、誤差Ｖ2eが小さくなるように出力電力パケットが有する電力が設定される。より具体的には、伝送制御処理のステップＳ１１では、出力電力パケットが有する電力の設定のため、入力電力パケット６０の電力が示す論理値に対して適用される演算が選択される。実施形態においては、入力電力パケット６０の電力が示す論理値に対して適用される演算として、ＮＯＴ演算及びＴｈｒｏｕｇｈ演算のうち、誤差Ｖ2eが小さくなる方の演算が選択される。演算の選択のため、前述の誤差が計算される。ここでの誤差は、負荷５０への理想出力電圧（理想負荷電圧Ｖ2l）と、負荷５０への実際の出力電圧（実際の負荷電圧Ｖ2r）と、の差Ｖ2eである。ある時間枠ｔにおいて生じる誤差Ｖ2eは、過去から蓄積した誤差に加えて、その時間枠ｔにおける入出力の値によって決まる。したがって、ある時間枠ｔにおいて生じる誤差Ｖ2eは、その時間枠ｔにおける入力電力パケット６０の論理値、すなわち入力電力パケットが有する電力の値（入力電力値）が判明すれば、出力電力パケット６０として「１」を出力するか「０」を出力するかによって決まる。なお、ここでは、簡単化のため、入力電力パケット６０のアナログ値は、同じ論理値については、一定であり、変動しないものとする。 FIG. 9 shows a transmission control process for determining the modified output. This transmission control process is executed by the controller 41. In step S11 of the transmission control process, the power contained in the output power packet is set so that the error V 2e becomes small. More specifically, in step S11 of the transmission control process, an operation applied to the logical value indicated by the power of the input power packet 60 is selected for setting the power of the output power packet. In the embodiment, as the operation applied to the logical value indicated by the power of the input power packet 60, the operation of the NOT operation and the Through operation, whichever has the smaller error V 2e, is selected. The above error is calculated for the choice of operation. The error here is the difference V 2e between the ideal output voltage to the load 50 (ideal load voltage V 2l ) and the actual output voltage to the load 50 (actual load voltage V 2r ). The error V 2e that occurs in a certain time frame t is determined by the input / output values in that time frame t in addition to the error accumulated from the past. Therefore, the error V 2e that occurs in a certain time frame t can be regarded as the output power packet 60 if the logical value of the input power packet 60 in the time frame t, that is, the power value (input power value) of the input power packet is known. It depends on whether to output "1" or "0". Here, for the sake of simplicity, it is assumed that the analog value of the input power packet 60 is constant and does not fluctuate with respect to the same logical value.
　具体的には、まず、ステップＳ１０において、コントローラ４１は、負荷５０から、時間枠ｔにおける電力パケット要求を受信する。ここでの電力パケット要求は、「０」又は「１」を示す。なお、電力パケット要求は、ルータ４０と負荷５０とが同期することにより、時間枠ｔそれぞれにおいて、負荷５０から与えられる。つまり、図９に示す伝送制御処理は、時間枠ｔそれぞれにおいて実行される。ただし、電力パケット要求は、時間枠ｔそれぞれにおいて与えられる必要はない。電力パケット要求が時間枠ｔそれぞれにおいて与えられない場合、コントローラ４１は、電力パケット要求が負荷５０から受信したことをトリガとして、伝送制御処理の実行を開始することができる。 Specifically, first, in step S10, the controller 41 receives the power packet request in the time frame t from the load 50. The power packet request here indicates "0" or "1". The power packet request is given from the load 50 in each time frame t by synchronizing the router 40 and the load 50. That is, the transmission control process shown in FIG. 9 is executed in each time frame t. However, the power packet request does not have to be given in each time frame t. When the power packet request is not given in each of the time frames t, the controller 41 can start the execution of the transmission control process by using the power packet request received from the load 50 as a trigger.
　続くステップＳ１１に含まれるステップＳ１１１において、入力電力パケット６０の入力電力値が、「０」であるか「１」であるか判定される。入力電力値が「１」である場合には、ステップＳ１１２において、入力電力値が「１」であることを前提に、出力電力パケットが有する電力についての候補値（出力電力候補値）である「０」を出力したときの誤差Ｖ2e10と、他の出力電力候補値である「１」を出力したときに誤差Ｖ2e10と、がそれぞれ計算される。前述のように、誤差Ｖ2e10は、負荷５０への理想出力電圧（理想負荷電圧Ｖ2l）と、負荷５０への実際の出力電圧（実際の負荷電圧Ｖ2r）と、の差Ｖ2eである。理想出力電圧（理想負荷電圧Ｖ2l）は、ステップＳ１０において受信した電力パケット要求に従って出力される理想的な電圧であり、受信した電力パケット要求が示す値に基づいて求められる。実際の出力電圧（実際の負荷電圧Ｖ2r）は、入力電圧値と出力電力値候補値とに基づいて求められる。 In step S111 included in the following step S11, it is determined whether the input power value of the input power packet 60 is "0" or "1". When the input power value is "1", in step S112, assuming that the input power value is "1", it is a candidate value (output power candidate value) for the power possessed by the output power packet. 0 "and the error V 2E10 when outputting the, the error V 2E10 when outputs" 1 "which is another output power candidate value, but are calculated respectively. As described above, the error V 2e10 is the difference V 2e between the ideal output voltage to the load 50 (ideal load voltage V 2l ) and the actual output voltage to the load 50 (actual load voltage V 2r). .. The ideal output voltage (ideal load voltage V 2l ) is an ideal voltage output according to the power packet request received in step S10, and is obtained based on the value indicated by the received power packet request. The actual output voltage (actual load voltage V 2r ) is obtained based on the input voltage value and the output power value candidate value.
　また、入力電力値が「０」である場合には、ステップＳ１１６において、入力電力値が「０」であることを前提に、出力電力候補値である「０」を出力したときの誤差Ｖ2e00と、他の出力電力候補値である「１」を出力したときに誤差Ｖ2e11と、がそれぞれ計算される。誤差Ｖ2e11の計算は、ステップＳ１２２と同様に行われる。 If the input power value is "0", the error V 2e00 when the output power candidate value "0" is output on the premise that the input power value is "0" in step S116. And the error V 2e11 when the other output power candidate value "1" is output, respectively, are calculated. The calculation of the error V 2e11 is performed in the same manner as in step S122.
　続いて、入力電力パケット６０に対する演算として、ＮＯＴ演算及びＴｈｒｏｕｇｈ演算のうち、誤差Ｖ2eが小さくなる方の演算が選択される。具体的には、ステップＳ１１３，Ｓ１１７において、誤差Ｖ2eを最小にする出力電力候補値が０であるか１であるかが決定される。入力電力値が「１」の時に、０を出力したほうが誤差Ｖ2eを小さくできるのであれば、ステップＳ１１４において、ＮＯＴ演算が選択される（選択Ｄ10）。一方、１を出力したほうが誤差Ｖ2eを小さくできるのであれば、ステップＳ１１５において、Ｔｈｒｏｕｇｈ演算が選択される（選択Ｄ11）。 Subsequently, as the operation for the input power packet 60, the operation of the NOT operation and the Through operation, whichever has the smaller error V 2e, is selected. Specifically, in steps S113 and S117, it is determined whether the output power candidate value that minimizes the error V 2e is 0 or 1. If the error V 2e can be reduced by outputting 0 when the input power value is "1", the NOT operation is selected in step S114 (selection D 10 ). On the other hand, if the error V 2e can be reduced by outputting 1, the Throw operation is selected in step S115 (selection D 11 ).
　また、入力電力値が「０」の時に、１を出力した方が誤差Ｖ2eを小さくできるのであれば、ステップＳ１１８において、ＮＯＴ演算が選択される（選択Ｄ01）。一方、０を出力した方が誤差Ｖ2eを小さくできるのであれば、ステップＳ１１９において、Ｔｈｒｏｕｇｈ演算が選択される（選択Ｄ11）。出力電力パケットが有する出力電力は、選択された論理演算を、入力電力パケット６０が有する電力が示す論理値に対して適用して得られる演算結果に応じた値に設定される。例えば、入力電力値が「１」のときにＮＯＴ演算が選択されると、出力電力の論理値は「０」に設定される。入力電力値が「１」のときにＴｈｒｏｕｇｈ演算が選択されると、出力電力の論理値は「１」に設定される。入力電力値が「０」のときにＮＯＴ演算が選択されると、出力電力の論理値は「１」に設定される。入力電力値が「０」のときにＴｈｒｏｕｇｈ演算が選択されると、出力電力の論理値は「０」に設定される。なお、ここでは、ステップＳ１１の処理を、誤差が小さくなる演算の選択として捉えて説明したが、ステップＳ１１の処理は、誤差が小さくなる出力電力候補値の選択として捉えてもよい。 If the error V 2e can be reduced by outputting 1 when the input power value is "0", the NOT operation is selected in step S118 (selection D 01 ). On the other hand, if the error V 2e can be reduced by outputting 0, the Throw operation is selected in step S119 (selection D 11 ). The output power of the output power packet is set to a value corresponding to the calculation result obtained by applying the selected logical operation to the logical value indicated by the power of the input power packet 60. For example, if the NOT operation is selected when the input power value is "1", the logical value of the output power is set to "0". If the Through operation is selected when the input power value is "1", the logical value of the output power is set to "1". If the NOT operation is selected when the input power value is "0", the logical value of the output power is set to "1". If the Through operation is selected when the input power value is "0", the logical value of the output power is set to "0". Although the process of step S11 has been described here as the selection of the operation that reduces the error, the process of step S11 may be regarded as the selection of the output power candidate value that reduces the error.
　演算が選択されると、ステップＳ１２において、演算が実行される。選択された演算が、入力電力パケット６０に対して実行されるように、コントローラ４１は、パワープロセッシング回路４５を制御する。パワープロセッシング回路４５は、入力電力パケット６０に対する演算を実行し、演算結果に相当する出力電力パケットを生成する。なお、ステップＳ１３の処理は、選択された出力電力候補値の電力が設定された出力電力パケットの生成として捉えてもよい。すなわち、パワープロセッシング回路４５は、ステップＳ１１の伝送制御処理によって設定された出力電力の論理値に応じたアナログ値の出力電力を有する出力電力パケットを生成する。 When the calculation is selected, the calculation is executed in step S12. The controller 41 controls the power processing circuit 45 so that the selected operation is performed on the input power packet 60. The power processing circuit 45 executes an operation on the input power packet 60 and generates an output power packet corresponding to the operation result. The process of step S13 may be regarded as the generation of an output power packet in which the power of the selected output power candidate value is set. That is, the power processing circuit 45 generates an output power packet having an analog value output power corresponding to the logical value of the output power set by the transmission control process in step S11.
　実施形態に係る電力パケット伝送システム１０においては、実施形態に係る伝送制御処理を実行できるルータ４０を複数設けることができる。この場合、電源２０側に近く負荷５０から離れたルータ４０では、電力パケット要求に対して厳密に応答して電力パケットを出力する必要は低く、電力パケット要求に対しておおまかに応答して、可能な範囲で電力パケットを出力することが許容される。電源２０に近いルータ４０が、電力パケット要求とは異なる電力パケットを出力しても、負荷５０に近いルータ４０は、電力パケット要求との誤差が小さくなるように電力を負荷５０へ供給することができる。 In the power packet transmission system 10 according to the embodiment, a plurality of routers 40 capable of executing the transmission control process according to the embodiment can be provided. In this case, the router 40, which is close to the power supply 20 side and away from the load 50, does not need to output the power packet in a strict response to the power packet request, and can roughly respond to the power packet request. It is permissible to output power packets within a range. Even if the router 40 close to the power source 20 outputs a power packet different from the power packet request, the router 40 close to the load 50 can supply power to the load 50 so as to reduce the error from the power packet request. it can.
　本実施形態では、上記した演算の選択のため、動的量子化器の動作を応用する。動的量子化器は、入力が離散値に限られるような制御系設計において用いられる。動的量子化器は、連続値入力の場合における出力値と、離散化した入力における出力値と、の蓄積誤差を最小にするように動作する。 In this embodiment, the operation of the dynamic quantizer is applied for the selection of the above-mentioned calculation. Dynamic quantizers are used in control system designs where the input is limited to discrete values. The dynamic quantizer operates to minimize the accumulation error between the output value in the case of continuous value input and the output value in the case of discretized input.
　図１０は、プラントＰと動的量子化器Ｑとで構成される開ループ系を示している。動的量子化器Ｑは、連続値入力ｕ（ｋ）が与えられ、離散値出力ｖ（ｋ）を生成する。プラントＰは、動的量子化器Ｑの離散値出力ｖ（ｋ）が入力（離散値入力）として与えられ、出力ｙ（ｋ）を生成する。動的量子化器Ｑは、量子化誤差がプラントＰの出力ｙ（ｋ）に与える影響が小さくなるように、入力ｕ（ｋ）を離散化する。 FIG. 10 shows an open-loop system composed of a plant P and a dynamic quantizer Q. The dynamic quantizer Q is given a continuous value input u (k) and produces a discrete value output v (k). In the plant P, the discrete value output v (k) of the dynamic quantizer Q is given as an input (discrete value input), and the output y (k) is generated. The dynamic quantizer Q discretizes the input u (k) so that the quantization error has a small effect on the output y (k) of the plant P.
　プラントＰは、図１０の式（１－１）及び式（１－２）によって定義される。動的量子化器Ｑは、図１０の式（２－１）及び式（２－２）によって定義される。連続値入力ｕ（ｋ）を量子化したことによる量子化誤差によって生じる、プラントＰの出力ｙ（ｋ）の蓄積誤差が最小化するように、動的量子化器Ｑのパラメータを設定すると、図１０の式（３－１）及び式（３－２）のようになる。式（３－１）に示されるように、動的量子化器Ｑの状態ξ及び出力ｖ（ｋ）は、プラントＰのパラメータＡ，Ｂ，Ｃの影響を受ける。 Plant P is defined by equations (1-1) and (1-2) of FIG. The dynamic quantizer Q is defined by the equations (2-1) and (2-2) of FIG. When the parameters of the dynamic quantizer Q are set so as to minimize the accumulation error of the output y (k) of the plant P caused by the quantization error due to the quantization of the continuous value input u (k), the figure shows. It becomes like the formula (3-1) and the formula (3-2) of 10. As shown in equation (3-1), the state ξ and output v (k) of the dynamic quantizer Q are affected by the parameters A, B, C of the plant P.
　ここでは、動的量子化器の動作が応用される電力パケット伝送システム１０として、図１１に示す回路を想定する。図１１に示す回路では、負荷５０は、コンデンサＣ２と抵抗Ｒ２とを備える。コンデンサＣ２は、電力パケット６０によって伝送された電力を蓄える。抵抗Ｒ２は、電力を消費する。負荷５０の前段には、電力パケット６０を負荷５０へ与える電力ルータ４０が接続されている。電力ルータ４０の前段には、電源２０（Ｖin）が接続されている。電源２０は、一定の電圧Ｅ（例えば、Ｅ＝２０Ｖ）を出力する。 Here, the circuit shown in FIG. 11 is assumed as the power packet transmission system 10 to which the operation of the dynamic quantizer is applied. In the circuit shown in FIG. 11, the load 50 includes a capacitor C 2 and a resistor R 2 . The capacitor C 2 stores the power transmitted by the power packet 60. The resistor R 2 consumes power. A power router 40 that supplies a power packet 60 to the load 50 is connected to the stage before the load 50. A power supply 20 (V in ) is connected to the front stage of the power router 40. The power supply 20 outputs a constant voltage E (for example, E = 20V).
　電力ルータ４０は、１入力１出力であり、パワープロセッシング回路４５を備える。パワープロセッシング回路４５は、蓄電部４６として動作するコンデンサＣ１を備える。コンデンサＣ１よりも入力側（電源２０側）には、第１スイッチＳＷ１が設けられ、コンデンサＣ１よりも、出力側（負荷５０側）には、第２スイッチＳＷ２が設けられている。第１スイッチＳＷ１及び第２スイッチＳＷ２は、それぞれ、ＭＯＳＦＥＴによって構成されている。ＭＯＳＦＥＴそれぞれのＯＮ抵抗は、ｒで表される。なお、第１スイッチＳＷ１よりも入力側には、測定用抵抗Ｒ１が設けられている。 The power router 40 has one input and one output, and includes a power processing circuit 45. The power processing circuit 45 includes a capacitor C 1 that operates as a power storage unit 46. The input side of the capacitor C 1 (power supply 20 side), the first switch SW 1 is provided, than a capacitor C 1, to the output side (load 50 side), a second switch SW 2 is provided .. The first switch SW1 and the second switch SW2 are each composed of MOSFETs. The ON resistance of each MOSFET is represented by r. Incidentally, the first input side of the switch SW 1 is provided with measuring resistor R 1.
　第１スイッチＳＷ１がＯＮになれば、電源２０からコンデンサＣ１側へ電力が供給されるため、第１スイッチＳＷ１のＯＮは、値が「１」である電力パケットの入力に相当する。第１スイッチＳＷ１がＯＦＦになれば、電源２０からコンデンサＣ１側へ電力が供給されなくなるため、値が「０」である電力パケットの入力に相当する。 When the first switch SW 1 is turned on, power is supplied from the power supply 20 to the capacitor C1 side. Therefore, turning on the first switch SW 1 corresponds to the input of a power packet having a value of “1”. When the first switch SW 1 is turned off, power is not supplied from the power supply 20 to the capacitor C1 side, which corresponds to the input of a power packet having a value of “0”.
　第２スイッチＳＷ２がＯＮになれば、ルータ４０から負荷５０へ電力が供給されるため、第２スイッチＳＷ２のＯＮは、値が「１」である電力パケットの出力に相当する。第２スイッチＳＷ２がＯＦＦになれば、ルータ４０から負荷５０へ電力が供給されなくなるため、値が「０」である電力パケットの出力に相当する。 When the second switch SW 2 is turned on, power is supplied from the router 40 to the load 50. Therefore, turning on the second switch SW 2 corresponds to the output of a power packet having a value of “1”. When the second switch SW 2 is turned off, power is not supplied from the router 40 to the load 50, which corresponds to the output of a power packet having a value of “0”.
　コンデンサＣ１の電圧をＶ１、コンデンサＣ２の電圧をＶ２とすると、図１１に示す回路の状態方程式は、図１１に示される式のとおりである。式（４－１－１）は、時刻ｔにおいて入力が「１」であるときに「１」を出力する場合（Ｔｈｒｏｕｇｈ演算）における蓄電部電圧Ｖ１を示す。式（４－１－２）は、時刻ｔにおいて入力が「１」であるときに「１」を出力する場合（Ｔｈｒｏｕｇｈ演算）における負荷電圧Ｖ２を示す。以下では、式（４－１－１）及び式（４－１－２）の演算を、Ｐ11と表す。 Assuming that the voltage of the capacitor C 1 is V 1 and the voltage of the capacitor C 2 is V 2 , the equation of state of the circuit shown in FIG. 11 is as shown in FIG. Equation (4-1-1) shows the storage voltage V 1 in the case where “1” is output when the input is “1” at time t (Through calculation). Equation (4-1-2) shows the load voltage V 2 when "1" is output when the input is "1" at time t (Through calculation). In the following, the operations of equations (4-1-1) and equations (4-1-2) are referred to as P 11 .
　式（４－２－１）は、時刻ｔにおいて入力が「１」であるときに「０」を出力する場合（ＮＯＴ演算）における蓄電部電圧Ｖ１を示す。式（４－２－２）は、時刻ｔにおいて入力が「１」であるときに「０」を出力する場合（ＮＯＴ演算）における負荷電圧Ｖ２を示す。以下では、式（４－２－１）及び式（４－２－２）の演算を、Ｐ10と表す。 Equation (4-2-1) shows the power storage voltage V 1 when "0" is output when the input is "1" at time t (NOT calculation). Equation (4-2-2) shows the load voltage V 2 when "0" is output when the input is "1" at time t (NOT calculation). In the following, the operation of Equation (4-2-1) and (4-2-2), represented as P 10.
　式（５－１－１）は、時刻ｔにおいて入力が「０」であるときに「０」を出力する場合（Ｔｈｒｏｕｇｈ演算）における蓄電部電圧Ｖ１を示す。式（５－１－２）は、時刻ｔにおいて入力が「０」であるときに「０」を出力する場合（Ｔｈｒｏｕｇｈ演算）における負荷電圧Ｖ２を示す。以下では、式（５－１－１）及び式（５－１－２）の演算を、Ｐ00と表す。 Equation (5-1-1) shows the power storage voltage V 1 when "0" is output when the input is "0" at time t (Through calculation). Equation (5-1-2) shows the load voltage V 2 when "0" is output when the input is "0" at time t (Through calculation). In the following, the operations of equations (5-1-1) and equations (5-1-2) are referred to as P 00 .
　式（５－２－１）は、時刻ｔにおいて入力が「０」であるときに「１」を出力する場合（ＮＯＴ演算）における蓄電部電圧Ｖ１を示す。式（５－２－２）は、時刻ｔにおいて入力が「０」であるときに「１」を出力する場合（ＮＯＴ演算）における負荷電圧Ｖ２を示す。以下では、式（５－１－１）及び式（５－２－２）の演算を、Ｐ01と表す。 Equation (5-2-1) shows the power storage voltage V 1 when "1" is output when the input is "0" at time t (NOT calculation). Equation (5-2-2) shows the load voltage V 2 when "1" is output when the input is "0" at time t (NOT calculation). In the following, the operations of equations (5-1-1) and equations (5-2-2) are referred to as P 01 .
　図１２に示すように、状態ξ（ｔ）＝［Ｖ１（ｔ），Ｖ２（ｔ）］Ｔとおき、離散化する。さらに、ξ（ｔ＋１）＝Ａijξ（ｔ）＋ＢijＥを満たすパラメータＡ，Ｂを設定する。ここで、ｉは入力の論理値を示し，ｊは出力の論理値を示す。 As shown in FIG. 12, the state ξ (t) = [V 1 (t), V 2 (t)] T is set and discretized. Further, parameters A and B satisfying ξ (t + 1) = A ij ξ (t) + B ij E are set. Here, i indicates the logical value of the input, and j indicates the logical value of the output.
　入力が「１」である場合、及び、入力が「０」である場合それぞれについて、図１２に示す式に従って、状態の誤差ξeが算出される。ここで、ξl（ｔ）を理想的な状態と、ξrを実際の状態とする。状態の誤差ξeは、実際の状態ξrと理想的な状態ξlとの差によって表される。 For each case where the input is "1" and the input is "0", the state error ξ e is calculated according to the equation shown in FIG. Here, let ξ l (t) be the ideal state and let ξ r be the actual state. The state error ξ e is represented by the difference between the actual state ξ r and the ideal state ξ l.
　入力ｉが「１」の場合の誤差は、図１２に示す式（６－１）（６－２）（６－３）に従って計算される。式（６－１）（６－２）（６－３）は、出力ｊが「０」及び「１」の場合それぞれについて適用される。つまり、入力ｉが「１」であるときに出力ｊが「０」であるときの誤差ξe10と、入力ｉが「１」であるときに出力ｊが「１」であるときの誤差ξe11と、が計算される。 The error when the input i is "1" is calculated according to the equations (6-1), (6-2), and (6-3) shown in FIG. Equations (6-1), (6-2), and (6-3) are applied when the output j is "0" and "1", respectively. That is, the error xi] e10 when output j when the input i is "1" is "0", error in the output j when the input i is "1" is "1" xi] e11 And are calculated.
　入力ｉが「０」の場合の誤差は、式（７－１）（７－２）（７－３）に従って計算される。式（７－１）（７－２）（７－３）は、出力ｊが「０」及び「１」の場合それぞれについて適用される。つまり、入力ｉが「０」であるときに出力ｊが「０」であるときの誤差ξe00と、入力ｉが「０」であるときに出力ｊが「１」であるときの誤差ξe01と、が計算される。 The error when the input i is "0" is calculated according to the equations (7-1), (7-2), and (7-3). Equations (7-1), (7-2), and (7-3) are applied when the output j is "0" and "1", respectively. That is, the error xi] e00 when output j when the input i is "0" is "0", error in the output j when the input i is "0" is "1" xi] e01 And are calculated.
　そして、次の時刻ｔ＋１における出力誤差（ここでは、負荷電圧Ｖ２の誤差Ｖ２e）が、最小化されるように、演算が選択される。この演算の選択は、図９に示すステップＳ１１の処理に相当する。図１３の上側図は、ステップＳ１１における演算の選択の仕方を、状態の誤差ξeを用いて表している。ξの定義及びＣ＝［０，１］より、図１３の上側図は、図１３の下側図のように書き換えられる。コントローラ４１は、図１３に従って、誤差が小さくなる演算を選択する。 Then, the calculation is selected so that the output error at the next time t + 1 (here, the error V 2e of the load voltage V 2) is minimized. The selection of this operation corresponds to the process of step S11 shown in FIG. The upper view of FIG. 13 shows how to select the operation in step S11 by using the state error ξ e. From the definition of ξ and C = [0,1], the upper view of FIG. 13 is rewritten as the lower view of FIG. The controller 41 selects an operation that reduces the error according to FIG.
　ここで、図１３におけるＶ2e10は、入力ｉが「１」であるときに出力ｊが「０」である場合の負荷電圧誤差を示す。Ｖ2e11は、入力ｉが「１」であるときに出力ｊが「１」である場合の負荷電圧誤差を示す。Ｖ2e01は、入力ｉが「０」であるときに出力ｊが「１」である場合の負荷電圧誤差を示す。Ｖ2e00は、入力ｉが「０」であるときに出力ｊが「０」である場合の負荷電圧誤差を示す。 Here, V 2e10 in FIG. 13 indicates a load voltage error when the output j is “0” when the input i is “1”. V 2e 11 indicates a load voltage error when the output j is “1” when the input i is “1”. V 2e01 indicates a load voltage error when the output j is “1” when the input i is “0”. V 2e00 indicates a load voltage error when the output j is “0” when the input i is “0”.
　図１３におけるＤ10は、図９のステップＳ１１４における選択Ｄ10に対応する。図１３におけるＤ11は、図９のステップＳ１１５における選択Ｄ11に対応する。図１３におけるＤ01は、図９のステップＳ１１８における選択Ｄ01に対応する。図１３におけるＤ00は、図９のステップＳ１１９における選択Ｄ00に対応する。 D 10 in FIG. 13 corresponds to selection D 10 in step S114 of FIG. D 11 in FIG. 13 corresponds to selection D 11 in step S115 of FIG. D 01 in FIG. 13 corresponds to the selection D 01 in step S118 of FIG. D 00 in FIG. 13 corresponds to the selection D 00 in step S119 of FIG.
　コントローラは、状態の誤差ξeを計算するため、ルータ出力側（負荷５０）の回路モデル４３のパラメータと、ルータ４０のパワープロセッシング回路４５の回路モデル４２のパラメータを有している（図３参照）。ある値の電力パケット要求があった場合における理想的な状態ξl及び実際の状態ξrは、回路モデル４２，４３が既知であれば、ルータ４０に与えられる入力電力の値（入力電力パケット６０が有する電力の値）に基づいて計算できる。ルータ４０に与えられる入力の値は、論理値として与えられても良いし、アナログ値として与えられてもよい。ルータ４０は、ルータ４０に与えられる入力電力の値を、ルータ４０の入力側装置（例えば、電源２０）から取得してもよいし、ルータ４０において測定することにより取得してもよい。 The controller has parameters of the circuit model 43 on the router output side (load 50) and parameters of the circuit model 42 of the power processing circuit 45 of the router 40 in order to calculate the state error ξ e (see FIG. 3). ). The ideal state ξ l and the actual state ξ r when there is a power packet request of a certain value are the values of the input power given to the router 40 (input power packet 60) if the circuit models 42 and 43 are known. It can be calculated based on the value of the electric power that the router has. The value of the input given to the router 40 may be given as a logical value or as an analog value. The router 40 may acquire the value of the input power given to the router 40 from the input side device (for example, the power supply 20) of the router 40, or may acquire the value by measuring at the router 40.
　なお、誤差ξeの計算に用いられる蓄電部電圧（蓄電部に蓄えられたエネルギー値）Ｖ１は、ルータ４０に与えられる入力電力の値がわかれば、計算によって求めることができる。ただし、コントローラ４１は、蓄電部電圧（蓄電部に蓄えられたエネルギー値）Ｖ１を計測する計測部４６Ａ（図３参照）から、電圧Ｖ１を取得し、取得した電圧Ｖ１を誤差ξeの計算に用いてもよい。この場合、電圧Ｖ１を計測することで、電圧Ｖ１を計算で求める場合に比べて、電圧Ｖ１の計算誤差を抑えることができる。 Incidentally, the error ξ electricity storage unit voltage (energy value stored in the power storage unit) used in the calculation of e V 1 is, knowing the value of the input power supplied to the router 40 can be obtained by calculation. However, the controller 41 acquires the voltage V 1 from the measuring unit 46A (see FIG. 3) that measures the power storage unit voltage (energy value stored in the power storage unit) V 1, and sets the acquired voltage V 1 as an error ξ e. It may be used for the calculation of. In this case, by measuring the voltages V 1, as compared with the case of obtaining the voltages V 1 in the calculation, it is possible to suppress the calculation error of the voltages V 1.
［１．３．評価］ [1.3. Evaluation]
　図１４から図１７は、実施形態に係る伝送制御処理（図９参照）を評価した結果を示す。評価には、図１１に示す回路を用い、時間枠ｔの時間長を４００μｓとし、電源電圧Ｅを２０Ｖとした。また、図１１に示す回路において、ＭＯＳＦＥＴのＯＮ抵抗ｒを２２ｍΩとし、測定用抵抗Ｒ１を１．５ｋΩとし、ルータ４０内コンデンサＣ１を４７００μＦとし、負荷コンデンサＣ２を４７００μＦとし、負荷抵抗Ｒ２を１０Ωとした。状態ξの初期状態ξ（０）＝［１８　１５］Ｔとした。また、各時間枠ｔにおいて、ルータ４０への入力は、負荷５０からの要求とは無関係にランダムに与えられるものとし、ルータ４０への入力が「１」となる確率（伝送確率）をｐとする。評価では、ｐを１／２，１／３，１／４に変化させた。 14 to 17 show the results of evaluating the transmission control process (see FIG. 9) according to the embodiment. For the evaluation, the circuit shown in FIG. 11 was used, the time length of the time frame t was 400 μs, and the power supply voltage E was 20 V. Further, in the circuit shown in FIG. 11, the ON resistance r of the MOSFET is 22 mΩ, the measurement resistance R 1 is 1.5 kΩ, the capacitor C 1 in the router 40 is 4700 μF, the load capacitor C 2 is 4700 μF, and the load resistance R 2 was set to 10Ω. The initial state ξ (0) = [18 15] T of the state ξ was set. Further, in each time frame t, the input to the router 40 is randomly given regardless of the request from the load 50, and the probability (transmission probability) that the input to the router 40 becomes "1" is defined as p. To do. In the evaluation, p was changed to 1/2, 1/3, 1/4.
　図１４において、「demand」は、負荷５０がルータ４０へ要求した電力パケット系列（要求パケット系列）を示している。図１４に示す要求パケット系列では、「１」と「０」とが交互に発生している。 In FIG. 14, “demand” indicates a power packet sequence (request packet sequence) requested by the load 50 to the router 40. In the request packet sequence shown in FIG. 14, "1" and "0" are alternately generated.
　図１４において、「input」は、ルータ４０へ入力された電力パケット系列（入力パケット系列）を示している。図１４に示す入力パケット系列は、要求パケット系列とは一致せず、「１」と「０」とがランダムに生じている。 In FIG. 14, “input” indicates a power packet sequence (input packet sequence) input to the router 40. The input packet sequence shown in FIG. 14 does not match the request packet sequence, and "1" and "0" are randomly generated.
　図１４において、「modified output」は、実施形態に係る伝送制御処理によって決定された出力電力パケット系列を示している。図１４に示す出力電力パケット系列は、要求パケット系列から一部修正されている。図１４に示す出力電力パケット系列において、要求パケット系列と一致する部分は、Ｔｈｒｏｕｇｈ演算が選択されており、図１４に示す出力電力パケット系列において、要求パケット系列と一致しない部分は、ＮＯＴ演算が選択されていることを示す。 In FIG. 14, “modified output” indicates an output power packet sequence determined by the transmission control process according to the embodiment. The output power packet sequence shown in FIG. 14 is partially modified from the request packet sequence. In the output power packet sequence shown in FIG. 14, the Through operation is selected for the portion that matches the request packet sequence, and in the output power packet sequence shown in FIG. 14, the NOT operation is selected for the portion that does not match the request packet sequence. Indicates that it has been done.
　図１５は、負荷電圧（ルータ４０の出力電圧）Ｖ２の変化を示している。図１５において、「Ideal」は、理想的な電圧Ｖ２lの変化を示す。「Without algorithm」は、負荷５０の要求論理値とおりにルータ４０の出力を決定する方法を示す。「With algorithm」は、実施形態に係る伝送制御処理（図９参照）に従ってルータ４０の出力を決定する方法を示す。図１５によれば、「With algorithm」の方が、理想に近いことがわかる。 FIG. 15 shows a change in the load voltage (output voltage of the router 40) V 2. In FIG. 15, “Ideal” indicates a change in the ideal voltage V 2l. The “Without algorithm” shows a method of determining the output of the router 40 according to the required logical value of the load 50. “With algorithm” indicates a method of determining the output of the router 40 according to the transmission control process (see FIG. 9) according to the embodiment. According to FIG. 15, it can be seen that the “With algorithm” is closer to the ideal.
　図１６は、理想的な電圧に対する実際の電圧の誤差Ｖ２eを示している。図１６によれば「With algorithm」の方が、誤差Ｖ２eが小さいことがわかる。 FIG. 16 shows the error V 2e of the actual voltage with respect to the ideal voltage. According to FIG. 16, it can be seen that the error V 2e is smaller in the “With algorithm”.
　図１７は、伝送確率と平均誤差の差との関係を示している。ここでは、実施形態に係る伝送制御処理の適用の有無による平均誤差の差を、図１７に示すように設定した。平均誤差の差は、大きいほど、実施形態に係る伝送制御処理が有用であることを示す。図１７は、伝送確率ｐを、１／２，１／３，１／４とした場合それぞれについて、０．２ｓの時点で計算される平均誤差の差を示している。図１７によれば、電力パケットの伝送確率、つまり、「１」が入力される確率が低いほど、実施形態に係る伝送制御処理が有効であることがわかる。 FIG. 17 shows the relationship between the transmission probability and the difference in the average error. Here, the difference in the average error depending on whether or not the transmission control process according to the embodiment is applied is set as shown in FIG. The larger the difference in the average error, the more useful the transmission control process according to the embodiment. FIG. 17 shows the difference in the average error calculated at 0.2 s when the transmission probability p is set to 1/2, 1/3, 1/4, respectively. According to FIG. 17, it can be seen that the lower the transmission probability of the power packet, that is, the probability that "1" is input, the more effective the transmission control process according to the embodiment.
＜２．第２の開示＞ <2. Second disclosure>
　第２の開示は、電力の演算に関する。第２の開示は、例えば、電力演算装置、電力伝送システム、及び電力パケットのデータ構造に関する。第２の開示は、２０１８年５月１４日出願の日本出願第２０１８－０９２６６８号及び２０１９年５月１０日出願の国際出願ＰＣＴ／ＪＰ２０１９／０１８８２９に記載された全ての記載内容を援用する。 The second disclosure relates to power calculation. The second disclosure relates to, for example, power arithmetic units, power transmission systems, and data structures of power packets. The second disclosure incorporates all the statements contained in Japanese Application No. 2018-092668 filed May 14, 2018 and International Application PCT / JP2019 / 018829 filed May 10, 2019.
＜２．１　第２の開示の背景技術＞ <2.1 Background technology of the second disclosure>
　前述の特許文献１及び特許文献２は、電力パケットが伝送される電力伝送システムを開示している。電力パケットは、伝送される電力がパルス化されたペイロードと、ヘッダなどの情報タグと、を備えている。 The above-mentioned Patent Document 1 and Patent Document 2 disclose a power transmission system in which a power packet is transmitted. The power packet includes a payload in which the transmitted power is pulsed and an information tag such as a header.
＜２．２　第２の開示の概要＞ <2.2 Outline of the second disclosure>
　電力パケットのように電力をパルス化することで、電力を離散化して伝送することができる。電力が離散化されていることで、電力の伝送量をパケット又はパルスの個数又は密度として考えることができる。 By pulsed power like a power packet, power can be discreteized and transmitted. Since the power is discretized, the amount of power transmitted can be considered as the number or density of packets or pulses.
　第２の開示は、上述の電力の離散化した伝送という特徴を生かすべく、離散化電力を演算するという概念を提示する。 The second disclosure presents the concept of calculating discretized power in order to take advantage of the above-mentioned feature of discretized power transmission.
　第２の開示の第１の側面は、電力演算装置である。電力演算装置は、パルス化された入力電力に対する演算をする。電力演算装置は、入力電力を蓄える蓄電部と、入力電力に対する演算結果に相当する出力電力を前記蓄電部から出力する演算処理を実行する処理回路と、を備える。 The first aspect of the second disclosure is the power arithmetic unit. The power arithmetic unit performs an operation on the pulsed input power. The power calculation device includes a power storage unit that stores input power, and a processing circuit that executes calculation processing that outputs output power corresponding to a calculation result for the input power from the power storage unit.
　第２の開示の他の側面は、電力伝送システムである。電力伝送システムは、前記電力演算装置を備える。 Another aspect of the second disclosure is the power transmission system. The power transmission system includes the power arithmetic unit.
　第２の開示のさらに他の側面は、電力パケットのデータ構造である。データ構造は、伝送される電力を有するペイロードと、前記演算処理に関する制御に用いる演算情報と、を備える。演算情報は、電力演算装置に用いられる。 Yet another aspect of the second disclosure is the data structure of the power packet. The data structure includes a payload having electric power to be transmitted and arithmetic information used for controlling the arithmetic processing. The calculation information is used in the power calculation device.
　更なる詳細は、後述される。 Further details will be described later.
＜２．３　第２の開示を実施するための形態＞ <2.3 Form for implementing the second disclosure>
＜２．３．１　電力演算装置、電力伝送システム、電力パケットのデータ構造の概要＞ <2.3.1 Outline of data structure of power arithmetic unit, power transmission system, and power packet>
　（１）実施形態に係る電力演算装置は、パルス化された第１入力電力に対する演算をする。電力演算装置は、前記第１入力電力を蓄える蓄電部を備える。蓄電部は、例えば、キャパシタである。電力演算装置は、前記第１入力電力に対する演算結果に相当する出力電力を前記蓄電部から出力する演算処理を実行する処理回路を備える。処理回路の出力電力は、入力電力に対する演算結果となっているため、電力の演算が実現される。なお、ここでの電力の演算は、演算結果が物理的な電力量として反映されるものであり、演算結果が論理的な値にすぎない一般的な信号演算とは異なる。なお、蓄電部は、信号演算において、信号を記憶するメモリに相当する要素として機能する。 (1) The power calculation device according to the embodiment calculates the pulsed first input power. The power arithmetic unit includes a power storage unit that stores the first input power. The power storage unit is, for example, a capacitor. The power calculation device includes a processing circuit that executes a calculation process for outputting an output power corresponding to a calculation result for the first input power from the power storage unit. Since the output power of the processing circuit is the calculation result for the input power, the power calculation is realized. The power calculation here reflects the calculation result as a physical electric energy, and is different from the general signal calculation in which the calculation result is only a logical value. The power storage unit functions as an element corresponding to a memory for storing signals in signal calculation.
　電力演算装置は、特許文献１又は２に記載の電力ルータに組み込まれていてもよいし、電力ルータとは別の装置として、電力伝送システム中に設けられていてもよい。電力演算装置が、電力ルータに組み込まれていると、ルータ内部の演算処理で、電力パケットの電力を変化させることができる。 The power arithmetic unit may be incorporated in the power router described in Patent Document 1 or 2, or may be provided in the power transmission system as a device separate from the power router. When the power arithmetic unit is incorporated in the power router, the power of the power packet can be changed by the arithmetic processing inside the router.
　（２）前記処理回路は、複数の種別の演算処理を実行可能なスイッチ回路として構成されてもよい。複数の種別の演算処理を実行可能であることで、汎用性が高まる。また、多数の処理回路を集積化することで、電力演算集積回路を実現できる。 (2) The processing circuit may be configured as a switch circuit capable of executing a plurality of types of arithmetic processing. Being able to execute multiple types of arithmetic processing enhances versatility. Further, by integrating a large number of processing circuits, a power calculation integrated circuit can be realized.
　（３）前記電力演算装置は、選択された種別の演算処理が実行されるように前記処理回路を制御するコントローラを更に備えることができる。コントローラが、処理回路を制御することで、同一の処理回路に様々な種別の演算処理を実行させることができる。すなわち、書き換え可能な処理回路が実現される。 (3) The power arithmetic unit can further include a controller that controls the processing circuit so that the arithmetic processing of the selected type is executed. By controlling the processing circuit, the controller can cause the same processing circuit to execute various types of arithmetic processing. That is, a rewritable processing circuit is realized.
　（４）パルス化された電力は、電力パケットに含まれていてもよい。すなわち、前記第１入力電力は、第１入力電力パケットに含まれていてもよい。電力パケットは、例えば、ペイロードにおいて電力を有することができる。 (4) The pulsed power may be included in the power packet. That is, the first input power may be included in the first input power packet. The power packet can have power in the payload, for example.
　前記第１入力電力パケットは、前記コントローラにおいて、前記演算処理に関する制御に用いられる演算情報を含むことができる。この場合、電力パケットの演算情報によって、演算処理を制御することができる。 The first input power packet can include arithmetic information used for controlling the arithmetic processing in the controller. In this case, the arithmetic processing can be controlled by the arithmetic information of the power packet.
（５）前記演算情報は、前記演算処理の種別を示す演算種別情報を有することができる。前記コントローラは、前記処理回路にて実行される演算処理として、前記演算種別情報が示す演算処理を選択することができる。この場合、演算種別情報によって、処理回路にて実行される演算処理の種別を制御することができる。 (5) The calculation information may include calculation type information indicating the type of the calculation process. The controller can select the arithmetic processing indicated by the arithmetic type information as the arithmetic processing executed by the processing circuit. In this case, the type of arithmetic processing executed in the processing circuit can be controlled by the arithmetic type information.
（６）前記演算情報は、第２入力電力を有する第２入力電力パケットの識別情報を有することができる。前記出力電力は、前記第１入力電力と、前記識別情報によって識別される前記第２入力電力パケットの前記第２入力電力と、に対する演算結果に相当する電力であってもよい。すなわち、前記コントローラは、前記第１入力電力と、前記識別情報によって識別される前記第２入力電力パケットの前記第２入力電力と、に対する演算結果に相当する出力電力を前記蓄電部から出力する演算処理を実行することができる。 (6) The calculation information may include identification information of a second input power packet having a second input power. The output power may be power corresponding to a calculation result for the first input power and the second input power of the second input power packet identified by the identification information. That is, the controller outputs an output power corresponding to a calculation result for the first input power and the second input power of the second input power packet identified by the identification information from the power storage unit. The process can be executed.
（７）前記コントローラは、前記演算処理の実行の可否を判定するよう構成されていてもよい。この場合、コントローラは、電力演算装置が、電力パケットを受け入れて、演算処理を実行するか否かを選択することができる。 (7) The controller may be configured to determine whether or not the arithmetic processing can be executed. In this case, the controller can select whether or not the power arithmetic unit accepts the power packet and executes the arithmetic processing.
　前記演算処理の実行の可否の判定は、前記蓄電部の電圧及び演算対象となる入力電力パケットの入力電力に基づいて行われるのが好ましい。 It is preferable that the determination as to whether or not the calculation process can be executed is performed based on the voltage of the power storage unit and the input power of the input power packet to be calculated.
　前記演算処理の実行の可否の判定は、さらに、前記演算処理の種別に基づいて行われるのが好ましい。 It is preferable that the determination as to whether or not the arithmetic processing can be executed is further performed based on the type of the arithmetic processing.
（８）前記演算処理の実行の可否の判定は、前記蓄電部の電圧を所望の電圧にするために行われるのが好ましい。 (8) It is preferable that the determination as to whether or not the arithmetic processing can be executed is performed in order to make the voltage of the power storage unit a desired voltage.
（９）前記処理回路は、前記蓄電部へ電力を蓄える入力状態及び前記出力電力を前記蓄電部から出力する出力状態を含む複数の状態に切り替え可能に構成されているのが好ましい。前記複数の状態は、前記蓄電部へ前記入力電力を蓄えることと前記出力電力を前記蓄電部から出力することが同時に行われる入出力状態を更に含んでもよい。前記複数の状態は、前記蓄電部へ前記入力電力を蓄えることも前記出力電力を前記蓄電部から出力することも行わない非演算状態を更に含んでもよい。 (9) It is preferable that the processing circuit is configured to be switchable to a plurality of states including an input state for storing electric power in the power storage unit and an output state for outputting the output power from the power storage unit. The plurality of states may further include an input / output state in which the input power is stored in the power storage unit and the output power is output from the power storage unit at the same time. The plurality of states may further include a non-calculation state in which the input power is neither stored in the power storage unit nor the output power is output from the power storage unit.
（１０）前記出力電力を有する出力電力パケットを生成するパケット生成部を更に備えることができる。この場合、出力電力を有する電力パケットを生成でき、出力電力の伝送が可能となる。 (10) A packet generation unit that generates an output power packet having the output power can be further provided. In this case, a power packet having output power can be generated, and output power can be transmitted.
（１１）実施形態に係る電力伝送システムは、（１）から（１０）のいずれか１項に記載の電力演算装置を備えることができる。 (11) The power transmission system according to the embodiment may include the power calculation device according to any one of (1) to (10).
（１２）実施形態に係る電力パケットのデータ構造は、伝送される電力を有するペイロードと、ペイロードが有する電力に対する演算結果に相当する電力を出力する演算処理を実行する電力演算装置が、前記演算処理に関する制御に用いる演算情報と、を備える。 (12) The data structure of the power packet according to the embodiment is such that the power calculation device that executes the calculation process for outputting the payload having the power to be transmitted and the power corresponding to the calculation result for the power included in the payload performs the calculation process. It is provided with arithmetic information used for controlling the above.
　前記演算情報は、前記演算処理の種別を示す演算種別情報を有することができる。前記演算種別情報は、前記電力演算装置が、前記演算処理の種別を選択するために用いられる。 The calculation information can have calculation type information indicating the type of the calculation process. The calculation type information is used by the power calculation device to select the type of the calculation process.
　前記演算情報は、演算対象となる電力パケットの識別情報を有することができる。前記識別情報は、前記電力演算装置が、前記演算処理の対象となる電力パケットを識別するために用いられる。 The calculation information can include identification information of a power packet to be calculated. The identification information is used by the power arithmetic unit to identify a power packet to be subjected to the arithmetic processing.
＜２．３．２　電力演算装置、電力伝送システム、電力パケットのデータ構造の例＞ <2.3.2 Example of data structure of power arithmetic unit, power transmission system, power packet>
　図１８は、電力伝送システム１０を示している。システム１０は、電源２０から負荷５０へ電力を電力パケット６０によって伝送するネットワークである。電源２０は、例えば、発電設備又は電池である。実施形態において、電源２０は、直流電源である。 FIG. 18 shows the power transmission system 10. The system 10 is a network that transmits electric power from the power source 20 to the load 50 by the electric power packet 60. The power source 20 is, for example, a power generation facility or a battery. In the embodiment, the power supply 20 is a DC power supply.
　システム１０は、ミキサ３０を備える。ミキサ３０は、電源２０から供給される電力から、電力パケット６０を生成する。図１８に示す電力パケット６０は、パルス化された電力を有するペイロード６２と、ヘッダ６１及びフッタ６３からなる情報タグと、を備えている。ミキサ３０が生成した電力パケット６０は、システム１０内のルータ４０へ送信される。 System 10 includes a mixer 30. The mixer 30 generates a power packet 60 from the power supplied from the power source 20. The power packet 60 shown in FIG. 18 includes a payload 62 having pulsed power and an information tag including a header 61 and a footer 63. The power packet 60 generated by the mixer 30 is transmitted to the router 40 in the system 10.
　図１８に示すように、ミキサ３０は、コントローラ３１と、ゲートドライバ３２と、スイッチ回路３３と、を備えている。図示のスイッチ回路３３は、２入力１出力回路である。スイッチ回路３３の２入力には、それぞれ、電源２０，２０が接続されている。スイッチ回路３３は、２つの電源２０，２０のいずれか一方から電力パケット６０を生成し、出力することができる。 As shown in FIG. 18, the mixer 30 includes a controller 31, a gate driver 32, and a switch circuit 33. The switch circuit 33 shown is a 2-input 1-output circuit. Power supplies 20 and 20 are connected to the two inputs of the switch circuit 33, respectively. The switch circuit 33 can generate and output a power packet 60 from any one of the two power supplies 20 and 20.
　スイッチ回路３３は、入力と出力との間に設けられたスイッチ素子３０１，３０５を備えている。スイッチ素子３０１，３０５のＯＮ／ＯＦＦ切り替えにより、図１８に示す電力パケット６０が生成される。各スイッチ素子３０１，３０５と出力との間には、ダイオード３０３，３０７が設けられている。ダイオード３０３，３０７は、入力側から出力側へ向かう方向の電流を許容し、逆方向への電流を阻止する。なお、スイッチ素子３０１，３０５と、ダイオード３０３，３０７との間には、一端がグランドに接続された抵抗３０２，３０６の他端が接続されている。 The switch circuit 33 includes switch elements 301 and 305 provided between the input and the output. The power packet 60 shown in FIG. 18 is generated by switching ON / OFF of the switch elements 301 and 305. Diodes 303 and 307 are provided between the switch elements 301 and 305 and the output. The diodes 303 and 307 allow a current in the direction from the input side to the output side and block the current in the opposite direction. The other ends of the resistors 302 and 306, one end of which is connected to the ground, are connected between the switch elements 301 and 305 and the diodes 303 and 307.
　コントローラ３１は、スイッチ素子３０１，３０５のスイッチング制御のための制御信号を、ゲートドライバ３２に与える。ゲートドライバ３２は、制御信号に従って、スイッチ素子３０１，３０５のＯＮ／ＯＦＦを制御するゲート電圧を出力する。スイッチ素子３０１がＯＮ／ＯＦＦ制御されると、スイッチ素子３０１に接続された電源２０からの電力により電力パケットが生成され、出力される。また、スイッチ素子３０５がＯＮ／ＯＦＦ制御されると、スイッチ素子３０５に接続された電源２０からの電力により電力パケットが生成され、出力される。 The controller 31 gives a control signal for switching control of the switch elements 301 and 305 to the gate driver 32. The gate driver 32 outputs a gate voltage that controls ON / OFF of the switch elements 301 and 305 according to the control signal. When the switch element 301 is ON / OFF controlled, a power packet is generated and output by the power from the power source 20 connected to the switch element 301. Further, when the switch element 305 is ON / OFF controlled, a power packet is generated and output by the power from the power source 20 connected to the switch element 305.
　システム１０は、ルータ４０を備える。電力パケット６０は、ルータ４０を介して、ネットワーク内で転送され、負荷へ到達する。ルータ４０は、ネットワーク内で、電力パケット６０を中継する。ルータ４０は、電力パケット６０を転送するルートを決定するルーティングを行う。実施形態のルータ４０は、電力演算装置として機能する。ルータ４０は、入力された電力パケットの電力に対する演算を行い、演算結果に相当する電力を有する電力パケットを出力することができる。 The system 10 includes a router 40. The power packet 60 is forwarded in the network via the router 40 to reach the load. The router 40 relays the power packet 60 in the network. The router 40 performs routing that determines a route for forwarding the power packet 60. The router 40 of the embodiment functions as a power arithmetic unit. The router 40 can perform an operation on the power of the input power packet and output a power packet having a power corresponding to the operation result.
　図１９Ａに示すように、ルータ４０は、コントローラ４１と、ゲートドライバ４２と、スイッチ回路４３と、アイソレータ４４と、を備えている。図示のスイッチ回路４３は、２入力２出力回路である。スイッチ回路４３は、入力された電力パケットをいずれの出力から送出するかを選択することができる。出力の選択により、電力パケットのルーティングが行われる。 As shown in FIG. 19A, the router 40 includes a controller 41, a gate driver 42, a switch circuit 43, and an isolator 44. The switch circuit 43 shown is a 2-input 2-output circuit. The switch circuit 43 can select from which output the input power packet is transmitted. The output selection routes the power packets.
　図示のスイッチ回路４３は、２つの電力演算部４５０Ａ、４５０Ｂを備える。電力演算部４５０Ａ，４５０Ｂは、それぞれ、処理回路４５１と蓄電部４５２とを備える。実施形態の蓄電部４５２は、キャパシタによって構成されている。蓄電部は、応答が早いストレージ素子であってもよい。 The illustrated switch circuit 43 includes two power calculation units 450A and 450B. The power calculation units 450A and 450B each include a processing circuit 451 and a power storage unit 452, respectively. The power storage unit 452 of the embodiment is composed of a capacitor. The power storage unit may be a storage element having a quick response.
　スイッチ回路４３の各入力には、それぞれ、２つのスイッチ素子が接続されている。例えば、第１の入力には、スイッチ素子４０１及びスイッチ素子４０２が並列に接続されている。スイッチ素子４０１がＯＮになると、第１の入力は、電力演算部４５０Ｂに接続される。スイッチ素子４０２がＯＮになると、第１の入力は、電力演算部４５０Ａに接続される。また、第２の入力には、スイッチ素子４０３及びスイッチ素子４０４が並列に接続されている。スイッチ素子４０３がＯＮになると、第２の入力は、電力演算部４５０Ｂに接続される。スイッチ素子４０４がＯＮになると、第２の入力は、電力演算部４５０Ａに接続される。 Two switch elements are connected to each input of the switch circuit 43. For example, the switch element 401 and the switch element 402 are connected in parallel to the first input. When the switch element 401 is turned on, the first input is connected to the power calculation unit 450B. When the switch element 402 is turned on, the first input is connected to the power calculation unit 450A. Further, the switch element 403 and the switch element 404 are connected in parallel to the second input. When the switch element 403 is turned on, the second input is connected to the power calculation unit 450B. When the switch element 404 is turned on, the second input is connected to the power calculation unit 450A.
　各スイッチ素子４０１，４０２，４０３，４０４と電力演算部４５０Ａ，４５０Ｂとの間には、ダイオード４０５，４０６，４０７，４０８が設けられている。ダイオード４０５，４０６，４０７，４０８は、入力側から電力演算部４５０Ａ，４５０Ｂへ向かう方向の電流を許容し、逆方向への電流を阻止する。 Diodes 405, 406, 407, and 408 are provided between the switch elements 401, 402, 403, and 404 and the power calculation units 450A and 450B. The diodes 405, 406, 407, and 408 allow the current in the direction from the input side toward the power calculation units 450A and 450B, and block the current in the opposite direction.
　電力演算部４５０Ａ，４５０Ｂの各出力には、それぞれ、２つのスイッチ素子が接続されている。例えば、電力演算部４５０Ａの出力には、スイッチ素子４１１及びスイッチ素子４１２が並列に接続されている。スイッチ素子４１１がＯＮになると、電力演算部４５０Ａの出力は、第２の出力に接続される。スイッチ素子４１２がＯＮになると、電力演算部４５０Ａの出力は、第１の出力に接続される。また、電力演算部４５０Ｂの出力には、スイッチ素子４１３及びスイッチ素子４１４が並列に接続されている。スイッチ素子４１３がＯＮになると、電力演算部４５０Ｂの出力は、第２の出力に接続される。スイッチ素子４０４がＯＮになると、電力演算部４５０Ｂの出力は、第１の出力に接続される。 Two switch elements are connected to the outputs of the power calculation units 450A and 450B, respectively. For example, the switch element 411 and the switch element 412 are connected in parallel to the output of the power calculation unit 450A. When the switch element 411 is turned on, the output of the power calculation unit 450A is connected to the second output. When the switch element 412 is turned on, the output of the power calculation unit 450A is connected to the first output. Further, a switch element 413 and a switch element 414 are connected in parallel to the output of the power calculation unit 450B. When the switch element 413 is turned on, the output of the power calculation unit 450B is connected to the second output. When the switch element 404 is turned on, the output of the power calculation unit 450B is connected to the first output.
　各スイッチ素子４１１，４１２，４１３，４１４と出力との間には、ダイオード４１５，４１６，４１７，４１８が設けられている。ダイオード４１５，４１６，４１７，４１８は、電力演算部４５０Ａ，４５０Ｂから出力へ向かう方向の電流を許容し、逆方向への電流を阻止する。 Diodes 415, 416, 417, 418 are provided between each switch element 411, 421, 413, 414 and the output. The diodes 415, 416, 417, 418 allow the current in the direction from the power calculation units 450A, 450B to the output, and block the current in the opposite direction.
　図２０は、電力演算部４５０Ａ，４５０Ｂの回路図である。電力演算部は、処理回路４５１は、蓄電部４５２への充放電を制御するスイッチ回路である。図２０の処理回路４５１は、３つのスイッチ素子５０１，５０２，５０３を備える。また、処理回路４５１は、意図されている方向にだけ電流を流すためのダイオード５１１，５１２，５１３，５１４が設けられている。さらに、処理回路４５１の入力（図２０の処理回路４５１の左端）とダイオード５１１との間には、一端がグランドに接続された抵抗５０５の他端が接続されている。 FIG. 20 is a circuit diagram of the power calculation units 450A and 450B. In the power calculation unit, the processing circuit 451 is a switch circuit that controls charging / discharging to the power storage unit 452. The processing circuit 451 of FIG. 20 includes three switch elements 501, 502, and 503. Further, the processing circuit 451 is provided with diodes 511, 512, 513, 514 for allowing current to flow only in an intended direction. Further, the other end of the resistor 505, one end of which is connected to the ground, is connected between the input of the processing circuit 451 (the left end of the processing circuit 451 of FIG. 20) and the diode 511.
　図２１Ａは、３つのスイッチ素子５０１，５０２，５０３がすべてＯＦＦである状態を示している。図２１Ａの状態において、処理回路４５１の入力に電力パケットが与えられたとしても、処理回路４５１は、電力パケットを受け付けない。図２１Ａの状態は、非演算状態である。非演算状態では、入力された電力を蓄電部４５２へ蓄えることは行われず、処理回路４５１からの電力の出力も行われない。 FIG. 21A shows a state in which all three switch elements 501, 502, and 503 are OFF. In the state of FIG. 21A, even if a power packet is given to the input of the processing circuit 451, the processing circuit 451 does not accept the power packet. The state of FIG. 21A is a non-calculation state. In the non-calculation state, the input power is not stored in the power storage unit 452, and the power is not output from the processing circuit 451.
　図２１Ｂは、スイッチ素子５０１がＯＮであり、スイッチ素子５０２，５０３がＯＦＦである状態を示している。図２１Ｂの状態は、電力の入力状態（蓄電状態）である。入力状態では、処理回路４５１の入力に与えられた電力が、蓄電部４５２に蓄えられる。 FIG. 21B shows a state in which the switch element 501 is ON and the switch elements 502 and 503 are OFF. The state of FIG. 21B is a power input state (storage state). In the input state, the electric power given to the input of the processing circuit 451 is stored in the power storage unit 452.
　図２１Ｃは、スイッチ素子５０１，５０２，５０３がすべてＯＮである状態を示している。図２１Ｃの状態は、電力の入出力状態（蓄電・放電状態）である。入出力状態では、処理回路４５１に与えられた電力が、蓄電部４５２に蓄えられるとともに、蓄電部４５２に蓄えられた電力を処理回路４５１から出力することができる。 FIG. 21C shows a state in which the switch elements 501, 502, and 503 are all ON. The state of FIG. 21C is a power input / output state (storage / discharge state). In the input / output state, the electric power given to the processing circuit 451 is stored in the power storage unit 452, and the electric power stored in the power storage unit 452 can be output from the processing circuit 451.
　図２１Ｄは、スイッチ素子５０２，５０３がＯＮであり、スイッチ素子５０１がＯＦＦである状態を示している。図２１Ｄの状態は、電力の出力状態（放電状態）である。出力状態では、蓄電部４５２に蓄えられた電力を処理回路４５１から出力することができる。 FIG. 21D shows a state in which the switch elements 502 and 503 are ON and the switch element 501 is OFF. The state of FIG. 21D is a power output state (discharge state). In the output state, the electric power stored in the power storage unit 452 can be output from the processing circuit 451.
　図２Ａに戻り、コントローラ４１は、スイッチ回路４３に含まれるスイッチ素子のスイッチング制御のための制御信号を、ゲートドライバ４２に与える。ゲートドライバ４２は、制御信号に従って、スイッチ回路４３に含まれるスイッチ素子のＯＮ／ＯＦＦを制御するゲート電圧を出力する。 Returning to FIG. 2A, the controller 41 gives the gate driver 42 a control signal for switching control of the switch element included in the switch circuit 43. The gate driver 42 outputs a gate voltage that controls ON / OFF of the switch element included in the switch circuit 43 according to the control signal.
　コントローラ４１が、スイッチ素子４０１，４０２，４０３，４０４のＯＮ／ＯＦＦ制御をすることにより、入力された電力パケットの電力を、複数の電力演算部４５０Ａ，４５０Ｂのいずれに与えるかが選択される。また、スイッチ素子４１１，４１２，４１３，４１４のＯＮ／ＯＦＦ制御により、いずれの電力演算部４５０Ａ，４５０Ｂから出力された電力から生成される電力パケットを、スイッチ回路４３（ルータ４０）の２出力のうちのいずれから出力するかが選択される。 When the controller 41 controls ON / OFF of the switch elements 401, 402, 403, 404, it is selected which of the plurality of power calculation units 450A and 450B is given the power of the input power packet. Further, by ON / OFF control of the switch elements 411, 421, 413 and 414, the power packet generated from the power output from any of the power calculation units 450A and 450B is sent to the two outputs of the switch circuit 43 (router 40). Which of them is output is selected.
　スイッチ素子４１１，４１２，４１３，４１４は、電力演算部４５０Ａ，４５０Ｂから出力された電力から、ヘッダ６１及びフッタ６３を有する電力パケット６０を生成するパケット生成部を構成している。スイッチ素子４１１，４１２，４１３，４１４のＯＮ／ＯＦＦにより、ヘッダ６１及びフッタ６３を構成するパルスが生成される。 The switch elements 411, 421, 413, 414 constitute a packet generation unit that generates a power packet 60 having a header 61 and a footer 63 from the power output from the power calculation units 450A and 450B. By turning ON / OFF the switch elements 411, 421, 413 and 414, the pulses constituting the header 61 and the footer 63 are generated.
　コントローラ４１が、スイッチ素子５０１，５０２，５０３のＯＮ／ＯＦＦ制御をすることにより、処理回路４５１の状態は、非演算状態、入力状態、入出力状態、及び出力状態のいずれかに一つに選択的に切り替えられる。処理回路４５１の状態の切り替えにより所望の演算処理が実行される。演算処理の詳細は、後述する。 The controller 41 controls ON / OFF of the switch elements 501, 502, and 503, so that the state of the processing circuit 451 is selected as one of a non-calculation state, an input state, an input / output state, and an output state. Can be switched. The desired arithmetic processing is executed by switching the state of the processing circuit 451. The details of the arithmetic processing will be described later.
　図２２は、実施形態に係るパケット６０のヘッダ６１を示している。ヘッダ６１は、アイソレータ４４を介して、コントローラ４１により読み取られる。ヘッダ６１は、パケットＩＤ６０１が格納される領域を有している。パケットＩＤ６０１は、パケットの識別子である。ヘッダ６１は、演算情報６０２が格納される領域を有している。演算情報６０２は、コントローラ４１において、電力の演算処理に関する制御に用いられる。 FIG. 22 shows the header 61 of the packet 60 according to the embodiment. The header 61 is read by the controller 41 via the isolator 44. The header 61 has an area in which the packet ID 601 is stored. The packet ID 601 is an identifier of the packet. The header 61 has an area in which the calculation information 602 is stored. The calculation information 602 is used in the controller 41 for controlling the power calculation processing.
　演算情報６０２は、演算種別情報６１１を有する。演算種別情報６１１は、電力演算部４５０Ａ，４５０Ｂで行われる演算処理の種別を示す。演算処理は、論理演算であってもよいし、四則演算処理であってもよい。論理演算は、例えば、ＡＮＤ演算、ＯＲ演算、ＮＯＴ演算、ＸＯＲ演算、ＮＯＲ演算、及びＮＡＮＤ演算を含む。四則演算は、例えば、加算（ＡＤＤ）及び減算（ＳＵＢ）を含む。演算種別情報６１１は、これらの演算のうち、どの種別の演算が、電力パケットに対して行われるかを示す。 The calculation information 602 has the calculation type information 611. The calculation type information 611 indicates the type of calculation processing performed by the power calculation units 450A and 450B. The arithmetic processing may be a logical operation or a four arithmetic operation. Logical operations include, for example, AND operations, OR operations, NOT operations, XOR operations, NOR operations, and NAND operations. The four arithmetic operations include, for example, addition (ADD) and subtraction (SUB). The operation type information 611 indicates which type of operation among these operations is performed on the power packet.
　演算情報６０２は、演算対象識別情報６１２を有する。演算対象識別情報６１２は、演算処理の演算対象となる電力パケットのＩＤ６０１を示す。演算対象識別情報６１２は、他の電力パケット６０のＩＤ６０１を示す。演算対象識別情報６１２は、自パケット６０のＩＤ６０１を示してもよい。演算対象識別情報６１２は、複数のパケット６０のＩＤ６０１を含むことができる。 The calculation information 602 has the calculation target identification information 612. The calculation target identification information 612 indicates the ID 601 of the power packet to be calculated by the calculation process. The calculation target identification information 612 indicates the ID 601 of the other power packet 60. The calculation target identification information 612 may indicate the ID 601 of the own packet 60. The calculation target identification information 612 can include ID 601 of a plurality of packets 60.
　ヘッダ６１は、アドレス情報６０３が格納される領域を有している。アドレス情報６０３は、ルータ４０におけるルーティングに用いられる。アドレス情報６０３は、送信元アドレス６２１及び送信先アドレス６２２を有する。 The header 61 has an area in which the address information 603 is stored. The address information 603 is used for routing in the router 40. The address information 603 has a source address 621 and a destination address 622.
　図２３は、コントローラ４１によって実行される処理を示している。コントローラ４１によって実行される処理は、演算種別識別処理７０１を含む。演算種別識別処理７０１では、電力パケット６０に含まれる演算種別情報６１１が読み取られ、電力パケット６０に対する演算種別が識別される。図２３において、ＩＤ６０１がＡである電力パケット６０及びＩＤ６０１がＢである電力パケット６０の演算種別情報６１１は、演算種別として「ＡＮＤ」を示している。したがって、演算種別識別処理７０１では、演算種別として「ＡＮＤ」が識別される。 FIG. 23 shows the process executed by the controller 41. The process executed by the controller 41 includes the operation type identification process 701. In the calculation type identification process 701, the calculation type information 611 included in the power packet 60 is read, and the calculation type for the power packet 60 is identified. In FIG. 23, the calculation type information 611 of the power packet 60 in which the ID 601 is A and the power packet 60 in which the ID 601 is B indicates “AND” as the calculation type. Therefore, in the operation type identification process 701, "AND" is identified as the operation type.
　コントローラ４１によって実行される処理は、演算対象識別処理７０２を含む。演算対象識別処理７０２では、電力パケット６０に含まれる演算対象識別情報６１２が読み取られ、演算の対象となる電力パケット６０が識別される。図２３において、ＩＤ６０１がＡである電力パケット６０の演算対象識別情報６１２は、演算対象のＩＤとして、Ｂを示している。また、ＩＤ６０１がＢである電力パケット６０の演算対象識別情報６１２は、演算対象のＩＤとして、Ａを示している。したがって、コントローラ４１は、演算種別「ＡＮＤ」の演算対象として、ＩＤがＡの電力パケット６０と、ＩＤがＢの電力パケット６０とを識別する。 The process executed by the controller 41 includes the calculation target identification process 702. In the calculation target identification process 702, the calculation target identification information 612 included in the power packet 60 is read, and the power packet 60 to be calculated is identified. In FIG. 23, the calculation target identification information 612 of the power packet 60 whose ID 601 is A indicates B as the calculation target ID. Further, the calculation target identification information 612 of the power packet 60 in which the ID 601 is B indicates A as the calculation target ID. Therefore, the controller 41 identifies the power packet 60 having the ID A and the power packet 60 having the ID B as the calculation target of the calculation type “AND”.
　コントローラ４１によって実行される処理は、演算対象の電力を検出する処理７０３を含む。検出処理７０３では、例えば、演算対象の電力量又は電力量が示す論理値が検出される。演算対象の電力量は、例えば、コントローラ４１が、アイソレータ４４を介して、ペイロード６２の時間長さ、又は電圧値を測定することで、検出される。演算対象の電力量は、ヘッダ６１に格納された電力情報（図示省略）を読み取ることによって検出されてもよい。演算対象の電力量が示す論理値は、例えば、ペイロード６２の電圧値を識別することで、検出される。例えば、ペイロード６２圧値が、閾値よりも高ければ（Ｈｉｇｈレベルである場合）、論理値“１”が検出され、閾値よりも低ければ（Ｌｏｗレベルである場合）、論理値“０”が検出される。電力量が示す論理値は、ヘッダ６１に格納された電力情報（図示省略）を読み取ることによって検出されてもよい。 The process executed by the controller 41 includes the process 703 for detecting the power to be calculated. In the detection process 703, for example, the electric energy to be calculated or the logical value indicated by the electric energy is detected. The electric energy to be calculated is detected, for example, by the controller 41 measuring the time length of the payload 62 or the voltage value via the isolator 44. The electric energy to be calculated may be detected by reading the electric power information (not shown) stored in the header 61. The logical value indicated by the electric energy to be calculated is detected, for example, by identifying the voltage value of the payload 62. For example, if the payload 62 pressure value is higher than the threshold value (high level), the logical value “1” is detected, and if it is lower than the threshold value (low level), the logical value “0” is detected. Will be done. The logical value indicated by the electric energy may be detected by reading the electric power information (not shown) stored in the header 61.
　コントローラ４１によって実行される処理は、演算制御処理７０４を含む。演算制御処理７０４では、演算対象の電力パケット６０が有する電力に対する演算結果に相当する電力を処理回路４５１から出力させる演算処理を処理回路４５１に実行させるように、処理回路４５１を制御する。例えば、ＩＤがＡの電力パケット６０が有する電力量が示す論理値がＰ１であり、ＩＤがＢの電力パケット６０が有する電力量が示す論理値がＰ２である場合、Ｐ１　ＡＮＤ　Ｐ２の演算結果に相当する電力が、処理回路４５１から出力される。例えば、Ｐ１　ＡＮＤ　Ｐ２が、１であれば、Ｈｉｇｈレベルの電圧が処理回路４５１から出力され、Ｐ１　ＡＮＤ　Ｐ２が、０であれば、Ｌｏｗレベルの電圧が処理回路４５１から出力される。なお、ＡＮＤ演算及びその他の演算における、処理回路４５１の動作の詳細については後述する。 The process executed by the controller 41 includes the arithmetic control process 704. In the arithmetic control process 704, the processing circuit 451 is controlled so that the processing circuit 451 executes an arithmetic processing for outputting the electric power corresponding to the arithmetic result with respect to the electric power of the electric power packet 60 to be calculated from the processing circuit 451. For example, when the logical value indicated by the electric energy of the power packet 60 having the ID A is P1 and the logical value indicated by the electric energy of the electric energy packet 60 having the ID B is P2, the calculation result of P1 AND P2 Corresponding power is output from the processing circuit 451. For example, if P1 AND P2 is 1, a high level voltage is output from the processing circuit 451 and if P1 AND P2 is 0, a low level voltage is output from the processing circuit 451. The details of the operation of the processing circuit 451 in the AND operation and other operations will be described later.
　コントローラ４１によって実行される処理は、パケット生成処理７０５を含む。パケット生成処理７０５では、スイッチ素子４１１，４１２，４１３，４１４が制御され、処理回路４５１から出力された電力（演算結果に相当する電力）をペイロード６２に有する電力パケット６０（図２３において、ＩＤ６０１がＣである電力パケット）を生成する。生成された電力パケット６０は、ルータ４０から出力される。 The process executed by the controller 41 includes the packet generation process 705. In the packet generation process 705, the switch elements 411, 421, 413, 414 are controlled, and the power packet 60 having the power output from the processing circuit 451 (power corresponding to the calculation result) in the payload 62 (ID 601 in FIG. 23). Power packet that is C) is generated. The generated power packet 60 is output from the router 40.
　以下、演算処理の例として、論理演算であるＡＮＤ演算、ＯＲ演算、ＮＯＴ演算、ＸＯＲ演算、ＮＯＲ演算、及びＮＡＮＤ演算について説明する。ここでは、電力パケットの時間長を一定とする。電力パケットの長さをｔとし、その長さｔを、各電力パケットの時間枠とよぶ。ある時間枠の電圧がＨｉｇｈレベルであれば、“１”、Ｌｏｗレベルであれば“０”と論理を定義する。“１”と“０”の割り当て方法を、図２４Ａに示す。ここでは、連続する２つの電力パケットｆ，ｂを一つのペアとみなす。ここでの論理演算は、これら連続した２個の電力パケットｆ，ｂを入力として定義される。図２４Ａの例では、“１０”が入力された後に、“１１”が入力されている。入力に対する演算結果は、電力パケットｂの時間枠に出力されるものとする。 Hereinafter, as an example of arithmetic processing, AND operation, OR operation, NOT operation, XOR operation, NOR operation, and NAND operation, which are logical operations, will be described. Here, the time length of the power packet is constant. The length of the power packet is t, and the length t is called the time frame of each power packet. The logic is defined as "1" if the voltage in a certain time frame is at the High level and "0" if it is at the Low level. The method of assigning “1” and “0” is shown in FIG. 24A. Here, two consecutive power packets f and b are regarded as one pair. The logical operation here is defined by taking these two consecutive power packets f and b as inputs. In the example of FIG. 24A, "11" is input after "10" is input. It is assumed that the calculation result for the input is output in the time frame of the power packet b.
　また、以下の説明では、簡単のために、ヘッダ６１及びフッタ６３からなる情報タグは０ビットとし、ペイロード６２のみが存在するものとする。ここでは、電力パケットｆ，ｂそれぞれの長さｔを０．０５秒とし、論理演算を行うクロック周期Ｔを０．１秒とした。処理回路４５１の入力に与えられる電圧は、１０Ｖの直流電圧とし、蓄電部４５２の初期電圧を８．０Ｖとした。各時間枠における入力電力パケットの論理値は、０又は１からそれぞれ１／２の確率で選択される。 Further, in the following description, for the sake of simplicity, it is assumed that the information tag consisting of the header 61 and the footer 63 has 0 bits, and only the payload 62 exists. Here, the length t of each of the power packets f and b is set to 0.05 seconds, and the clock period T for performing the logical operation is set to 0.1 seconds. The voltage applied to the input of the processing circuit 451 was a DC voltage of 10 V, and the initial voltage of the power storage unit 452 was 8.0 V. The logical value of the input power packet in each time frame is selected from 0 or 1 with a probability of 1/2.
　図２４Ｂは、ＡＮＤの真理値表を示している。ＡＮＤ演算の場合、図２４Ｂに示すように、入力電力パケットｆ，ｂが“１１”の場合、ｂの時間枠において１が出力され、それ以外の場合には、０が出力される。 FIG. 24B shows the truth table of AND. In the case of the AND operation, as shown in FIG. 24B, when the input power packets f and b are "11", 1 is output in the time frame of b, and 0 is output in other cases.
　ＡＮＤ演算の演算処理アルゴリズムは、以下のとおりである。 The arithmetic processing algorithm for AND arithmetic is as follows.
　初期状態において、処理回路４５１のスイッチ素子５０１，５０２，５０３はすべて開かれている。そして、電力パケットｆ，ｂの論理値が識別される。電力パケットｆの時間枠において、電力パケットｆの論理値が“１”であることが検出されると、処理回路４５１のスイッチ素子５０１が閉じられ、電力パケットｆの電力が蓄電部４５２に蓄えられる入力状態となる（図２１Ｂ参照）。 In the initial state, all the switch elements 501, 502, and 503 of the processing circuit 451 are open. Then, the logical values of the power packets f and b are identified. When it is detected that the logical value of the power packet f is "1" in the time frame of the power packet f, the switch element 501 of the processing circuit 451 is closed, and the power of the power packet f is stored in the power storage unit 452. It is in the input state (see FIG. 21B).
　電力パケットｆの論理値が“０”であることが検出された場合、処理回路４５１のスイッチ素子５０１，５０２，５０３はすべて開かれたままである（図２１Ａ参照）。 When it is detected that the logical value of the power packet f is "0", all the switch elements 501, 502, and 503 of the processing circuit 451 remain open (see FIG. 21A).
　電力パケットｆの論理値が“１”である場合に、電力パケットｂの時間枠において電力パケットｂの論理値が“１”であることが検出されると、処理回路４５１のすべてのスイッチ素子５０１，５０２，５０２が閉じられ、入出力状態となる（図２１Ｃ参照）。この入出力状態においては、電力パケットｂの電力が、蓄電部４５２に蓄えられつつ、蓄電部４５２の電力が出力される。 When the logical value of the power packet f is "1" and it is detected that the logical value of the power packet b is "1" in the time frame of the power packet b, all the switch elements 501 of the processing circuit 451 , 502, 502 are closed and the input / output state is set (see FIG. 21C). In this input / output state, the electric power of the electric power packet b is stored in the electric power storage unit 452, and the electric power of the electric power storage unit 452 is output.
　電力パケットｆの論理値が“０”である場合に、電力パケットｂの時間枠において電力パケットｂの論理値が“１”であることが検出されると、処理回路４５１のスイッチ素子５０１が閉じられ、電力パケットｂの電力が蓄電部４５２に蓄えられる入力状態となる（図２１Ｂ参照）。 When the logical value of the power packet f is "0" and it is detected that the logical value of the power packet b is "1" in the time frame of the power packet b, the switch element 501 of the processing circuit 451 closes. Then, the power of the power packet b is stored in the power storage unit 452 (see FIG. 21B).
　電力パケットｂの時間枠において電力パケットｂの論理値が“０”であることが検出された場合、処理回路４５１のスイッチ素子５０１，５０２，５０３はすべて開かれる（図２１Ａ参照）。 When it is detected that the logical value of the power packet b is "0" in the time frame of the power packet b, all the switch elements 501, 502, and 503 of the processing circuit 451 are opened (see FIG. 21A).
　図２５Ａ、図２５Ｂ、図２６Ａ及び図２６Ｂは、以上のＡＮＤの演算処理アルゴリズムを図２０の電力演算部において実行したシミュレーション結果を示している。図２５Ａは、入力電力パケットｆ，ｂのペアを１０個示している。図２５Ｂは、出力電力パケットの電圧を示し、図２６Ａは、出力電流を示している。図２５Ｂの出力は、図２４Ｂの真理値表に従った演算結果に相当する電圧を示しているため、正しい結果であると言える。 25A, 25B, 26A and 26B show the simulation results of executing the above AND arithmetic processing algorithm in the power arithmetic unit of FIG. FIG. 25A shows 10 pairs of input power packets f and b. FIG. 25B shows the voltage of the output power packet and FIG. 26A shows the output current. It can be said that the output of FIG. 25B is a correct result because it shows a voltage corresponding to the calculation result according to the truth table of FIG. 24B.
　図２６Ｂは、蓄電部４５２の電圧を示している。“１０”入力の場合には、電力パケットｆの電力が、蓄電部４５２に蓄積されるため、蓄電部４５２の電圧が上昇する。“１１”入力の場合、電力パケットｆの電力が、蓄電部４５２に蓄積されて、蓄電部４５２の電圧が上昇し、電力パケットｂの電力は、蓄電部４５２への蓄積と、電力出力に用いられる。“０１”入力の場合、電力パケットｂの電力が、蓄電部４５２に蓄積されて、蓄電部４５２の電圧が上昇する。以上より、ＡＮＤ演算が正しく実行されていることがわかる。 FIG. 26B shows the voltage of the power storage unit 452. In the case of "10" input, the power of the power packet f is stored in the power storage unit 452, so that the voltage of the power storage unit 452 rises. In the case of "11" input, the power of the power packet f is stored in the power storage unit 452, the voltage of the power storage unit 452 rises, and the power of the power packet b is used for storage in the power storage unit 452 and power output. Be done. In the case of "01" input, the power of the power packet b is stored in the power storage unit 452, and the voltage of the power storage unit 452 rises. From the above, it can be seen that the AND operation is executed correctly.
　図２７Ａ及び図２７Ｂは、ＡＮＤ演算の実験結果を示している。実験では、ペイロード６２にヘッダ６１が付加されたパケット６０を演算対象とした。ヘッダ６１は、演算種別情報６１１を有する。演算種別情報６１１は、演算の種別を示す。実験において、ペイロード６１は、第１ペイロード部ｆ及び第２ペイロード部ｂを有する。実験では、第１ペイロード部ｆ及び第２ペイロード部ｂに対して、演算種別情報６１１が示す演算が行われる。ここでは、演算種別情報６１１は、ＡＮＤ演算を示す。したがって、図２０の電力演算部で実行される演算処理アルゴリズムは、ＡＮＤ演算に設定される。なお、実験では、図２２に示すパケットＩＤ６０１、演算対象情報６１２及びアドレス情報６０３は省略した。 27A and 27B show the experimental results of the AND operation. In the experiment, the packet 60 in which the header 61 is added to the payload 62 was used as the calculation target. The header 61 has calculation type information 611. The calculation type information 611 indicates the type of calculation. In the experiment, the payload 61 has a first payload section f and a second payload section b. In the experiment, the calculation indicated by the calculation type information 611 is performed on the first payload section f and the second payload section b. Here, the operation type information 611 indicates an AND operation. Therefore, the arithmetic processing algorithm executed by the power arithmetic unit of FIG. 20 is set to the AND operation. In the experiment, the packet ID 601 shown in FIG. 22, the calculation target information 612, and the address information 603 were omitted.
　図２７Ａでは、電力演算部に入力されるパケットの第１ペイロード部ｆ及び第２ペイロード部ｂのペアが４個示されているとともに、電力演算部から出力されるパケットの第１ペイロード部ｆ及び第２ペイロード部ｂのペアも４個示されている。図２７Ｂは、出力電流Ｉoutを示している。図２７Ａ及び図２７Ｂの出力（OUTPUT）も、シミュレーション結果と同様に図２４Ｂの真理値表に従った演算結果に相当する電圧及び電流を示している。 In FIG. 27A, four pairs of the first payload section f and the second payload section b of the packet input to the power calculation section are shown, and the first payload section f and the packet output from the power calculation section are shown. Four pairs of second payload parts b are also shown. FIG. 27B shows the output current Iout. The outputs (OUTPUTs) of FIGS. 27A and 27B also show the voltage and current corresponding to the calculation results according to the truth table of FIG. 24B as well as the simulation results.
　図２８は、ＯＲ演算の真理値表Ｔ１、ＮＯＴ演算の真理値表Ｔ２、ＥＸＯＲ演算の真理値表Ｔ３、ＮＯＲ演算の真理値表Ｔ４、ＮＡＮＤ演算の真理値表Ｔ５を示している。 FIG. 28 shows a truth table T1 for OR operation, a truth table T2 for NOT operation, a truth table T3 for EXOR operation, a truth table T4 for NOR operation, and a truth table T5 for NAND operation.
　ＯＲ演算の演算処理アルゴリズムは、以下のとおりである。 The arithmetic processing algorithm for OR arithmetic is as follows.
　初期状態において、処理回路４５１のスイッチ素子５０１，５０２，５０３はすべて開かれている。そして、電力パケットｆ，ｂの論理値が識別される。電力パケットｆの時間枠において、電力パケットｆの論理値が“１”であることが検出されると、処理回路４５１のスイッチ素子５０１が閉じられ、電力パケットｆの電力が蓄電部４５２に蓄えられる入力状態となる（図２１Ｂ参照）。 In the initial state, all the switch elements 501, 502, and 503 of the processing circuit 451 are open. Then, the logical values of the power packets f and b are identified. When it is detected that the logical value of the power packet f is "1" in the time frame of the power packet f, the switch element 501 of the processing circuit 451 is closed, and the power of the power packet f is stored in the power storage unit 452. It is in the input state (see FIG. 21B).
　電力パケットｆの論理値が“０”であることが検出された場合、処理回路４５１のスイッチ素子５０１，５０２，５０３はすべて開かれたままである（図２１Ａ参照）。 When it is detected that the logical value of the power packet f is "0", all the switch elements 501, 502, and 503 of the processing circuit 451 remain open (see FIG. 21A).
　電力パケットｂの時間枠において電力パケットｂの論理値が“１”であることが検出されると、処理回路４５１のすべてのスイッチ素子５０１，５０２，５０３が閉じられ、入出力状態となる（図２１Ｃ参照）。この入出力状態においては、電力パケットｂの電力が、蓄電部４５２に蓄えられつつ、蓄電部４５２の電力が出力される。 When it is detected that the logical value of the power packet b is "1" in the time frame of the power packet b, all the switch elements 501, 502, 503 of the processing circuit 451 are closed, and the input / output state is entered (FIG. FIG. See 21C). In this input / output state, the electric power of the electric power packet b is stored in the electric power storage unit 452, and the electric power of the electric power storage unit 452 is output.
　電力パケットｆの論理値が“１”である場合に、電力パケットｂの時間枠において電力パケットｂの論理値が“０”であることが検出されると、処理回路４５１のスイッチ素子５０２，５０３が閉じられ、蓄電部４５２の電力が、出力される出力状態となる（図２１Ｄ参照）。 When the logical value of the power packet f is "1" and it is detected that the logical value of the power packet b is "0" in the time frame of the power packet b, the switch elements 502 and 503 of the processing circuit 451 are detected. Is closed, and the power of the power storage unit 452 is output (see FIG. 21D).
　電力パケットｆの論理値が“０”である場合に、電力パケットｂの時間枠において電力パケットｂの論理値が“０”であることが検出されると、処理回路４５１のスイッチ素子５０１，５０２，５０３はすべて開かれたままである（図２１Ａ参照）。 When the logical value of the power packet f is "0" and it is detected that the logical value of the power packet b is "0" in the time frame of the power packet b, the switch elements 501 and 502 of the processing circuit 451 , 503 all remain open (see Figure 21A).
　ＮＯＴ演算の演算処理アルゴリズムは、以下のとおりである。ＮＯＴ演算は、一つの電力パケットの電力に対する演算であるため、ここでは、電力パケットｂに対するＮＯＴ演算のアルゴリズムを説明する。 The operation processing algorithm of NOT operation is as follows. Since the NOT operation is an operation on the power of one power packet, the algorithm of the NOT operation on the power packet b will be described here.
　まず、電力パケットｂの論理値が識別される。電力パケットｂの時間枠において、電力パケットｂの論理値が“０”であることが検出されると、処理回路４５１のスイッチ素子５０２，５０３が閉じられ、蓄電部４５２の電力が、出力される出力状態となる（図２１Ｄ参照）。 First, the logical value of the power packet b is identified. When it is detected that the logical value of the power packet b is "0" in the time frame of the power packet b, the switch elements 502 and 503 of the processing circuit 451 are closed, and the power of the power storage unit 452 is output. It is in the output state (see FIG. 21D).
　電力パケットｂの時間枠において、電力パケットｆの論理値が“１”であることが検出されると、処理回路４５１のスイッチ素子５０１が閉じられ、電力パケットｆの電力が蓄電部４５２に蓄えられる入力状態となる（図２１Ｂ参照）。 When it is detected that the logical value of the power packet f is "1" in the time frame of the power packet b, the switch element 501 of the processing circuit 451 is closed, and the power of the power packet f is stored in the power storage unit 452. It is in the input state (see FIG. 21B).
　ＥＸＯＲ演算の演算処理アルゴリズムは、以下のとおりである。 The arithmetic processing algorithm of the EXOR operation is as follows.
　初期状態において、処理回路４５１のスイッチ素子５０１，５０２，５０３はすべて開かれている。そして、電力パケットｆ，ｂの論理値が識別される。電力パケットｆの時間枠において、電力パケットｆの論理値が“１”であることが検出されると、処理回路４５１のスイッチ素子５０１が閉じられ、電力パケットｆの電力が蓄電部４５２に蓄えられる入力状態となる（図２１Ｂ参照）。 In the initial state, all the switch elements 501, 502, and 503 of the processing circuit 451 are open. Then, the logical values of the power packets f and b are identified. When it is detected that the logical value of the power packet f is "1" in the time frame of the power packet f, the switch element 501 of the processing circuit 451 is closed, and the power of the power packet f is stored in the power storage unit 452. It is in the input state (see FIG. 21B).
　電力パケットｆの論理値が“０”であることが検出された場合、処理回路４５１のスイッチ素子５０１，５０２，５０３はすべて開かれたままである（図２１Ａ参照）。 When it is detected that the logical value of the power packet f is "0", all the switch elements 501, 502, and 503 of the processing circuit 451 remain open (see FIG. 21A).
　電力パケットｆの論理値が“０”である場合に、電力パケットｂの時間枠において電力パケットｂの論理値が“１”であることが検出されると、処理回路４５１のすべてのスイッチ素子５０１，５０２，５０３が閉じられ、入出力状態となる（図２１Ｃ参照）。この入出力状態においては、電力パケットｂの電力が、蓄電部４５２に蓄えられつつ、蓄電部４５２の電力が出力される。 When the logical value of the power packet f is "0" and it is detected that the logical value of the power packet b is "1" in the time frame of the power packet b, all the switch elements 501 of the processing circuit 451 , 502, 503 are closed and the input / output state is set (see FIG. 21C). In this input / output state, the electric power of the electric power packet b is stored in the electric power storage unit 452, and the electric power of the electric power storage unit 452 is output.
　電力パケットｆの論理値が“１”である場合に、電力パケットｂの時間枠において電力パケットｂの論理値が“１”であることが検出されると、処理回路４５１のスイッチ素子５０１が閉じられ、電力パケットｆの電力が蓄電部４５２に蓄えられる入力状態となる（図２１Ｂ参照）。 When the logical value of the power packet f is "1" and it is detected that the logical value of the power packet b is "1" in the time frame of the power packet b, the switch element 501 of the processing circuit 451 closes. Then, the power of the power packet f is stored in the power storage unit 452 (see FIG. 21B).
　電力パケットｆの論理値が“１”である場合に、電力パケットｂの時間枠において電力パケットｂの論理値が“０”であることが検出されると、処理回路４５１のスイッチ素子５０２，５０３が閉じられ、蓄電部４５２の電力が、出力される出力状態となる（図２１Ｄ参照）。 When the logical value of the power packet f is "1" and it is detected that the logical value of the power packet b is "0" in the time frame of the power packet b, the switch elements 502 and 503 of the processing circuit 451 are detected. Is closed, and the power of the power storage unit 452 is output (see FIG. 21D).
　ＮＯＲ演算の演算処理アルゴリズムは、以下のとおりである。 The arithmetic processing algorithm of NOR operation is as follows.
　初期状態において、処理回路４５１のスイッチ素子５０１，５０２，５０３はすべて開かれている。そして、電力パケットｆ，ｂの論理値が識別される。電力パケットｆの時間枠において、電力パケットｆの論理値が“１”であることが検出されると、処理回路４５１のスイッチ素子５０１が閉じられ、電力パケットｆの電力が蓄電部４５２に蓄えられる入力状態となる（図２１Ｂ参照）。 In the initial state, all the switch elements 501, 502, and 503 of the processing circuit 451 are open. Then, the logical values of the power packets f and b are identified. When it is detected that the logical value of the power packet f is "1" in the time frame of the power packet f, the switch element 501 of the processing circuit 451 is closed, and the power of the power packet f is stored in the power storage unit 452. It is in the input state (see FIG. 21B).
　電力パケットｆの論理値が“０”であることが検出された場合、処理回路４５１のスイッチ素子５０１，５０２，５０３はすべて開かれたままである（図２１Ａ参照）。 When it is detected that the logical value of the power packet f is "0", all the switch elements 501, 502, and 503 of the processing circuit 451 remain open (see FIG. 21A).
　電力パケットｆの論理値が“０”である場合に、電力パケットｂの時間枠において電力パケットｂの論理値が“０”であることが検出されると、処理回路４５１のスイッチ素子５０２，５０３が閉じられ、蓄電部４５２の電力が、出力される出力状態となる（図２１Ｄ参照）。 When the logical value of the power packet f is "0" and it is detected that the logical value of the power packet b is "0" in the time frame of the power packet b, the switch elements 502 and 503 of the processing circuit 451 are detected. Is closed, and the power of the power storage unit 452 is output (see FIG. 21D).
　電力パケットｂの時間枠において電力パケットｂの論理値が“１”であることが検出されると、処理回路４５１のスイッチ素子５０１が閉じられ、電力パケットｆの電力が蓄電部４５２に蓄えられる入力状態となる（図２１Ｂ参照）。 When it is detected that the logical value of the power packet b is "1" in the time frame of the power packet b, the switch element 501 of the processing circuit 451 is closed, and the power of the power packet f is stored in the power storage unit 452. It becomes a state (see FIG. 21B).
　電力パケットｆの論理値が“１”である場合に、電力パケットｂの時間枠において電力パケットｂの論理値が“０”であることが検出されると、処理回路４５１のスイッチ素子５０１が閉じられ、電力パケットｆの電力が蓄電部４５２に蓄えられる入力状態となる（図２１Ｂ参照）。 When the logical value of the power packet f is "1" and it is detected that the logical value of the power packet b is "0" in the time frame of the power packet b, the switch element 501 of the processing circuit 451 closes. Then, the power of the power packet f is stored in the power storage unit 452 (see FIG. 21B).
　ＮＡＮＤ演算の演算処理アルゴリズムは、以下のとおりである。 The arithmetic processing algorithm for NAND arithmetic is as follows.
　初期状態において、処理回路４５１のスイッチ素子５０１，５０２，５０３はすべて開かれている。そして、電力パケットｆ，ｂの論理値が識別される。電力パケットｆの時間枠において、電力パケットｆの論理値が“１”であることが検出されると、処理回路４５１のスイッチ素子５０１が閉じられ、電力パケットｆの電力が蓄電部４５２に蓄えられる入力状態となる（図２１Ｂ参照）。 In the initial state, all the switch elements 501, 502, and 503 of the processing circuit 451 are open. Then, the logical values of the power packets f and b are identified. When it is detected that the logical value of the power packet f is "1" in the time frame of the power packet f, the switch element 501 of the processing circuit 451 is closed, and the power of the power packet f is stored in the power storage unit 452. It is in the input state (see FIG. 21B).
　電力パケットｆの論理値が“０”であることが検出された場合、処理回路４５１のスイッチ素子５０１，５０２，５０３はすべて開かれたままである（図２１Ａ参照）。 When it is detected that the logical value of the power packet f is "0", all the switch elements 501, 502, and 503 of the processing circuit 451 remain open (see FIG. 21A).
　電力パケットｆの論理値が“０”である場合に、電力パケットｂの時間枠において電力パケットｂの論理値が“０”であることが検出されると、処理回路４５１のスイッチ素子５０２，５０３が閉じられ、蓄電部４５２の電力が、出力される出力状態となる（図２１Ｄ参照）。 When the logical value of the power packet f is "0" and it is detected that the logical value of the power packet b is "0" in the time frame of the power packet b, the switch elements 502 and 503 of the processing circuit 451 are detected. Is closed, and the power of the power storage unit 452 is output (see FIG. 21D).
　電力パケットｆの論理値が“０”である場合に、電力パケットｂの時間枠において電力パケットｂの論理値が“１”であることが検出されると、処理回路４５１のすべてのスイッチ素子５０１，５０２，５０３が閉じられ、入出力状態となる（図２１Ｃ参照）。この入出力状態においては、電力パケットｂの電力が、蓄電部４５２に蓄えられつつ、蓄電部４５２の電力が出力される。 When the logical value of the power packet f is "0" and it is detected that the logical value of the power packet b is "1" in the time frame of the power packet b, all the switch elements 501 of the processing circuit 451 , 502, 503 are closed and the input / output state is set (see FIG. 21C). In this input / output state, the electric power of the electric power packet b is stored in the electric power storage unit 452, and the electric power of the electric power storage unit 452 is output.
　電力パケットｆの論理値が“１”である場合に、電力パケットｂの時間枠において電力パケットｂの論理値が“１”であることが検出されると、処理回路４５１のスイッチ素子５０１が閉じられ、電力パケットｆの電力が蓄電部４５２に蓄えられる入力状態となる（図２１Ｂ参照）。 When the logical value of the power packet f is "1" and it is detected that the logical value of the power packet b is "1" in the time frame of the power packet b, the switch element 501 of the processing circuit 451 closes. Then, the power of the power packet f is stored in the power storage unit 452 (see FIG. 21B).
　電力パケットｆの論理値が“１”である場合に、電力パケットｂの時間枠において電力パケットｂの論理値が“０”であることが検出されると、処理回路４５１のスイッチ素子５０２，５０３が閉じられ、蓄電部４５２の電力が、出力される出力状態となる（図２１Ｄ参照）。 When the logical value of the power packet f is "1" and it is detected that the logical value of the power packet b is "0" in the time frame of the power packet b, the switch elements 502 and 503 of the processing circuit 451 are detected. Is closed, and the power of the power storage unit 452 is output (see FIG. 21D).
　図２９Ａ、図２９Ｂ、図３０Ａ及び図３０Ｂは、ＮＡＮＤの演算処理アルゴリズムを図３の電力演算部において実行したシミュレーション結果を示している。図２９Ａは、入力電力パケットｆ，ｂのペアを１０個示している。図２９Ｂは、出力電力パケットの電圧を示し、図３０Ａは、出力電流を示している。図３０Ｂの出力は、図２８におけるＮＡＮＤの真理値表Ｔ５に従った演算結果に相当する電圧を示しているため、正しい結果であると言える。 29A, 29B, 30A and 30B show the simulation results of executing the NAND arithmetic processing algorithm in the power arithmetic unit of FIG. FIG. 29A shows 10 pairs of input power packets f and b. FIG. 29B shows the voltage of the output power packet and FIG. 30A shows the output current. Since the output of FIG. 30B shows the voltage corresponding to the calculation result according to the NAND truth table T5 in FIG. 28, it can be said that the result is correct.
　図３０Ｂは、ＮＡＮＤ演算実行時の蓄電部４５２の電圧を示している。“１０”入力の場合には、電力パケットｆの時間枠において、蓄電部４５２の電圧が上昇し、電力パケットｂの時間枠において、蓄電部４５２の電圧が減少する。“０１”入力の場合には、電力パケットｂの電力は、蓄電部４５２への蓄積と、電力出力に用いられる。“１１”入力の場合、電力パケットｆ及び電力パケットｂの電力が、蓄電部４５２に蓄積されて、蓄電部４５２の電圧が上昇する。“００”入力の場合、電力パケットｂの時間枠において、出力電力パケットが生成するため、蓄電部４５２の電圧が減少する。以上より、ＮＡＮＤ演算が正しく実行されていることがわかる。 FIG. 30B shows the voltage of the power storage unit 452 when the NAND calculation is executed. In the case of "10" input, the voltage of the power storage unit 452 increases in the time frame of the power packet f, and the voltage of the power storage unit 452 decreases in the time frame of the power packet b. In the case of "01" input, the power of the power packet b is used for storage in the power storage unit 452 and power output. In the case of "11" input, the power of the power packet f and the power packet b is stored in the power storage unit 452, and the voltage of the power storage unit 452 rises. In the case of "00" input, the output power packet is generated in the time frame of the power packet b, so that the voltage of the power storage unit 452 decreases. From the above, it can be seen that the NAND operation is executed correctly.
　図３１Ａ及び図３１Ｂは、ＮＡＮＤ演算の実験結果を示している。ここでは、演算種別情報６１１は、ＮＡＮＤ演算を示す。したがって、図３の電力演算部で実行される演算処理アルゴリズムは、ＡＮＤ演算に設定される。図３１Ａでは、電力演算部に入力されるパケットの第１ペイロード部ｆ及び第２ペイロード部ｂのペアが４個示されているとともに、電力演算部から出力されるパケットの第１ペイロード部ｆ及び第２ペイロード部ｂのペアも４個示されている。図３１Ｂは、出力電流Ｉoutを示している。図３１Ａ及び図３１Ｂの出力（OUTPUT）も、シミュレーション結果と同様に図２８におけるＮＡＮＤの真理値表に従った演算結果に相当する電圧及び電流を示している。 FIGS. 31A and 31B show the experimental results of the NAND operation. Here, the operation type information 611 indicates a NAND operation. Therefore, the arithmetic processing algorithm executed by the power arithmetic unit of FIG. 3 is set to the AND operation. In FIG. 31A, four pairs of the first payload section f and the second payload section b of the packet input to the power calculation section are shown, and the first payload section f and the packet output from the power calculation section are shown. Four pairs of second payload parts b are also shown. FIG. 31B shows the output current Iout. The outputs (OUTPUTs) of FIGS. 31A and 31B also show the voltage and current corresponding to the calculation results according to the NAND truth table in FIG. 28, as in the simulation results.
＜２．３．３　演算による蓄電部の電圧制御＞ <2.3.3 Voltage control of power storage unit by calculation>
　図３２は、コントローラ４１によって実行される処理の他の例を示している。図３２のコントローラ４１は、処理回路４５１に演算処理を実行させることにより、蓄電部４５２の電圧を所望の電圧に制御する。 FIG. 32 shows another example of processing executed by the controller 41. The controller 41 of FIG. 32 controls the voltage of the power storage unit 452 to a desired voltage by causing the processing circuit 451 to execute arithmetic processing.
　前述のように、蓄電部４５２の電圧は、演算によって変化する。例えば、“１０”入力に対してＡＮＤ演算が行われると、蓄電部４５２の電圧が上昇する。また、“００”入力に対してＮＡＮＤ演算が行われると、蓄電部４５２の電圧が減少する。したがって、実行される演算を適切に選択することで、蓄電部４５２の電圧を増減させる制御が可能である。蓄電部４５２の電圧の制御により、電力パケット６０の電圧を所望の電圧にすることができる。例えば、電力パケット６０の電圧を、規定の電圧に保ったり、伝送電力の調整のため、電圧を昇圧したり、降圧したりすることができる。 As described above, the voltage of the power storage unit 452 changes by calculation. For example, when the AND operation is performed on the "10" input, the voltage of the power storage unit 452 rises. Further, when the NAND operation is performed on the "00" input, the voltage of the power storage unit 452 decreases. Therefore, it is possible to control the voltage of the power storage unit 452 to be increased or decreased by appropriately selecting the operation to be executed. By controlling the voltage of the power storage unit 452, the voltage of the power packet 60 can be set to a desired voltage. For example, the voltage of the power packet 60 can be maintained at a specified voltage, or the voltage can be stepped up or down in order to adjust the transmission power.
　実行される演算を適切に選択するには、電力パケット６０に対する演算処理の実行の可否を判定すればよい。例えば、蓄電部４５２の電圧を所望の電圧に維持又は変更できる演算処理については、実行可能と判定し、蓄電部４５２の電圧が所望の電圧から外れる演算処理については、実行できないと判定すればよい。ルータ４０は、演算処理を実行できないと判定された電力パケット６０については受け入れないことで、演算処理を実行可能な他のルータ４０に演算処理を委ねることができる。 In order to properly select the calculation to be executed, it is sufficient to determine whether or not the calculation processing for the power packet 60 can be executed. For example, it may be determined that the arithmetic processing that can maintain or change the voltage of the storage unit 452 to a desired voltage can be executed, and that the arithmetic processing that the voltage of the storage unit 452 deviates from the desired voltage cannot be executed. .. By not accepting the power packet 60 determined that the arithmetic processing cannot be executed, the router 40 can entrust the arithmetic processing to another router 40 capable of executing the arithmetic processing.
　演算処理の実行の可否の判定のため、図３２に示すコントローラ４１は、蓄電部４５２の電圧検出処理７１１を実行する。電圧検出処理７１１により、コントローラ４１は、蓄電部４５２の電圧を監視することができる。 The controller 41 shown in FIG. 32 executes the voltage detection process 711 of the power storage unit 452 in order to determine whether or not the arithmetic processing can be executed. The voltage detection process 711 allows the controller 41 to monitor the voltage of the power storage unit 452.
　そして、図３２に示すコントローラ４１は、演算可否判定処理７１２を実行する。演算可否判定処理７１２は、電圧検出処理７１１により検出された蓄電部４５２の電圧と、演算対象の電力パケット６０の電圧に基づいて行うことができる。例えば、処理回路４５１が単一の演算処理しか実行しない場合、演算処理を実行した後の蓄電部４５２の電圧は、演算処理を実行する前の蓄電部４５２の電圧と、演算対象の電力パケット６０の電圧と、によって決定される。 Then, the controller 41 shown in FIG. 32 executes the calculation possibility determination process 712. The calculation possibility determination process 712 can be performed based on the voltage of the power storage unit 452 detected by the voltage detection process 711 and the voltage of the power packet 60 to be calculated. For example, when the processing circuit 451 executes only a single arithmetic processing, the voltage of the storage unit 452 after the arithmetic processing is executed is the voltage of the storage unit 452 before the arithmetic processing is executed and the power packet 60 to be calculated. Determined by the voltage of.
　したがって、演算可否判定処理７１２では、演算対象の電力パケット６０の電圧が、演算処理を実行する前の蓄電部４５２の電圧に鑑みて、蓄電部４５２の電圧を所望の電力状態にできるか否かの判定７１３を行えばよい。 Therefore, in the calculation possibility determination process 712, whether or not the voltage of the power packet 60 to be calculated can bring the voltage of the power storage unit 452 into a desired power state in view of the voltage of the power storage unit 452 before the calculation process is executed. The determination 713 may be performed.
　判定７１３において、所望の電力状態にできると判定された場合、演算制御処理７０４を実行する。一方、所望の電力状態から外れると判定された場合、電力パケットを受け入れないようにスイッチ制御７１５をする。演算制御処理７０４が実行された場合、処理回路４５１は、演算処理を行って、演算結果に相当する電力を出力する。コントローラ４１は、処理回路４５１から出力された電力から電力パケットを生成する処理７０４を実行する。 If it is determined in the determination 713 that the desired power state can be obtained, the arithmetic control process 704 is executed. On the other hand, when it is determined that the power state deviates from the desired power state, the switch control 715 is performed so as not to accept the power packet. When the arithmetic control process 704 is executed, the processing circuit 451 performs the arithmetic processing and outputs the electric power corresponding to the arithmetic result. The controller 41 executes the process 704 that generates a power packet from the power output from the process circuit 451.
　実施形態においては、処理回路４５１は、複数の演算処理を実行可能であるため、演算処理を実行した後の蓄電部４５２の電圧は、さらに、演算の種別に依存する。そこで、図３２に示す演算可否判定処理７１２では、演算種別識別処理７０１によって識別された演算処理の種別と演算対象の電力パケット６０の電圧とが、演算処理を実行する前の蓄電部４５２の電圧に鑑みて、蓄電部４５２の電圧を所望の電力状態にできるか否かの判定７１３が行われる。 In the embodiment, since the processing circuit 451 can execute a plurality of arithmetic processes, the voltage of the power storage unit 452 after the arithmetic processing is executed further depends on the type of arithmetic. Therefore, in the calculation possibility determination process 712 shown in FIG. 32, the type of the calculation process identified by the calculation type identification process 701 and the voltage of the power packet 60 to be calculated are the voltages of the power storage unit 452 before the calculation process is executed. In view of the above, determination 713 is performed as to whether or not the voltage of the power storage unit 452 can be set to a desired power state.
　図３３Ａ，図３３Ｂ，図３３Ｃ及び図３４は、蓄電部４５２の電圧の制御例を示している。ここでは、図３４に示すように、蓄電部４５２の電圧を、Ｓ－２，Ｓ－１，Ｓ０，Ｓ１，Ｓ２の５個の状態で表す。Ｓ－２は、８．５１Ｖ以上、８．８６Ｖ未満を示す。Ｓ－１は、８．１７Ｖ以上、８．５１Ｖ未満を示す。Ｓ０は、７．７４Ｖ以上、８．１７Ｖ未満を示す。Ｓ１は、７．５６Ｖ以上、７．７４未満を示す。Ｓ２は、７．０９Ｖ以上、７．３４Ｖ未満を示す。 33A, 33B, 33C and 34 show an example of controlling the voltage of the power storage unit 452. Here, as shown in FIG. 34, the voltage of the power storage unit 452, S -2, S -1, expressed in five states S 0, S 1, S 2 . S- 2 indicates 8.51V or more and less than 8.86V. S -1 indicates 8.17V or more and less than 8.51V. S 0 indicates 7.74 V or more and less than 8.17 V. S 1 indicates 7.56 V or more and less than 7.74. S 2 indicates 7.09 V or more and less than 7.34 V.
　制御例では、蓄電部４５２の電圧を、概ね状態Ｓ０に保つ。図３３Ａは、状態Ｓ０まわりの状態遷移図を示している。図３３Ａにおいて、２桁の数値は、２つの入力電力パケットのペアの論理値を示し、論理値の上のＡ又はＮは、その論理値に対して実行されるＡＮＤ演算又はＮＡＮＤ演算を示す。 In the control example, it keeps the voltage of the power storage unit 452, a generally state S 0. Figure 33A shows a state transition diagram of around state S 0. In FIG. 33A, a two-digit number indicates the logical value of a pair of two input power packets, and A or N above the logical value indicates an AND or NAND operation performed on that logical value.
　例えば、状態Ｓ０において、“００”入力に対するＡＮＤ演算、“０１”入力に対するＮＡＮＤ演算、“１１”入力に対するＡＮＤ演算が行われた場合、“１０”入力に対するＮＡＮＤ演算が行われた場合、状態Ｓ０が維持される。ただし、蓄電部４５２の電圧によっては、“１０”入力に対するＮＡＮＤ演算が行われた場合、状態Ｓ０から状態Ｓ－１へ遷移することがある。 For example, in the state S 0 , when the AND operation for the "00" input, the NAND operation for the "01" input, the AND operation for the "11" input is performed, and the NAND operation for the "10" input is performed, the state. S 0 is maintained. However, depending on the voltage of the power storage unit 452, when the NAND operation for the “10” input is performed, the state S 0 may transition to the state S -1.
　状態Ｓ１において、“０１”入力に対するＡＮＤ演算、“１１”入力に対するＮＡＮＤ演算、“１０”入力に対するＡＮＤ演算が行われた場合、状態Ｓ０へ復帰する。 In state S 1, "01" AND operation on the input, "11" NAND operation on the input, "10" if the AND operation is performed for the input and returns to state S 0.
　したがって、概ね状態Ｓ０を維持したければ、状態Ｓ０を維持する演算だけ選択して実行するか、状態Ｓ０以外の状態に遷移したときに状態Ｓ０に復帰する演算を選択して実行すればよい。 Therefore, if you want generally maintain state S 0, or selects and executes only operation to maintain the state S 0, and select the operation to return to the state S 0 when a transition to a state other than state S 0 Run do it.
　図３３Ｂは、入力電力パケットｆ，ｂ、選択された演算、出力、及び状態の例を示している。ここでは、選択される演算処理の種別は、ＡＮＤとＮＡＮＤとする。蓄電部４５２の初期の電圧は８Ｖ（状態Ｓ０）とする。図３３Ｂでは、演算周期（Ｔ１，Ｔ２，Ｔ３，Ｔ４，Ｔ５，Ｔ６，Ｔ７，Ｔ８，Ｔ９）において、（１０，１０，１１，００，１０，１１，１１，００，１１）が入力される。演算周期Ｔ１，Ｔ２，Ｔ３，Ｔ５，Ｔ６においては、演算処理の種別として、ＮＡＮＤが選択される。演算周期Ｔ４，Ｔ７，Ｔ８，Ｔ９においては、演算処理の種別として、ＡＮＤが選択される。 FIG. 33B shows examples of input power packets f, b, selected operations, outputs, and states. Here, the types of arithmetic processing selected are AND and NAND. The initial voltage of the power storage unit 452 is 8 V (state S 0 ). In FIG. 33B, (10,10,11,00,10,11,11,00,11) is input in the calculation cycle (T1, T2, T3, T4, T5, T6, T7, T8, T9). .. In the calculation cycles T1, T2, T3, T5, and T6, NAND is selected as the type of calculation processing. In the calculation cycles T4, T7, T8, and T9, AND is selected as the type of calculation processing.
　図３３Ｃ及び図３４に示すように、演算周期Ｔ２の終了時点において、状態はＳ－１に落ちるが、演算周期Ｔ３において、蓄電部４５２の電圧を上昇させる演算である（“１１”入力に対するＮＡＮＤ）を実行することで、状態Ｓ０に復帰することができる。また、その他の演算周期においては、状態Ｓ０を維持することができた。 As shown in FIGS. 33C and 34, at the end of the calculation cycle T2, the state drops to S-1 , but in the calculation cycle T3, the voltage of the power storage unit 452 is increased (NAND for the “11” input). ) by the execution, it is possible to return to the state S 0. In addition, the state S 0 could be maintained in other calculation cycles.
＜２．３．４　第２の開示に関する条項＞ <2.3.4 Clause regarding the second disclosure>
［条項（clause）１］
　パルス化された第１入力電力に対する演算をする電力演算装置であって、
　前記第１入力電力を蓄える蓄電部と、
　前記第１入力電力に対する演算結果に相当する出力電力を前記蓄電部から出力する演算処理を実行する処理回路と、
　を備える電力演算装置。
［条項２］
　前記処理回路は、複数の種別の演算処理を実行可能なスイッチ回路である
　条項１に記載の電力演算装置。
［条項３］
　選択された種別の演算処理が実行されるように前記処理回路を制御するコントローラを更に備える
　条項２に記載の電力演算装置。
［条項４］
　前記第１入力電力は、第１入力電力パケットに含まれ、
　前記第１入力電力パケットは、前記コントローラにおいて、前記演算処理に関する制御に用いられる演算情報を含む
　条項３に記載の電力演算装置。
［条項５］
　前記演算情報は、前記演算処理の種別を示す演算種別情報を有し、
　前記コントローラは、前記処理回路にて実行される演算処理として、前記演算種別情報が示す演算処理を選択する
　条項４に記載の電力演算装置。
［条項６］
　前記演算情報は、第２入力電力を有する第２入力電力パケットの識別情報を有し、
　前記出力電力は、前記第１入力電力と、前記識別情報によって識別される前記第２入力電力パケットの前記第２入力電力と、に対する演算結果に相当する電力である
　条項４又は条項５に記載の電力演算装置。
［条項７］
　前記コントローラは、前記演算処理の実行の可否を判定するよう構成されている
　条項３から条項６のいずれか１項に記載の電力演算装置。
［条項８］
　前記演算処理の実行の可否の判定は、前記蓄電部の電圧を所望の電圧にするために行われる
　条項７に記載の電力演算装置。
［条項９］
　前記処理回路は、前記蓄電部へ電力を蓄える入力状態及び前記出力電力を前記蓄電部から出力する出力状態を含む複数の状態に切り替え可能に構成されている
　条項１から条項８のいずれか１項に記載の電力演算装置。
［条項１０］
　前記出力電力を有する出力電力パケットを生成するパケット生成部を更に備える
　条項１から条項９のいずれか１項に記載の電力演算装置。
［条項１１］
　条項１から条項１０のいずれか１項に記載の電力演算装置を備える
　電力伝送システム。
［条項１２］
電力パケットのデータ構造であって、
　伝送される電力を有するペイロードと、
　ペイロードが有する電力に対する演算結果に相当する電力を出力する演算処理を実行する電力演算装置が、前記演算処理に関する制御に用いる演算情報と、
　を備える電力パケットのデータ構造。 [Clause 1]
It is a power calculation device that calculates the pulsed first input power.
The power storage unit that stores the first input power and
A processing circuit that executes arithmetic processing to output output power corresponding to the arithmetic result for the first input electric power from the power storage unit, and
A power arithmetic unit equipped with.
[Clause 2]
The power arithmetic unit according to Clause 1, wherein the processing circuit is a switch circuit capable of executing a plurality of types of arithmetic processing.
[Clause 3]
The power arithmetic unit according to Clause 2, further comprising a controller that controls the processing circuit so that the arithmetic processing of the selected type is executed.
[Clause 4]
The first input power is included in the first input power packet.
The power arithmetic unit according to Clause 3, wherein the first input power packet includes arithmetic information used for controlling the arithmetic processing in the controller.
[Clause 5]
The calculation information includes calculation type information indicating the type of the calculation process.
The power arithmetic unit according to Clause 4, wherein the controller selects the arithmetic processing indicated by the arithmetic type information as the arithmetic processing executed by the processing circuit.
[Clause 6]
The calculation information includes identification information of a second input power packet having a second input power.
The output power is the power corresponding to the calculation result for the first input power and the second input power of the second input power packet identified by the identification information, as described in Clause 4 or Clause 5. Power computing device.
[Clause 7]
The power arithmetic unit according to any one of Articles 3 to 6, wherein the controller is configured to determine whether or not the arithmetic processing can be executed.
[Clause 8]
The power arithmetic unit according to Article 7, wherein the determination as to whether or not the arithmetic processing can be executed is performed in order to make the voltage of the power storage unit a desired voltage.
[Clause 9]
The processing circuit is configured to be switchable to a plurality of states including an input state for storing electric power in the power storage unit and an output state for outputting the output power from the power storage unit. The power arithmetic unit described in.
[Clause 10]
The power arithmetic unit according to any one of Articles 1 to 9, further comprising a packet generation unit for generating an output power packet having the output power.
[Clause 11]
A power transmission system comprising the power arithmetic unit according to any one of Articles 1 to 10.
[Clause 12]
The data structure of the power packet
With the payload that has the power to be transmitted,
The arithmetic information used by the power arithmetic unit that executes the arithmetic processing that outputs the electric power corresponding to the arithmetic result for the electric power of the payload for the control related to the arithmetic processing, and
Power packet data structure with.
＜３．付記＞
　本発明は、上記実施形態に限定されるものではなく、様々な変形が可能である。 <3. Addendum>
The present invention is not limited to the above embodiment, and various modifications are possible.
＜第１の開示＞
１０　　　　：電力伝送システム
２０　　　　：電源
３０　　　　：ミキサ
４０　　　　：電力ルータ
４１　　　　：コントローラ
４２　　　　：回路モデル
４３　　　　：回路モデル
４５　　　　：パワープロセッシング回路
４５Ａ　　　：入力ポート
４５Ｂ　　　：出力ポート
４６　　　　：蓄電部
４６Ａ　　　：計測部
４７　　　　：スイッチ回路
４８　　　　：スイッチ回路
５０　　　　：負荷
６０　　　　：電力パケット
６１　　　　：ヘッダ
６２　　　　：ペイロード
６３　　　　：フッタ
Ａ　　　　　：パラメータ
Ｂ　　　　　：パラメータ
Ｃ　　　　　：パラメータ
Ｃ１　　　　：コンデンサ
Ｃ２　　　　：コンデンサ <First disclosure>
10: Power transmission system 20: Power supply 30: Mixer 40: Power router 41: Controller 42: Circuit model 43: Circuit model 45: Power processing circuit 45A: Input port 45B: Output port 46: Power storage unit 46A: Measurement unit 47: Switch Circuit 48: Switch circuit 50: Load 60: Power packet 61: Header 62: payload 63: Footer A: Parameter B: Parameter C: Parameter C 1 : Capacitor C 2 : Capacitor
＜第２の開示＞
　１０　電力伝送システム
　２０　電源
　３０　ミキサ
　３１　コントローラ
　３２　ゲートドライバ
　３３　スイッチ回路
　４０　ルータ（電力演算装置）
　４１　コントローラ
　４２　ゲートドライバ
　４３　スイッチ回路
　４４　アイソレータ
　５０　負荷
　６０　電力パケット
　６１　ヘッダ
　６２　ペイロード
　６３　フッタ
３０１　スイッチ素子
３０２　抵抗
３０３　ダイオード
３０５　スイッチ素子
３０６　抵抗
３０７　ダイオード
４０１，４０２，４０３，４０４　スイッチ素子
４０５，４０６，４０７，４０８　ダイオード
４１１，４１２，４１３，４１４　スイッチ素子（パケット生成部）
４１５，４１６，４１７，４１８　ダイオード
４５０Ａ　電力演算部
４５０Ｂ　電力演算部
４５１　処理回路
４５２　蓄電部（キャパシタ）
５０１，５０２，５０３　スイッチ素子
５０５　抵抗
５１１，５１２，５１３，５１４　ダイオード
６０１　パケットＩＤ
６０２　演算情報
６０３　アドレス情報
６１１　演算種別情報
６１２　演算対象識別情報
６２１　送信元アドレス
６２２　送信先アドレス
７０１　演算種別識別処理
７０２　演算対象識別処理
７０３　電力検出処理
７０４　演算制御処理
７０５　パケット生成処理
７１１　電圧検出処理
７１２　演算可否判定処理
７１３　判定処理
７１５　電力パケットを受け入れない処理 <Second disclosure>
10 Power transmission system 20 Power supply 30 Mixer 31 Controller 32 Gate driver 33 Switch circuit 40 Router (power arithmetic unit)
41 Controller 42 Gate driver 43 Switch circuit 44 Isolator 50 Load 60 Power packet 61 Header 62 payload 63 Footer 301 Switch element 302 Resistance 303 Diode 305 Switch element 306 Resistance 307 Diode 401, 402, 403, 404 Switch element 405, 406, 407, 408 Diode 411,421,413,414 Switch element (packet generator)
415, 416,417,418 Diode 450A Power calculation unit 450B Power calculation unit 451 Processing circuit 452 Storage unit (capacitor)
501,502,503 Switch element 505 Resistor 511,512,513,514 Diode 601 Packet ID
602 Calculation information 603 Address information 611 Calculation type information 612 Calculation target identification information 621 Source address 622 Destination address 701 Calculation type identification processing 702 Calculation target identification processing 703 Power detection processing 704 Calculation control processing 705 Packet generation processing 711 Voltage detection processing 712 Calculation possibility judgment process 713 Judgment process 715 Process that does not accept power packets

Claims (13)

  1. 　電力パケット伝送装置であって、
    　前記電力パケット伝送装置の出力側からの電力パケット要求によって決まる理想出力電力と、前記電力パケット伝送装置から出力される出力電力パケットから決まる実出力電力と、の差が小さくなるように前記出力電力パケットが有する電力を設定することを含む伝送制御処理を実行するコントローラを備える
    　電力パケット伝送装置。     It is a power packet transmission device
    The output power packet so that the difference between the ideal output power determined by the power packet request from the output side of the power packet transmission device and the actual output power determined by the output power packet output from the power packet transmission device is small. A power packet transmission device comprising a controller that executes transmission control processing including setting the power possessed by the power packet transmission device.
  2. 　前記出力電力パケットが有する電力を設定することは、複数の論理演算のうちから、前記差を最小にする論理演算を選択することを含み、
    　前記出力電力パケットが有する電力は、前記電力パケット伝送装置へ入力される入力電力パケットが有する電力が示す論理値に対して、選択された前記論理演算を適用して得られる演算結果に応じて設定される
    　請求項１に記載の電力パケット伝送装置。     Setting the power contained in the output power packet includes selecting the logical operation that minimizes the difference from the plurality of logical operations.
    The power of the output power packet is set according to the calculation result obtained by applying the selected logical operation to the logical value indicated by the power of the input power packet input to the power packet transmission device. The power packet transmission device according to claim 1.
  3. 　前記伝送制御処理は、前記出力電力パケットが有する電力についての複数の候補値毎に前記差を演算することを含み、
    　前記出力電力パケットが有する電力は、前記複数の候補値のうち前記差を最小にする候補値に設定される
    　請求項１又は２に記載の電力パケット伝送装置。     The transmission control process includes calculating the difference for each of a plurality of candidate values for the power of the output power packet.
    The power packet transmission device according to claim 1 or 2, wherein the power contained in the output power packet is set to a candidate value that minimizes the difference among the plurality of candidate values.
  4. 　前記複数の候補値それぞれは、論理値である
    　請求項３に記載の電力パケット伝送装置。     The power packet transmission device according to claim 3, wherein each of the plurality of candidate values is a logical value.
  5. 　前記出力電力パケットが有する電力は、前記電力パケット要求とは異なる値に設定されることがある
    　請求項１から４のいずれか１項に記載の電力パケット伝送装置。     The power packet transmission device according to any one of claims 1 to 4, wherein the power contained in the output power packet may be set to a value different from the power packet request.
  6. 　前記差は、前記電力パケット伝送装置へ入力される入力電力パケットが有する電力の値に基づいて計算される
    　請求項１から５のいずれか１項に記載の電力パケット伝送装置。     The power packet transmission device according to any one of claims 1 to 5, wherein the difference is calculated based on the value of the power of the input power packet input to the power packet transmission device.
  7. 　前記差は、前記出力側の回路モデルに基づいて計算される
    　請求項１から６のいずれか１項に記載の電力パケット伝送装置。     The power packet transmission device according to any one of claims 1 to 6, wherein the difference is calculated based on the circuit model on the output side.
  8. 　前記電力パケット伝送装置へ入力される入力電力パケットが有する電力を蓄える蓄電部を更に備える
    　請求項１から７のいずれか１項に記載の電力パケット伝送装置。     The power packet transmission device according to any one of claims 1 to 7, further comprising a power storage unit for storing the power of the input power packet input to the power packet transmission device.
  9. 　前記差は、前記蓄電部に蓄えられたエネルギー値に基づいて計算される
    　請求項８に記載の電力パケット伝送装置。     The power packet transmission device according to claim 8, wherein the difference is calculated based on the energy value stored in the power storage unit.
  10. 　前記エネルギー値を計測する計測部を更に備える
    　請求項９に記載の電力パケット伝送装置。     The power packet transmission device according to claim 9, further comprising a measuring unit for measuring the energy value.
  11. 　前記電力パケット要求は、電力供給先である負荷装置において生成された要求である
    　請求項１から１０のいずれか１項に記載の電力パケット伝送装置。     The power packet transmission device according to any one of claims 1 to 10, wherein the power packet request is a request generated by a load device that is a power supply destination.
  12. 　請求項１から１１のいずれか１項に記載の電力パケット伝送装置を備える
    　電力パケット伝送システム。     A power packet transmission system comprising the power packet transmission device according to any one of claims 1 to 11.
  13. 　電力パケット要求によって決まる理想出力電力と、前記電力パケット要求に基づいて出力される出力電力パケットから決まる実出力電力と、の差が小さくなるように前記出力電力パケットが有する電力を設定することを備える
    　電力パケット伝送制御方法。     The power included in the output power packet is set so that the difference between the ideal output power determined by the power packet request and the actual output power determined by the output power packet output based on the power packet request becomes small. Power packet transmission control method.
PCT/JP2020/035202 2019-09-17 2020-09-17 Power packet transmitting device, power packet transmitting system, and power packet transmission control method WO2021054387A1 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011142771A (en) * 2010-01-08 2011-07-21 Yokogawa Electric Corp Power packet system
WO2014189051A1 (en) * 2013-05-21 2014-11-27 国立大学法人京都大学 Power packet generation device, power router, and power network
WO2015037212A1 (en) * 2013-09-10 2015-03-19 日本電気株式会社 Power-network system, method for controlling same, computer-readable medium, power router, and management server

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011142771A (en) * 2010-01-08 2011-07-21 Yokogawa Electric Corp Power packet system
WO2014189051A1 (en) * 2013-05-21 2014-11-27 国立大学法人京都大学 Power packet generation device, power router, and power network
WO2015037212A1 (en) * 2013-09-10 2015-03-19 日本電気株式会社 Power-network system, method for controlling same, computer-readable medium, power router, and management server

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