WO2021051389A1

WO2021051389A1 - Coa type array substrate and manufacturing method for coa type array substrate

Info

Publication number: WO2021051389A1
Application number: PCT/CN2019/107002
Authority: WO
Inventors: 秦文鹏; 黄小骅; 李卓; 胡佳乔
Original assignee: 咸阳彩虹光电科技有限公司
Priority date: 2019-09-20
Filing date: 2019-09-20
Publication date: 2021-03-25

Abstract

A COA type array substrate, comprising a substrate (10), a pixel control layer (20), a first passivation layer (30), a color resist layer (40), a second passivation layer (50), a light shielding layer (60), a third passivation layer (70), a first pixel electrode (81), and a second pixel electrode (82) which are sequentially stacked. The light shielding layer (60) is provided on one side of the second passivation layer (50) away from the color resist layer (40) and covers a data line (DL); the third passivation layer (70) is provided on one side of the second passivation layer (50) away from the color resist layer (40) and covers the light shielding layer (60). The first pixel electrode (81) and the second pixel electrode (82) are provided at intervals on one side of the third passivation layer (70) away from the second passivation layer (50), and two adjacent ends of the first pixel electrode (81) and the second pixel electrode (82) respectively extend above the light shielding layer (60) and overlap with the light shielding layer (60). The light shielding layer (60), the first pixel electrode (81), and the second pixel electrode (82) form a storage capacitor, so that the conventional shielding metal is eliminated, the area of a light shielding region can be effectively reduced, and the aperture ratio of a pixel is increased.

Description

COA type array substrate and COA type array substrate manufacturing method

Technical field

The present invention relates to the field of display technology, in particular to a COA type array substrate and a COA type array substrate manufacturing method.

Background technique

The traditional liquid crystal display device includes a liquid crystal display panel and a backlight module. The liquid crystal display panel mainly includes a thin film transistor array substrate, a color filter, and a liquid crystal composition between the two substrates. The working principle is to apply a driving voltage on the two substrates. The rotation of the liquid crystal molecules is controlled to refract the light from the backlight module to produce a picture.

COA (Color Filter On Array) is a technology that integrates color filters on an array substrate, which can improve the transmittance of the display, and can avoid the deviation of the array substrate and the color film substrate when the box is aligned, resulting in a reduction in aperture ratio and light leakage problem.

In the known COA type array substrate, in order to avoid light leakage between adjacent pixel electrodes and between data lines and pixel electrodes, metal shielding lines, such as metal shielding lines arranged on the same layer as the pixel electrodes and located between adjacent pixel electrodes, are often used. The layer (or Com electrode) and the metal layer (or Com line) located between the pixel electrode and the data line and below the layer where the data line is used as the electrode plate of the storage capacitor (or Com line) will reduce the pixel aperture ratio and the display’s penetration Poor transmittance increase, which affects the display quality. In addition, the COA-type array substrate will reduce the capacitance value of the pixel storage capacitor. The reduction of the storage capacitor will cause the risk of high feedthrough voltage, resulting in unstable pixel voltage. Issues affecting display quality.

Summary of the invention

In order to solve the above-mentioned problems, an embodiment of the present invention provides a COA type array substrate, including: a substrate; a pixel control layer disposed on the substrate and including a data line; a first passivation layer covering and including the data Line of the pixel control layer; a color resist layer, arranged on the side of the first passivation layer away from the pixel control layer; a second passivation layer, arranged on the color resist layer away from the first passivation layer A light-shielding layer is arranged on the side of the second passivation layer away from the color resist layer and covers the data line; a third passivation layer is arranged on the second passivation layer away from One side of the color resist layer and covering the light-shielding layer; and the first pixel electrode and the second pixel electrode are arranged at a distance from each other on the side of the third passivation layer away from the second passivation layer, Wherein the adjacent two ends of the first pixel electrode and the second pixel electrode respectively extend to the light shielding layer and overlap the light shielding layer, and the light shielding layer forms a memory with the first pixel electrode and the second pixel electrode. A capacitor, the first pixel electrode and the second pixel electrode are electrically connected to the pixel control layer.

In an embodiment of the present invention, the pixel control layer further includes a gate electrode, a gate insulating layer, a channel layer, an ohmic contact layer, and a gate electrode, a gate insulating layer, a channel layer, and an ohmic contact layer located between the substrate and the first passivation layer and stacked in sequence. A source-drain layer, the source-drain layer includes a source and a drain, the data line is electrically connected to one of the source and the drain, and the first pixel electrode is electrically connected to the source and For the other of the drain electrodes, the light shielding layer is electrically connected to the common electrode.

In an embodiment of the present invention, the width of the light shielding layer in the distance direction between the first pixel electrode and the second pixel electrode is greater than or equal to the width of the data line in the distance direction.

In an embodiment of the present invention, each of the adjacent ends of the first pixel electrode and the second pixel electrode and the light shielding layer are connected to the first pixel electrode and the second pixel electrode. The value of the overlap length in the distance direction of the electrodes ranges from 1 micrometer to 5 micrometers.

In an embodiment of the present invention, the thickness of the second passivation layer is greater than or equal to 500 angstroms, and the thickness of the third passivation layer is greater than or equal to 2500 angstroms.

In an embodiment of the present invention, no shielding metal is provided between the first passivation layer and the substrate and in the vertical projection area of the adjacent two ends on the substrate.

In an embodiment of the present invention, the light shielding layer is a transparent electrode.

In an embodiment of the present invention, the first pixel electrode and the second pixel electrode further include a strip-shaped main electrode, the light shielding layer and the main electrode form a counter-plate capacitance, and the counter-plate capacitance is connected to the main electrode. The storage capacitors form a network distribution.

In an embodiment of the present invention, the color resist layer includes a plurality of color resists of different colors.

In addition, an embodiment of the present invention also provides a COA type array substrate manufacturing method, including: providing a substrate; disposing a pixel control layer on the substrate, wherein the pixel control layer includes a data line; forming a first passivation Layer to cover the pixel control layer including the data line; a color resist layer is provided on a side of the first passivation layer away from the pixel control layer; a color resist layer is provided on a side of the color resist layer away from the first A second passivation layer is provided on one side of the passivation layer; a light shielding layer is provided on the side of the second passivation layer away from the color resist layer, wherein the light shielding layer covers the data line; A third passivation layer is provided on the side of the second passivation layer away from the color resist layer, wherein the third passivation layer covers the light-shielding layer; and the third passivation layer is away from the second passivation layer One side of the passivation layer is provided with a first pixel electrode and a second pixel electrode, wherein the first pixel electrode and the second pixel electrode are spaced apart from each other, and adjacent ends of the first pixel electrode and the second pixel electrode Respectively extend to the light-shielding layer to overlap with the light-shielding layer, the light-shielding layer forms a storage capacitor with the first pixel electrode and the second pixel electrode, and the first pixel electrode and the second pixel electrode are electrically connected The pixel control layer.

In an embodiment of the present invention, the disposing of the pixel control layer on the substrate includes: forming a gate electrode of the pixel control layer on the substrate through a first mask process; A mask process forms a gate insulating layer, a channel layer, and an ohmic contact layer sequentially stacked on the gate electrode; and forms a source and drain layer of the pixel control layer on the ohmic contact layer through a third mask process And synchronously form the data line, wherein the source-drain layer includes a source electrode and a drain electrode, one of the source electrode and the drain electrode is electrically connected to the data line, and the source electrode and the drain electrode are The other is electrically connected to the first pixel electrode.

In an embodiment of the present invention, said disposing a light-shielding layer on a side of the second passivation layer away from the color resist layer includes: forming the light-shielding layer through a fourth masking process, wherein the The light-shielding layer is electrically connected to the common electrode; the disposing a third passivation layer on a side of the second passivation layer away from the color resist layer includes: sequentially forming the first passivation layer through a fifth mask process The second passivation layer and the third passivation layer, and the yellowing process is only performed when the third passivation layer is formed; and the distance between the third passivation layer and the third passivation layer Disposing the first pixel electrode and the second pixel electrode on one side of the second passivation layer includes: forming the first pixel electrode and the second pixel electrode through a sixth mask process.

It can be seen from the above that the embodiment of the present invention extends the first pixel electrode and the second pixel electrode directly above the light-shielding layer to overlap the light-shielding layer, and combines the first pixel electrode and the second pixel electrode The overlapping portion between the pixel electrode and the light shielding layer serves as the storage capacitor of the pixel structure, eliminating the need for traditional shielding metal, thereby effectively reducing the area of the light shielding area, increasing the pixel aperture ratio, and improving the display quality.

Description of the drawings

In order to explain the technical solutions of the embodiments of the present invention more clearly, the following will briefly introduce the drawings used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. A person of ordinary skill in the art can obtain other drawings based on these drawings without creative work.

FIG. 1 is a schematic cross-sectional view of a partial structure of a COA type array substrate provided by the present invention.

2 is a schematic cross-sectional view of another view of the partial structure of the COA array substrate provided by the present invention.

FIG. 3 is a schematic diagram of the mesh distribution of the COA type array substrate provided by the present invention.

4 is a schematic diagram of the mesh distribution of another light-shielding layer of the COA type array substrate provided by the present invention.

FIG. 5 is a schematic diagram of the pixel structure layout of the COA type array substrate in the related art.

FIG. 6 is a schematic diagram of the pixel structure layout of the COA type array substrate provided by the present invention.

FIG. 7 is a flow chart of the manufacturing method of the COA type array substrate provided by the present invention.

[Description of main component symbols]

10: substrate; 20: pixel control layer; 21: gate electrode; 22: gate insulating layer; 23: channel layer; 24: ohmic contact layer; 251: source; 252: drain; PT: pixel transistor; 30: Passivation layer; 40: color resist layer; 50: passivation layer; 60: light-shielding layer; 70: passivation layer; 81: pixel electrode; 82: pixel electrode; 83: backbone electrode; DL: data line; GL: scan Line; D1: thickness of passivation layer 50; D2: thickness of passivation layer 70; L1: overlapping length; L2: width; L3: width; VPA: vertical projection area; AR: aperture ratio width.

detailed description

The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of the present invention.

Please refer to FIGS. 1 and 2. FIG. 1 is a schematic cross-sectional view of a partial structure of the COA type array substrate provided by the present invention; FIG. 2 is a schematic cross-sectional view of a partial structure of the COA type array substrate provided by the present invention from another perspective. Specifically, a COA type array substrate provided by an embodiment of the present invention includes: a substrate 10, a pixel control layer 20, a passivation layer 30, a color resist layer 40, a passivation layer 50, a light-shielding layer 60, and a passivation layer 70. The pixel electrode 81 and the pixel electrode 82.

Wherein, the pixel control layer 20 is disposed on the substrate 10 and includes a data line DL. The passivation layer 30 covers the pixel control layer 20 including the data line DL. The color resist layer 40 is disposed on the side of the passivation layer 30 away from the pixel control layer 20, wherein the color resist layer 40 includes a plurality of color resists of different colors, such as red color resist (R), green color resist (G) and blue color resist. Color resistance (B). The passivation layer 50 is disposed on a side of the color resist layer 40 away from the passivation layer 30, wherein the thickness D1 of the passivation layer 50 is, for example, greater than or equal to 500 angstroms to protect the color resist layer 40 to the greatest extent. The light-shielding layer 60 is disposed on a side of the passivation layer 50 away from the color resist layer 40 and covers the data line DL, wherein the light-shielding layer 60 may be a transparent electrode. The passivation layer 70 is disposed on the side of the passivation layer 50 away from the color resist layer 40 and covers the light-shielding layer 60. The thickness D2 of the passivation layer 70 is greater than or equal to 2500 angstroms to prevent the pixel electrode 81 and the pixel electrode to the greatest extent. 82 and the light shielding layer 60 are short-circuited. The pixel electrode 81 and the pixel electrode 82 are spaced apart from each other on the side of the passivation layer 70 away from the passivation layer 50. The pixel electrode 81 and the pixel electrode 82 are electrically connected to the pixel control layer 20. The pixel electrode 81 and the pixel electrode 82 are adjacent to each other. The ends respectively extend above the light-shielding layer 60 and overlap the light-shielding layer 60, and the pixel electrode 81 and the pixel electrode 82 and the light-shielding layer 60 form a storage capacitor, thereby eliminating the shielding metal used as the Com line in the traditional technology, so that the embodiment of the present invention can be effective The area of the shading area is reduced, and the aperture ratio of the pixel structure is increased, so that the transmittance is significantly improved.

In a specific embodiment, each of the adjacent two ends of the pixel electrode 81 and the pixel electrode 82 and the light shielding layer 60 are in a distance direction between the pixel electrode 81 and the pixel electrode 82 (for example, the horizontal direction in FIG. 1) The value of the overlap length L1 above ranges from 1 μm to 5 μm, and the pixel electrode 81 and the pixel electrode 82 may be ITO (Indium Tin Oxide, indium tin oxide) electrodes or transparent electrodes made of other materials.

In a specific embodiment, for example, as shown in FIG. 3, the pixel electrode 81 and the pixel electrode 82 further include a strip-shaped trunk electrode 83, and the light shielding layer 60 and the trunk electrode 83 form a counter-plate capacitance. Please refer to FIG. 4, the storage capacitors and the counter-board capacitors form a mesh distribution, which can effectively reduce the Feedthrogh voltage, reduce the risk of excessive Feedthrough voltage, and improve the display quality. The mesh distribution is shown at the dotted line in FIG. 4.

In a specific embodiment, for example, as shown in FIG. 2, the pixel control layer 20 further includes a gate electrode 21, a gate insulating layer 22, a channel layer 23, and an ohmic contact located between the substrate 10 and the passivation layer 30 and stacked in sequence. The layer 24 and the source-drain layer, wherein the source-drain layer includes a source electrode 251 and a drain electrode 252, the data line DL is electrically connected to one of the source electrode 251 and the drain electrode 252, such as the source electrode 251, and the pixel electrode 81 or the pixel electrode 82 is connected to the other of the source electrode 251 and the drain electrode 252, such as the drain electrode 252, and the light shielding layer 60 is electrically connected to the common electrode. It is worth mentioning here that the gate electrode 21, the gate insulating layer 22, the channel layer 23, the ohmic contact layer 24, and the source drain layer together constitute the pixel transistor PT (see FIG. 6) of the embodiment of the present invention, which is electrically connected to the pixel The data line DL and the scan line GL of the control layer 20 are electrically connected to the pixel electrode 81 or the pixel electrode 82.

In a specific embodiment, the width L2 of the light shielding layer 60 in the distance direction between the pixel electrode 81 and the pixel electrode 82 is greater than or equal to the width L3 of the data line DL in the distance direction.

In a specific embodiment, no shielding metal is provided in the vertical projection area VPA between the passivation layer 30 and the substrate 10 and located at the adjacent ends of the pixel electrode 81 and the pixel electrode 82, that is, no conventional technology is provided. As the shielding metal of the Com line.

For a more specific description, please refer to Figures 5 and 6. Figure 5 shows the COA type array substrate in the traditional technology (with the shielding of the electrode plate between the pixel electrode and the data line and below the layer where the data line is located, as a storage capacitor). Schematic diagram of the pixel structure layout of metal); FIG. 6 is a schematic diagram of the pixel structure layout of the COA type array substrate provided by the present invention. Compared with Figure 5, the COA type array substrate provided in Figure 6 has a higher aperture ratio (ie AR=B/A*100%). Take a 70-inch 8K COA type array substrate as an example. Please refer to the experimental data Table 1.

Table 1 Comparison table of the opening area of the COA type array substrate of the embodiment of the present invention

It can be seen from Table 1 and FIG. 6 that the COA type array substrate of the embodiment of the present invention extends the adjacent ends of the pixel electrode 81 and the pixel electrode 82 to the light shielding layer 60 and partially overlaps the light shielding layer 60, while eliminating The shielding metal on both sides of each pixel electrode in the traditional technology can reduce the area of the shielding area, and the width of the opening area is increased by at least 29%. For example, as shown in Figure 5 and Figure 6 (58μm-45μm)/45μm≈29%, the opening area The area is significantly increased, and the penetration rate is significantly improved.

Please refer to FIG. 1, FIG. 2 and FIG. 7 together. The embodiment of the present invention also provides a COA type array substrate manufacturing method, which includes the following steps, for example:

Provide substrate 10;

A pixel control layer 20 is provided on the substrate 10, wherein the pixel control layer 20 includes a data line DL;

Forming a passivation layer 30 to cover the pixel control layer 20 including the data line DL;

A color resist layer 40 is provided on the side of the passivation layer 30 away from the pixel control layer 20, wherein the color resist layer 40 includes a plurality of color resists of different colors, such as red color resist (R), green color resist (G), and blue color resist. Resistance (B);

A passivation layer 50 is provided on the side of the color resist layer 40 away from the passivation layer 30;

A light-shielding layer 60 is provided on the side of the passivation layer 50 away from the color resist layer 40, wherein the light-shielding layer 60 covers the data line DL, and the light-shielding layer 60 may be a transparent electrode;

A passivation layer 70 is provided on the side of the passivation layer 50 away from the color resist layer 40, wherein the passivation layer 70 covers the light shielding layer 60; and

A pixel electrode 81 and a pixel electrode 82 are provided on the side of the passivation layer 70 away from the passivation layer 50, wherein the pixel electrode 81 and the pixel electrode 82 are separated from each other, and adjacent ends of the pixel electrode 81 and the pixel electrode 82 respectively extend to the light shielding layer The upper part of 60 overlaps with the light shielding layer 60, the light shielding layer 60 forms a storage capacitor with the pixel electrode 81 and the pixel electrode 82, and the pixel electrode 81 and the pixel electrode 82 are electrically connected to the pixel control layer 20.

In a specific embodiment, the step of disposing a pixel control layer on the substrate includes the following sub-steps:

(i) The gate electrode 21 of the pixel control layer 20 is formed on the substrate 10 through the first mask process;

(ii) The gate insulating layer 22, the channel layer 23, and the ohmic contact layer 24 are sequentially stacked on the gate electrode 21 through the second mask process; and

(iii) The source and drain layer 25 of the pixel control layer 20 is formed on the ohmic contact layer 24 by the third mask process and the data line DL is simultaneously formed. The source and drain layer 25 includes a source electrode 251 and a drain electrode 252. One of the electrode 251 and the drain electrode 252, such as the source electrode 251, is electrically connected to the data line DL, and the other of the source electrode 251 and the drain electrode 252, such as the drain electrode 252, is electrically connected to the pixel electrode 81 or the pixel electrode 82. It is worth noting here that the mask process is well-known to those skilled in the art, so it will not be described in detail here.

In a specific embodiment, the step of disposing the light-shielding layer 60 on the side of the passivation layer 50 away from the color resist layer 40 includes a sub-step: forming the light-shielding layer 60 through the fourth masking process, wherein the light-shielding layer 60 Electrically connected to the common electrode;

The step of disposing the passivation layer 70 on the side of the passivation layer 50 away from the color resist layer 40 includes sub-steps: sequentially forming the passivation layer 30, the passivation layer 50, and the passivation layer 70 through the fifth mask process. , Wherein the fifth mask process only performs the yellow light process when the passivation layer 70 is formed; and

The step of disposing the pixel electrode 81 and the pixel electrode 82 on the side of the passivation layer 70 away from the passivation layer 50 includes a sub-step: forming the pixel electrode 81 and the pixel electrode 82 through a sixth mask process.

In a specific embodiment, the value range of the overlap length L1 of each of the adjacent ends of the pixel electrode 81 and the pixel electrode 82 and the light shielding layer 60 in the distance direction between the pixel electrode 81 and the pixel electrode 82 Preferably it is 1 micrometer to 5 micrometers.

In a specific embodiment, the thickness D1 of the passivation layer 50 is greater than or equal to 500 angstroms, and the thickness D2 of the passivation layer 70 is greater than or equal to 2500 angstroms to effectively prevent the pixel electrode 81 and the pixel electrode 82 from the light shielding layer 60 A short circuit occurred.

In a specific embodiment, no shielding metal is provided in the vertical projection area VPA between the passivation layer 30 and the substrate 10 and located at the adjacent ends of the pixel electrode 81 and the pixel electrode 82, that is, no shielding metal is provided in the conventional technology. As a shielding metal for Com lines.

The COA type array substrate manufacturing method provided by the embodiment of the present invention is formed through a 6-mask manufacturing process. Compared with the traditional technology (that is, the five-mask manufacturing process), the embodiment of the present invention provides The COA type array substrate manufacturing method takes 70-inch 8K as an example, and its penetration rate is higher than that of the traditional technology. Please refer to Table 2 for its experimental data.

Table 2 Comparison table of transmittance of COA type array substrate of the present invention

From the experimental data in Table 2, it can be shown that the aperture ratio of the COA array substrate formed by the six mask processes provided by the embodiment of the present invention is increased by at least 34% (that is, [63.99%-47.63%]/47.63%≈34%). The increase in light rate is greater than or equal to 7.88% (that is, 88.84%-82.35%] / 82.35%≈7.88%), the penetration rate is increased by at least 45%, and the penetration rate is significantly increased.

It is worth mentioning that the COA type array substrate provided by the embodiment of the present invention, compared with the conventional COA type array substrate, the COA type array substrate provided by the embodiment of the present invention takes ITO as an example, and the pixel storage capacitor Cst has the following advantages:

The ratio of Cdc (capacitance between Data and TFT-com) and Cdlc (capacitance between Data and CF-com) of the COA type array substrate structure provided by the embodiment of the present invention to Cdata (sum of capacitances related to DL) The smallest; under the COA type array substrate structure provided by the embodiment of the present invention, the TFT-com voltage and the CF-com voltage are less coupled by the Data voltage, and the TFT-com and CF-com voltages are relatively stable. Because the pixel voltage is coupled to a minimum, the normal display voltage is maintained and the display quality is guaranteed. Please refer to Table 3 for the experimental data;

Referring to Table 3, the COA type array substrate structure provided by the embodiment of the present invention has the smallest ratio of Cdlc to Cdata, so that the coupling effect of Data to CF-com is the smallest, and the pixel voltage is the most stable;

The capacitance value of the pixel storage capacitor Cst of the COA structure provided by the embodiment of the present invention has increased significantly. The Cst value of the COA type array substrate provided by the embodiment of the present invention is 0.371 pF, which is 3.2 times that of the conventional COA type array substrate. 2.5 times that of the array substrate, it can effectively reduce the Feedthrogh voltage and reduce the risk that the Feedthrough voltage is too large, which will cause the pixel voltage to be unstable and affect the display quality. Please refer to Table 4 for the experimental data.

Table 3 Comparison table of pixel storage capacitor values

Table 4 Comparison table of pixel storage capacitor values

设计方式Design method	Cst(pF)Cst(pF)
传统技术(5mask)COA型阵列基板Traditional technology (5mask) COA type array substrate	0.1160.116
非COA型阵列基板Non-COA type array substrate	0.1490.149
本发明实施例(6mask)COA型阵列基板Embodiment of the present invention (6mask) COA type array substrate	0.3710.371

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: The technical solutions recorded in the foregoing embodiments are modified, or some of the technical features thereof are equivalently replaced; these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

A COA type array substrate includes:

Substrate

A pixel control layer, which is disposed on the substrate and includes a data line;

A first passivation layer covering the pixel control layer including the data line;

A color resist layer disposed on the side of the first passivation layer away from the pixel control layer;

The second passivation layer is disposed on a side of the color resist layer away from the first passivation layer;

A light-shielding layer disposed on a side of the second passivation layer away from the color resist layer and covering the data line;

The third passivation layer is disposed on a side of the second passivation layer away from the color resist layer and covers the light-shielding layer; and

The first pixel electrode and the second pixel electrode are arranged at a distance from each other on the side of the third passivation layer away from the second passivation layer, wherein two adjacent ones of the first pixel electrode and the second pixel electrode The ends respectively extend to the light-shielding layer and overlap the light-shielding layer, the light-shielding layer forms a storage capacitor with the first pixel electrode and the second pixel electrode, and the first pixel electrode and the second pixel electrode are electrically connected to each other. Connect the pixel control layer.
The COA type array substrate according to claim 1, wherein the pixel control layer further comprises a gate electrode, a gate insulating layer, and a channel layer located between the substrate and the first passivation layer and stacked in sequence. , An ohmic contact layer and a source-drain layer, the source-drain layer includes a source and a drain, the data line is electrically connected to one of the source and the drain, and the first pixel electrode is electrically connected The other of the source electrode and the drain electrode, and the light shielding layer is electrically connected to a common electrode.
The COA type array substrate according to claim 1, wherein the width of the light shielding layer in the distance direction between the first pixel electrode and the second pixel electrode is greater than or equal to that of the data line in the distance direction. The width on the top.
The COA type array substrate according to claim 1, wherein each of the adjacent ends of the first pixel electrode and the second pixel electrode and the light-shielding layer are located between the first pixel electrode and the second pixel electrode. The overlap length in the distance direction of the second pixel electrode ranges from 1 micrometer to 5 micrometers.
The COA type array substrate according to claim 1, wherein the thickness of the second passivation layer is greater than or equal to 500 angstroms, and the thickness of the third passivation layer is greater than or equal to 2500 angstroms.
The COA type array substrate according to claim 1, wherein, between the first passivation layer and the substrate and located at the adjacent two ends, there is no vertical projection area on the substrate. Shade the metal.
The COA type array substrate according to claim 1, wherein the light shielding layer is a transparent electrode.
The COA type array substrate according to claim 1, wherein the first pixel electrode and the second pixel electrode further comprise a strip-shaped main electrode, and the light shielding layer and the main electrode form a counter-plate capacitance, so The pair of plate capacitors and the storage capacitors form a net-like distribution.
The COA type array substrate according to claim 1, wherein the color resist layer comprises a plurality of color resists of different colors.
A method for manufacturing a COA type array substrate includes:

Provide substrate;

Disposing a pixel control layer on the substrate, wherein the pixel control layer includes a data line;

Forming a first passivation layer to cover the pixel control layer including the data line;

Disposing a color resist layer on the side of the first passivation layer away from the pixel control layer;

Disposing a second passivation layer on a side of the color resist layer away from the first passivation layer;

Disposing a light-shielding layer on a side of the second passivation layer away from the color resist layer, wherein the light-shielding layer covers the data line;

Disposing a third passivation layer on a side of the second passivation layer away from the color resist layer, wherein the third passivation layer covers the light shielding layer; and

A first pixel electrode and a second pixel electrode are provided on a side of the third passivation layer away from the second passivation layer, wherein the first pixel electrode and the second pixel electrode are spaced apart from each other, and the The adjacent two ends of the first pixel electrode and the second pixel electrode respectively extend to the light shielding layer to overlap with the light shielding layer, and the light shielding layer forms a storage capacitor with the first pixel electrode and the second pixel electrode, so The first pixel electrode and the second pixel electrode are electrically connected to the pixel control layer.
11. The COA type array substrate manufacturing method according to claim 10, wherein said disposing a pixel control layer on said substrate comprises:

Forming the gate electrode of the pixel control layer on the substrate through a first mask process;

Forming a gate insulating layer, a channel layer, and an ohmic contact layer sequentially stacked on the gate electrode through a second mask process; and

The source and drain layers of the pixel control layer are formed on the ohmic contact layer through a third mask process and the data lines are simultaneously formed, wherein the source and drain layers include a source and a drain, and the source One of the electrode and the drain is electrically connected to the data line, and the other of the source and the drain is electrically connected to the first pixel electrode.
11. The COA type array substrate manufacturing method of claim 11, wherein said disposing a light-shielding layer on a side of the second passivation layer away from the color resist layer comprises:

Forming the light-shielding layer through a fourth mask process, wherein the light-shielding layer is electrically connected to a common electrode;

The disposing a third passivation layer on a side of the second passivation layer away from the color resist layer includes:

The first passivation layer, the second passivation layer, and the third passivation layer are sequentially formed through the fifth mask process, and the yellow light process is performed only when the third passivation layer is formed ;as well as

The disposing of the first pixel electrode and the second pixel electrode on a side of the third passivation layer away from the second passivation layer includes:

The first pixel electrode and the second pixel electrode are formed through a sixth mask process.
The COA type array substrate manufacturing method according to claim 10, wherein the width of the light-shielding layer in the distance direction between the first pixel electrode and the second pixel electrode is greater than or equal to that of the data line in the The width in the distance direction.
The COA type array substrate manufacturing method according to claim 10, wherein each of the adjacent ends of the first pixel electrode and the second pixel electrode and the light shielding layer are in the first pixel The value range of the overlap length in the distance direction between the electrode and the second pixel electrode is 1 μm to 5 μm.
10. The manufacturing method of the COA type array substrate according to claim 10, wherein the thickness of the second passivation layer is greater than or equal to 500 angstroms, and the thickness of the third passivation layer is greater than or equal to 2500 angstroms.
The COA type array substrate manufacturing method according to claim 10, wherein, between the first passivation layer and the substrate and located in the vertical projection area of the adjacent two ends on the substrate No shielding metal is provided.
10. The method for manufacturing a COA type array substrate according to claim 10, wherein the light shielding layer is a transparent electrode.
The COA type array substrate manufacturing method of claim 10, wherein the first pixel electrode and the second pixel electrode further comprise a strip-shaped main electrode, and the light shielding layer and the main electrode form a counter-plate capacitance , The pair of plate capacitors and the storage capacitors form a net-like distribution.
10. The COA type array substrate manufacturing method according to claim 10, wherein the color resist layer comprises a plurality of color resists of different colors.