WO2021051367A1

WO2021051367A1 - Cyclic redundancy check schemes for unequal error protection with forward error corrections

Info

Publication number: WO2021051367A1
Application number: PCT/CN2019/106866
Authority: WO
Inventors: Jian Li; Changlong Xu; Liangming WU; Hao Xu
Original assignee: Qualcomm Incorporated
Priority date: 2019-09-20
Filing date: 2019-09-20
Publication date: 2021-03-25

Abstract

Methods, systems, and devices for wireless communications are described. A communication device may divide a set of information bits into a first subset of information bits associated with a first forward error correction stream and a second subset of information bits associated with a second forward error correction stream. The communication device may process, at the first forward error correction stream, the first subset by appending a first set of one or more cyclic redundancy check bits to the first subset and encoding the first subset in accordance with a first forward error correction scheme. Additionally, the communication device may process, at the second forward error correction stream, the second subset by encoding the second subset in accordance with a second forward error correction scheme. The communication device may transmit one or more modulation symbols carrying the processed first subset and the processed second subset.

Description

CYCLIC REDUNDANCY CHECK SCHEMES FOR UNEQUAL ERROR PROTECTION WITH FORWARD ERROR CORRECTIONS

FIELD OF TECHNOLOGY

The following relates generally to wireless communications and more specifically to cyclic redundancy check schemes for unequal error protection with forward error corrections.

BACKGROUND

Wireless communications systems are widely deployed to provide various types of communication content such as voice, video, packet data, messaging, broadcast, and so on. These systems may be capable of supporting communication with multiple users by sharing the available system resources (e.g., time, frequency, and power) . Examples of such multiple-access systems include fourth generation (4G) systems such as Long Term Evolution (LTE) systems, LTE-Advanced (LTE-A) systems, or LTE-A Pro systems, and fifth generation (5G) systems which may be referred to as New Radio (NR) systems. These systems may employ technologies such as code division multiple access (CDMA) , time division multiple access (TDMA) , frequency division multiple access (FDMA) , orthogonal frequency division multiple access (OFDMA) , or discrete Fourier transform spread orthogonal frequency division multiplexing (DFT-S-OFDM) .

A wireless multiple-access communications system may include a number of base stations or network access nodes, each simultaneously supporting communication for multiple communication devices, which may be otherwise known as user equipments (UEs) . Some wireless communications systems may support high reliability and low latency communications. Some wireless communications systems may also support various error detection or correction techniques to support the high reliability and low latency communications.

SUMMARY

The described techniques may relate to configuring a communication device, which may be a base station (e.g., eNodeB (eNBs) , next-generation NodeB or giga-NodeB (any of which may be referred to as a gNB) ) or a user equipment (UE) , to support one or more cyclic redundancy check schemes for unequal error protection with forward error corrections. The communication device may be configured, in some examples, to encode a set of information bits with one or more cyclic redundancy check bits to protect all the information bits of the set. After encoding the set of information bits with the one or more cyclic redundancy check bits, the communication device may process the information bits by distributing (e.g., dividing) the information bits into multiple subsets of information bits (e.g., at least two subsets of information bits) to process the subsets separately. Alternatively, in some examples, the communication device may ignore encoding the set of information bits with the one or more cyclic redundancy check bits and directly divide the information bits into the multiple subsets.

The communication device may handle each subset separately. For example, the communication device may encode a first subset of information bits with a first forward error correction scheme and a second subset of information bits with a second error correction scheme. In some examples, the communication device may append a first set of one or more cyclic redundancy check bits to the first subset of information bits before encoding the first subset of information bits in accordance with the first forward error correction scheme. Additionally, or alternatively, the communication device may append a second set of one or more cyclic redundancy check bits to the second subset of information bits before encoding the second subset of information bits in accordance with the second forward error correction scheme. The communication device may, as a result, include features for improvements to power consumption, early termination, partial retransmission, spectral efficiency, higher data rates and, in some examples, may promote enhanced efficiency for high reliability and low latency operations, among other benefits by appending cyclic redundancy check bits to subsets of information bits in forward error correction streams.

A method of wireless communication is described. The method may include dividing a set of information bits into a first subset of information bits associated with a first forward error correction stream and a second subset of information bits associated with a second forward error correction stream, processing, at the first forward error correction stream, the first subset of information bits by appending a first set of one or more cyclic redundancy check bits to the first subset of information bits and encoding the first subset of information bits in accordance with a first forward error correction scheme, processing, at the second forward error correction stream, the second subset of information bits by encoding the second subset of information bits in accordance with a second forward error correction scheme, and transmitting one or more modulation symbols carrying the processed first subset of information bits and the processed second subset of information bits.

An apparatus for wireless communication is described. The apparatus may include a processor, memory coupled with the processor, and instructions stored in the memory. The instructions may be executable by the processor to cause the apparatus to divide a set of information bits into a first subset of information bits associated with a first forward error correction stream and a second subset of information bits associated with a second forward error correction stream, process, at the first forward error correction stream, the first subset of information bits by appending a first set of one or more cyclic redundancy check bits to the first subset of information bits and encoding the first subset of information bits in accordance with a first forward error correction scheme, process, at the second forward error correction stream, the second subset of information bits by encoding the second subset of information bits in accordance with a second forward error correction scheme, and transmit one or more modulation symbols carrying the processed first subset of information bits and the processed second subset of information bits.

Another apparatus for wireless communication is described. The apparatus may include means for dividing a set of information bits into a first subset of information bits associated with a first forward error correction stream and a second subset of information bits associated with a second forward error correction stream, processing, at the first forward error correction stream, the first subset of information bits by appending a first set of one or more cyclic redundancy check bits to the first subset of information bits and encoding the first subset of information bits in accordance with a first forward error correction scheme, processing, at the second forward error correction stream, the second subset of information bits by encoding the second subset of information bits in accordance with a second forward error correction scheme, and transmitting one or more modulation symbols carrying the processed first subset of information bits and the processed second subset of information bits.

A non-transitory computer-readable medium storing code for wireless communication is described. The code may include instructions executable by a processor to divide a set of information bits into a first subset of information bits associated with a first forward error correction stream and a second subset of information bits associated with a second forward error correction stream, process, at the first forward error correction stream, the first subset of information bits by appending a first set of one or more cyclic redundancy check bits to the first subset of information bits and encoding the first subset of information bits in accordance with a first forward error correction scheme, process, at the second forward error correction stream, the second subset of information bits by encoding the second subset of information bits in accordance with a second forward error correction scheme, and transmit one or more modulation symbols carrying the processed first subset of information bits and the processed second subset of information bits.

Some examples of the method, apparatuses, and non-transitory computer-readable medium described herein may further include operations, features, means, or instructions for appending a second set of one or more cyclic redundancy check bits to the set of information bits prior to processing at the first forward error correction stream and at the second forward error correction stream.

In some examples of the method, apparatuses, and non-transitory computer-readable medium described herein, a length of the second set of one or more cyclic redundancy check bits appended to the set of information bits may be greater than a length of the first set of one or more cyclic redundancy check bits.

In some examples of the method, apparatuses, and non-transitory computer-readable medium described herein, processing, at the first forward error correction stream, the first subset of information bits may include operations, features, means, or instructions for appending the first set of one or more cyclic redundancy check bits to the first subset of information bits before encoding the first subset of information bits in accordance with the first forward error correction scheme.

In some examples of the method, apparatuses, and non-transitory computer-readable medium described herein, the first set of one or more cyclic redundancy check bits includes an indication for early termination associated with decoding one or more of the one or more modulation symbols carrying the processed first subset of information bits or the processed second subset of information bits.

In some examples of the method, apparatuses, and non-transitory computer-readable medium described herein, the first set of one or more cyclic redundancy check bits includes an indication for partial retransmission of one or more of the one or more modulation symbols carrying the processed first subset of information bits or the processed second subset of information bits.

In some examples of the method, apparatuses, and non-transitory computer-readable medium described herein, processing, at the second forward error correction stream, the second subset of information bits may include operations, features, means, or instructions for appending a second set of one or more cyclic redundancy check bits to the second subset of information bits before encoding the second subset of information bits in accordance with the second forward error correction scheme.

In some examples of the method, apparatuses, and non-transitory computer-readable medium described herein, the second set of one or more cyclic redundancy check bits includes an indication for early termination associated with decoding one or more of the one or more modulation symbols carrying the processed first subset of information bits or the processed second subset of information bits.

In some examples of the method, apparatuses, and non-transitory computer-readable medium described herein, the second set of one or more cyclic redundancy check bits includes an indication for partial retransmission of one or more of the one or more modulation symbols carrying the processed first subset of information bits or the processed second subset of information bits.

In some examples of the method, apparatuses, and non-transitory computer-readable medium described herein, the first forward error correction scheme may be different from the second forward error correction scheme.

Some examples of the method, apparatuses, and non-transitory computer-readable medium described herein may further include operations, features, means, or instructions for retransmitting the one or more modulation symbols carrying the processed first subset of information bits and the processed second subset of information bits based on a feedback including a negative acknowledgment.

Some examples of the method, apparatuses, and non-transitory computer-readable medium described herein may further include operations, features, means, or instructions for modulating, in accordance with a modulation scheme, the processed first subset of information bits and the processed second subset of information bits, , and where transmitting the one or more modulation symbols carrying the processed first subset of information bits and the processed second subset of information bits may be based on the modulating.

In some examples of the method, apparatuses, and non-transitory computer-readable medium described herein, modulating the processed first subset of information bits may include operations, features, means, or instructions for mapping the processed first subset of information bits to an inner constellation associated with the modulation scheme.

In some examples of the method, apparatuses, and non-transitory computer-readable medium described herein, modulating the processed second subset of information bits may include operations, features, means, or instructions for mapping the processed second subset of information bits to an outer constellation associated with the modulation scheme.

In some examples of the method, apparatuses, and non-transitory computer-readable medium described herein, the modulation scheme includes a quadrature amplitude modulation (QAM) or a quadrature phase shift keying (QPSK) .

A method of wireless communication is described. The method may include dividing a set of processed information bits into a first subset of information bits associated with a first forward error correction stream and a second subset of information bits associated with a second forward error correction stream, processing, at a first forward error correction stream, the first subset of information bits by decoding a first set of one or more cyclic redundancy check bits of the first subset of information bits and decoding the first subset of information bits in accordance with the first forward error correction scheme, and processing, at a second forward error correction stream, the second subset of information bits based on decoding the first set of one or more cyclic redundancy check bits of the first subset of information bits.

An apparatus for wireless communication is described. The apparatus may include a processor, memory coupled with the processor, and instructions stored in the memory. The instructions may be executable by the processor to cause the apparatus to divide a set of processed information bits into a first subset of information bits associated with a first forward error correction stream and a second subset of information bits associated with a second forward error correction stream, process, at a first forward error correction stream, the first subset of information bits by decoding a first set of one or more cyclic redundancy check bits of the first subset of information bits and decoding the first subset of information bits in accordance with the first forward error correction scheme, and process, at a second forward error correction stream, the second subset of information bits based on decoding the first set of one or more cyclic redundancy check bits of the first subset of information bits.

Another apparatus for wireless communication is described. The apparatus may include means for dividing a set of processed information bits into a first subset of information bits associated with a first forward error correction stream and a second subset of information bits associated with a second forward error correction stream, processing, at a first forward error correction stream, the first subset of information bits by decoding a first set of one or more cyclic redundancy check bits of the first subset of information bits and decoding the first subset of information bits in accordance with the first forward error correction scheme, and processing, at a second forward error correction stream, the second subset of information bits based on decoding the first set of one or more cyclic redundancy check bits of the first subset of information bits.

A non-transitory computer-readable medium storing code for wireless communication is described. The code may include instructions executable by a processor to divide a set of processed information bits into a first subset of information bits associated with a first forward error correction stream and a second subset of information bits associated with a second forward error correction stream, process, at a first forward error correction stream, the first subset of information bits by decoding a first set of one or more cyclic redundancy check bits of the first subset of information bits and decoding the first subset of information bits in accordance with the first forward error correction scheme, and process, at a second forward error correction stream, the second subset of information bits based on decoding the first set of one or more cyclic redundancy check bits of the first subset of information bits.

In some examples of the method, apparatuses, and non-transitory computer-readable medium described herein, processing, at the second forward error correction stream, the second subset of information bits may include operations, features, means, or instructions for terminating decoding the second subset of information bits based on a failure to decode the first set of one or more cyclic redundancy check bits of the first subset of information bits.

Some examples of the method, apparatuses, and non-transitory computer-readable medium described herein may further include operations, features, means, or instructions for transmitting a feedback including a negative acknowledgment associated with the failure to decode the first set of one or more cyclic redundancy check bits of the first subset of information bits.

In some examples of the method, apparatuses, and non-transitory computer-readable medium described herein, processing, at the second forward error correction stream, the second subset of information bits may include operations, features, means, or instructions for decoding a second set of one or more cyclic redundancy check bits of the second subset of information bits and decoding the second subset of information bits in accordance with the second forward error correction scheme based on successfully decoding the first set of one or more cyclic redundancy check bits of the first subset of information bits.

Some examples of the method, apparatuses, and non-transitory computer-readable medium described herein may further include operations, features, means, or instructions for demodulating, in accordance with a demodulation scheme, the one or more modulation symbols carrying the set of processed information bits, where dividing the one or more modulation symbols carrying the set of processed information bits may be based on the demodulating.

In some examples of the method, apparatuses, and non-transitory computer-readable medium described herein, the demodulation scheme includes a QAM or a QPSK.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGs. 1 and 2 illustrate examples of wireless communications systems that support cyclic redundancy check schemes for unequal error protection with forward error corrections in accordance with aspects of the present disclosure.

FIGs. 3 through 7 illustrate examples of block diagrams of devices that support cyclic redundancy check schemes for unequal error protection with forward error corrections in accordance with aspects of the present disclosure.

FIGs. 8 and 9 show block diagrams of devices that support cyclic redundancy check schemes for unequal error protection with forward error corrections in accordance with aspects of the present disclosure.

FIG. 10 shows a block diagram of a communications manager that supports cyclic redundancy check schemes for unequal error protection with forward error corrections in accordance with aspects of the present disclosure.

FIG. 11 shows a diagram of a system including a device that supports cyclic redundancy check schemes for unequal error protection with forward error corrections in accordance with aspects of the present disclosure.

FIGs. 12 through 17 show flowcharts illustrating methods that support cyclic redundancy check schemes for unequal error protection with forward error corrections in accordance with aspects of the present disclosure.

DETAILED DESCRIPTION

Some wireless communication systems may include one or more communication devices, such as user equipments (UEs) and base stations, for example, next-generation NodeBs or giga-NodeBs (either of which may be referred to as a gNB) that may support multiple radio access technologies including 4G systems such as Long Term Evolution (LTE) systems, fifth generation (5G) systems which may be referred to as New Radio (NR) systems. The communication devices may be configured, in some examples, to encode a set of information bits with one or more cyclic redundancy check bits to protect all the information bits of the set. A set of information bits may be represented as one or more bits b ₀b ₁b ₂…b _n, where b represents individual bits. After encoding the set of information bits with the one or more cyclic redundancy check bits, the communication devices may process the information bits by dividing the information bits into multiple subsets of information bits (e.g., at least two subsets of information bits) to process the subsets separately. Alternatively, in some examples, the communication devices may ignore (e.g., skip) encoding the set of information bits with the one or more cyclic redundancy check bits and directly distribute the information bits into the multiple subsets.

The communication devices may handle each subset separately. For example, the communication devices may encode a first subset of information bits with a first forward error correction scheme and a second subset of information bits with a second error correction scheme. The communication devices may use the forward error correction schemes to enhance the reliability of transmitting the first subset of information bits and the second subset of information bits by including redundant data (e.g. redundant bits) called error correcting code, prior to data transmission or storage. The communication devices may then modulate a processed first subset of information bits associated with the first stream and a processed second subset of information bits associated with the second stream by mapping the processed first subset of information bits and the processed second subset of information bits to one or more symbols.

In some examples, the communication devices may append a first set of one or more cyclic redundancy check bits to the first subset of information bits before encoding the first subset of information bits in accordance with the first forward error correction scheme. Additionally, or alternatively, the communication devices may append a second set of one or more cyclic redundancy check bits to the second subset of information bits before encoding the second subset of information bits in accordance with the second forward error correction scheme. In some other examples, the communication devices may append one or more cyclic redundancy check bits to the first subset of information bits or the second subset of information bits after appending one or more cyclic redundancy check bits to the set of information bits.

Particular aspects of the subject matter described in this disclosure may be implemented to realize one or more of the following potential advantages. The techniques employed by the described one or more communication devices may provide benefits and enhancements to the operation of the communication devices. For example, operations performed by the described one or more communication devices may provide improvements to wireless operations. In some examples, the described one or more communication devices may support high reliability and low latency communications, among other examples, in accordance with one or more cyclic redundancy check schemes for unequal error protection with forward error corrections. The described techniques may thus include features for improvements to power consumption, spectral efficiency, higher data rates and, in some examples, may promote enhanced efficiency for high reliability and low latency operations, among other benefits.

By way of example, the described one or more communication devices may encode one or more subset of information bits, associated with different forward error correction streams, with one or more cyclic redundancy check bits. The encoded (e.g., appended) cyclic redundancy check bits to the subset of information bits may be used for early termination or partial retransmission of the bits. For example, the described one or more communication devices may, in some examples, decode a subset of information bits with appended cyclic redundancy check bits and associated with one of many forward error correction streams. If the described one or more communication devices successfully decode the cyclic redundancy check bits, the described one or more communication devices may continue to process the subset of information bits. Otherwise, the described one or more communication devices may perform an early termination (e.g., abandon decoding other subset of information bits associated with other forward error correction streams) to conserve resources (e.g., battery life) . Additionally, or alternatively, the described one or more communication devices may receive a partial retransmission of the subset of information bits based on a failure to decode the cyclic redundancy check bits. Thereby, also reducing latency in wireless operations by supporting partial retransmission rather than pending a failure of all subsets of information bits.

Aspects of the disclosure are initially described in the context of wireless communications systems. Aspects of the disclosure are then illustrated by and described with reference to a process flow that relates to cyclic redundancy check schemes for unequal error protection with forward error corrections. Aspects of the disclosure are further illustrated by and described with reference to apparatus diagrams, system diagrams, and flowcharts that relate to cyclic redundancy check schemes for unequal error protection with forward error corrections in wireless communications systems.

FIG. 1 illustrates an example of a wireless communications system 100 that supports cyclic redundancy check schemes for unequal error protection with forward error corrections in accordance with aspects of the present disclosure. The wireless communications system 100 may include one or more base stations 105, one or more UEs 115, and a core network 130. In some examples, the wireless communications system 100 may be a Long Term Evolution (LTE) network, an LTE-Advanced (LTE-A) network, an LTE-A Pro network, or a New Radio (NR) network. In some examples, the wireless communications system 100 may support enhanced broadband communications, ultra-reliable (e.g., mission critical) communications, low latency communications, communications with low-cost and low-complexity devices, or any combination thereof.

The base stations 105 may be dispersed throughout a geographic area to form the wireless communications system 100 and may be devices in different forms or having different capabilities. The base stations 105 and the UEs 115 may wirelessly communicate via one or more communication links 125. Each base station 105 may provide a coverage area 110 over which the UEs 115 and the base station 105 may establish one or more communication links 125. The coverage area 110 may be an example of a geographic area over which a base station 105 and a UE 115 may support the communication of signals according to one or more radio access technologies.

The UEs 115 may be dispersed throughout a coverage area 110 of the wireless communications system 100, and each UE 115 may be stationary, or mobile, or both at different times. The UEs 115 may be devices in different forms or having different capabilities. Some example UEs 115 are illustrated in FIG. 1. The UEs 115 described herein may be able to communicate with various types of devices, such as other UEs 115, the base stations 105, or network equipment (e.g., core network nodes, relay devices, integrated access and backhaul (IAB) nodes, or other network equipment) , as shown in FIG. 1.

The base stations 105 may communicate with the core network 130, or with one another, or both. For example, the base stations 105 may interface with the core network 130 through one or more backhaul links 120 (e.g., via an S1, N2, N3, or other interface) . The base stations 105 may communicate with one another over the backhaul links 120 (e.g., via an X2, Xn, or other interface) either directly (e.g., directly between base stations 105) , or indirectly (e.g., via core network 130) , or both. In some examples, the backhaul links 120 may be or include one or more wireless links.

One or more of the base stations 105 described herein may include or may be referred to by a person having ordinary skill in the art as a base transceiver station, a radio base station, an access point, a radio transceiver, a NodeB, an eNodeB (eNB) , a next-generation NodeB or a giga-NodeB (either of which may be referred to as a gNB) , a Home NodeB, a Home eNodeB, or other suitable terminology.

A UE 115 may include or may be referred to as a mobile device, a wireless device, a remote device, a handheld device, or a subscriber device, or some other suitable terminology, where the “device” may also be referred to as a unit, a station, a terminal, or a client, among other examples. A UE 115 may also include or may be referred to as a personal electronic device such as a cellular phone, a personal digital assistant (PDA) , a tablet computer, a laptop computer, or a personal computer. In some examples, a UE 115 may include or be referred to as a wireless local loop (WLL) station, an Internet of Things (IoT) device, an Internet of Everything (IoE) device, or a machine type communications (MTC) device, among other examples, which may be implemented in various objects such as appliances, or vehicles, meters, among other examples.

The UEs 115 described herein may be able to communicate with various types of devices, such as other UEs 115 that may sometimes act as relays as well as the base stations 105 and the network equipment including macro eNBs or gNBs, small cell eNBs or gNBs, or relay base stations, among other examples, as shown in FIG. 1.

The UEs 115 and the base stations 105 may wirelessly communicate with one another via one or more communication links 125 over one or more carriers. The term “carrier” may refer to a set of radio frequency spectrum resources having a defined physical layer structure for supporting the communication links 125. For example, a carrier used for a communication link 125 may include a portion of a radio frequency spectrum band (e.g., a bandwidth part (BWP) ) that is operated according to one or more physical layer channels for a given radio access technology (e.g., LTE, LTE-A, LTE-A Pro, NR) . Each physical layer channel may carry acquisition signaling (e.g., synchronization signals, system information) , control signaling that coordinates operation for the carrier, user data, or other signaling. The wireless communications system 100 may support communication with a UE 115 using carrier aggregation or multi-carrier operation. A UE 115 may be configured with multiple downlink component carriers and one or more uplink component carriers according to a carrier aggregation configuration. Carrier aggregation may be used with both frequency division duplexing (FDD) and time division duplexing (TDD) component carriers.

In some examples (e.g., in a carrier aggregation configuration) , a carrier may also have acquisition signaling or control signaling that coordinates operations for other carriers. A carrier may be associated with a frequency channel (e.g., an evolved universal mobile telecommunication system terrestrial radio access (E-UTRA) absolute radio frequency channel number (EARFCN) ) and may be positioned according to a channel raster for discovery by the UEs 115. A carrier may be operated in a standalone mode where initial acquisition and connection may be conducted by the UEs 115 via the carrier, or the carrier may be operated in a non-standalone mode where a connection is anchored using a different carrier (e.g., of the same or a different radio access technology) .

The communication links 125 shown in the wireless communications system 100 may include uplink transmissions from a UE 115 to a base station 105, or downlink transmissions from a base station 105 to a UE 115. Carriers may carry downlink or uplink communications (e.g., in an FDD mode) or may be configured to carry downlink and uplink communications (e.g., in a TDD mode) .

A carrier may be associated with a particular bandwidth of the radio frequency spectrum, and in some examples the carrier bandwidth may be referred to as a “system bandwidth” of the carrier or the wireless communications system 100. For example, the carrier bandwidth may be one of a number of determined bandwidths for carriers of a particular radio access technology (e.g., 1.4, 3, 5, 10, 15, 20, 40, or 80 megahertz (MHz) ) . Devices of the wireless communications system 100 (e.g., the base stations 105, the UEs 115, or both) may have hardware configurations that support communications over a particular carrier bandwidth or may be configurable to support communications over one of a set of carrier bandwidths. In some examples, the wireless communications system 100 may include base stations 105 or UEs 115 that support simultaneous communications via carriers associated with multiple carrier bandwidths. In some examples, each served UE 115 may be configured for operating over portions (e.g., a sub-band, a BWP) or all of a carrier bandwidth.

Signal waveforms transmitted over a carrier may be made up of multiple subcarriers (e.g., using multi-carrier modulation (MCM) techniques such as orthogonal frequency division multiplexing (OFDM) or discrete Fourier transform spread OFDM (DFT-S-OFDM) ) . In a system employing MCM techniques, a resource element may consist of one symbol period (e.g., a duration of one modulation symbol) and one subcarrier, where the symbol period and subcarrier spacing are inversely related. The number of bits carried by each resource element may depend on the modulation scheme (e.g., the order of the modulation scheme, the coding rate of the modulation scheme, or both) . Thus, the more resource elements that a UE 115 receives and the higher the order of the modulation scheme, the higher the data rate may be for the UE 115. A wireless communications resource may refer to a combination of a radio frequency spectrum resource, a time resource, and a spatial resource (e.g., spatial layers or beams) , and the use of multiple spatial layers may further increase the data rate or data integrity for communications with a UE 115.

One or more numerologies for a carrier may be supported, where a numerology may include a subcarrier spacing (Δf) and a cyclic prefix. A carrier may be divided into one or more BWPs having the same or different numerologies. In some examples, a UE 115 may be configured with multiple BWPs. In some examples, a single BWP for a carrier may be active at a given time and communications for the UE 115 may be restricted to one or more active BWPs.

The time intervals for the base stations 105 or the UEs 115 may be expressed in multiples of a basic time unit which may, for example, refer to a sampling period of T _s=1/ (Δf _maxN _f) seconds, where Δf _max may represent the maximum supported subcarrier spacing, and N _f may represent the maximum supported discrete Fourier transform (DFT) size. Time intervals of a communications resource may be organized according to radio frames each having a specified duration (e.g., 10 milliseconds (ms) ) . Each radio frame may be identified by a system frame number (SFN) (e.g., ranging from 0 to 1023) .

Each frame may include multiple consecutively numbered subframes or slots, and each subframe or slot may have the same duration. In some examples, a frame may be divided (e.g., in the time domain) into subframes, and each subframe may be further divided into a number of slots. Alternatively, each frame may include a variable number of slots, and the number of slots may depend on subcarrier spacing. Each slot may include a number of symbol periods (e.g., depending on the length of the cyclic prefix prepended to each symbol period) . In some wireless communications systems 100, a slot may further be divided into multiple mini-slots containing one or more symbols. Excluding the cyclic prefix, each symbol period may contain one or more (e.g., N _f) sampling periods. The duration of a symbol period may depend on the subcarrier spacing or frequency band of operation.

A subframe, a slot, a mini-slot, or a symbol may be the smallest scheduling unit (e.g., in the time domain) of the wireless communications system 100 and may be referred to as a transmission time interval (TTI) . In some examples, the TTI duration (e.g., the number of symbol periods in a TTI) may be variable. Additionally or alternatively, the smallest scheduling unit of the wireless communications system 100 may be dynamically selected (e.g., in bursts of shortened TTIs (sTTIs) ) .

In some examples, base stations 105 and/or UEs 115 may divide a set of information bits into a first subset of information bits associated with a first forward error correction stream and a second subset of information bits associated with a second forward error correction stream. The base stations 105 and/or UEs 115 may process, at the first forward error correction stream, the first subset by appending a first set of one or more cyclic redundancy check bits to the first subset and encoding the first subset in accordance with a first forward error correction scheme. Additionally, the base stations 105 and/or UEs 115 may process, at the second forward error correction stream, the second subset by encoding the second subset in accordance with a second forward error correction scheme. The base stations 105 and/or UEs 115 may transmit one or more modulation symbols carrying the processed first subset and the processed second subset.

Physical channels may be multiplexed on a carrier according to various techniques. A physical control channel and a physical data channel may be multiplexed on a downlink carrier, for example, using one or more of time division multiplexing (TDM) techniques, frequency division multiplexing (FDM) techniques, or hybrid TDM-FDM techniques. A control region (e.g., a control resource set (CORESET) ) for a physical control channel may be defined by a number of symbol periods and may extend across the system bandwidth or a subset of the system bandwidth of the carrier. One or more control regions (e.g., CORESETs) may be configured for a set of the UEs 115. For example, one or more of the UEs 115 may monitor or search control regions for control information according to one or more search space sets, and each search space set may include one or multiple control channel candidates in one or more aggregation levels arranged in a cascaded manner. An aggregation level for a control channel candidate may refer to a number of control channel resources (e.g., control channel elements (CCEs) ) associated with encoded information for a control information format having a given payload size. Search space sets may include common search space sets configured for sending control information to multiple UEs 115 and UE-specific search space sets for sending control information to a specific UE 115.

Each base station 105 may provide communication coverage via one or more cells, for example a macro cell, a small cell, a hot spot, or other types of cells, or any combination thereof. The term “cell” may refer to a logical communication entity used for communication with a base station 105 (e.g., over a carrier) and may be associated with an identifier for distinguishing neighboring cells (e.g., a physical cell identifier (PCID) , a virtual cell identifier (VCID) , or others) . In some examples, a cell may also refer to a geographic coverage area 110 or a portion of a geographic coverage area 110 (e.g., a sector) over which the logical communication entity operates. Such cells may range from smaller areas (e.g., a structure, a subset of structure) to larger areas depending on various factors such as the capabilities of the base station 105. For example, a cell may be or include a building, a subset of a building, or exterior spaces between or overlapping with geographic coverage areas 110, among other examples.

A macro cell generally covers a relatively large geographic area (e.g., several kilometers in radius) and may allow unrestricted access by the UEs 115 with service subscriptions with the network provider supporting the macro cell. A small cell may be associated with a lower-powered base station 105, as compared with a macro cell, and a small cell may operate in the same or different (e.g., licensed, unlicensed) frequency bands as macro cells. Small cells may provide unrestricted access to the UEs 115 with service subscriptions with the network provider or may provide restricted access to the UEs 115 having an association with the small cell (e.g., the UEs 115 in a closed subscriber group (CSG) , the UEs 115 associated with users in a home or office) . A base station 105 may support one or multiple cells and may also support communications over the one or more cells using one or multiple component carriers.

In some examples, a carrier may support multiple cells, and different cells may be configured according to different protocol types (e.g., MTC, narrowband IoT (NB-IoT) , enhanced mobile broadband (eMBB) ) that may provide access for different types of devices.

In some examples, a base station 105 may be movable and therefore provide communication coverage for a moving geographic coverage area 110. In some examples, different geographic coverage areas 110 associated with different technologies may overlap, but the different geographic coverage areas 110 may be supported by the same base station 105. In other examples, the overlapping geographic coverage areas 110 associated with different technologies may be supported by different base stations 105. The wireless communications system 100 may include, for example, a heterogeneous network in which different types of the base stations 105 provide coverage for various geographic coverage areas 110 using the same or different radio access technologies.

The wireless communications system 100 may support synchronous or asynchronous operation. For synchronous operation, the base stations 105 may have similar frame timings, and transmissions from different base stations 105 may be approximately aligned in time. For asynchronous operation, the base stations 105 may have different frame timings, and transmissions from different base stations 105 may, in some examples, not be aligned in time. The techniques described herein may be used for either synchronous or asynchronous operations.

Some UEs 115, such as MTC or IoT devices, may be low cost or low complexity devices and may provide for automated communication between machines (e.g., via Machine-to-Machine (M2M) communication) . M2M communication or MTC may refer to data communication technologies that allow devices to communicate with one another or a base station 105 without human intervention. In some examples, M2M communication or MTC may include communications from devices that integrate sensors or meters to measure or capture information and relay such information to a central server or application program that makes use of the information or presents the information to humans interacting with the application program. Some UEs 115 may be designed to collect information or enable automated behavior of machines or other devices. Examples of applications for MTC devices include smart metering, inventory monitoring, water level monitoring, equipment monitoring, healthcare monitoring, wildlife monitoring, weather and geological event monitoring, fleet management and tracking, remote security sensing, physical access control, and transaction-based business charging.

Some UEs 115 may be configured to employ operating modes that reduce power consumption, such as half-duplex communications (e.g., a mode that supports one-way communication via transmission or reception, but not transmission and reception simultaneously) . In some examples, half-duplex communications may be performed at a reduced peak rate. Other power conservation techniques for the UEs 115 include entering a power saving deep sleep mode when not engaging in active communications, operating over a limited bandwidth (e.g., according to narrowband communications) , or a combination of these techniques. For example, some UEs 115 may be configured for operation using a narrowband protocol type that is associated with a defined portion or range (e.g., set of subcarriers or resource blocks (RBs) ) within a carrier, within a guard-band of a carrier, or outside of a carrier.

The wireless communications system 100 may be configured to support ultra-reliable communications or low-latency communications, or various combinations thereof. For example, the wireless communications system 100 may be configured to support ultra-reliable low-latency communications (URLLC) or mission critical communications. The UEs 115 may be designed to support ultra-reliable, low-latency, or critical functions (e.g., mission critical functions) . Ultra-reliable communications may include private communication or group communication and may be supported by one or more mission critical services such as mission critical push-to-talk (MCPTT) , mission critical video (MCVideo) , or mission critical data (MCData) . Support for mission critical functions may include prioritization of services, and mission critical services may be used for public safety or general commercial applications. The terms ultra-reliable, low-latency, mission critical, and ultra-reliable low-latency may be used interchangeably herein.

In some examples, a UE 115 may also be able to communicate directly with other UEs 115 over a device-to-device (D2D) communication link 135 (e.g., using a peer-to-peer (P2P) or D2D protocol) . One or more UEs 115 utilizing D2D communications may be within the geographic coverage area 110 of a base station 105. Other UEs 115 in such a group may be outside the geographic coverage area 110 of a base station 105 or be otherwise unable to receive transmissions from a base station 105. In some examples, groups of the UEs 115 communicating via D2D communications may utilize a one-to-many (1: M) system in which each UE 115 transmits to every other UE 115 in the group. In some examples, a base station 105 facilitates the scheduling of resources for D2D communications. In other cases, D2D communications are carried out between the UEs 115 without the involvement of a base station 105.

In some systems, the D2D communication link 135 may be an example of a communication channel, such as a sidelink communication channel, between vehicles (e.g., UEs 115) . In some examples, vehicles may communicate using vehicle-to-everything (V2X) communications, vehicle-to-vehicle (V2V) communications, or some combination of these. A vehicle may signal information related to traffic conditions, signal scheduling, weather, safety, emergencies, or any other information relevant to a V2X system. In some examples, vehicles in a V2X system may communicate with roadside infrastructure, such as roadside units, or with the network via one or more network nodes (e.g., base stations 105) using vehicle-to-network (V2N) communications, or with both.

The core network 130 may provide user authentication, access authorization, tracking, Internet Protocol (IP) connectivity, and other access, routing, or mobility functions. The core network 130 may be an evolved packet core (EPC) or 5G core (5GC) , which may include at least one control plane entity that manages access and mobility (e.g., a mobility management entity (MME) , an access and mobility management function (AMF) ) and at least one user plane entity that routes packets or interconnects to external networks (e.g., a serving gateway (S-GW) , a Packet Data Network (PDN) gateway (P-GW) , or a user plane function (UPF) ) . The control plane entity may manage non-access stratum (NAS) functions such as mobility, authentication, and bearer management for the UEs 115 served by the base stations 105 associated with the core network 130. User IP packets may be transferred through the user plane entity, which may provide IP address allocation as well as other functions. The user plane entity may be connected to the network operators IP services 150. The operators IP services 150 may include access to the Internet, Intranet (s) , an IP Multimedia Subsystem (IMS) , or a Packet-Switched Streaming Service.

Some of the network devices, such as a base station 105, may include subcomponents such as an access network entity 140, which may be an example of an access node controller (ANC) . Each access network entity 140 may communicate with the UEs 115 through one or more other access network transmission entities 145, which may be referred to as radio heads, smart radio heads, or transmission/reception points (TRPs) . Each access network transmission entity 145 may include one or more antenna panels. In some configurations, various functions of each access network entity 140 or base station 105 may be distributed across various network devices (e.g., radio heads and ANCs) or consolidated into a single network device (e.g., a base station 105) .

The wireless communications system 100 may operate using one or more frequency bands, typically in the range of 300 megahertz (MHz) to 300 gigahertz (GHz) . Generally, the region from 300 MHz to 3 GHz is known as the ultra-high frequency (UHF) region or decimeter band because the wavelengths range from approximately one decimeter to one meter in length. The UHF waves may be blocked or redirected by buildings and environmental features, but the waves may penetrate structures sufficiently for a macro cell to provide service to the UEs 115 located indoors. The transmission of UHF waves may be associated with smaller antennas and shorter ranges (e.g., less than 100 kilometers) compared to transmission using the smaller frequencies and longer waves of the high frequency (HF) or very high frequency (VHF) portion of the spectrum below 300 MHz.

The wireless communications system 100 may also operate in a super high frequency (SHF) region using frequency bands from 3 GHz to 30 GHz, also known as the centimeter band, or in an extremely high frequency (EHF) region of the spectrum (e.g., from 30 GHz to 300 GHz) , also known as the millimeter band. In some examples, the wireless communications system 100 may support millimeter wave (mmW) communications between the UEs 115 and the base stations 105, and EHF antennas of the respective devices may be smaller and more closely spaced than UHF antennas. In some examples, this may facilitate use of antenna arrays within a device. The propagation of EHF transmissions, however, may be subject to even greater atmospheric attenuation and shorter range than SHF or UHF transmissions. The techniques disclosed herein may be employed across transmissions that use one or more different frequency regions, and designated use of bands across these frequency regions may differ by country or regulating body.

The wireless communications system 100 may utilize both licensed and unlicensed radio frequency spectrum bands. For example, the wireless communications system 100 may employ License Assisted Access (LAA) , LTE-Unlicensed (LTE-U) radio access technology, or NR technology in an unlicensed band such as the 5 GHz industrial, scientific, and medical (ISM) band. When operating in unlicensed radio frequency spectrum bands, devices such as the base stations 105 and the UEs 115 may employ carrier sensing for collision detection and avoidance. In some examples, operations in unlicensed bands may be based on a carrier aggregation configuration in conjunction with component carriers operating in a licensed band (e.g., LAA) . Operations in unlicensed spectrum may include downlink transmissions, uplink transmissions, P2P transmissions, or D2D transmissions, among other examples.

A base station 105 or a UE 115 may be equipped with multiple antennas, which may be used to employ techniques such as transmit diversity, receive diversity, multiple-input multiple-output (MIMO) communications, or beamforming. The antennas of a base station 105 or a UE 115 may be located within one or more antenna arrays or antenna panels, which may support MIMO operations or transmit or receive beamforming. For example, one or more base station antennas or antenna arrays may be co-located at an antenna assembly, such as an antenna tower. In some examples, antennas or antenna arrays associated with a base station 105 may be located in diverse geographic locations. A base station 105 may have an antenna array with a number of rows and columns of antenna ports that the base station 105 may use to support beamforming of communications with a UE 115. Likewise, a UE 115 may have one or more antenna arrays that may support various MIMO or beamforming operations. Additionally or alternatively, an antenna panel may support radio frequency beamforming for a signal transmitted via an antenna port.

The base stations 105 or the UEs 115 may use MIMO communications to exploit multipath signal propagation and increase the spectral efficiency by transmitting or receiving multiple signals via different spatial layers. Such techniques may be referred to as spatial multiplexing. The multiple signals may, for example, be transmitted by the transmitting device via different antennas or different combinations of antennas. Likewise, the multiple signals may be received by the receiving device via different antennas or different combinations of antennas. Each of the multiple signals may be referred to as a separate spatial stream and may carry bits associated with the same data stream (e.g., the same codeword) or different data streams (e.g., different codewords) . Different spatial layers may be associated with different antenna ports used for channel measurement and reporting. MIMO techniques include single-user MIMO (SU-MIMO) , where multiple spatial layers are transmitted to the same receiving device, and multiple-user MIMO (MU-MIMO) , where multiple spatial layers are transmitted to multiple devices.

Beamforming, which may also be referred to as spatial filtering, directional transmission, or directional reception, is a signal processing technique that may be used at a transmitting device or a receiving device (e.g., a base station 105, a UE 115) to shape or steer an antenna beam (e.g., a transmit beam, a receive beam) along a spatial path between the transmitting device and the receiving device. Beamforming may be achieved by combining the signals communicated via antenna elements of an antenna array such that some signals propagating at particular orientations with respect to an antenna array experience constructive interference while others experience destructive interference. The adjustment of signals communicated via the antenna elements may include a transmitting device or a receiving device applying amplitude offsets, phase offsets, or both to signals carried via the antenna elements associated with the device. The adjustments associated with each of the antenna elements may be defined by a beamforming weight set associated with a particular orientation (e.g., with respect to the antenna array of the transmitting device or receiving device, or with respect to some other orientation) .

A base station 105 or a UE 115 may use beam sweeping techniques as part of beam forming operations. For example, a base station 105 may use multiple antennas or antenna arrays (e.g., antenna panels) to conduct beamforming operations for directional communications with a UE 115. Some signals (e.g., synchronization signals, reference signals, beam selection signals, or other control signals) may be transmitted by a base station 105 multiple times in different directions. For example, the base station 105 may transmit a signal according to different beamforming weight sets associated with different directions of transmission. Transmissions in different beam directions may be used to identify (e.g., by a transmitting device, such as a base station 105, or by a receiving device, such as a UE 115) a beam direction for later transmission or reception by the base station 105.

Some signals, such as data signals associated with a particular receiving device, may be transmitted by a base station 105 in a single beam direction (e.g., a direction associated with the receiving device, such as a UE 115) . In some examples, the beam direction associated with transmissions along a single beam direction may be determined based on a signal that was transmitted in one or more beam directions. For example, a UE 115 may receive one or more of the signals transmitted by the base station 105 in different directions and may report to the base station 105 an indication of the signal that the UE 115 received with a highest signal quality or an otherwise acceptable signal quality.

In some examples, transmissions by a device (e.g., by a base station 105 or a UE 115) may be performed using multiple beam directions, and the device may use a combination of digital precoding or radio frequency beamforming to generate a combined beam for transmission (e.g., from a base station 105 to a UE 115) . The UE 115 may report feedback that indicates precoding weights for one or more beam directions, and the feedback may correspond to a configured number of beams across a system bandwidth or one or more sub-bands. The base station 105 may transmit a reference signal (e.g., a cell-specific reference signal (CRS) , a channel state information reference signal (CSI-RS) ) , which may be precoded or unprecoded. The UE 115 may provide feedback for beam selection, which may be a precoding matrix indicator (PMI) or codebook-based feedback (e.g., a multi-panel type codebook, a linear combination type codebook, a port selection type codebook) . Although these techniques are described with reference to signals transmitted in one or more directions by a base station 105, a UE 115 may employ similar techniques for transmitting signals multiple times in different directions (e.g., for identifying a beam direction for subsequent transmission or reception by the UE 115) or for transmitting a signal in a single direction (e.g., for transmitting data to a receiving device) .

A receiving device (e.g., a UE 115) may try multiple receive configurations (e.g., directional listening) when receiving various signals from the base station 105, such as synchronization signals, reference signals, beam selection signals, or other control signals. For example, a receiving device may try multiple receive directions by receiving via different antenna subarrays, by processing received signals according to different antenna subarrays, by receiving according to different receive beamforming weight sets (e.g., different directional listening weight sets) applied to signals received at multiple antenna elements of an antenna array, or by processing received signals according to different receive beamforming weight sets applied to signals received at multiple antenna elements of an antenna array, any of which may be referred to as “listening” according to different receive configurations or receive directions. In some examples, a receiving device may use a single receive configuration to receive along a single beam direction (e.g., when receiving a data signal) . The single receive configuration may be aligned in a beam direction determined based on listening according to different receive configuration directions (e.g., a beam direction determined to have a highest signal strength, highest signal-to-noise ratio (SNR) , or otherwise acceptable signal quality based on listening according to multiple beam directions) .

The wireless communications system 100 may be a packet-based network that operates according to a layered protocol stack. In the user plane, communications at the bearer or Packet Data Convergence Protocol (PDCP) layer may be IP-based. A Radio Link Control (RLC) layer may perform packet segmentation and reassembly to communicate over logical channels. A Medium Access Control (MAC) layer may perform priority handling and multiplexing of logical channels into transport channels. The MAC layer may also use error detection techniques, error correction techniques, or both to support retransmissions at the MAC layer to improve link efficiency. In the control plane, the Radio Resource Control (RRC) protocol layer may provide establishment, configuration, and maintenance of an RRC connection between a UE 115 and a base station 105 or a core network 130 supporting radio bearers for user plane data. At the physical layer, transport channels may be mapped to physical channels.

The UEs 115 and the base stations 105 may support retransmissions of data to increase the likelihood that data is received successfully. Hybrid automatic repeat request (HARQ) feedback is one technique for increasing the likelihood that data is received correctly over a communication link 125. HARQ may include a combination of error detection (e.g., using a cyclic redundancy check (CRC) ) , forward error correction (FEC) , and retransmission (e.g., automatic repeat request (ARQ) ) . HARQ may improve throughput at the MAC layer in poor radio conditions (e.g., low signal-to-noise conditions) . In some examples, a device may support same-slot HARQ feedback, where the device may provide HARQ feedback in a specific slot for data received in a previous symbol in the slot. In other cases, the device may provide HARQ feedback in a subsequent slot, or according to some other time interval.

FIG. 2 illustrates an example of a wireless communications system 200 that supports cyclic redundancy check schemes for unequal error protection with forward error corrections in accordance with aspects of the present disclosure. The wireless communications system 200 may include a base station 105-a and a UE 115-a, which may be examples of the corresponding devices described with reference to FIG. 1. In some examples, the wireless communications system 200 may implement aspects of the wireless communications system 100. For example, the base station 105-a and the UE 115-a may support cyclic redundancy check schemes for unequal error protection with forward error corrections to use for early termination or partial retransmission. In some examples, one or more of the base station 105-a or the UE 115-a may be configured with one or more of an encoding pipeline 201 or a decoding pipeline 202 to support cyclic redundancy check schemes for unequal error protection with forward error corrections to use for early termination or partial retransmission. As a result, the base station 105-a and the UE 115-a may support improvements to power consumption, spectral efficiency, higher data rates and, in some examples, may promote enhanced efficiency for high reliability and low latency operations, among other benefits.

The encoding pipeline 201 may include a cyclic redundancy check component 210-a, a segmentation component 215-a, a cyclic redundancy check component 225-a, a cyclic redundancy check component 230-a, a forward error correction component 245-a, a forward error correction component 250-a, and a modulation component 255. The decoding pipeline 201 may include a de-modulation component 265, a cyclic redundancy check component 210-b, a segmentation component 215-b, a cyclic redundancy check component 225-b, a cyclic redundancy check component 230-b, a forward error correction component 245-b, a forward error correction component 250-b. Each of these components may be implemented in hardware, code (e.g., software or firmware) executed by a processor, or any combination thereof. If implemented in code executed by a processor, the functions of these components may be executed by a general-purpose processor, a DSP, an ASIC, a FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described in the present disclosure. Each of these components may be in communication with one another (e.g., via one or more buses) .

In some examples, one or more of the base station 105-a or the UE 115-a may generate a set of information bits related to user data, or control information associated with various information channels (e.g., control channels, data channels, etc. ) . For example, with reference to the encoding pipeline 201, one or more of the base station 105-a or the UE 115-a may generate a set of information bits 205 and pass the set of information bits 205 to other components of the encoding pipeline, such as the cyclic redundancy check component 210-a.

The cyclic redundancy check component 210-a may append one or more cyclic redundancy check bits to one or more bits of the set of information bits 205. In some examples, the one or more cyclic redundancy check bits may include a copy of one or more information bits of the set of information bits 2050 that may be appended to the ending of the set of information bits 205. One or more of the base station 105-a or the UE 115-a may thus encode one or more cyclic redundancy check bits to one or more bits of the set of information bits 205, prior to one or more error protection streams, to protect all the information bits 205. One or more of the base station 105-a or the UE 115-a may pass the information bits 205, appended with the one or more cyclic redundancy check bits, to other components of the encoding pipeline, such as the segmentation component 215-a. In some examples, the cyclic redundancy check component 210-a may be an optional component in the encoding pipeline. In this case, one or more of the base station 105-a or the UE 115-a may avoid appending the set of information bits 205 with the one or more cyclic redundancy check bits and directly pass the set of information bits 205 to the segmentation component 215-a.

The segmentation component 215-a may distribute the information bits 205, appended with a cyclic redundancy check, to one or more error protection streams associated with the encoding pipeline 201. For example, the segmentation component 215-a may segment and distribute a first subset of information bits of the set of information bits 205 to a first forward error correction stream 235-a and a second subset of information bits of the set of information bits 205 to a second forward error correction stream 240-a. The first forward error correction stream 235-a may correspond to the forward error correction component 245-a, while the second forward error correction stream 240-a may correspond to the forward error correction component 250-a. One or more of the base station 105-a or the UE 115-a may hence support unequal error protection by distributing the information bits 205 across multiple error protection streams.

In some examples, prior to processing the first subset of information bits of the set of information bits 205 by the forward error correction component 245-a, the segmentation component 215-a may pass the first subset of information bits to the cyclic redundancy check component 225-a, which may correspond to (e.g., be part of) the first forward error correction stream 235-a in the encoding pipeline 201. The cyclic redundancy check component 225-a may append a first set of one or more cyclic redundancy check bits to one or more bits of the first subset of information bits. In some examples, the first set of one or more cyclic redundancy check bits may include a copy of one or more information bits of the first subset of information bits that may be appended to the ending of the first subset of information bits. As such, the first set of one or more cyclic redundancy check bits appended (e.g., by the cyclic redundancy check component 225-a) to the ending of the first subset of information bits may be smaller in length (e.g., number of bits) compared to the set of one or more cyclic redundancy check bits appended to the ending of the set of information bits 205 (e.g., by the cyclic redundancy check component 215-a) . One or more of the base station 105-a or the UE 115-a may thus encode a first set of one or more cyclic redundancy check bits to one or more bits of the first subset of information bits, prior to forwarding the first subset to the forward error correction component 245-a, to further protect the information bits 205.

Additionally, in some examples, prior to processing the second subset of information bits of the set of information bits 205 by the forward error correction component 250-a, the segmentation component 215-a may pass the second subset of information bits to the cyclic redundancy check component 230-a, which may correspond to (e.g., be part of) the second forward error correction stream 240-a. The cyclic redundancy check component 230-a may append a second set of one or more cyclic redundancy check bits to one or more bits of the second subset of information bits. In some examples, the second set of one or more cyclic redundancy check bits may include a copy of one or more information bits of the second subset of information bits that may be appended to the ending of the second subset of information bits. As such, the second set of one or more cyclic redundancy check bits appended (e.g., by the cyclic redundancy check component 230-a) to the ending of the second subset of information bits may be smaller in length (e.g., number of bits) compared to the set of one or more cyclic redundancy check bits appended to the ending of the set of information bits 205 (e.g., by the cyclic redundancy check component 210-a) . One or more of the base station 105-a or the UE 115-a may thus encode the second set of one or more cyclic redundancy check bits to one or more bits of the second subset of information bits, prior to forwarding the second subset to the forward error correction component 250-a, to further protect the information bits 205. In some examples, the cyclic redundancy check component 230-a may be an optional component in the encoding pipeline.

One or more of the base station 105-a or the UE 115-a may pass the first subset of information bits, appended with multiple sets of one or more cyclic redundancy check bits, to other components of the encoding pipeline 201, such as the forward error correction component 245-a. Similarly, one or more of the base station 105-a or the UE 115-a may pass the second subset of information bits of the set of information bits 205, appended with multiple sets of one or more cyclic redundancy check bits, to the second forward error correction component 250-a. The forward error correction components 245-a, 250-a may support one or more forward error correction codes.

In some examples, the forward error correction component 245-a may encode the first subset of information bits of the set of information bits 205, appended with multiple sets of one or more cyclic redundancy check bits, in accordance with a first forward error correction code, and generate a first subset of processed information bits (e.g., c ₀c ₁c ₂c ₃... c _m, where m represents a number of coded bits according to the first forward error correction code) . In some examples, the forward error correction component 250-a may encode the second subset of information bits of the set of information bits 205, appended with multiple sets of one or more cyclic redundancy check bits, in accordance with a second forward error correction code, and generate a second subset of processed information bits (e.g., u ₀u ₁u ₂u ₃... u _n, where n represent a number of coded bits according to the first forward error correction code) . The second forward error correction code may, in some examples, be different from the first forward error correction code. In some other examples, the second forward error correction code and the first forward error correction code may be a same forward error correction code. One or more of the base station 105-a or the UE 115-a may thus support error protection of the information bits 205 by processing subsets of the information bits across multiple forward error correction streams.

One or more of the base station 105-a or the UE 115-a may pass the processed information bits to other components of the encoding pipeline 201, such as the modulation component 255. For example, the forward error correction components 245-a, 250-a may pass the first subset of processed information bits and the second subset of processed information bits to the modulation component 255. The modulation component 255 may modulate the first subset of processed information bits and the second subset of processed information bits, in accordance with a modulation scheme, to generate one or more modulation symbols 260. Each modulation symbol 260 may be represented by the first subset of processed information bits and the second subset of processed information bits (e.g., u ₀u ₁u ₂u ₃... u _n c ₀c ₁c ₂c ₃... c _m) .

In some examples, the modulation component 255 may map the first subset of processed information bits and the second subset of processed information bits to modulation symbols 260 in a constellation associated with a modulation scheme. Each modulation symbol may be represented as coordinates of a location in an I-Q plane. The arrangement of modulation symbols in the I-Q plane may be referred to as the constellation. In the example of FIG. 2, the first subset of processed information bits (e.g., c ₀c ₁c ₂c ₃... c _m) may be mapped to an inner constellation, while the second subset of processed information bits (e.g., u ₀u ₁u ₂u ₃... u _n) may be mapped to an outer constellation.

With reference to the encoding pipeline 201, in some examples, encoding one or more of the first or second subset of information bits with one or more cyclic redundancy check bits may be used for early termination and partial retransmission of the information bits 205 (and/or the first, second subset of information bits) in the decoding pipeline 202. For example, with reference to decoding pipeline, the demodulation component 265 may receive and demodulate the modulation symbols 260. The demodulation component 265 may pass the demodulated symbols to the segmentation component 215-b, which may divide the demodulated symbols into the first subset of processed information bits (e.g., c ₀c ₁c ₂c ₃... c _m) and the second subset of processed information bits (e.g., u ₀u ₁u ₂u ₃... u _n) . One or more of the base station 105-a or the UE 115-a may pass the first subset of processed information bits (e.g., c ₀c ₁c ₂c ₃... c _m) and the second subset of processed information bits (e.g., u ₀u ₁u ₂u ₃... u _n) to one or more of the cyclic redundancy check component 225-b or the cyclic redundancy check component 230-b in the decoding pipeline 202.

In some examples, with reference to the decoding pipeline 202, when decoding the first subset of information bits with the appended first set of one or more cyclic redundancy check bits, based on a successful or an unsuccessful decoding of the first subset of information bits with the appended first set of one or more cyclic redundancy check bits, one or more of the base station 105-a or the UE 115-a may perform an early termination. That is, one or more of the base station 105-a or the UE 115-a may ignore decoding the second subset of information bits of the set of information bits 205 associated with the second forward error correction stream 240-b thereby reducing latency in encoding operations. Instead, one or more of the base station 105-a or the UE 115-a may transmit an indication for partial retransmission of the information bits 205 (i.e., the first subset of information bits) . Alternatively, if the decoding the first subset of information bits with the appended first set of one or more cyclic redundancy check bits is successful, one or more of the base station 105-a or the UE 115-a may proceed to also decode the second subset of information bits associated with the second forward error correction stream 240-b. Therefore, encoding the first set of one or more cyclic redundancy check bits to one or more bits of the first subset of information bits and the second set of one or more cyclic redundancy check bits to one or more bits of the second subset of information bits, prior to forwarding the forward error correction components 245-b, 250-b, may benefit one or more of the base station 105-a or the UE 115-a for early termination or partial retransmission.

One or more of the base station 105-a or the UE 115-a may therefore use the first set or the second set of one or more cyclic redundancy check bits appended, in the encoding pipeline 201, as an indication for early termination associated with decoding, in the decoding pipeline 202, one or more of the one or more modulation symbols 260 carrying the processed first subset of information bits or the processed second subset of information bits. Alternatively or additionally, one or more of the base station 105-a or the UE 115-a may use the first set or the second set of one or more cyclic redundancy check bits as an indication for partial retransmission of one or more of the one or more modulation symbols 205 carrying the processed first subset of information bits or the processed second subset of information bits. One or more of the base station 105-a or the UE 115-a may thus include features for improvements to power consumption, early termination, partial retransmission, spectral efficiency, higher data rates and, in some examples, may promote enhanced efficiency for high reliability and low latency operations, among other benefits.

FIG. 3 illustrates an example of a block diagram 300 of a device 305 that supports cyclic redundancy check schemes for unequal error protection with forward error corrections in accordance with aspects of the present disclosure. The device 305 may be an example of aspects of one or more of a base station 105 or a UE 115 as described herein. The device 305 may include a segmentation component 315, a forward error correction component 330, a forward error correction component 335, and a modulation component 340. The device 305 may also include a processor. Each of these components may be in communication with one another (e.g., via one or more buses) . Additionally, each of these components may be implemented in hardware, code (e.g., software or firmware) executed by a processor, or any combination thereof. If implemented in code executed by a processor, the functions of these components may be executed by a general-purpose processor, a digital signal processor (DSP) , an application-specific integrated circuit (ASIC) , a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described in the present disclosure. Although in the following description of FIG. 3 the operations are performed from an encoding perspective, complimentary operations may also be performed from a decoding perspective.

The device 305 may, in some examples, include a receiver as described herein. A receiver may utilize a single antenna or a set of antennas. In some examples, a receiver may be an example of aspects of a transceiver as described herein. The device 305 may receive, via a receiver, information such as packets, user data, or control information associated with various information channels (e.g., control channels, data channels, etc. ) . Information may be passed on to other components of the device 305. For example, the device 305 may receive using a receiver a set of information bits 310 (i.e., a set of information bits b ₀b ₁b ₂b ₃…, which may be associated with various information channels) . The device 305 may pass the received information bits 310 to other components of the device 305, such as the segmentation component 315.

The segmentation component 315 may allocate (e.g., segment, partition) and distribute the information bits 310 to one or more error protection streams (also referred to as forward error correction streams) associated with the device 305. For example, the segmentation component 315 may divide and distribute a first subset of information bits of the set of information bits 310 to a first forward error correction stream 320 and a second subset of information bits of the set of information bits 310 to a second forward error correction stream 325. The first forward error correction stream 320 may correspond to the forward error correction component 330, while the second forward error correction stream 325 may correspond to the forward error correction component 335. In some examples, allocation and distribution of the information bits 310 across one or more error protection streams may be random. In other examples, allocation and distribution of the information bits 310 across one or more error protection streams may be in accordance with a predefined rule (e.g., based on a number of information bits in a set) . The device 305 may therefore support unequal error protection by distributing the information bits 310 across multiple error protection streams (e.g., multiple forward error correction streams) .

The forward

error correction components

330, 335 may support one or more forward error correction codes. In some examples, the forward error correction component 330 may encode the first subset of information bits of the set of information bits 310 in accordance with a first forward error correction code, and generate a first subset of processed information bits (e.g., c ₀c ₁c ₂c ₃... c _m, where m represents a number of coded bits according to the first forward error correction code) . In some examples, the forward error correction component 335 may encode the second subset of information bits of the set of information bits 310 in accordance with a second forward error correction code, and generate a second subset of processed information bits (e.g., u ₀u ₁u ₂u ₃... u _n, where n represent a number of coded bits according to the first forward error correction code) . The second forward error correction code may, in some examples, be different from the first forward error correction code. In some other examples, the second forward error correction code and the first forward error correction code may be a same forward error correction code. The device 305 may therefore support error protection of the information bits 310 by processing subsets of the information bits 310 across multiple forward error correction streams.

The device 305 may pass the processed information bits to other components of the device 305, such as the modulation component 340. For example, the forward

error correction components

330, 335 may pass the first subset of processed information bits and the second subset of processed information bits to the modulation component 340. The modulation component 340 may then modulate the first subset of processed information bits and the second subset of processed information bits, in accordance with a modulation scheme, to generate one or more modulation symbols 345. Each modulation symbol 345 may be represented by the first subset of processed information bits and the second subset of processed information bits (e.g., u ₀u ₁u ₂u ₃... u _n c ₀c ₁c ₂c ₃... c _m) .

In some examples, the modulation component 340 may map the first subset of processed information bits and the second subset of processed information bits to modulation symbols 345 in a constellation associated with a modulation scheme. Each modulation symbol may be represented as coordinates of a location in an in-phase quadrature (I-Q) plane. The arrangement of modulation symbols in the I-Q plane may be referred to as the constellation. In the example of FIG. 3, the first subset of processed information bits (e.g., c ₀c ₁c ₂c ₃... c _m) may be mapped to an inner constellation, while the second subset of processed information bits (e.g., u ₀u ₁u ₂u ₃... u _n) may be mapped to an outer constellation. An example of a modulation scheme may include a QAM scheme, such as 16QAM, 64QAM, 256QAM, or 1024QAM. In this, example, the modulation symbols 450 may be QAM symbols. Other examples of a modulation scheme may include a QPSK scheme.

The device 305 may pass the modulation symbols 345 to other components of the device 305. For example, the device 305 may, in some examples, include a transmitter as described herein. A transmitter may utilize a single antenna or a set of antennas. In some examples, a transmitter may be collocated with a receiver in a transceiver module as described herein. The modulation symbols 345 may be filtered to produce a baseband waveform, with one or more spectral properties. This baseband waveform or signal may then be upconverted to a carrier frequency, which can be transmitted by the device 305 using a transmitter over the air, through coaxial cable, or through fiber or some other medium.

FIG. 4 illustrates an example of a block diagram 400 of a device 405 that supports cyclic redundancy check schemes for unequal error protection with forward error corrections in accordance with aspects of the present disclosure. The device 405 may be an example of aspects of one or more of a base station 105 or a UE 115 as described herein. The device 405 may include a cyclic redundancy check component 415, a segmentation component 420, a forward error correction component 435, a forward error correction component 440, and a modulation component 445. The device 405 may also include a processor. Additionally, each of these components may be implemented in hardware, code (e.g., software or firmware) executed by a processor, or any combination thereof. If implemented in code executed by a processor, the functions of these components may be executed by a general-purpose processor, a DSP, an ASIC, a FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described in the present disclosure. Each of these components may be in communication with one another (e.g., via one or more buses) . Although in the following description of FIG. 4 the operations are performed from an encoding perspective, complimentary operations may also be performed from a decoding perspective.

The device 405 may, in some examples, include a receiver as described herein. A receiver may utilize a single antenna or a set of antennas. In some examples, a receiver may be an example of aspects of a transceiver as described herein. The device 405 may receive, via a receiver, information such as packets, user data, or control information associated with various information channels (e.g., control channels, data channels, etc. ) . Information may be passed on to other components of the device 405. For example, the device 405 may receive using a receiver a set of information bits 410 (i.e., a set of information bits b ₀b ₁b ₂b ₃…, which may be associated with various information channels) . The device 405 may pass the received information bits 410 to other components of the device 405, such as the cyclic redundancy check component 415.

The cyclic redundancy check component 415 may append one or more cyclic redundancy check bits to one or more bits of the set of information bits 410 (i.e., b ₀b ₁b ₂b ₃…) . In some examples, the one or more cyclic redundancy check bits may include a copy of one or more information bits of the set of information bits 410 that may be appended to the ending of the set of information bits 410. The device 405 may thus encode one or more cyclic redundancy check bits to one or more bits of the set of information bits 410 (i.e., b ₀b ₁b ₂b ₃…) , prior to one or more error protection streams, to protect all the information bits 410. The device 405 may pass the received information bits 410, appended with the one or more cyclic redundancy check bits, to other components of the device 405, such as the segmentation component 420.

The segmentation component 420 may assign (e.g., divide) and distribute the information bits 410, appended with the one or more cyclic redundancy check bits, to one or more error protection streams associated with the device 405. For example, the segmentation component 420 may segment and distribute a first subset of information bits of the set of information bits 410 to a first forward error correction stream 425 and a second subset of information bits of the set of information bits 410 to a second forward error correction stream 430. The first forward error correction stream 425 may correspond to the forward error correction component 435, while the second forward error correction stream 430 may correspond to the forward error correction component 440. In some examples, distribution of the information bits 410, appended with the one or more cyclic redundancy check bits, across one or more error protection streams may be random. In other examples, distribution of the information bits 410 across one or more error protection streams may be in accordance with a predefined rule (e.g., based on a number of information bits in a set) . The device 405 may therefore support unequal error protection by distributing the information bits 410 across multiple error protection streams.

The forward error correction components 435, 440 may support one or more forward error correction codes. In some examples, the forward error correction component 435 may encode the first subset of information bits of the set of information bits 410, appended with the one or more cyclic redundancy check bits, in accordance with a first forward error correction code, and generate a first subset of processed information bits (also referred to as a processed first subset of information bits) (e.g., c ₀c ₁c ₂c ₃... c _m, where m represent a number of coded bits according to the first forward error correction code) . In some examples, the forward error correction component 440 may encode the second subset of information bits of the set of information bits 410, appended with the one or more cyclic redundancy check bits, in accordance with a second forward error correction code, and generate a second subset of processed information bits (also referred to as a processed second subset of information bits) (e.g., u ₀u ₁u ₂u ₃... u _n, where n represent a number of coded bits according to the first forward error correction code) . The second forward error correction code may, in some examples, be different from the first forward error correction code. In some other examples, the second forward error correction code and the first forward error correction code may be a same forward error correction code. The device 405 may thus support error protection of the information bits 410 by processing subsets of the information bits 410 across multiple forward error correction streams.

The device 405 may pass the processed information bits to other components of the device 405, such as the modulation component 445. For example, the forward error correction components 435, 440 may pass the first subset of processed information bits and the second subset of processed information bits to the modulation component 445. The modulation component 445 may modulate the first subset of processed information bits and the second subset of processed information bits, in accordance with a modulation scheme, to generate one or more modulation symbols 450. Each modulation symbol 450 may be represented by the first subset of processed information bits and the second subset of processed information bits (e.g., u ₀u ₁u ₂u ₃... u _n c ₀c ₁c ₂c ₃... c _m) .

In some examples, the modulation component 445 may map the first subset of processed information bits and the second subset of processed information bits to modulation symbols 450 in a constellation associated with a modulation scheme. Each modulation symbol may be represented as coordinates of a location in an I-Q plane. The arrangement of modulation symbols in the I-Q plane may be referred to as the constellation. In the example of FIG. 4, the first subset of processed information bits (e.g., c ₀c ₁c ₂c ₃... c _m) may be mapped to an inner constellation, while the second subset of processed information bits (e.g., u ₀u ₁u ₂u ₃... u _n) may be mapped to an outer constellation. An example of a modulation scheme may include a QAM scheme, such as 16QAM, 64QAM, 256QAM, or 1024QAM. In this, example, the modulation symbols 450 may be QAM symbols. Other examples of a modulation scheme may include a QPSK scheme.

The device 405 may pass the modulation symbols 450 to other components of the device 405. For example, the device 405 may, in some examples, include a transmitter as described herein. A transmitter may utilize a single antenna or a set of antennas. In some examples, a transmitter may be collocated with a receiver in a transceiver module as described herein. The modulation symbols 450 may be transmitted by the device 405 using a transmitter.

FIG. 5 illustrates an example of a block diagram 500 of a device 505 that supports cyclic redundancy check schemes for unequal error protection with forward error corrections in accordance with aspects of the present disclosure. The device 505 may be an example of aspects of one or more of a base station 105 or a UE 115 as described herein. The device 505 may include a cyclic redundancy check component 515, a segmentation component 520, a cyclic redundancy check component 525, a forward error correction component 540, a forward error correction component 545, and a modulation component 550. The device 505 may also include a processor. Each of these components may be in communication with one another (e.g., via one or more buses) . Additionally, each of these components may be implemented in hardware, code (e.g., software or firmware) executed by a processor, or any combination thereof. If implemented in code executed by a processor, the functions of these components may be executed by a general-purpose processor, a DSP, an ASIC, a FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described in the present disclosure. Although in the following description of FIG. 5 the operations are performed from an encoding perspective, complimentary operations may also be performed from a decoding perspective.

Particular aspects of the block diagram 500 may be implemented to realize one or more of the following potential advantages. The block diagram 500 employed by the device 505 may provide benefits and enhancements to the operation of the device 505. For example, operations performed by the device 505 may provide improvements to early termination and retransmission of information. In some examples, the device 505 may support one or more cyclic redundancy check schemes, as illustrated in FIG. 5, for the device 505 to use to support improvements to power consumption, spectral efficiency, higher data rates and, in some examples, may promote enhanced efficiency for high reliability and low latency operations, among other benefits.

The device 505 may, in some examples, include a receiver as described herein. A receiver may utilize a single antenna or a set of antennas. In some examples, a receiver may be an example of aspects of a transceiver as described herein. The device 505 may receive, via a receiver, information such as packets, user data, or control information associated with various information channels (e.g., control channels, data channels, etc. ) . Information may be passed on to other components of the device 505. For example, the device 505 may receive using a receiver a set of information bits 510 (i.e., a set of information bits b ₀b ₁b ₂b ₃…, which may be associated with various information channels) . The device 505 may pass the received information bits 510 to other components of the device 505, such as the cyclic redundancy check component 515.

The cyclic redundancy check component 515 may append one or more cyclic redundancy check bits to one or more bits of the set of information bits 510 (i.e., b ₀b ₁b ₂b ₃…) . In some examples, the one or more cyclic redundancy check bits may include a copy of one or more information bits of the set of information bits 510 that may be appended to the ending of the set of information bits 510. The device 505 may thus encode one or more cyclic redundancy check bits to one or more bits of the set of information bits 510 (i.e., b ₀b ₁b ₂b ₃…) , prior to one or more error protection streams, to protect all the information bits 510. The device 505 may pass the received information bits 510, appended with the one or more cyclic redundancy check bits, to other components of the device 505, such as the segmentation component 520.

The segmentation component 520 may divide the information bits 510, appended with the one or more cyclic redundancy check bits, to one or more error protection streams associated with the device 505. For example, the segmentation component 520 may segment and distribute a first subset of information bits of the set of information bits 510 to a first forward error correction stream 530 and a second subset of information bits of the set of information bits 510 to a second forward error correction stream 535. The first forward error correction stream 530 may correspond to the forward error correction component 540, while the second forward error correction stream 535 may correspond to the forward error correction component 545. In some examples, distribution of the information bits 510, appended with the one or more cyclic redundancy check bits, across one or more error protection streams may be random. In other examples, distribution of the information bits 510 across one or more error protection streams may be in accordance with a predefined rule (e.g., based on a number of information bits in a stream) . The device 505 may therefore support unequal error protection by distributing the information bits 510 across multiple error protection streams.

In some examples, prior to processing the first subset of information bits of the set of information bits 510 by the forward error correction component 540, the segmentation component 520 may pass the first subset of information bits to the cyclic redundancy check component 525, which may correspond to (e.g., be part of) the first forward error correction stream 530. The cyclic redundancy check component 525 may append a first set of one or more cyclic redundancy check bits to one or more bits of the first subset of information bits. In some examples, the first set of one or more cyclic redundancy check bits may include a copy of one or more information bits of the first subset of information bits that may be appended to the ending of the first subset of information bits. As such, the first set of one or more cyclic redundancy check bits appended (e.g., by the cyclic redundancy check component 525) to the ending of the first subset of information bits may be smaller in length (e.g., number of bits) compared to the one or more cyclic redundancy check bits appended to the ending of the set of information bits 510 (e.g., by the cyclic redundancy check component 515) . The device 505 may thus encode the first set of one or more cyclic redundancy check bits to one or more bits of the first subset of information bits, prior to forwarding the first subset to the forward error correction component 540, to further protect the information bits 510.

Encoding the first subset of information bits with the first set of one or more cyclic redundancy check bits may be used for early termination and partial retransmission of the information bits 510 (and/or the first subset of information bits) . For example, when decoding the first subset of information bits with the appended first set of one or more cyclic redundancy check bits, based on a successful or an unsuccessful decoding of the first subset of information bits with the appended first set of one or more cyclic redundancy check bits, the device 505 may perform an early termination. That is, the device 505 may skip decoding the second subset of information bits of the set of information bits 510 associated with the second forward error correction stream 535 thereby reducing latency in overall encoding operations. Instead, the device 505 may transmit an indication for partial retransmission of the information bits 510 (i.e., the first subset of information bits) . Alternatively, if the decoding of the first subset of information bits with the appended first set of one or more cyclic redundancy check bits is successful, the device 505 may proceed to also decode the second subset of information bits. Therefore, encoding one or more cyclic redundancy check bits to one or more bits of the first subset of information bits, prior to forwarding the first subset to the forward error correction component 540, may benefit devices, such as a base station 105 or a UE 115 for early termination or partial retransmission.

The device 505 may pass the first subset of information bits, appended with multiple cyclic redundancy check bits, to other components of the device 505, such as the forward error correction component 540. Similarly, the device may pass the second subset of information bits of the set of information bits 510 to the second forward error correction stream 535. The forward error correction components 540, 545 may support one or more forward error correction codes. In some examples, the forward error correction component 540 may encode the first subset of information bits of the set of information bits 510, appended with multiple sets of one or more cyclic redundancy check bits, in accordance with a first forward error correction code, and generate a first subset of processed information bits (e.g., c ₀c ₁c ₂c ₃... c _m, where m represents a number of coded bits according to the first forward error correction code) . In some examples, the forward error correction component 545 may encode the second subset of information bits of the set of information bits 510, appended with a single set of one or more cyclic redundancy check bits, in accordance with a second forward error correction code, and generate a second subset of processed information bits (e.g., u ₀u ₁u ₂u ₃... u _n, where n represent a number of coded bits according to the first forward error correction code) . The second forward error correction code may, in some examples, be different from the first forward error correction code. In some other examples, the second forward error correction code and the first forward error correction code may be a same forward error correction code. The device 505 may thus support error protection of the information bits 510 by processing subsets of the information bits 510 across multiple forward error correction streams.

The device 505 may pass the processed information bits to other components of the device 505, such as the modulation component 550. For example, the forward error correction components 540, 545 may pass the first subset of processed information bits and the second subset of processed information bits to the modulation component 550. The modulation component 550 may modulate the first subset of processed information bits and the second subset of processed information bits, in accordance with a modulation scheme, to generate one or more modulation symbols 555. Each modulation symbol 555 may be represented by the first subset of processed information bits and the second subset of processed information bits (e.g., u ₀u ₁u ₂u ₃... u _n c ₀c ₁c ₂c ₃... c _m) .

In some examples, the modulation component 550 may map the first subset of processed information bits and the second subset of processed information bits to modulation symbols 555 in a constellation associated with a modulation scheme. Each modulation symbol may be represented as coordinates of a location in an I-Q plane. The arrangement of modulation symbols in the I-Q plane may be referred to as the constellation. In the example of FIG. 5, the first subset of processed information bits (e.g., c ₀c ₁c ₂c ₃... c _m) may be mapped to an inner constellation, while the second subset of processed information bits (e.g., u ₀u ₁u ₂u ₃... u _n) may be mapped to an outer constellation. An example of a modulation scheme may include a QAM scheme, such as 16QAM, 64QAM, 256QAM, or 1024QAM. In this, example, the modulation symbols 555 may be QAM symbols. Other examples of a modulation scheme may include a QPSK scheme.

The device 505 may pass the modulation symbols 555 to other components of the device 505. For example, the device 505 may, in some examples, include a transmitter as described herein. A transmitter may utilize a single antenna or a set of antennas. In some examples, a transmitter may be collocated with a receiver in a transceiver module as described herein. The modulation symbols 555 may be transmitted by the device 505 using a transmitter.

FIG. 6 illustrates an example of a block diagram 600 of a device 605 that supports cyclic redundancy check schemes for unequal error protection with forward error corrections in accordance with aspects of the present disclosure. The device 605 may be an example of aspects of one or more of a base station 105 or a UE 115 as described herein. The device 605 may include a cyclic redundancy check component 615, a segmentation component 620, a cyclic redundancy check component 625, a cyclic redundancy check component 630, a forward error correction component 645, a forward error correction component 650, and a modulation component 655. The device 605 may also include a processor. Additionally, each of these components may be implemented in hardware, code (e.g., software or firmware) executed by a processor, or any combination thereof. If implemented in code executed by a processor, the functions of these components may be executed by a general-purpose processor, a DSP, an ASIC, a FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described in the present disclosure. Each of these components may be in communication with one another (e.g., via one or more buses) . Although in the following description of FIG. 6 the operations are performed from an encoding perspective, complimentary operations may also be performed from a decoding perspective.

The device 605 may, in some examples, include a receiver as described herein. A receiver may utilize a single antenna or a set of antennas. In some examples, a receiver may be an example of aspects of a transceiver as described herein. The device 605 may receive, via a receiver, information such as packets, user data, or control information associated with various information channels (e.g., control channels, data channels, etc. ) . Information may be passed on to other components of the device 605. For example, the device 605 may receive using a receiver a set of information bits 610 (i.e., a set of information bits b ₀b ₁b ₂b ₃…, which may be associated with various information channels) . The device 605 may pass the received information bits 610 to other components of the device 605, such as the cyclic redundancy check component 615.

The cyclic redundancy check component 615 may append one or more cyclic redundancy check bits to one or more bits of the set of information bits 610 (i.e., b ₀b ₁b ₂b ₃…) . In some examples, the one or more cyclic redundancy check bits may include a copy of one or more information bits of the set of information bits 610 that may be appended to the ending of the set of information bits 610. The device 605 may thus encode one or more cyclic redundancy check bits to one or more bits of the set of information bits 610 (i.e., b ₀b ₁b ₂b ₃…) , prior to one or more error protection streams, to protect all the information bits 610. The device 605 may pass the received information bits 610, appended with the one or more cyclic redundancy check bits, to other components of the device 605, such as the segmentation component 620.

The segmentation component 620 may distribute the information bits 610, appended with a cyclic redundancy check, to one or more error protection streams associated with the device 605. For example, the segmentation component 620 may segment and distribute a first subset of information bits of the set of information bits 610 to a first forward error correction stream 635 and a second subset of information bits of the set of information bits 610 to a second forward error correction stream 640. The first forward error correction stream 635 may correspond to the forward error correction component 645, while the second forward error correction stream 640 may correspond to the forward error correction component 650. In some examples, distribution of the information bits 610, appended with the one or more cyclic redundancy check bits, across one or more error protection streams may be random. In other examples, distribution of the information bits 610 across one or more error protection streams may be in accordance with a predefined rule (e.g., based on a number of information bits in a set) . The device 605 may hence support unequal error protection by distributing the information bits 610 across multiple error protection streams.

In some examples, prior to processing the first subset of information bits of the set of information bits 610 by the forward error correction component 645, the segmentation component 620 may pass the first subset of information bits to the cyclic redundancy check component 625, which may correspond to (e.g., be part of) the first forward error correction stream 635. The cyclic redundancy check component 625 may append a first set of one or more cyclic redundancy check bits to one or more bits of the first subset of information bits. In some examples, the first set of one or more cyclic redundancy check bits may include a copy of one or more information bits of the first subset of information bits that may be appended to the ending of the first subset of information bits. As such, the first set of one or more cyclic redundancy check bits appended (e.g., by the cyclic redundancy check component 625) to the ending of the first subset of information bits may be smaller in length (e.g., number of bits) compared to the set of one or more cyclic redundancy check bits appended to the ending of the set of information bits 610 (e.g., by the cyclic redundancy check component 615) . The device 605 may thus encode a first set of one or more cyclic redundancy check bits to one or more bits of the first subset of information bits, prior to forwarding the first subset to the forward error correction component 645, to further protect the information bits 610.

Additionally, in some examples, prior to processing the second subset of information bits of the set of information bits 610 by the forward error correction component 650, the segmentation component 620 may pass the second subset of information bits to the cyclic redundancy check component 630, which may correspond to (e.g., be part of) the second forward error correction stream 640. The cyclic redundancy check component 630 may append a second set of one or more cyclic redundancy check bits to one or more bits of the second subset of information bits. In some examples, the second set of one or more cyclic redundancy check bits may include a copy of one or more information bits of the second subset of information bits that may be appended to the ending of the second subset of information bits. As such, the second set of one or more cyclic redundancy check bits appended (e.g., by the cyclic redundancy check component 630) to the ending of the second subset of information bits may be smaller in length (e.g., number of bits) compared to the set of one or more cyclic redundancy check bits appended to the ending of the set of information bits 610 (e.g., by the cyclic redundancy check component 615) . The device 605 may thus encode the second set of one or more cyclic redundancy check bits to one or more bits of the second subset of information bits, prior to forwarding the second subset to the forward error correction component 650, to further protect the information bits 610.

Encoding one or more of the first or second subset of information bits with one or more cyclic redundancy check bits may be used for early termination and partial retransmission of the information bits 610 (and/or the first, second subset of information bits) . For example, when decoding the first subset of information bits with the appended first set of one or more cyclic redundancy check bits, based on a successful or an unsuccessful decoding of the first subset of information bits with the appended first set of one or more cyclic redundancy check bits, the device 605 may perform an early termination. That is, the device 605 may ignore decoding the second subset of information bits of the set of information bits 610 associated with the second forward error correction stream 640 thereby reducing latency in encoding operations. Instead, the device 605 may transmit an indication for partial retransmission of the information bits 610 (i.e., the first subset of information bits) . Alternatively, if the decoding the first subset of information bits with the appended first set of one or more cyclic redundancy check bits is successful, the device 605 may proceed to also decode the second subset of information bits. Therefore, encoding the first set of one or more cyclic redundancy check bits to one or more bits of the first subset of information bits and the second set of one or more cyclic redundancy check bits to one or more bits of the second subset of information bits, prior to forwarding the forward

error correction components

645, 650, may benefit devices, such as a base station 105 or a UE 115 for early termination or partial retransmission.

The device 605 may pass the first subset of information bits, appended with multiple sets of one or more cyclic redundancy check bits, to other components of the device 605, such as the forward error correction component 645. Similarly, the device may pass the second subset of information bits of the set of information bits 610, appended with multiple sets of one or more cyclic redundancy check bits, to the second forward error correction stream 640. The forward

error correction components

645, 650 may support one or more forward error correction codes. In some examples, the forward error correction component 645 may encode the first subset of information bits of the set of information bits 610, appended with multiple sets of one or more cyclic redundancy check bits, in accordance with a first forward error correction code, and generate a first subset of processed information bits (e.g., c ₀c ₁c ₂c ₃... c _m, where m represents a number of coded bits according to the first forward error correction code) . In some examples, the forward error correction component 650 may encode the second subset of information bits of the set of information bits 610, appended with multiple sets of one or more cyclic redundancy check bits, in accordance with a second forward error correction code, and generate a second subset of processed information bits (e.g., u ₀u ₁u ₂u ₃... u _n, where n represent a number of coded bits according to the first forward error correction code) . The second forward error correction code may, in some examples, be different from the first forward error correction code. In some other examples, the second forward error correction code and the first forward error correction code may be a same forward error correction code. The device 605 may thus support error protection of the information bits 610 by processing subsets of the information bits 610 across multiple forward error correction streams.

The device 605 may pass the processed information bits to other components of the device 605, such as the modulation component 655. For example, the forward

error correction components

645, 650 may pass the first subset of processed information bits and the second subset of processed information bits to the modulation component 655. The modulation component 655 may modulate the first subset of processed information bits and the second subset of processed information bits, in accordance with a modulation scheme, to generate one or more modulation symbols 660. Each modulation symbol 660 may be represented by the first subset of processed information bits and the second subset of processed information bits (e.g., u ₀u ₁u ₂u ₃... u _n c ₀c ₁c ₂c ₃... c _m) .

In some examples, the modulation component 655 may map the first subset of processed information bits and the second subset of processed information bits to modulation symbols 660 in a constellation associated with a modulation scheme. Each modulation symbol may be represented as coordinates of a location in an I-Q plane. The arrangement of modulation symbols in the I-Q plane may be referred to as the constellation. In the example of FIG. 6, the first subset of processed information bits (e.g., c ₀c ₁c ₂c ₃... c _m) may be mapped to an inner constellation, while the second subset of processed information bits (e.g., u ₀u ₁u ₂u ₃... u _n) may be mapped to an outer constellation. An example of a modulation scheme may include QAM scheme, such as 16QAM, 64QAM, etc. Other examples of a modulation scheme may include a QPSK scheme.

The device 605 may pass the modulation symbols 660 to other components of the device 605. For example, the device 605 may, in some examples, include a transmitter as described herein. A transmitter may utilize a single antenna or a set of antennas. In some examples, a transmitter may be collocated with a receiver in a transceiver module as described herein. The modulation symbols 660 may be transmitted by the device 605 using a transmitter.

Particular aspects of the block diagram 600 may be implemented to realize one or more of the following potential advantages. The block diagram 600 employed by the device 505 may provide benefits and enhancements to the operation of the device 605. For example, operations performed by the device 605 may provide improvements to early termination and retransmission of information. In some examples, the device 605 may support one or more cyclic redundancy check schemes, as illustrated in FIG. 6, for the device 605 to use to support improvements to power consumption, spectral efficiency, higher data rates and, in some examples, may promote enhanced efficiency for high reliability and low latency operations, among other benefits.

FIG. 7 illustrates an example of a block diagram 700 of a device 705 that supports cyclic redundancy check schemes for unequal error protection with forward error corrections in accordance with aspects of the present disclosure. The device 705 may be an example of aspects of one or more of a base station 105 or a UE 115 as described herein. The device 705 may include a segmentation component 715, a cyclic redundancy check component 720, a cyclic redundancy check component 725, a forward error correction component 740, a forward error correction component 745, and a modulation component 750. The device 705 may also include a processor. Additionally, each of these components may be implemented in hardware, code (e.g., software or firmware) executed by a processor, or any combination thereof. If implemented in code executed by a processor, the functions of these components may be executed by a general-purpose processor, a DSP, an ASIC, a FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described in the present disclosure. Each of these components may be in communication with one another (e.g., via one or more buses) .

Particular aspects of the block diagram 700 may be implemented to realize one or more of the following potential advantages. The block diagram 700 employed by the device 705 may provide benefits and enhancements to the operation of the device 705. For example, operations performed by the device 605 may provide improvements to early termination and retransmission of information. Although in the following description of FIG. 7 the operations are performed from an encoding perspective, complimentary operations may also be performed from a decoding perspective.

The device 705 may, in some examples, include a receiver as described herein. A receiver may utilize a single antenna or a set of antennas. In some examples, a receiver may be an example of aspects of a transceiver as described herein. The device 705 may receive, via a receiver, information such as packets, user data, or control information associated with various information channels (e.g., control channels, data channels, etc. ) . Information may be passed on to other components of the device 705. For example, the device 705 may receive using a receiver a set of information bits 710 (i.e., a set of information bits b ₀b ₁b ₂b ₃…, which may be associated with various information channels) . The device 705 may pass the received information bits 710 to other components of the device 705, such as the segmentation component 715.

The segmentation component 715 may distribute the information bits 710 to one or more error protection streams associated with the device 705. For example, the segmentation component 715 may segment and distribute a first subset of information bits of the set of information bits 710 to a first forward error correction stream 730 and a second subset of information bits of the set of information bits 710 to a second forward error correction stream 735. The first forward error correction stream 730 may correspond to the forward error correction component 740, while the second forward error correction stream 735 may correspond to the forward error correction component 745. The device 705 may hence support unequal error protection by distributing the information bits 710 across multiple error protection streams.

In some examples, prior to processing the first subset of information bits of the set of information bits 710 by the forward error correction component 740, the segmentation component 715 may pass the first subset of information bits to the cyclic redundancy check component 720, which may correspond to (e.g., be part of) the first forward error correction stream 730. The cyclic redundancy check component 720 may append a first set of one or more cyclic redundancy check bits to one or more bits of the first subset of information bits. In some examples, the one or more cyclic redundancy check bits may include a copy of one or more information bits of the first subset of information bits that may be appended to the ending of the first subset of information bits. The device 705 may thus encode the first set of one or more cyclic redundancy check bits to one or more bits of the first subset of information bits, prior to forwarding the first subset to the forward error correction component 740.

In addition, in some examples, prior to processing the second subset of information bits of the set of information bits 710 by the forward error correction component 745, the segmentation component 715 may pass the second subset of information bits to the cyclic redundancy check component 725, which may correspond to (e.g., be part of) the second forward error correction stream 735. The cyclic redundancy check component 725 may append a second set of one or more cyclic redundancy check bits to one or more bits of the second subset of information bits. In some examples, the second set of one or more cyclic redundancy check bits may include a copy of one or more information bits of the second subset of information bits that may be appended to the ending of the second subset of information bits. The device 705 may therefore encode the second set of one or more cyclic redundancy check bits to one or more bits of the second subset of information bits, prior to forwarding the second subset to the forward error correction component 745.

Encoding one or more of the first or second subset of information bits with one or more cyclic redundancy check bits may be used for early termination and partial retransmission of the information bits 710 (and/or the first, second subset of information bits) . For example, when decoding the first subset of information bits with the appended one or more cyclic redundancy check bits, based on a successful or an unsuccessful decoding of the first subset of information bits with the appended one or more cyclic redundancy check bits, the device 705 may perform an early termination. That is, the device 705 may ignore decoding the second subset of information bits of the set of information bits 710 associated with the second forward error correction stream 735 thereby reducing latency in encoding operations. Rather, the device 705 may transmit an indication for partial retransmission of the information bits 710 (i.e., the first subset of information bits) . For example, retransmitting the one or more modulation symbols carrying the processed first subset of information bits and the processed second subset of information bits based at least in part on a feedback comprising a negative acknowledgment. Alternatively, if decoding the first subset of information bits with the appended one or more cyclic redundancy check bits is successful, the device 705 may proceed to also decode the second subset of information bits. Therefore, encoding one or more cyclic redundancy check bits to one or more bits of the first subset of information bits and one or more bits of the second subset of information bits, prior to forwarding the forward

error correction components

740, 745, may benefit devices, such as a base station 105 or a UE 115 for early termination or partial retransmission.

The device 705 may pass the first subset of information bits, appended with one or more cyclic redundancy check bits, to other components of the device 705, such as the forward error correction component 740. Similarly, the device may pass the second subset of information bits, appended with one or more cyclic redundancy check bits, to the forward error correction component 745. The forward

error correction components

740, 745 may support one or more forward error correction codes. In some examples, the forward error correction component 740 may encode the first subset of information bits, appended with one or more cyclic redundancy check bits, in accordance with a first forward error correction code, and generate a first subset of processed information bits (e.g., c ₀c ₁c ₂c ₃... c _m, where m represents a number of coded bits according to the first forward error correction code) . In some examples, the forward error correction component 745 may encode the second subset of information bits, appended with one or more cyclic redundancy check bits, in accordance with a second forward error correction code, and generate a second subset of processed information bits (e.g., u ₀u ₁u ₂u ₃... u _n, where n represent a number of coded bits according to the first forward error correction code) . The device 705 may thus support error protection of the information bits 710 by processing subsets of the information bits 710 across multiple forward error correction streams.

The device 705 may pass the processed information bits to other components of the device 705, such as the modulation component 750. For example, the forward

error correction components

740, 745 may pass the first subset of processed information bits and the second subset of processed information bits to the modulation component 750. The modulation component 750 may modulate the first subset of processed information bits and the second subset of processed information bits, in accordance with a modulation scheme, to generate one or more modulation symbols 755. Each modulation symbol 755 may be represented by the first subset of processed information bits and the second subset of processed information bits (e.g., u ₀u ₁u ₂u ₃... u _n c ₀c ₁c ₂c ₃... c _m) .

In some examples, the modulation component 750 may map the first subset of processed information bits and the second subset of processed information bits to modulation symbols 755 in a constellation associated with a modulation scheme. Each modulation symbol may be represented as coordinates of a location in an I-Q plane. The arrangement of modulation symbols in the I-Q plane may be referred to as the constellation. In the example of FIG. 7, the first subset of processed information bits (e.g., c ₀c ₁c ₂c ₃... c _m) may be mapped to an inner constellation, while the second subset of processed information bits (e.g., u ₀u ₁u ₂u ₃... u _n) may be mapped to an outer constellation. The device 705 may pass the modulation symbols 755 to other components of the device 705. For example, the device 705 may, in some examples, include a transmitter as described herein. A transmitter may utilize a single antenna or a set of antennas. In some examples, a transmitter may be collocated with a receiver in a transceiver module as described herein. The modulation symbols 755 may be transmitted by the device 705 using a transmitter.

FIG. 8 shows a block diagram 800 of a device 805 that supports cyclic redundancy check schemes for unequal error protection with forward error corrections in accordance with aspects of the present disclosure. The device 805 may be an example of aspects of a device as described herein. The device 805 may include a receiver 810, a communications manager 815, and a transmitter 820. The device 805 may also include a processor. Each of these components may be in communication with one another (e.g., via one or more buses) .

The receiver 810 may receive information such as packets, user data, or control information associated with various information channels (e.g., control channels, data channels, and information related to cyclic redundancy check schemes for unequal error protection with forward error corrections, etc. ) . Information may be passed on to other components of the device 805. The receiver 810 may be an example of aspects of the transceiver 1120 described with reference to FIG. 11. The receiver 810 may utilize a single antenna or a set of antennas.

The communications manager 815 may divide a set of information bits into a first subset of information bits associated with a first forward error correction stream and a second subset of information bits associated with a second forward error correction stream, process, at the first forward error correction stream, the first subset of information bits by appending a first set of one or more cyclic redundancy check bits to the first subset of information bits and encoding the first subset of information bits in accordance with a first forward error correction scheme, process, at the second forward error correction stream, the second subset of information bits by encoding the second subset of information bits in accordance with a second forward error correction scheme, and transmit one or more modulation symbols carrying the processed first subset of information bits and the processed second subset of information bits.

The communications manager 815 may also divide a set of processed information bits into a first subset of information bits associated with a first forward error correction stream and a second subset of information bits associated with a second forward error correction stream, process, at a first forward error correction stream, the first subset of information bits by decoding a first set of one or more cyclic redundancy check bits of the first subset of information bits and decoding the first subset of information bits in accordance with the first forward error correction scheme, and process, at a second forward error correction stream, the second subset of information bits based on decoding the first set of one or more cyclic redundancy check bits of the first subset of information bits. The communications manager 815 may be an example of aspects of the communications manager 1110 described herein.

The communications manager 815, or its sub-components, may be implemented in hardware, code (e.g., software or firmware) executed by a processor, or any combination thereof. If implemented in code executed by a processor, the functions of the communications manager 815, or its sub-components may be executed by a general-purpose processor, a DSP, an application-specific integrated circuit (ASIC) , a FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described in the present disclosure.

The communications manager 815, or its sub-components, may be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations by one or more physical components. In some examples, the communications manager 815, or its sub-components, may be a separate and distinct component in accordance with various aspects of the present disclosure. In some examples, the communications manager 815, or its sub-components, may be combined with one or more other hardware components, including but not limited to an input/output (I/O) component, a transceiver, a network server, another computing device, one or more other components described in the present disclosure, or a combination thereof in accordance with various aspects of the present disclosure.

The transmitter 820 may transmit signals generated by other components of the device 805. In some examples, the transmitter 820 may be collocated with a receiver 810 in a transceiver module. For example, the transmitter 820 may be an example of aspects of the transceiver 1120 described with reference to FIG. 11. The transmitter 820 may utilize a single antenna or a set of antennas.

FIG. 9 shows a block diagram 900 of a device 905 that supports cyclic redundancy check schemes for unequal error protection with forward error corrections in accordance with aspects of the present disclosure. The device 905 may be an example of aspects of a device 805 or a device 115 as described herein. The device 905 may include a receiver 910, a communications manager 915, and a transmitter 935. The device 905 may also include a processor. Each of these components may be in communication with one another (e.g., via one or more buses) .

The receiver 910 may receive information such as packets, user data, or control information associated with various information channels (e.g., control channels, data channels, and information related to cyclic redundancy check schemes for unequal error protection with forward error corrections, etc. ) . Information may be passed on to other components of the device 905. The receiver 910 may be an example of aspects of the transceiver 1120 described with reference to FIG. 11. The receiver 910 may utilize a single antenna or a set of antennas.

The communications manager 915 may be an example of aspects of the communications manager 815 as described herein. The communications manager 915 may include a segmentation component 920, a bit processing component 925, and a symbol component 930. The communications manager 915 may be an example of aspects of the communications manager 1110 described herein.

The segmentation component 920 may divide a set of information bits into a first subset of information bits associated with a first forward error correction stream and a second subset of information bits associated with a second forward error correction stream. The bit processing component 925 may process, at the first forward error correction stream, the first subset of information bits by appending a first set of one or more cyclic redundancy check bits to the first subset of information bits and encoding the first subset of information bits in accordance with a first forward error correction scheme and process, at the second forward error correction stream, the second subset of information bits by encoding the second subset of information bits in accordance with a second forward error correction scheme. The symbol component 930 may transmit one or more modulation symbols carrying the processed first subset of information bits and the processed second subset of information bits.

The segmentation component 920 may divide a set of processed information bits into a first subset of information bits associated with a first forward error correction stream and a second subset of information bits associated with a second forward error correction stream. The bit processing component 925 may process, at a first forward error correction stream, the first subset of information bits by decoding a first set of one or more cyclic redundancy check bits of the first subset of information bits and decoding the first subset of information bits in accordance with the first forward error correction scheme and process, at a second forward error correction stream, the second subset of information bits based on decoding the first set of one or more cyclic redundancy check bits of the first subset of information bits.

The transmitter 935 may transmit signals generated by other components of the device 905. In some examples, the transmitter 935 may be collocated with a receiver 910 in a transceiver module. For example, the transmitter 935 may be an example of aspects of the transceiver 1120 described with reference to FIG. 11. The transmitter 935 may utilize a single antenna or a set of antennas.

FIG. 10 shows a block diagram 1000 of a communications manager 1005 that supports cyclic redundancy check schemes for unequal error protection with forward error corrections in accordance with aspects of the present disclosure. The communications manager 1005 may be an example of aspects of a communications manager 815, a communications manager 915, or a communications manager 1110 described herein. The communications manager 1005 may include a segmentation component 1010, a bit processing component 1015, a symbol component 1020, a cyclic redundancy check component 1025, a modulation component 1030, a mapping component 1035, a termination component 1040, a feedback component 1045, a decoding component 1050, and a demodulation component 1055. Each of these modules may communicate, directly or indirectly, with one another (e.g., via one or more buses) .

The segmentation component 1010 may divide a set of information bits into a first subset of information bits associated with a first forward error correction stream and a second subset of information bits associated with a second forward error correction stream. In some examples, the segmentation component 1010 may divide a set of processed information bits into a first subset of information bits associated with a first forward error correction stream and a second subset of information bits associated with a second forward error correction stream.

The bit processing component 1015 may process, at the first forward error correction stream, the first subset of information bits by appending a first set of one or more cyclic redundancy check bits to the first subset of information bits and encoding the first subset of information bits in accordance with a first forward error correction scheme. In some examples, the bit processing component 1015 may process, at the second forward error correction stream, the second subset of information bits by encoding the second subset of information bits in accordance with a second forward error correction scheme. In some examples, the bit processing component 1015 may process, at a first forward error correction stream, the first subset of information bits by decoding a first set of one or more cyclic redundancy check bits of the first subset of information bits and decoding the first subset of information bits in accordance with the first forward error correction scheme. In some examples, the bit processing component 1015 may process, at a second forward error correction stream, the second subset of information bits based on decoding the first set of one or more cyclic redundancy check bits of the first subset of information bits. In some cases, the first forward error correction scheme is different from the second forward error correction scheme.

The symbol component 1020 may transmit one or more modulation symbols carrying the processed first subset of information bits and the processed second subset of information bits. In some examples, the symbol component 1020 may retransmit the one or more modulation symbols carrying the processed first subset of information bits and the processed second subset of information bits based on a feedback including a negative acknowledgment. The cyclic redundancy check component 1025 may append a second set of one or more cyclic redundancy check bits to the set of information bits prior to processing at the first forward error correction stream and at the second forward error correction stream. In some examples, the cyclic redundancy check component 1025 may append the first set of one or more cyclic redundancy check bits to the first subset of information bits before encoding the first subset of information bits in accordance with the first forward error correction scheme. In some examples, the cyclic redundancy check component 1025 may append a second set of one or more cyclic redundancy check bits to the second subset of information bits before encoding the second subset of information bits in accordance with the second forward error correction scheme. In some cases, a length of the second set of one or more cyclic redundancy check bits appended to the set of information bits is greater than a length of the first set of one or more cyclic redundancy check bits.

In some cases, the first set of one or more cyclic redundancy check bits includes an indication for early termination associated with decoding one or more of the one or more modulation symbols carrying the processed first subset of information bits or the processed second subset of information bits. In some cases, the first set of one or more cyclic redundancy check bits includes an indication for partial retransmission of one or more of the one or more modulation symbols carrying the processed first subset of information bits or the processed second subset of information bits. In some cases, the second set of one or more cyclic redundancy check bits includes an indication for early termination associated with decoding one or more of the one or more modulation symbols carrying the processed first subset of information bits or the processed second subset of information bits. In some cases, the second set of one or more cyclic redundancy check bits includes an indication for partial retransmission of one or more of the one or more modulation symbols carrying the processed first subset of information bits or the processed second subset of information bits.

The modulation component 1030 may modulate, in accordance with a modulation scheme, the processed first subset of information bits and the processed second subset of information bits, where transmitting the one or more modulation symbols carrying the processed first subset of information bits and the processed second subset of information bits is based on the modulating. In some cases, the modulation scheme includes a QAM or a QPSK. The mapping component 1035 may map the processed first subset of information bits to an inner constellation associated with the modulation scheme. In some examples, the mapping component 1035 may map the processed second subset of information bits to an outer constellation associated with the modulation scheme. The termination component 1040 may terminate decoding the second subset of information bits based on a failure to decode the first set of one or more cyclic redundancy check bits of the first subset of information bits. The feedback component 1045 may transmit a feedback including a negative acknowledgment associated with the failure to decode the first set of one or more cyclic redundancy check bits of the first subset of information bits.

The decoding component 1050 may decode a second set of one or more cyclic redundancy check bits of the second subset of information bits and decoding the second subset of information bits in accordance with the second forward error correction scheme based on successfully decoding the first set of one or more cyclic redundancy check bits of the first subset of information bits. The demodulation component 1055 may demodulate, in accordance with a demodulation scheme, the one or more modulation symbols carrying the set of processed information bits, where dividing the one or more modulation symbols carrying the set of processed information bits is based on the demodulating. In some cases, the demodulation scheme includes a QAM or a QPSK.

FIG. 11 shows a diagram of a system 1100 including a device 1105 that supports cyclic redundancy check schemes for unequal error protection with forward error corrections in accordance with aspects of the present disclosure. The device 1105 may be an example of or include the components of device 805, device 905, or a device as described herein. The device 1105 may include components for bi-directional voice and data communications including components for transmitting and receiving communications, including a communications manager 1110, an I/O controller 1115, a transceiver 1120, an antenna 1125, memory 1130, a processor 1140, and a coding manager 1150. These components may be in electronic communication via one or more buses (e.g., bus 1145) .

The communications manager 1110 may divide a set of information bits into a first subset of information bits associated with a first forward error correction stream and a second subset of information bits associated with a second forward error correction stream, process, at the first forward error correction stream, the first subset of information bits by appending a first set of one or more cyclic redundancy check bits to the first subset of information bits and encoding the first subset of information bits in accordance with a first forward error correction scheme, process, at the second forward error correction stream, the second subset of information bits by encoding the second subset of information bits in accordance with a second forward error correction scheme, and transmit one or more modulation symbols carrying the processed first subset of information bits and the processed second subset of information bits.

The communications manager 1110 may also divide a set of processed information bits into a first subset of information bits associated with a first forward error correction stream and a second subset of information bits associated with a second forward error correction stream, process, at a first forward error correction stream, the first subset of information bits by decoding a first set of one or more cyclic redundancy check bits of the first subset of information bits and decoding the first subset of information bits in accordance with the first forward error correction scheme, and process, at a second forward error correction stream, the second subset of information bits based on decoding the first set of one or more cyclic redundancy check bits of the first subset of information bits.

The I/O controller 1115 may manage input and output signals for the device 1105. The I/O controller 1115 may also manage peripherals not integrated into the device 1105. In some cases, the I/O controller 1115 may represent a physical connection or port to an external peripheral. In some cases, the I/O controller 1115 may utilize an operating system such as iOS, ANDROID, MS-DOS, MS-WINDOWS, OS/2, UNIX, LINUX, or another known operating system. In other cases, the I/O controller 1115 may represent or interact with a modem, a keyboard, a mouse, a touchscreen, or a similar device. In some cases, the I/O controller 1115 may be implemented as part of a processor. In some cases, a user may interact with the device 1105 via the I/O controller 1115 or via hardware components controlled by the I/O controller 1115.

The transceiver 1120 may communicate bi-directionally, via one or more antennas, wired, or wireless links as described above. For example, the transceiver 1120 may represent a wireless transceiver and may communicate bi-directionally with another wireless transceiver. The transceiver 1120 may also include a modem to modulate the packets and provide the modulated packets to the antennas for transmission, and to demodulate packets received from the antennas. In some cases, the device 1105 may include a single antenna 1125. However, in some cases the device 1105 may have more than one antenna 1125, which may be capable of concurrently transmitting or receiving multiple wireless transmissions.

The memory 1130 may include RAM and ROM. The memory 1130 may store computer-readable, computer-executable code 1135 including instructions that, when executed, cause the processor to perform various functions described herein. In some cases, the memory 1130 may contain, among other things, a BIOS which may control basic hardware or software operation such as the interaction with peripheral components or devices.

The processor 1140 may include an intelligent hardware device, (e.g., a general-purpose processor, a DSP, a CPU, a microcontroller, an ASIC, an FPGA, a programmable logic device, a discrete gate or transistor logic component, a discrete hardware component, or any combination thereof) . In some cases, the processor 1140 may be configured to operate a memory array using a memory controller. In other cases, a memory controller may be integrated into the processor 1140. The processor 1140 may be configured to execute computer-readable instructions stored in a memory (e.g., the memory 1130) to cause the device 1105 to perform various functions (e.g., functions or tasks supporting cyclic redundancy check schemes for unequal error protection with forward error corrections) .

The code 1135 may include instructions to implement aspects of the present disclosure, including instructions to support wireless communications. The code 1135 may be stored in a non-transitory computer-readable medium such as system memory or other type of memory. In some cases, the code 1135 may not be directly executable by the processor 1140 but may cause a computer (e.g., when compiled and executed) to perform functions described herein.

FIG. 12 shows a flowchart illustrating a method 1200 that supports cyclic redundancy check schemes for unequal error protection with forward error corrections in accordance with aspects of the present disclosure. The operations of method 1200 may be implemented by a device (e.g., a base station, a UE) or its components as described herein. For example, the operations of method 1200 may be performed by a communications manager as described with reference to FIGs. 8 through 11. In some examples, a device may execute a set of instructions to control the functional elements of the device to perform the functions described below. Additionally or alternatively, a device may perform aspects of the functions described below using special-purpose hardware.

At 1205, the device may divide a set of information bits into a first subset of information bits associated with a first forward error correction stream and a second subset of information bits associated with a second forward error correction stream. The operations of 1205 may be performed according to the methods described herein. In some examples, aspects of the operations of 1205 may be performed by a segmentation component as described with reference to FIGs. 8 through 11.

At 1210, the device may process, at the first forward error correction stream, the first subset of information bits by appending a first set of one or more cyclic redundancy check bits to the first subset of information bits and encoding the first subset of information bits in accordance with a first forward error correction scheme. The operations of 1210 may be performed according to the methods described herein. In some examples, aspects of the operations of 1210 may be performed by a bit processing component as described with reference to FIGs. 8 through 11.

At 1215, the device may process, at the second forward error correction stream, the second subset of information bits by encoding the second subset of information bits in accordance with a second forward error correction scheme. The operations of 1215 may be performed according to the methods described herein. In some examples, aspects of the operations of 1215 may be performed by a bit processing component as described with reference to FIGs. 8 through 11.

At 1220, the device may transmit one or more modulation symbols carrying the processed first subset of information bits and the processed second subset of information bits. The operations of 1220 may be performed according to the methods described herein. In some examples, aspects of the operations of 1220 may be performed by a symbol component as described with reference to FIGs. 8 through 11.

FIG. 13 shows a flowchart illustrating a method 1300 that supports cyclic redundancy check schemes for unequal error protection with forward error corrections in accordance with aspects of the present disclosure. The operations of method 1300 may be implemented by a device (e.g., a base station, a UE) or its components as described herein. For example, the operations of method 1300 may be performed by a communications manager as described with reference to FIGs. 8 through 11. In some examples, a device may execute a set of instructions to control the functional elements of the device to perform the functions described below. Additionally or alternatively, a device may perform aspects of the functions described below using special-purpose hardware.

At 1305, the device may divide a set of information bits into a first subset of information bits associated with a first forward error correction stream and a second subset of information bits associated with a second forward error correction stream. The operations of 1305 may be performed according to the methods described herein. In some examples, aspects of the operations of 1305 may be performed by a segmentation component as described with reference to FIGs. 8 through 11.

At 1310, the device may process, at the first forward error correction stream, the first subset of information bits by appending a first set of one or more cyclic redundancy check bits to the first subset of information bits and encoding the first subset of information bits in accordance with a first forward error correction scheme. The operations of 1310 may be performed according to the methods described herein. In some examples, aspects of the operations of 1310 may be performed by a bit processing component as described with reference to FIGs. 8 through 11.

At 1315, the device may process, at the second forward error correction stream, the second subset of information bits by encoding the second subset of information bits in accordance with a second forward error correction scheme. The operations of 1315 may be performed according to the methods described herein. In some examples, aspects of the operations of 1315 may be performed by a bit processing component as described with reference to FIGs. 8 through 11.

At 1320, the device may append a second set of one or more cyclic redundancy check bits to the second subset of information bits before encoding the second subset of information bits in accordance with the second forward error correction scheme. The operations of 1320 may be performed according to the methods described herein. In some examples, aspects of the operations of 1320 may be performed by a cyclic redundancy check component as described with reference to FIGs. 8 through 11.

At 1325, the device may transmit one or more modulation symbols carrying the processed first subset of information bits and the processed second subset of information bits. The operations of 1325 may be performed according to the methods described herein. In some examples, aspects of the operations of 1325 may be performed by a symbol component as described with reference to FIGs. 8 through 11.

FIG. 14 shows a flowchart illustrating a method 1400 that supports cyclic redundancy check schemes for unequal error protection with forward error corrections in accordance with aspects of the present disclosure. The operations of method 1400 may be implemented by a device (e.g., a base station, a UE) or its components as described herein. For example, the operations of method 1400 may be performed by a communications manager as described with reference to FIGs. 8 through 11. In some examples, a device may execute a set of instructions to control the functional elements of the device to perform the functions described below. Additionally or alternatively, a device may perform aspects of the functions described below using special-purpose hardware.

At 1405, the device may divide a set of information bits into a first subset of information bits associated with a first forward error correction stream and a second subset of information bits associated with a second forward error correction stream. The operations of 1405 may be performed according to the methods described herein. In some examples, aspects of the operations of 1405 may be performed by a segmentation component as described with reference to FIGs. 8 through 11.

At 1410, the device may process, at the first forward error correction stream, the first subset of information bits by appending a first set of one or more cyclic redundancy check bits to the first subset of information bits and encoding the first subset of information bits in accordance with a first forward error correction scheme. The operations of 1410 may be performed according to the methods described herein. In some examples, aspects of the operations of 1410 may be performed by a bit processing component as described with reference to FIGs. 8 through 11.

At 1415, the device may process, at the second forward error correction stream, the second subset of information bits by encoding the second subset of information bits in accordance with a second forward error correction scheme. The operations of 1415 may be performed according to the methods described herein. In some examples, aspects of the operations of 1415 may be performed by a bit processing component as described with reference to FIGs. 8 through 11.

At 1420, the device may map the processed first subset of information bits to an inner constellation associated with a modulation scheme. The operations of 1420 may be performed according to the methods described herein. In some examples, aspects of the operations of 1420 may be performed by a mapping component as described with reference to FIGs. 8 through 11.

At 1425, the device may map the processed second subset of information bits to an outer constellation associated with the modulation scheme. The operations of 1425 may be performed according to the methods described herein. In some examples, aspects of the operations of 1425 may be performed by a mapping component as described with reference to FIGs. 8 through 11.

At 1430, the device may transmit one or more modulation symbols carrying the processed first subset of information bits and the processed second subset of information bits. The operations of 1430 may be performed according to the methods described herein. In some examples, aspects of the operations of 1430 may be performed by a symbol component as described with reference to FIGs. 8 through 11.

FIG. 15 shows a flowchart illustrating a method 1500 that supports cyclic redundancy check schemes for unequal error protection with forward error corrections in accordance with aspects of the present disclosure. The operations of method 1500 may be implemented by a device (e.g., a base station, a UE) or its components as described herein. For example, the operations of method 1500 may be performed by a communications manager as described with reference to FIGs. 8 through 11. In some examples, a device may execute a set of instructions to control the functional elements of the device to perform the functions described below. Additionally or alternatively, a device may perform aspects of the functions described below using special-purpose hardware.

At 1505, the device may divide a set of processed information bits into a first subset of information bits associated with a first forward error correction stream and a second subset of information bits associated with a second forward error correction stream. The operations of 1505 may be performed according to the methods described herein. In some examples, aspects of the operations of 1505 may be performed by a segmentation component as described with reference to FIGs. 8 through 11.

At 1510, the device may process, at a first forward error correction stream, the first subset of information bits by decoding a first set of one or more cyclic redundancy check bits of the first subset of information bits and decoding the first subset of information bits in accordance with the first forward error correction scheme. The operations of 1510 may be performed according to the methods described herein. In some examples, aspects of the operations of 1510 may be performed by a bit processing component as described with reference to FIGs. 8 through 11.

At 1515, the device may process, at a second forward error correction stream, the second subset of information bits based on decoding the first set of one or more cyclic redundancy check bits of the first subset of information bits. The operations of 1515 may be performed according to the methods described herein. In some examples, aspects of the operations of 1515 may be performed by a bit processing component as described with reference to FIGs. 8 through 11.

FIG. 16 shows a flowchart illustrating a method 1600 that supports cyclic redundancy check schemes for unequal error protection with forward error corrections in accordance with aspects of the present disclosure. The operations of method 1600 may be implemented by a device (e.g., a base station, a UE) or its components as described herein. For example, the operations of method 1600 may be performed by a communications manager as described with reference to FIGs. 8 through 11. In some examples, a device may execute a set of instructions to control the functional elements of the device to perform the functions described below. Additionally or alternatively, a device may perform aspects of the functions described below using special-purpose hardware.

At 1605, the device may divide a set of processed information bits into a first subset of information bits associated with a first forward error correction stream and a second subset of information bits associated with a second forward error correction stream. The operations of 1605 may be performed according to the methods described herein. In some examples, aspects of the operations of 1605 may be performed by a segmentation component as described with reference to FIGs. 8 through 11.

At 1610, the device may process, at a first forward error correction stream, the first subset of information bits by decoding a first set of one or more cyclic redundancy check bits of the first subset of information bits and decoding the first subset of information bits in accordance with the first forward error correction scheme. The operations of 1610 may be performed according to the methods described herein. In some examples, aspects of the operations of 1610 may be performed by a bit processing component as described with reference to FIGs. 8 through 11.

At 1615, the device may process, at a second forward error correction stream, the second subset of information bits based on decoding the first set of one or more cyclic redundancy check bits of the first subset of information bits. The operations of 1615 may be performed according to the methods described herein. In some examples, aspects of the operations of 1615 may be performed by a bit processing component as described with reference to FIGs. 8 through 11.

At 1620, the device may terminate decoding the second subset of information bits based on a failure to decode the first set of one or more cyclic redundancy check bits of the first subset of information bits. The operations of 1620 may be performed according to the methods described herein. In some examples, aspects of the operations of 1620 may be performed by a termination component as described with reference to FIGs. 8 through 11.

FIG. 17 shows a flowchart illustrating a method 1700 that supports cyclic redundancy check schemes for unequal error protection with forward error corrections in accordance with aspects of the present disclosure. The operations of method 1700 may be implemented by a device (e.g., a base station, a UE) or its components as described herein. For example, the operations of method 1700 may be performed by a communications manager as described with reference to FIGs. 8 through 11. In some examples, a device may execute a set of instructions to control the functional elements of the device to perform the functions described below. Additionally or alternatively, a device may perform aspects of the functions described below using special-purpose hardware.

At 1705, the device may divide a set of processed information bits into a first subset of information bits associated with a first forward error correction stream and a second subset of information bits associated with a second forward error correction stream. The operations of 1705 may be performed according to the methods described herein. In some examples, aspects of the operations of 1705 may be performed by a segmentation component as described with reference to FIGs. 8 through 11.

At 1710, the device may process, at a first forward error correction stream, the first subset of information bits by decoding a first set of one or more cyclic redundancy check bits of the first subset of information bits and decoding the first subset of information bits in accordance with the first forward error correction scheme. The operations of 1710 may be performed according to the methods described herein. In some examples, aspects of the operations of 1710 may be performed by a bit processing component as described with reference to FIGs. 8 through 11.

At 1715, the device may process, at a second forward error correction stream, the second subset of information bits based on decoding the first set of one or more cyclic redundancy check bits of the first subset of information bits. The operations of 1715 may be performed according to the methods described herein. In some examples, aspects of the operations of 1715 may be performed by a bit processing component as described with reference to FIGs. 8 through 11.

At 1720, the device may decode a second set of one or more cyclic redundancy check bits of the second subset of information bits and decode the second subset of information bits in accordance with the second forward error correction scheme based on successfully decoding the first set of one or more cyclic redundancy check bits of the first subset of information bits. The operations of 1720 may be performed according to the methods described herein. In some examples, aspects of the operations of 1720 may be performed by a decoding component as described with reference to FIGs. 8 through 11.

It should be noted that the methods described herein describe possible implementations, and that the operations and the steps may be rearranged or otherwise modified and that other implementations are possible. Further, aspects from two or more of the methods may be combined.

Although aspects of an LTE, LTE-A, LTE-A Pro, or NR system may be described for purposes of example, and LTE, LTE-A, LTE-A Pro, or NR terminology may be used in much of the description, the techniques described herein are applicable beyond LTE, LTE-A, LTE-A Pro, or NR networks. For example, the described techniques may be applicable to various other wireless communications systems such as Ultra Mobile Broadband (UMB) , Institute of Electrical and Electronics Engineers (IEEE) 802.11 (Wi-Fi) , IEEE 802.16 (WiMAX) , IEEE 802.20, Flash-OFDM, as well as other systems and radio technologies not explicitly mentioned herein.

Information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

The various illustrative blocks and components described in connection with the disclosure herein may be implemented or performed with a general-purpose processor, a DSP, an ASIC, a CPU, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration) .

The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Other examples and implementations are within the scope of the disclosure and appended claims. For example, due to the nature of software, functions described herein may be implemented using software executed by a processor, hardware, firmware, hardwiring, or combinations of any of these. Features implementing functions may also be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations.

Computer-readable media includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A non-transitory storage medium may be any available medium that may be accessed by a general-purpose or special purpose computer. By way of example, and not limitation, non-transitory computer-readable media may include random-access memory (RAM) , read-only memory (ROM) , electrically erasable programmable ROM (EEPROM) , flash memory, compact disk (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that may be used to carry or store desired program code means in the form of instructions or data structures and that may be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) , or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of computer-readable medium. Disk and disc, as used herein, include CD, laser disc, optical disc, digital versatile disc (DVD) , floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

As used herein, including in the claims, “or” as used in a list of items (e.g., a list of items prefaced by a phrase such as “at least one of” or “one or more of” ) indicates an inclusive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C) . Also, as used herein, the phrase “based on” shall not be construed as a reference to a closed set of conditions. For example, an example step that is described as “based on condition A” may be based on both a condition A and a condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase “based on” shall be construed in the same manner as the phrase “based at least in part on. ”

In the appended figures, similar components or features may have the same reference label. Further, various components of the same type may be distinguished by following the reference label by a dash and a second label that distinguishes among the similar components. If just the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the second reference label, or other subsequent reference label.

The description set forth herein, in connection with the appended drawings, describes example configurations and does not represent all the examples that may be implemented or that are within the scope of the claims. The term “example” used herein means “serving as an example, instance, or illustration, ” and not “preferred” or “advantageous over other examples. ” The detailed description includes specific details for the purpose of providing an understanding of the described techniques. These techniques, however, may be practiced without these specific details. In some instances, known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the described examples.

The description herein is provided to enable a person having ordinary skill in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to a person having ordinary skill in the art, and the generic principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not limited to the examples and designs described herein, but is to be accorded the broadest scope consistent with the principles and novel features disclosed herein.

Claims

A method for wireless communication, comprising:

dividing a set of information bits into a first subset of information bits associated with a first forward error correction stream and a second subset of information bits associated with a second forward error correction stream;

processing, at the first forward error correction stream, the first subset of information bits by appending a first set of one or more cyclic redundancy check bits to the first subset of information bits and encoding the first subset of information bits in accordance with a first forward error correction scheme;

processing, at the second forward error correction stream, the second subset of information bits by encoding the second subset of information bits in accordance with a second forward error correction scheme; and

transmitting one or more modulation symbols carrying the processed first subset of information bits and the processed second subset of information bits.
The method of claim 1, further comprising:

appending a second set of one or more cyclic redundancy check bits to the set of information bits prior to processing at the first forward error correction stream and at the second forward error correction stream.
The method of claim 2, wherein a length of the second set of one or more cyclic redundancy check bits appended to the set of information bits is greater than a length of the first set of one or more cyclic redundancy check bits.
The method of claim 1, wherein processing, at the first forward error correction stream, the first subset of information bits comprises:

appending the first set of one or more cyclic redundancy check bits to the first subset of information bits before encoding the first subset of information bits in accordance with the first forward error correction scheme.
The method of claim 1, wherein the first set of one or more cyclic redundancy check bits comprises an indication for early termination associated with decoding one or more of the one or more modulation symbols carrying the processed first subset of information bits or the processed second subset of information bits.
The method of claim 1, wherein the first set of one or more cyclic redundancy check bits comprises an indication for partial retransmission of one or more of the one or more modulation symbols carrying the processed first subset of information bits or the processed second subset of information bits.
The method of claim 1, wherein processing, at the second forward error correction stream, the second subset of information bits comprises:

appending a second set of one or more cyclic redundancy check bits to the second subset of information bits before encoding the second subset of information bits in accordance with the second forward error correction scheme.
The method of claim 7, wherein the second set of one or more cyclic redundancy check bits comprises an indication for early termination associated with decoding one or more of the one or more modulation symbols carrying the processed first subset of information bits or the processed second subset of information bits.
The method of claim 7, wherein the second set of one or more cyclic redundancy check bits comprises an indication for partial retransmission of one or more of the one or more modulation symbols carrying the processed first subset of information bits or the processed second subset of information bits.
The method of claim 1, wherein the first forward error correction scheme is different from the second forward error correction scheme.
The method of claim 1, further comprising:

retransmitting the one or more modulation symbols carrying the processed first subset of information bits and the processed second subset of information bits based at least in part on a feedback comprising a negative acknowledgment.
The method of claim 1, further comprising:

modulating, in accordance with a modulation scheme, the processed first subset of information bits and the processed second subset of information bits,

wherein transmitting the one or more modulation symbols carrying the processed first subset of information bits and the processed second subset of information bits is based at least in part on the modulating.
The method of claim 12, wherein modulating the processed first subset of information bits comprises:

mapping the processed first subset of information bits to an inner constellation associated with the modulation scheme.
The method of claim 12, wherein modulating the processed second subset of information bits comprises:

mapping the processed second subset of information bits to an outer constellation associated with the modulation scheme.
The method of claim 12, wherein the modulation scheme comprises a quadrature amplitude modulation (QAM) or a quadrature phase shift keying (QPSK) .
A method for wireless communication, comprising:

dividing a set of processed information bits into a first subset of information bits associated with a first forward error correction stream and a second subset of information bits associated with a second forward error correction stream;

processing, at a first forward error correction stream, the first subset of information bits by decoding a first set of one or more cyclic redundancy check bits of the first subset of information bits and decoding the first subset of information bits in accordance with the first forward error correction scheme; and

processing, at a second forward error correction stream, the second subset of information bits based at least in part on decoding the first set of one or more cyclic redundancy check bits of the first subset of information bits.
The method of claim 16, wherein processing, at the second forward error correction stream, the second subset of information bits comprises:

terminating decoding the second subset of information bits based at least in part on a failure to decode the first set of one or more cyclic redundancy check bits of the first subset of information bits.
The method of claim 16, further comprising:

transmitting a feedback comprising a negative acknowledgment associated with the failure to decode the first set of one or more cyclic redundancy check bits of the first subset of information bits.
The method of claim 16, wherein processing, at the second forward error correction stream, the second subset of information bits comprises:

decoding a second set of one or more cyclic redundancy check bits of the second subset of information bits and decoding the second subset of information bits in accordance with the second forward error correction scheme based at least in part on successfully decoding the first set of one or more cyclic redundancy check bits of the first subset of information bits.
The method of claim 16, further comprising:

demodulating, in accordance with a demodulation scheme, the one or more modulation symbols carrying the set of processed information bits,

wherein dividing the one or more modulation symbols carrying the set of processed information bits is based at least in part on the demodulating.
The method of claim 20, wherein the demodulation scheme comprises a quadrature amplitude modulation (QAM) or a quadrature phase shift keying (QPSK) .
An apparatus for wireless communication, comprising:

a processor,

memory coupled with the processor; and

instructions stored in the memory and executable by the processor to cause the apparatus to:

divide a set of information bits into a first subset of information bits associated with a first forward error correction stream and a second subset of information bits associated with a second forward error correction stream;

process, at the first forward error correction stream, the first subset of information bits by appending a first set of one or more cyclic redundancy check bits to the first subset of information bits and encoding the first subset of information bits in accordance with a first forward error correction scheme;

process, at the second forward error correction stream, the second subset of information bits by encoding the second subset of information bits in accordance with a second forward error correction scheme; and

transmit one or more modulation symbols carrying the processed first subset of information bits and the processed second subset of information bits.
An apparatus for wireless communication, comprising:

a processor,

memory coupled with the processor; and

instructions stored in the memory and executable by the processor to cause the apparatus to:

divide a set of processed information bits into a first subset of information bits associated with a first forward error correction stream and a second subset of information bits associated with a second forward error correction stream;

process, at a first forward error correction stream, the first subset of information bits by decoding a first set of one or more cyclic redundancy check bits of the first subset of information bits and decoding the first subset of information bits in accordance with the first forward error correction scheme; and

process, at a second forward error correction stream, the second subset of information bits based at least in part on decoding the first set of one or more cyclic redundancy check bits of the first subset of information bits.
An apparatus for wireless communication, comprising:

means for dividing a set of information bits into a first subset of information bits associated with a first forward error correction stream and a second subset of information bits associated with a second forward error correction stream;

means for processing, at the first forward error correction stream, the first subset of information bits by appending a first set of one or more cyclic redundancy check bits to the first subset of information bits and encoding the first subset of information bits in accordance with a first forward error correction scheme;

means for processing, at the second forward error correction stream, the second subset of information bits by encoding the second subset of information bits in accordance with a second forward error correction scheme; and

means for transmitting one or more modulation symbols carrying the processed first subset of information bits and the processed second subset of information bits.
An apparatus for wireless communication, comprising:

means for dividing a set of processed information bits into a first subset of information bits associated with a first forward error correction stream and a second subset of information bits associated with a second forward error correction stream;

means for processing, at a first forward error correction stream, the first subset of information bits by decoding a first set of one or more cyclic redundancy check bits of the first subset of information bits and decoding the first subset of information bits in accordance with the first forward error correction scheme; and

means for processing, at a second forward error correction stream, the second subset of information bits based at least in part on decoding the first set of one or more cyclic redundancy check bits of the first subset of information bits.
A non-transitory computer-readable medium storing code for wireless communication, the code comprising instructions executable by a processor to:

divide a set of information bits into a first subset of information bits associated with a first forward error correction stream and a second subset of information bits associated with a second forward error correction stream;

process, at the first forward error correction stream, the first subset of information bits by appending a first set of one or more cyclic redundancy check bits to the first subset of information bits and encoding the first subset of information bits in accordance with a first forward error correction scheme;

process, at the second forward error correction stream, the second subset of information bits by encoding the second subset of information bits in accordance with a second forward error correction scheme; and

transmit one or more modulation symbols carrying the processed first subset of information bits and the processed second subset of information bits.
A non-transitory computer-readable medium storing code for wireless communication, the code comprising instructions executable by a processor to:

divide a set of processed information bits into a first subset of information bits associated with a first forward error correction stream and a second subset of information bits associated with a second forward error correction stream;

process, at a first forward error correction stream, the first subset of information bits by decoding a first set of one or more cyclic redundancy check bits of the first subset of information bits and decoding the first subset of information bits in accordance with the first forward error correction scheme; and

process, at a second forward error correction stream, the second subset of information bits based at least in part on decoding the first set of one or more cyclic redundancy check bits of the first subset of information bits.