WO2021048978A1 - Electric device - Google Patents

Electric device Download PDF

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Publication number
WO2021048978A1
WO2021048978A1 PCT/JP2019/035937 JP2019035937W WO2021048978A1 WO 2021048978 A1 WO2021048978 A1 WO 2021048978A1 JP 2019035937 W JP2019035937 W JP 2019035937W WO 2021048978 A1 WO2021048978 A1 WO 2021048978A1
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WO
WIPO (PCT)
Prior art keywords
noise filter
wiring
inductance
circuit
capacitor
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Application number
PCT/JP2019/035937
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French (fr)
Japanese (ja)
Inventor
忍 長澤
Original Assignee
三菱電機株式会社
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Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to PCT/JP2019/035937 priority Critical patent/WO2021048978A1/en
Priority to JP2020510143A priority patent/JP6698975B1/en
Publication of WO2021048978A1 publication Critical patent/WO2021048978A1/en

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/12—Arrangements for reducing harmonics from ac input or output
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode

Definitions

  • the present invention relates to an electric device.
  • high-frequency conduction noise generated by the switching operation may flow out to the input power supply line.
  • high-frequency conduction noise may cause electromagnetic interference (EMI) such as malfunction, failure, and noise mixing in other electric devices connected to a common input power supply line. ..
  • EMI electromagnetic interference
  • Patent Document 1 in a noise reduction circuit (noise filter) having a common mode choke coil, a capacitor and a resistor are connected in series to each of the input side and the output side of the common mode choke coil. The configuration in which the body is provided is described.
  • each noise filter is usually adjusted so as to optimally suppress the conduction noise from the corresponding inverter circuit.
  • the present invention has been made to solve the above problems, and an object of the present invention is to provide an electric device having a configuration in which a plurality of power conversion circuits are connected to a common input power supply on the input power supply side. It is to enhance the effect of reducing the conduction noise of.
  • the electrical equipment includes a power receiving unit, first and second power conversion circuits including a switching element, first and second noise filter circuits, and first and second power conversion circuits. It is provided with a second wiring.
  • the power receiving unit has first and second power input nodes connected to the input power supply.
  • the first noise filter circuit is electrically connected between the power receiving unit and the first power conversion circuit.
  • the second noise filter circuit is electrically connected between the power receiving unit and the second power conversion circuit.
  • the first wiring electrically connects the power receiving unit and the first noise filter circuit.
  • the second wiring electrically connects the power receiving unit and the second noise filter circuit.
  • the first noise filter circuit includes a pair of first input terminals connected to the first wiring and a first capacitor.
  • the first capacitor is connected in parallel between the first input terminals with respect to the input power supply side of the first power conversion circuit.
  • the second noise filter circuit includes a pair of second input terminals connected to the second wiring and a second capacitor.
  • the second capacitor is connected in parallel between the second input terminals with respect to the input power supply side of the second power conversion circuit.
  • the first inductance of the first path formed between the first and second power input nodes via the first wiring and the first noise filter circuit, and the second wiring and The second inductance of the second path formed via the second noise filter circuit is such that the ratio of the first inductance to the second inductance is the second with respect to the first capacitance of the first capacitor. It is adjusted to follow the ratio of the second capacitance of the capacitor.
  • FIG. It is a circuit diagram explaining the structural example of the electric device which concerns on Embodiment 1.
  • FIG. It is a graph which shows the simulation result of the conduction noise leaking from the electric device shown in FIG. 1 to the input power source. It is a graph which shows the same simulation result as FIG. 2 under changing the parameter x. It is a graph which shows the simulation result of the change of the decrease amount of the peak value of conduction noise with respect to a parameter x.
  • FIG. It is a circuit diagram explaining the structure of the electric device which concerns on Embodiment 2.
  • FIG. It is a simple equivalent circuit diagram in the parallel resonance frequency of the resonance circuit formed on the input power source side of the electric device which concerns on Embodiment 2.
  • FIG. It is a graph which shows the same simulation result as FIG.
  • FIG. 2 in the electric apparatus which concerns on Embodiment 2.
  • FIG. It is a graph which shows the same simulation result as FIG. 3 in the electric apparatus which concerns on Embodiment 2.
  • FIG. It is a circuit diagram explaining the structural example of the electric device which concerns on Embodiment 3.
  • FIG. It is a circuit diagram explaining the structural example of the electric device which concerns on Embodiment 4.
  • FIG. It is a circuit diagram explaining the structural example of the electric device which concerns on Embodiment 5.
  • It is a circuit diagram explaining the structural example of the electric device which concerns on the modification of Embodiment 5.
  • It is a circuit diagram explaining the 1st configuration example of the electric apparatus which concerns on Embodiment 6.
  • FIG. 1 is a circuit diagram illustrating a configuration example of the electric device 100 according to the first embodiment.
  • the electric device 100 includes wirings 70a and 71a, wirings 70b and 71b, a power receiving unit 110, noise filter circuits 25a and 25b, and power conversion circuits 150a and 150b. To be equipped.
  • the power receiving unit 110 has power input nodes N0 and N1 connected to the input power source 10.
  • the input power supply 10 is composed of, for example, a commercial AC system power supply. That is, an AC voltage having a system frequency (for example, 50 [Hz] or 60 [Hz]) is input between the power input nodes N0 and N1.
  • the input side of the power conversion circuit 150a is connected to the power input nodes N0 and N1 (power receiving unit 110) via the wirings 70a and 71a and the noise filter circuit 25a.
  • the input side of the power conversion circuit 150b is connected to the power input nodes N0 and N1 (power receiving unit 110) via the wirings 70b and 71b and the noise filter circuit 25b.
  • the AC voltage from the input power supply 10 is input to each of the power conversion circuits 150a and 150b.
  • the wirings 70a, 71a, 70b, and 71b each have the same material and diameter, the wirings 70a and 71a have the same length, and the wirings 70b and 71b also have the same length. And.
  • the power input nodes N0 and N1 correspond to the "first power input node” and the "second power input node”
  • the wirings 70a and 71a correspond to the "first wiring”
  • the wirings 70b, 71b corresponds to the "second wiring”.
  • the power conversion circuit 150a corresponds to an embodiment of the "first power conversion circuit”
  • the power conversion circuit 150b corresponds to an embodiment of the "second power conversion circuit”.
  • the power conversion circuits 150a and 150b have a rectifier circuit (not shown) that converts the AC voltage from the input power supply 10 into a DC voltage, and the output voltage from the rectifier circuit is converted into an AC voltage by on / off control of the semiconductor switching element. It is configured to include an inverter circuit (not shown). Although not shown, a load (for example, a motor or the like) driven by the electric power converted by the electric power conversion circuits 150a and 150b is connected to the output side of the electric power conversion circuits 150a and 150b.
  • a load for example, a motor or the like
  • Noise filter circuits 25a and 25b are connected between the power receiving unit 110 and the power conversion circuits 150a and 150b, respectively, in order to suppress conduction noise on the input power supply 10 side due to the high frequency noise.
  • the input terminals 80a and 81a of the noise filter circuit 25a are connected to the power input nodes N0 and N1 of the power receiving unit 110 by the wirings 70a and 71a, respectively.
  • Each of the wirings 70a and 71a has a parasitic inductance L1.
  • the noise filter circuit 25a includes a capacitor 82a having a capacitance C1 and a common mode choke coil 85a.
  • the capacitor 82a having the parasitic inductance Lx1 is connected between the input terminals 80a and 81a.
  • the common mode choke coil 85a is connected between the capacitor 82a and the power conversion circuit 150a.
  • the input terminals 80b and 81b of the noise filter circuit 25b are connected to the power input nodes N0 and N1 of the power receiving unit 110 by the wirings 70b and 71b, respectively.
  • Each of the wires 70b and 71b has a parasitic inductance L2.
  • the noise filter circuit 25b includes a capacitor 82b having a capacitance C2 and a common mode choke coil 85b.
  • the capacitor 82b having the parasitic inductance Lx2 is connected between the input terminals 80b and 81b.
  • the common mode choke coil 85b is connected between the capacitor 82b and the power conversion circuit 150b.
  • the capacitors 82a and 82b are connected in parallel to the input side of the power conversion circuits 150a and 150b, and the common mode choke coils 85a and 85b are connected in series.
  • the noise filter circuit 25a corresponds to an embodiment of the “first noise filter circuit”
  • the noise filter circuit 25b corresponds to an embodiment of the “second noise filter circuit”.
  • the capacitor 82a corresponds to an embodiment of the "first capacitor”
  • the capacitor 82b corresponds to an embodiment of the "second capacitor”.
  • a first series is provided between the power receiving unit 110 and the power conversion circuit 150a by the capacitance C1 of the capacitor 82a and the parasitic inductance Lx1 and the parasitic inductance L1 of each of the wirings 70a and 71a.
  • a resonant circuit is formed.
  • a second series resonant circuit is formed between the power receiving unit 110 and the power conversion circuit 150b by the capacitance C2 of the capacitor 82b and the parasitic inductance Lx2, and the parasitic inductance L2 of each of the wirings 70b and 71b.
  • a parallel resonance circuit in which the first and second series resonance circuits are connected in parallel is formed in the path to which the input sides of the power conversion circuits 150a and 150b are connected via the power receiving unit 110.
  • FIG. 2 is a graph showing a simulation result of conduction noise leaking from the electric device 100 shown in FIG. 1 to the input power source 10.
  • the horizontal axis of FIG. 2 is a logarithmic display of the frequency [Hz], and the vertical axis is the intensity of conduction noise.
  • the characteristic line CL0 is a simulation result before applying the circuit constant setting described later.
  • the value relations of the circuit constants in the simulation are C1 ⁇ C2 and La ⁇ Lb.
  • the parasitic inductance Lx1 (Lx1 ⁇ L1) of the capacitor 82a and the parasitic inductance Lx2 (Lx2 ⁇ L2) of the capacitor 82b are also set.
  • the parasitic inductances Lx1 and Lx2 are set to about the number (%) of the parasitic inductances L1 and L2 (wiring 70a and 71a), respectively.
  • the characteristic line CL0 has a maximum peak of conduction noise due to parallel resonance by the above-mentioned parallel resonance circuit.
  • L1 >> Lx1 and L2 >> Lx2
  • the parallel resonance frequency fp at which the maximum peak occurs can be expressed by the following equation (1).
  • the conduction noise is maximized by setting the circuit constants for matching the parallel resonance frequency fp at which the maximum peak of the conduction noise occurs and the series resonance frequencies fs1 and fs2 at which the minimum peak occurs.
  • the parallel resonance peak can be extinguished.
  • the maximum point of the parallel resonance peak on the characteristic line CL0 is canceled by the two minimum points of the series resonance peak, so that the conduction at the maximum point near 500 [kHz] corresponding to the parallel resonance frequency fp
  • the peak value of noise is reduced.
  • the peak value is reduced by 30 [dB] or more from the peak value at the characteristic line CL0.
  • the capacitances C1 and C2 of the capacitors 82a and 82b in the noise filter circuits 25a and 25b need to be set to appropriate values corresponding to the noise characteristics of the power conversion circuits 150a and 150b which are noise sources. Therefore, it is difficult to adjust the capacitances C1 and C2 from the viewpoint of setting the circuit constants for reducing conduction noise.
  • the parasitic inductances L1 and L2 change depending on the wiring length, diameter, material, etc. of the wirings 70a and 71a and the wirings 70b and 71b.
  • the parasitic inductance of the wiring is proportional to the wiring length. Therefore, typically, the circuit constant setting for reducing conduction noise is realized by adjusting the wiring lengths of the wirings 70a and 71a and the wirings 70b and 71b. Is possible.
  • C2 can be realized by aligning the wiring lengths of the wirings 70a and 71a with the wiring lengths of the wirings 70b and 71b.
  • C2 m ⁇ C1 (real number of m: m> 0) from the noise characteristics of the power conversion circuits 150a and 150b
  • the wiring lengths of the wirings 70a and 71a are set to the wirings of the wirings 70b and 71b.
  • FIG. 3 is a graph showing the same simulation results as in FIG. 2 when the parameter x is changed.
  • the conduction noise at the parallel resonance frequency fp is reduced by 30 [dB] or more as compared with the characteristic line CL0.
  • the peak value at the maximum point at the resonance frequency fp * is larger than that in the characteristic line CL12.
  • FIG. 4 is a graph showing a simulation result of a change in the amount of decrease in the peak value of conduction noise with respect to the parameter x.
  • the parameter x When the parameter x deviates significantly from 1.0, for example, in the simulation result of FIG. 4, in the region of x ⁇ 0.76 and x> 1.2, the resonance frequency after setting the circuit constant (fp * in FIG. 2). It is understood that the conduction noise in (corresponding to) increases more than the characteristic line CL0. Therefore, in light of the simulation results of FIG. 4, the parameter x is preferably in the range of 0.76 ⁇ x ⁇ 1.2.
  • a capacitor in a noise filter circuit corresponding to a plurality of power conversion circuits in a configuration in which a plurality of power conversion circuits are connected to a common input power supply can be realized by setting the circuit constant according to the above-mentioned inverse ratio of the capacitance of the above and the parasitic inductance of the wiring or the like.
  • Embodiment 2 In the second embodiment, a circuit configuration will be described in which the capacitances C1 and C2 of the capacitors 82a and 82b of the noise filter circuits 25a and 25b further enhance the noise reduction effect under the inconsistency.
  • FIG. 5 is a circuit diagram illustrating a configuration example of the electric device according to the second embodiment.
  • a resistance element 86 resistance value R1
  • R1 resistance element 86
  • FIG. 5 shows an example of a circuit configuration when C1 ⁇ C2. Therefore, the resistance element 86 is connected in series with the capacitor 82a between the input terminals 80a and 81a in the noise filter circuit 25a.
  • the configuration of the noise filter circuit 25b including the capacitor 82b (capacitance C2) is the same as that of the first embodiment (FIG. 1).
  • the resistance value R1 of the resistance element 86 can be set based on the simple equivalent circuit diagram shown in FIG.
  • FIG. 6 is a simple equivalent circuit diagram at the parallel resonance frequency fp (FIG. 2) of the resonance circuit formed on the input power supply 10 side of the electric device 101.
  • the capacitor 82a (C1) acts as a capacitance in the noise filter circuit 25a, while the parasitic inductance L1 of the wirings 70a and 71a can be ignored on the resonance circuit.
  • the capacitor 82b (C2) does not act as a capacitance, while the parasitic inductance L2 of the wirings 70a and 71a acts.
  • Lb 2 ⁇ L1.
  • the following equation (6) can be obtained by arranging the equation (5) into a real number term and an imaginary number term.
  • the equation (10) specifies only the lower limit of the resistance value R1. On the other hand, if R1 becomes excessive, the noise reduction effect of the capacitor 82a (C1) is lost. Therefore, by further using the upper limit value from this viewpoint, the appropriate value of the resistance value R1 can be determined.
  • FIG. 7 is a graph showing the same simulation results as in FIG. 2 in the electric device 101 shown in FIG.
  • the characteristic line CL0 is the same as that of FIG. 2, and a maximum peak of conduction noise is generated at the parallel resonance frequency fp.
  • the noise reduction effect of the characteristic line CL0 at the parallel resonance frequency fp is the same as that of the characteristic line CL1 in the first embodiment.
  • the parallel resonance peak can be blunted by setting the resistance value R1 of the newly arranged resistance element 86 according to the equation (10).
  • the size of the parallel resonance peak at which the conduction noise is maximized can be made smaller than the size of the series resonance peak at which the conduction noise is at its minimum.
  • FIG. 8 is a graph showing the same simulation results as in FIG. 3 in the electric device 101 shown in FIG.
  • the conduction noise at the parallel resonance frequency fp is reduced by 30 [dB] or more as compared with the characteristic line CL0.
  • the parallel resonance peak is blunted by the arrangement of the resistance element 86, as compared with the first embodiment (FIG. 3). Therefore, it is understood that the peak value at the resonance frequency fp * is suppressed.
  • the noise reduction effect can be enhanced by arranging the resistance element 86 in the noise filter including the low-capacity capacitor.
  • the second embodiment is also applied when the capacitance C1 of the capacitor 82a is larger than the capacitance C2 of the capacitor 82b (C1> C2). be able to.
  • the resistance element 86 is connected in series with the capacitor 82b between the input terminals 80b and 81b in the noise filter circuit 25b.
  • the configuration of the noise filter circuit 25a including the capacitor 82a is the same as that of the first embodiment (FIG. 1).
  • the range of the resistance value R1 can be determined by substituting La for the inductance Lb and C2 for the capacitance C1.
  • FIG. 9 is a circuit diagram illustrating a configuration example of the electric device according to the third embodiment.
  • the noise filter circuits 25a and 25b have the adjusting inductors 87a and 88a as compared with the electric device 100 (FIG. 1) according to the first embodiment. And the adjustment inductors 87b and 88b are further provided. Since the configuration of the other parts of the electric device 102 is the same as that of the electric device 100, the detailed description will not be repeated.
  • the adjusting inductor 87a is electrically connected to the input power supply side of the capacitor 82a in a manner of being connected in series with the wiring 70a or 71a.
  • the adjusting inductor 88a is connected in series with the capacitor 82a.
  • the adjusting inductor 87a corresponds to one embodiment of the "first adjusting inductor”
  • the adjusting inductor 88a corresponds to one embodiment of the "second adjusting inductor”.
  • the adjusting inductor 87b is electrically connected to the input power supply side of the capacitor 82b in a manner of being connected in series to the wiring 70b or 71b.
  • the adjusting inductor 88b is connected in series with the capacitor 82b.
  • the adjusting inductor 87b corresponds to one embodiment of the "first adjusting inductor”
  • the adjusting inductor 88b corresponds to one embodiment of the "second adjusting inductor”.
  • La ⁇ C1 Lb, which is a setting condition of the circuit constant for matching the parallel resonance frequency at which the conduction noise is maximum and the series resonance frequency at which the conduction noise is minimum.
  • C2 is represented by the following equation (11) in consideration of the inductances of the adjusting inductors 87a, 87b, 88a, 88b.
  • the parasitic inductances L1 and L2 can be adjusted to some extent by the lengths of the wirings 70a and 71a and the wirings 70b and 71b, but it is generally difficult to adjust them with high accuracy.
  • FIG. 10 is a circuit diagram illustrating a configuration example of the electric device 103 according to the fourth embodiment.
  • the noise filter circuit 25a has the same resistance element as that of FIG. It differs in that it further has 86 (resistance value R1). That is, also in FIG. 10, the capacitances of the capacitors 82a and 82b are different between the noise filter circuits 25a and 25b, and a circuit configuration example when C1 ⁇ C2 is shown as in FIG.
  • the electric device 103 as described in the third embodiment, it is possible to arrange only a part of the adjusting inductors 87a, 87b, 88a, 88b. Further, as described in the second embodiment, the resistance element 86 is also connected in series with the capacitor 82b between the input terminals 80b and 81b in the noise filter circuit 25b when C2 ⁇ C1.
  • FIG. 11 is a circuit diagram illustrating a configuration example of the electric device according to the fifth embodiment.
  • the electric device 104 has a different configuration of the noise filter circuits 25a and 25b from the electric device 100 shown in FIG. Specifically, in the noise filter circuit 25a, the common mode choke coil 85a is connected between the input terminals 80a and 81a and the capacitor 82a, and the capacitor 82a is between the common mode choke coil 85a and the power conversion circuit 150a. Connected to. Similarly, in the noise filter circuit 25b, the common mode choke coil 85b is connected between the input terminals 80b and 81b and the capacitor 82b, and the capacitor 82b is connected between the common mode choke coil 85b and the power conversion circuit 150b. Will be done.
  • La ⁇ C1 Lb ⁇ C2
  • Ldm1 and Ldm2 the common mode choke coils 85a and 85b.
  • the circuit constants for reducing conduction noise are set by combining the leakage inductances Ldm1 and Ldm2 with the adjustment of the lengths of the wirings 70a and 71a and the wirings 70b and 71b.
  • the feasibility of La ⁇ C1 Lb ⁇ C2) can be improved.
  • FIG. 12 is a circuit diagram illustrating a configuration example of an electric device 105 according to a modification of Embodiment 5.
  • the electric device 105 according to the modified example of the fifth embodiment is the same as that of FIG. 9 (3rd embodiment) in addition to the configuration of the electric device 104 (FIG. 10) according to the fifth embodiment.
  • the point that the adjusting inductors 87a and 88a and the adjusting inductors 87b and 88b are further provided, and the point that the noise filter circuit 25a further has the same resistance element 86 (resistance value R1) as in FIG. 5 (Embodiment 2). Is different. That is, also in FIG. 12, the capacitances of the capacitors 82a and 82b are different between the noise filter circuits 25a and 25b, and a circuit configuration example when C1 ⁇ C2 is shown as in FIG.
  • the inductance La 2, L1 + 2, Ldm1 + La1 + Lxa1 of the path formed between the power input nodes N0 and N1 via the noise filter circuit 25a.
  • the conditions of the circuit constants for reducing the conduction noise La ⁇ C1 are obtained by additionally arranging the adjusting inductors 87a, 87b, 88a, 88b as compared with the fifth embodiment.
  • Lb ⁇ C2 can be realized more easily, and the parallel resonance peak can be blunted by arranging the resistance element 86.
  • Embodiment 6 In the sixth embodiment, a configuration example will be described in the case where the electric device is an air conditioner including an outdoor unit and an indoor unit.
  • FIG. 13 is a circuit diagram illustrating a first configuration example of the electric device according to the sixth embodiment.
  • the electric device 106 according to the first configuration example of the sixth embodiment includes a plug 11, a relay switch 200, an indoor unit 300a, and an outdoor unit that are electrically connected to the input power source 10. It is equipped with 300b.
  • the indoor unit 300a includes a noise filter circuit 25a and a power conversion circuit 150a similar to those in the first embodiment.
  • the indoor unit power receiving unit 110a installed internally in the indoor unit 300a is electrically connected to the noise filter circuit 25a.
  • the power conversion circuit 150a supplies AC power to a fan motor (not shown) of an indoor unit.
  • the outdoor unit 300b includes a noise filter circuit 25b and a power conversion circuit 150b similar to those in the first embodiment.
  • the outdoor unit power receiving unit 110b installed internally in the outdoor unit 300b is electrically connected to the noise filter circuit 25b.
  • the power conversion circuit 150b supplies AC power to the drive motor of the refrigerant compressor (not shown) of the outdoor unit.
  • the indoor unit power receiving unit 110a installed internally in the indoor unit 300a is electrically connected to the plug 11.
  • the outdoor unit power receiving unit 110b installed internally in the outdoor unit 300b is connected to the indoor unit power receiving unit 110a via the relay switch 200, so that power is supplied from the input power source 10 connected to the plug 11.
  • the electric device 106 air conditioner
  • the leakage current is suppressed by turning off the relay switch 200.
  • the indoor unit power receiving unit 110a and the outdoor unit power receiving unit 110b corresponding to the noise filter circuits 25a and 25b, respectively, are connected stepwise to the input power source, whereby the electric device 106 It is understood that the difference in wiring length between the "power receiving unit” of the above and each of the noise filter circuits 25a and 25b becomes large.
  • the indoor unit power receiving unit 110a connected to the input power supply via the plug 11 corresponds to the “power receiving unit”.
  • the parasitic inductance due to the wiring length between the indoor unit power receiving unit 110a and the outdoor unit power receiving unit 110b is included.
  • the parasitic inductance L1 (inductance La) on the noise filter circuit 25a side is smaller than the parasitic inductance L2 (inductance Lb) on the noise filter circuit 25b side (L1 ⁇ L2), and , The difference is relatively large.
  • FIG. 14 is a circuit diagram illustrating a second configuration example of the electric device according to the sixth embodiment.
  • the electric device 107 according to the second configuration example of the sixth embodiment includes a plug 11, a relay switch 200, and an indoor unit 300a similar to the electric device 106 shown in FIG. , The outdoor unit 300b is provided.
  • the outdoor unit power receiving unit 110b is electrically connected to the plug 11, and the indoor unit power receiving unit 110a is connected to the outdoor unit power receiving unit 110b via the outdoor unit power receiving unit 110b. It is connected in stages to the input power supply. As a result, even in the electric device 107, the difference in wiring length between the “power receiving unit” and each of the noise filter circuits 25a and 25b becomes large.
  • the outdoor unit power receiving unit 110b connected to the input power supply via the plug 11 corresponds to the “power receiving unit”.
  • the parasitic inductance due to the wiring length between the outdoor unit power receiving unit 110b and the indoor unit power receiving unit 110a is included.
  • the parasitic inductance L2 (inductance Lb) on the noise filter circuit 25b side is smaller than the parasitic inductance L1 (inductance La) on the noise filter circuit 25a side (L2 ⁇ L1), and , The difference is relatively large.
  • the configuration in which the resistance element 86 described in the second embodiment is connected in series with the capacitor 82a or 82b with respect to the electric devices 106 and 107 according to the sixth embodiment and the modified examples thereof is described in the third embodiment.
  • the common mode choke coils 85a and 85b are connected so as to utilize the configuration in which at least a part of the adjusting inductors 87a, 87b, 88a and 88b is additionally arranged and the leakage inductances Ldm1 and Ldm2 described in the fifth embodiment. It is also possible to combine some or all of the configurations.
  • the configuration in which the two power conversion circuits 150a and 150b are connected to the common power receiving unit 110 (input power supply 10) has been described, but the power receiving unit in which three or more power conversion circuits are common. It is possible to apply this embodiment to a configuration connected to (input power supply).
  • the circuit configuration and circuit constant conditions related to the noise filter circuit on the input side are set between the two power conversion circuits that generate a large amount of noise among the three or more power conversion circuits according to the first to sixth embodiments. Can be similar to any of.
  • the configurations described in the respective embodiments may be appropriately combined within a range that does not cause inconsistency or inconsistency, including combinations not mentioned in the specification.
  • the points planned from the beginning of the application will also be described in a confirmatory manner.
  • 10 input power supply 11 plug, 25a, 25b noise filter circuit, 70a, 70b, 71a, 71b wiring, 80a, 80b input terminal, 82a, 82b capacitor, 85a, 85b common mode choke coil, 86 resistance element, 87a, 87b, 88a, 88b Adjustment inductor, 100-107 electrical equipment, 110 power receiving unit, 110a indoor unit power receiving unit, 110b outdoor unit power receiving unit, 150a, 150b power conversion circuit, 200 relay switch, 300a indoor unit, 300b outdoor unit, N0, N1 power input node, R1 resistance value, fp parallel resonance frequency, fp * resonance frequency (after setting circuit constant conditions), fs1, fs2 series resonance frequency.

Abstract

A first power conversion circuit (150a) and a second power conversion circuit (150b) are connected in common to a power receiving part (110) connected to an input power supply (10) via a first noise filter circuit (25a) and a second noise filter circuit (25b). A first inductance (La) in a first path formed, through the first noise filter circuit (25a), between power supply input nodes (N0, N1) of the power receiving part (110) and a second inductance (Lb) in a second path formed, through the second noise filter circuit (25b), between the power supply input nodes (N0, N1) are adjusted so that the ratio (La/Lb) of the first inductance to the second inductance follows the ratio (C2/C1) of capacitance (C2) of a second capacitor (82b) to capacitance (C1) of a first capacitor (82a).

Description

電気機器Electrical equipment
　本発明は、電気機器に関する。 The present invention relates to an electric device.
　電気機器、特に、高周波スイッチングを伴う電力変換回路（例えば、インバータ回路）を内蔵する構成のものでは、当該スイッチング動作により発生する高周波の伝導ノイズが入力電源ラインに流出する可能性がある。このような高周波伝導ノイズは、共通の入力電源ラインに接続された他の電気機器に対して、誤動作、故障、及び、雑音混入等の電磁妨害（ＥＭＩ：Electromagnetic　Interference）を引き起こすことが懸念される。 In electrical equipment, especially those with a built-in power conversion circuit (for example, an inverter circuit) that involves high-frequency switching, high-frequency conduction noise generated by the switching operation may flow out to the input power supply line. There is a concern that such high-frequency conduction noise may cause electromagnetic interference (EMI) such as malfunction, failure, and noise mixing in other electric devices connected to a common input power supply line. ..
　このため、伝導ノイズ対策として、電気機器内に、入力電源及び電力変換回路（インバータ）の間にノイズフィルタを配置することが公知である。ノイズフィルタの配置により、所定の規格による規制値以下に伝導ノイズを抑制することが期待される。 Therefore, as a countermeasure against conduction noise, it is known to arrange a noise filter between the input power supply and the power conversion circuit (inverter) in the electric device. By arranging the noise filter, it is expected that the conduction noise is suppressed below the regulation value according to the predetermined standard.
　特開２０１７－１８４３２８号公報（特許文献１）には、コモンモードチョークコイルを有するノイズ低減回路（ノイズフィルタ）において、コモンモードチョークコイルの入力側及び出力側の各々に、コンデンサ及び抵抗の直列接続体を設ける構成が記載されている。 According to Japanese Patent Application Laid-Open No. 2017-184328 (Patent Document 1), in a noise reduction circuit (noise filter) having a common mode choke coil, a capacitor and a resistor are connected in series to each of the input side and the output side of the common mode choke coil. The configuration in which the body is provided is described.
　特許文献１によれば、配線等の寄生インダクタンス、及び、寄生容量によって形成される意図しないＬＣ共振回路のＱ値を、コンデンサに直列接続された抵抗によって低下させることが可能である。この結果、インバータ回路にて発生するノイズの流出を広い周波数帯域において抑制することが可能である。 According to Patent Document 1, it is possible to reduce the parasitic inductance of wiring and the Q value of an unintended LC resonant circuit formed by parasitic capacitance by a resistor connected in series with a capacitor. As a result, it is possible to suppress the outflow of noise generated in the inverter circuit in a wide frequency band.
特開２０１７－１８４３２８号公報Japanese Unexamined Patent Publication No. 2017-184328
　複数の電力変換回路（インバータ回路）を備えた電気機器では、入力電源と複数のインバータ回路の入力端子との間にそれぞれノイズフィルタを接続する構成とされることが一般的である。この際に、通常、各ノイズフィルタは、対応するインバータ回路からの伝導ノイズを最適に抑制できるように調整される。 In an electric device equipped with a plurality of power conversion circuits (inverter circuits), it is common that a noise filter is connected between the input power supply and the input terminals of the plurality of inverter circuits. At this time, each noise filter is usually adjusted so as to optimally suppress the conduction noise from the corresponding inverter circuit.
　しかしながら、上記構成では、共通の入力電源に対して複数のインバータ回路が接続されることにより、入力電源側の配線の寄生インダクタンス等によって意図しない共振回路が１又は複数形成される可能性がある。 However, in the above configuration, by connecting a plurality of inverter circuits to a common input power supply, there is a possibility that one or a plurality of unintended resonance circuits may be formed due to the parasitic inductance of the wiring on the input power supply side.
　このような共振回路が形成されると、各ノイズフィルタ単体で調整したフィルタ特性を発揮できなくなることが懸念される。又、各ノイズフィルタに特許文献１に記載された構成を適用した場合にも、形成された共振回路での共振ピークをなまらせる効果は生じるものの、十分なノイズ低減効果を得られないことが懸念される。 If such a resonance circuit is formed, there is a concern that the filter characteristics adjusted by each noise filter alone cannot be exhibited. Further, even when the configuration described in Patent Document 1 is applied to each noise filter, there is a concern that a sufficient noise reduction effect cannot be obtained, although the effect of smoothing the resonance peak in the formed resonance circuit is produced. Will be done.
　本発明は上記のような問題を解決するためになされたものであって、本発明の目的は、複数の電力変換回路が共通の入力電源と接続される構成の電気機器において、入力電源側での伝導ノイズの低減効果を高めることである。 The present invention has been made to solve the above problems, and an object of the present invention is to provide an electric device having a configuration in which a plurality of power conversion circuits are connected to a common input power supply on the input power supply side. It is to enhance the effect of reducing the conduction noise of.
　本発明のある局面によれば、電気機器は、受電部と、スイッチング素子を含んで構成された第１及び第２の電力変換回路と、第１及び第２のノイズフィルタ回路と、第１及び第２の配線とを備える。受電部は、入力電源と接続された第１及び第２の電源入力ノードを有する。第１のノイズフィルタ回路は、受電部及び第１の電力変換回路の間に電気的に接続される。第２のノイズフィルタ回路は、受電部及び第２の電力変換回路の間に電気的に接続される。第１の配線は、受電部及び第１のノイズフィルタ回路を電気的に接続する。第２の配線は、受電部及び第２のノイズフィルタ回路を電気的に接続する。第１のノイズフィルタ回路は、第１の配線と接続される１対の第１入力端子と、第１のコンデンサとを含む。第１のコンデンサは、第１入力端子間に、第１の電力変換回路の入力電源側に対して並列接続される。第２のノイズフィルタ回路は、第２の配線と接続される１対の第２入力端子と、第２のコンデンサとを含む。第２のコンデンサは、第２入力端子間に、第２の電力変換回路の入力電源側に対して並列接続される。更に、第１及び第２の電源入力ノードの間に、第１の配線及び第１のノイズフィルタ回路を経由して形成される第１の経路の第１のインダクタンス、並びに、第２の配線及び前記第２のノイズフィルタ回路を経由して形成される第２の経路の第２のインダクタンスは、第２のインダクタンスに対する第１のインダクタンスの比が、第１のコンデンサの第１のキャパシタンスに対する第２のコンデンサの第２のキャパシタンスの比に従うように調整される。 According to an aspect of the present invention, the electrical equipment includes a power receiving unit, first and second power conversion circuits including a switching element, first and second noise filter circuits, and first and second power conversion circuits. It is provided with a second wiring. The power receiving unit has first and second power input nodes connected to the input power supply. The first noise filter circuit is electrically connected between the power receiving unit and the first power conversion circuit. The second noise filter circuit is electrically connected between the power receiving unit and the second power conversion circuit. The first wiring electrically connects the power receiving unit and the first noise filter circuit. The second wiring electrically connects the power receiving unit and the second noise filter circuit. The first noise filter circuit includes a pair of first input terminals connected to the first wiring and a first capacitor. The first capacitor is connected in parallel between the first input terminals with respect to the input power supply side of the first power conversion circuit. The second noise filter circuit includes a pair of second input terminals connected to the second wiring and a second capacitor. The second capacitor is connected in parallel between the second input terminals with respect to the input power supply side of the second power conversion circuit. Further, the first inductance of the first path formed between the first and second power input nodes via the first wiring and the first noise filter circuit, and the second wiring and The second inductance of the second path formed via the second noise filter circuit is such that the ratio of the first inductance to the second inductance is the second with respect to the first capacitance of the first capacitor. It is adjusted to follow the ratio of the second capacitance of the capacitor.
　本発明によれば、複数の電力変換回路が共通の入力電源と接続される構成の電気機器において、入力電源側での伝導ノイズの低減効果を高めることができる。 According to the present invention, it is possible to enhance the effect of reducing conduction noise on the input power supply side in an electric device having a configuration in which a plurality of power conversion circuits are connected to a common input power supply.
実施の形態１に係る電気機器の構成例を説明する回路図である。It is a circuit diagram explaining the structural example of the electric device which concerns on Embodiment 1. FIG. 図１に示された電気機器から入力電源に漏れ出す伝導ノイズのシミュレーション結果を示すグラフである。It is a graph which shows the simulation result of the conduction noise leaking from the electric device shown in FIG. 1 to the input power source. パラメータｘを変化させた下での図２と同様のシミュレーション結果を示すグラフである。It is a graph which shows the same simulation result as FIG. 2 under changing the parameter x. パラメータｘに対する伝導ノイズのピーク値の減少量の変化のシミュレーション結果を示すグラフである。It is a graph which shows the simulation result of the change of the decrease amount of the peak value of conduction noise with respect to a parameter x. 実施の形態２に係る電気機器の構成を説明する回路図である。It is a circuit diagram explaining the structure of the electric device which concerns on Embodiment 2. FIG. 実施の形態２に係る電気機器の入力電源側に形成される共振回路の並列共振周波数における簡易等価回路図である。It is a simple equivalent circuit diagram in the parallel resonance frequency of the resonance circuit formed on the input power source side of the electric device which concerns on Embodiment 2. FIG. 実施の形態２に係る電気機器における図２と同様のシミュレーション結果を示すグラフである。It is a graph which shows the same simulation result as FIG. 2 in the electric apparatus which concerns on Embodiment 2. FIG. 実施の形態２に係る電気機器における図３と同様のシミュレーション結果を示すグラフである。It is a graph which shows the same simulation result as FIG. 3 in the electric apparatus which concerns on Embodiment 2. FIG. 実施の形態３に係る電気機器の構成例を説明する回路図である。It is a circuit diagram explaining the structural example of the electric device which concerns on Embodiment 3. FIG. 実施の形態４に係る電気機器の構成例を説明する回路図である。It is a circuit diagram explaining the structural example of the electric device which concerns on Embodiment 4. FIG. 実施の形態５に係る電気機器の構成例を説明する回路図である。It is a circuit diagram explaining the structural example of the electric device which concerns on Embodiment 5. 実施の形態５の変形例に係る電気機器の構成例を説明する回路図である。It is a circuit diagram explaining the structural example of the electric device which concerns on the modification of Embodiment 5. 実施の形態６に係る電気機器の第１の構成例を説明する回路図である。It is a circuit diagram explaining the 1st configuration example of the electric apparatus which concerns on Embodiment 6. 実施の形態６に係る電気機器の第２の構成例を説明する回路図である。It is a circuit diagram explaining the 2nd structural example of the electric apparatus which concerns on Embodiment 6.
　以下に、本発明の実施の形態について、図面を参照して詳細に説明する。なお、以下では、図中の同一又は相当部分には同一符号を付して、その説明は原則的に繰返さないものとする。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following, the same or corresponding parts in the drawings will be designated by the same reference numerals, and the explanations will not be repeated in principle.
　実施の形態１．
　図１は、実施の形態１に係る電気機器１００の構成例を説明する回路図である。 Embodiment 1.
FIG. 1 is a circuit diagram illustrating a configuration example of the electric device 100 according to the first embodiment.
　図１を参照して、実施の形態１に係る電気機器１００は、配線７０ａ，７１ａと、配線７０ｂ，７１ｂと、受電部１１０と、ノイズフィルタ回路２５ａ，２５ｂと、電力変換回路１５０ａ，１５０ｂとを備える。 With reference to FIG. 1, the electric device 100 according to the first embodiment includes wirings 70a and 71a, wirings 70b and 71b, a power receiving unit 110, noise filter circuits 25a and 25b, and power conversion circuits 150a and 150b. To be equipped.
　受電部１１０は、入力電源１０と接続される電源入力ノードＮ０及びＮ１を有する。入力電源１０は、例えば、商用の交流系統電源によって構成される。即ち、電源入力ノードＮ０及びＮ１の間には、系統周波数（例えば、５０［Ｈｚ］又は６０［Ｈｚ］）の交流電圧が入力される。 The power receiving unit 110 has power input nodes N0 and N1 connected to the input power source 10. The input power supply 10 is composed of, for example, a commercial AC system power supply. That is, an AC voltage having a system frequency (for example, 50 [Hz] or 60 [Hz]) is input between the power input nodes N0 and N1.
　電力変換回路１５０ａの入力側は、配線７０ａ，７１ａ及びノイズフィルタ回路２５ａを経由して、電源入力ノードＮ０及びＮ１（受電部１１０）と接続される。同様に、電力変換回路１５０ｂの入力側は、配線７０ｂ，７１ｂ及びノイズフィルタ回路２５ｂを経由して、電源入力ノードＮ０及びＮ１（受電部１１０）と接続される。 The input side of the power conversion circuit 150a is connected to the power input nodes N0 and N1 (power receiving unit 110) via the wirings 70a and 71a and the noise filter circuit 25a. Similarly, the input side of the power conversion circuit 150b is connected to the power input nodes N0 and N1 (power receiving unit 110) via the wirings 70b and 71b and the noise filter circuit 25b.
　これにより、電力変換回路１５０ａ及び１５０ｂの各々には、入力電源１０からの交流電圧が入力される。本実施の形態では、配線７０ａ，７１ａ，７０ｂ，７１ｂの各々は、同じ材質及び径を有し、更に、配線７０ａ及び７１ａは等長であり、かつ、配線７０ｂ及び７１ｂも等長であるものとする。 As a result, the AC voltage from the input power supply 10 is input to each of the power conversion circuits 150a and 150b. In the present embodiment, the wirings 70a, 71a, 70b, and 71b each have the same material and diameter, the wirings 70a and 71a have the same length, and the wirings 70b and 71b also have the same length. And.
　図１において、電源入力ノードＮ０及びＮ１は「第１の電源入力ノード」及び「第２の電源入力ノード」に対応し、配線７０ａ，７１ａは「第１の配線」に対応し、配線７０ｂ，７１ｂは「第２の配線」に対応する。又、電力変換回路１５０ａは「第１の電力変換回路」の一実施例に対応し、電力変換回路１５０ｂは「第２の電力変換回路」の一実施例に対応する。 In FIG. 1, the power input nodes N0 and N1 correspond to the "first power input node" and the "second power input node", the wirings 70a and 71a correspond to the "first wiring", and the wirings 70b, 71b corresponds to the "second wiring". Further, the power conversion circuit 150a corresponds to an embodiment of the "first power conversion circuit", and the power conversion circuit 150b corresponds to an embodiment of the "second power conversion circuit".
　例えば、電力変換回路１５０ａ及び１５０ｂは、入力電源１０からの交流電圧を直流電圧に変換する整流回路（図示せず）と、整流回路からの出力電圧を半導体スイッチング素子のオンオフ制御によって交流電圧に変換するインバータ回路（図示せず）とを含んで構成される。尚、図示は省略するが、電力変換回路１５０ａ及び１５０ｂの出力側には、電力変換回路１５０ａ及び１５０ｂによって変換された電力によって駆動される負荷（例えば、モータ等）が接続される。 For example, the power conversion circuits 150a and 150b have a rectifier circuit (not shown) that converts the AC voltage from the input power supply 10 into a DC voltage, and the output voltage from the rectifier circuit is converted into an AC voltage by on / off control of the semiconductor switching element. It is configured to include an inverter circuit (not shown). Although not shown, a load (for example, a motor or the like) driven by the electric power converted by the electric power conversion circuits 150a and 150b is connected to the output side of the electric power conversion circuits 150a and 150b.
　通常、半導体スイッチング素子が高周波でスイッチングされることにより、インバータ回路が出力する交流電圧に、高周波ノイズが重畳する。当該高周波ノイズに起因する入力電源１０側での伝導ノイズを抑制するために、ノイズフィルタ回路２５ａ及び２５ｂが、受電部１１０と、電力変換回路１５０ａ及び１５０ｂとの間に、それぞれ接続される。 Normally, when the semiconductor switching element is switched at high frequency, high frequency noise is superimposed on the AC voltage output by the inverter circuit. Noise filter circuits 25a and 25b are connected between the power receiving unit 110 and the power conversion circuits 150a and 150b, respectively, in order to suppress conduction noise on the input power supply 10 side due to the high frequency noise.
　ノイズフィルタ回路２５ａの入力端子８０ａ及び８１ａは、配線７０ａ及び７１ａによって、受電部１１０の電源入力ノードＮ０及びＮ１とそれぞれ接続される。配線７０ａ及び７１ａの各々は、寄生インダクタンスＬ１を有する。 The input terminals 80a and 81a of the noise filter circuit 25a are connected to the power input nodes N0 and N1 of the power receiving unit 110 by the wirings 70a and 71a, respectively. Each of the wirings 70a and 71a has a parasitic inductance L1.
　ノイズフィルタ回路２５ａは、キャパシタンスＣ１のコンデンサ８２ａと、コモンモードチョークコイル８５ａとを含む。寄生インダクタンスＬｘ１を有するコンデンサ８２ａは、入力端子８０ａ及び８１ａの間に接続される。コモンモードチョークコイル８５ａは、コンデンサ８２ａと、電力変換回路１５０ａとの間に接続される。 The noise filter circuit 25a includes a capacitor 82a having a capacitance C1 and a common mode choke coil 85a. The capacitor 82a having the parasitic inductance Lx1 is connected between the input terminals 80a and 81a. The common mode choke coil 85a is connected between the capacitor 82a and the power conversion circuit 150a.
　ノイズフィルタ回路２５ｂの入力端子８０ｂ及び８１ｂは、配線７０ｂ及び７１ｂによって、受電部１１０の電源入力ノードＮ０及びＮ１とそれぞれ接続される。配線７０ｂ及び７１ｂの各々は、寄生インダクタンスＬ２を有する。 The input terminals 80b and 81b of the noise filter circuit 25b are connected to the power input nodes N0 and N1 of the power receiving unit 110 by the wirings 70b and 71b, respectively. Each of the wires 70b and 71b has a parasitic inductance L2.
　ノイズフィルタ回路２５ｂは、キャパシタンスＣ２のコンデンサ８２ｂと、コモンモードチョークコイル８５ｂとを含む。寄生インダクタンスＬｘ２を有するコンデンサ８２ｂは、入力端子８０ｂ及び８１ｂの間に接続される。コモンモードチョークコイル８５ｂは、コンデンサ８２ｂと、電力変換回路１５０ｂとの間に接続される。 The noise filter circuit 25b includes a capacitor 82b having a capacitance C2 and a common mode choke coil 85b. The capacitor 82b having the parasitic inductance Lx2 is connected between the input terminals 80b and 81b. The common mode choke coil 85b is connected between the capacitor 82b and the power conversion circuit 150b.
　このように、ノイズフィルタ回路２５ａ，２５ｂにおいて、電力変換回路１５０ａ，１５０ｂの入力側に対して、コンデンサ８２ａ，８２ｂは並列接続され、コモンモードチョークコイル８５ａ，８５ｂは直列接続される。 In this way, in the noise filter circuits 25a and 25b, the capacitors 82a and 82b are connected in parallel to the input side of the power conversion circuits 150a and 150b, and the common mode choke coils 85a and 85b are connected in series.
　図１において、ノイズフィルタ回路２５ａは「第１のノイズフィルタ回路」の一実施例に対応し、ノイズフィルタ回路２５ｂは「第２のノイズフィルタ回路」の一実施例に対応する。コンデンサ８２ａは「第１のコンデンサ」の一実施例に対応し、コンデンサ８２ｂは「第２のコンデンサ」の一実施例に対応する。 In FIG. 1, the noise filter circuit 25a corresponds to an embodiment of the “first noise filter circuit”, and the noise filter circuit 25b corresponds to an embodiment of the “second noise filter circuit”. The capacitor 82a corresponds to an embodiment of the "first capacitor", and the capacitor 82b corresponds to an embodiment of the "second capacitor".
　電気機器１００の入力電源１０側において、受電部１１０及び電力変換回路１５０ａの間には、コンデンサ８２ａのキャパシタンスＣ１及び寄生インダクタンスＬｘ１と、配線７０ａ，７１ａの各々の寄生インダクタンスＬ１とによる第１の直列共振回路が形成される。同様に、受電部１１０及び電力変換回路１５０ｂの間には、コンデンサ８２ｂのキャパシタンスＣ２及び寄生インダクタンスＬｘ２と、配線７０ｂ，７１ｂの各々の寄生インダクタンスＬ２とによる第２の直列共振回路が形成される。更に、受電部１１０を介して、電力変換回路１５０ａ及び１５０ｂの入力側が接続された経路には、上記第１及び第２の直列共振回路が並列接続された並列共振回路が形成される。 On the input power supply 10 side of the electric device 100, a first series is provided between the power receiving unit 110 and the power conversion circuit 150a by the capacitance C1 of the capacitor 82a and the parasitic inductance Lx1 and the parasitic inductance L1 of each of the wirings 70a and 71a. A resonant circuit is formed. Similarly, a second series resonant circuit is formed between the power receiving unit 110 and the power conversion circuit 150b by the capacitance C2 of the capacitor 82b and the parasitic inductance Lx2, and the parasitic inductance L2 of each of the wirings 70b and 71b. Further, a parallel resonance circuit in which the first and second series resonance circuits are connected in parallel is formed in the path to which the input sides of the power conversion circuits 150a and 150b are connected via the power receiving unit 110.
　図１において、一般的にＬ１＞＞Ｌｘ１であることからＬｘ１を無視すると、電源入力ノードＮ０及びＮ１間に、ノイズフィルタ回路２５ａを介して形成される経路のインダクタンスＬａは、Ｌａ＝２・Ｌ１で示すことができる。同様に、Ｌ２＞＞Ｌｘ２であることからＬｘ２を無視すると、電源入力ノードＮ０及びＮ１間に、ノイズフィルタ回路２５ｂを介して形成される経路のインダクタンスＬｂは、Ｌｂ＝２・Ｌ２で示すことができる。即ち、インダクタンスＬａは「第１のインダクタンス」に対応し、インダクタンスＬｂは「第２のインダクタンス」に対応し、キャパシタンスＣ１は「第１のキャパシタンス」に対応し、キャパシタンスＣ２は「第２のキャパシタンス」に対応する。 In FIG. 1, since L1 >> Lx1 in general, ignoring Lx1, the inductance La of the path formed between the power input nodes N0 and N1 via the noise filter circuit 25a is La = 2 · L1. Can be indicated by. Similarly, if Lx2 is ignored because L2 >> Lx2, the inductance Lb of the path formed between the power input nodes N0 and N1 via the noise filter circuit 25b can be indicated by Lb = 2 · L2. it can. That is, the inductance La corresponds to the "first inductance", the inductance Lb corresponds to the "second inductance", the capacitance C1 corresponds to the "first capacitance", and the capacitance C2 corresponds to the "second capacitance". Corresponds to.
　図２は、図１に示された電気機器１００から入力電源１０に漏れ出す伝導ノイズのシミュレーション結果を示すグラフである。図２の横軸には、周波数［Ｈｚ］が対数表示され、縦軸には伝導ノイズの強度が示される。 FIG. 2 is a graph showing a simulation result of conduction noise leaking from the electric device 100 shown in FIG. 1 to the input power source 10. The horizontal axis of FIG. 2 is a logarithmic display of the frequency [Hz], and the vertical axis is the intensity of conduction noise.
　図２を参照して、特性線ＣＬ０は、後述する回路定数の設定の適用前におけるシミュレーション結果である。尚、当該シミュレーションでの回路定数の値関係として、Ｃ１＜Ｃ２、及び、Ｌａ＜Ｌｂとしている。又、シミュレーションでは、コンデンサ８２ａの寄生インダクタンスＬｘ１（Ｌｘ１＜＜Ｌ１）、及び、コンデンサ８２ｂの寄生インダクタンスＬｘ２（Ｌｘ２＜＜Ｌ２）も設定されている。ここでは、寄生インダクタンスＬｘ１，Ｌｘ２（コンデンサ８２ａ，８２ｂ）は、それぞれ寄生インダクタンスＬ１，Ｌ２（配線７０ａ，７１ａ）の数（％）程度に設定した。 With reference to FIG. 2, the characteristic line CL0 is a simulation result before applying the circuit constant setting described later. The value relations of the circuit constants in the simulation are C1 <C2 and La <Lb. Further, in the simulation, the parasitic inductance Lx1 (Lx1 << L1) of the capacitor 82a and the parasitic inductance Lx2 (Lx2 << L2) of the capacitor 82b are also set. Here, the parasitic inductances Lx1 and Lx2 ( capacitors 82a and 82b) are set to about the number (%) of the parasitic inductances L1 and L2 ( wiring 70a and 71a), respectively.
　特性線ＣＬ０には、上述の並列共振回路による並列共振により、伝導ノイズの極大ピークが生じている。上述した、Ｌ１＞＞Ｌｘ１、かつ、Ｌ２＞＞Ｌｘ２の下では、極大ピークが生じる並列共振周波数ｆｐは、下記の式（１）で示すことができる。 The characteristic line CL0 has a maximum peak of conduction noise due to parallel resonance by the above-mentioned parallel resonance circuit. Under the above-mentioned L1 >> Lx1 and L2 >> Lx2, the parallel resonance frequency fp at which the maximum peak occurs can be expressed by the following equation (1).
Figure JPOXMLDOC01-appb-M000001
  
Figure JPOXMLDOC01-appb-M000001
  
　さらに、特性線ＣＬ０には、第１及び第２の直列共振回路のそれぞれにおける直列共振周波数ｆｓ１及びｆｓ２において、伝導ノイズの極小ピークが生じている。上記と同様に、Ｌ１＞＞Ｌｘ１、かつ、Ｌ２＞＞Ｌｘ２の下では、直列共振周波数ｆｓ１，ｆｓ２は、下記の式（２）及び式（３）で示すことができる。 Further, in the characteristic line CL0, a minimum peak of conduction noise occurs at the series resonance frequencies fs1 and fs2 in the first and second series resonance circuits, respectively. Similar to the above, under L1 >> Lx1 and L2 >> Lx2, the series resonance frequencies fs1 and fs2 can be represented by the following equations (2) and (3).
Figure JPOXMLDOC01-appb-M000002
  
Figure JPOXMLDOC01-appb-M000002
  
　実施の形態１に係る電気機器１００では、伝導ノイズの極大ピークが生じる並列共振周波数ｆｐ、極小ピークが生じる直列共振周波数ｆｓ１及びｆｓ２を一致させるための回路定数の設定により、伝導ノイズが極大となる並列共振ピークを消滅させることができる。 In the electric device 100 according to the first embodiment, the conduction noise is maximized by setting the circuit constants for matching the parallel resonance frequency fp at which the maximum peak of the conduction noise occurs and the series resonance frequencies fs1 and fs2 at which the minimum peak occurs. The parallel resonance peak can be extinguished.
　図２中の特性線ＣＬ１は、Ｌａ・Ｃ１＝Ｌｂ・Ｃ２の条件を成立させるために、２・Ｌ１・Ｃ１＝２・Ｌ２・Ｃ２（以下では、単に「Ｌ１・Ｃ１＝Ｌ２・Ｃ２」とも表記する）としたときのシミュレーション結果である。 The characteristic line CL1 in FIG. 2 is also referred to as 2, L1, C1 = 2, L2, C2 (hereinafter, simply "L1, C1 = L2, C2") in order to satisfy the condition of La, C1 = Lb, C2. It is a simulation result when (notation) is set.
　式（２）及び式（３）より、Ｌ１・Ｃ１＝Ｌ２・Ｃ２とすることで、ｆｓ１＝ｆｓ２が成立することが理解される。更に、式（１）中の（Ｃ１・Ｃ２）／（Ｃ１＋Ｃ２）＝Ｃ２／（１＋（Ｃ２／Ｃ１））に対して、Ｌ１・Ｃ１＝Ｌ２・Ｃ２を変形した（Ｃ２／Ｃ１）＝（Ｌ１／Ｌ２）を代入すると、ｆｐ＝１／（２π・√（Ｌ２・Ｃ２））が得られる。即ち、Ｌ１・Ｃ１＝Ｌ２・Ｃ２とする回路定数の設定により、ｆｐ＝ｆｓ１＝ｆｓ２とすることができる。図２中には、特性線ＣＬ０での並列共振周波数ｆｐと区別するために、Ｌ１・Ｃ１＝Ｌ２・Ｃ２としたときの共振周波数がｆｐ＊で示される。 From equations (2) and (3), it is understood that fs1 = fs2 is established by setting L1, C1 = L2, C2. Further, with respect to (C1 ・ C2) / (C1 + C2) = C2 / (1+ (C2 / C1)) in the equation (1), L1, C1 = L2 and C2 are modified (C2 / C1) = (L1). Substituting / L2) gives fp = 1 / (2π · √ (L2 · C2)). That is, by setting the circuit constants such that L1, C1 = L2 and C2, fp = fs1 = fs2 can be set. In FIG. 2, in order to distinguish from the parallel resonance frequency fp on the characteristic line CL0, the resonance frequency when L1 · C1 = L2 · C2 is shown by fp *.
　特性線ＣＬ１では、特性線ＣＬ０での並列共振ピークの極大点を直列共振ピークの２個の極小点で相殺することにより、並列共振周波数ｆｐ相当の５００［ｋＨｚ］近傍での極大点での伝導ノイズのピーク値が低減されている。例えば、今回のシミュレーション結果では、当該ピーク値が、特性線ＣＬ０でのピーク値から３０［ｄＢ］以上低減されている。尚、特性線ＣＬ１において、共振周波数ｆｐ＊相当の３５０［ｋＨｚ］近傍に僅かに残存する極大ピークは、特性線ＣＬ０における並列共振ピークを、直列共振ピークによって完全に相殺できなかったために発生するものである。これは、Ｌｘ１及びＬｘ２の存在により、Ｌａ・Ｃ１＝Ｌｂ・Ｃ２を完全に満足できなかったことに起因する。 In the characteristic line CL1, the maximum point of the parallel resonance peak on the characteristic line CL0 is canceled by the two minimum points of the series resonance peak, so that the conduction at the maximum point near 500 [kHz] corresponding to the parallel resonance frequency fp The peak value of noise is reduced. For example, in the result of this simulation, the peak value is reduced by 30 [dB] or more from the peak value at the characteristic line CL0. In the characteristic line CL1, the maximum peak slightly remaining in the vicinity of 350 [kHz] corresponding to the resonance frequency fp * is generated because the parallel resonance peak in the characteristic line CL0 cannot be completely canceled by the series resonance peak. Is. This is due to the fact that La · C1 = Lb · C2 could not be completely satisfied due to the presence of Lx1 and Lx2.
　次に、上述の回路定数設定（Ｌ１・Ｃ１＝Ｌ２・Ｃ２）の具体的な実現例について説明する。 Next, a specific implementation example of the circuit constant setting (L1, C1 = L2, C2) described above will be described.
　ノイズフィルタ回路２５ａ及び２５ｂ中のコンデンサ８２ａ及び８２ｂのキャパシタンスＣ１及びＣ２は、ノイズ発生源となる電力変換回路１５０ａ及び１５０ｂのノイズ特性に対応させて適正値に設定する必要がある。従って、伝導ノイズ低減のための回路定数設定の観点から、キャパシタンスＣ１，Ｃ２を調整することは困難である。 The capacitances C1 and C2 of the capacitors 82a and 82b in the noise filter circuits 25a and 25b need to be set to appropriate values corresponding to the noise characteristics of the power conversion circuits 150a and 150b which are noise sources. Therefore, it is difficult to adjust the capacitances C1 and C2 from the viewpoint of setting the circuit constants for reducing conduction noise.
　一方で、寄生インダクタンスＬ１及びＬ２は、配線７０ａ，７１ａ及び配線７０ｂ，７１ｂの配線長、径、及び、材質等によって変化する。一般的に、配線の寄生インダクタンスは配線長に比例するので、代表的には、配線７０ａ，７１ａ及び配線７０ｂ，７１ｂの配線長の調整によって、伝導ノイズ低減のための回路定数設定を実現することが可能である。 On the other hand, the parasitic inductances L1 and L2 change depending on the wiring length, diameter, material, etc. of the wirings 70a and 71a and the wirings 70b and 71b. In general, the parasitic inductance of the wiring is proportional to the wiring length. Therefore, typically, the circuit constant setting for reducing conduction noise is realized by adjusting the wiring lengths of the wirings 70a and 71a and the wirings 70b and 71b. Is possible.
　例えば、Ｃ１＝Ｃ２であるときには、配線７０ａ，７１ａの配線長と、配線７０ｂ，７１ｂの配線長とを揃えることで、Ｌ１・Ｃ１＝Ｌ２・Ｃ２を実現することができる。一方で、電力変換回路１５０ａ及び１５０ｂのノイズ特性からＣ２＝ｍ・Ｃ１（ｍ：ｍ＞０の実数）である場合には、配線７０ａ，７１ａの各配線長を、配線７０ｂ，７１ｂの各配線長のｍ倍とすることで、Ｌ１・Ｃ１＝Ｌ２・Ｃ２を実現することができる。 For example, when C1 = C2, L1, C1 = L2, C2 can be realized by aligning the wiring lengths of the wirings 70a and 71a with the wiring lengths of the wirings 70b and 71b. On the other hand, when C2 = m · C1 (real number of m: m> 0) from the noise characteristics of the power conversion circuits 150a and 150b, the wiring lengths of the wirings 70a and 71a are set to the wirings of the wirings 70b and 71b. By making it m times the length, L1, C1 = L2, C2 can be realized.
　伝導ノイズ低減のための、Ｌａ・Ｃ１＝Ｌｂ・Ｃ２とする回路定数設定は、電力変換回路１５０ａ及び１５０ｂのノイズ特性から定まるキャパシタンスＣ１及びＣ２の比（Ｃ１／Ｃ２）に対して、インダクタンスＬａ及びＬｂがその逆比を有するように（即ち、Ｌａ／Ｌｂ＝Ｃ２／Ｃ１）、配線７０ａ，７１ａ及び配線７０ｂ，７１ｂを設けることと等価である。 The circuit constant setting of La · C1 = Lb · C2 for reducing conduction noise is such that the inductance La and the inductance La and the ratio (C1 / C2) of the capacitances C1 and C2 determined from the noise characteristics of the power conversion circuits 150a and 150b are set. It is equivalent to providing the wirings 70a and 71a and the wirings 70b and 71b so that Lb has the inverse ratio (that is, La / Lb = C2 / C1).
　上述のように、一般的には、Ｌｘ１＜＜Ｌ１、及び、Ｌｘ２＜＜Ｌ２が成立するので、配線７０ａ，７１ａの寄生インダクタンスの合計である２・Ｌ１と、配線７０ｂ，７１ｂの寄生インダクタンスの合計である２・Ｌ２との比、即ち、（２・Ｌ１／２・Ｌ２＝Ｌ１／Ｌ２）を、キャパシタンスＣ１及びＣ２の逆比（Ｃ２／Ｃ１）に従って設定することで、伝導ノイズ低減のための回路定数設定（Ｌａ・Ｃ１＝Ｌｂ・Ｃ２）を等価的に実現することが可能である。 As described above, in general, since Lx1 << L1 and Lx2 << L2 are established, the total parasitic inductances of the wirings 70a and 71a, 2.L1, and the parasitic inductances of the wirings 70b and 71b By setting the ratio to the total 2 · L2, that is, (2 · L1 / 2 · L2 = L1 / L2) according to the inverse ratio (C2 / C1) of the capacitances C1 and C2, to reduce the conduction noise. It is possible to equivalently realize the circuit constant setting (La · C1 = Lb · C2) of.
　但し、実使用環境を想定すると、Ｌａ・Ｃ１（又は、Ｌ１・Ｃ１）及びＬｂ・Ｃ２（又は、Ｌ２・Ｃ２）を常に完全に一致させることは容易ではない。従って、一致度に対する伝導ノイズの変化を考察する。以下では、一致度を定量的に評価するために、両者の比に相当するパラメータｘを下記の式（４）で定義して、シミュレーションを行った。 However, assuming an actual usage environment, it is not easy to always completely match La / C1 (or L1 / C1) and Lb / C2 (or L2 / C2). Therefore, the change in conduction noise with respect to the degree of coincidence will be considered. In the following, in order to quantitatively evaluate the degree of agreement, the parameter x corresponding to the ratio of the two is defined by the following equation (4), and a simulation is performed.
Figure JPOXMLDOC01-appb-M000003
  
Figure JPOXMLDOC01-appb-M000003
  
　図３は、パラメータｘを変化させた下での図２と同様のシミュレーション結果を示すグラフである。 FIG. 3 is a graph showing the same simulation results as in FIG. 2 when the parameter x is changed.
　図３を参照して、特性線ＣＬ０は図２と同じである一方で、実施の形態１に係る特性線ＣＬ１１～ＣＬ１３では、回路定数設定のパラメータｘの値が異なる。具体的には、特性線ＣＬ１１はｘ＝０．７６のとき、特性線ＣＬ１２はｘ＝１．０のとき、特性線ＣＬ１３はｘ＝１．２のときのシミュレーション結果である。即ち、特性線ＣＬ１２（ｘ＝１）は、図２の特性線ＣＬ１と同じである。 With reference to FIG. 3, the characteristic line CL0 is the same as that of FIG. 2, while the values of the parameters x for setting the circuit constants are different in the characteristic lines CL11 to CL13 according to the first embodiment. Specifically, it is a simulation result when the characteristic line CL11 is x = 0.76, the characteristic line CL12 is x = 1.0, and the characteristic line CL13 is x = 1.2. That is, the characteristic line CL12 (x = 1) is the same as the characteristic line CL1 in FIG.
　特性線ＣＬ１１～ＣＬ１３のいずれについても、特性線ＣＬ０と比較すると、並列共振周波数ｆｐでの伝導ノイズは、３０［ｄＢ］以上低減されている。但し、ｘが１から離れる特性線ＣＬ１１，ＣＬ１３では、共振周波数ｆｐ＊での極大点でのピーク値は、特性線ＣＬ１２よりは大きくなることが理解される。 For all of the characteristic lines CL11 to CL13, the conduction noise at the parallel resonance frequency fp is reduced by 30 [dB] or more as compared with the characteristic line CL0. However, it is understood that in the characteristic lines CL11 and CL13 in which x is separated from 1, the peak value at the maximum point at the resonance frequency fp * is larger than that in the characteristic line CL12.
　図４は、パラメータｘに対する伝導ノイズのピーク値の減少量の変化のシミュレーション結果を示すグラフである。 FIG. 4 is a graph showing a simulation result of a change in the amount of decrease in the peak value of conduction noise with respect to the parameter x.
　図４では、プロットされる各点でのパラメータｘについて、図３と同様のシミュレーションを実行したときの、共振周波数ｆｐ＊の極大点でのピーク値の、特性線ＣＬ０の当該共振周波数での伝導ノイズ値に対する低減量を縦軸にプロットしている。 In FIG. 4, for the parameter x at each plotted point, the conduction of the peak value at the maximum point of the resonance frequency fp * at the resonance frequency of the characteristic line CL0 when the same simulation as in FIG. 3 is executed. The amount of reduction with respect to the noise value is plotted on the vertical axis.
　図４において、ｘ＝１．０で伝導ノイズ差が最大となっていないのは、コンデンサ８２ａ，８２ｂの寄生インダクタンスＬｘ１，Ｌｘ２が存在することで、ｘ＝１．０にてＬａ・Ｃ１＝Ｌｂ・Ｃ２を完全に満足できなかったことに起因する。仮に、寄生インダクタンスＬｘ１及びＬｘ２の影響が完全に無視できる場合には、ｘ＝１．０において伝導ノイズ差が最大となる。 In FIG. 4, the difference in conduction noise is not maximized at x = 1.0 because the parasitic inductances Lx1 and Lx2 of the capacitors 82a and 82b are present, and La · C1 = Lb at x = 1.0.・ It is caused by not being completely satisfied with C2. If the effects of the parasitic inductances Lx1 and Lx2 can be completely ignored, the conduction noise difference becomes maximum at x = 1.0.
　パラメータｘが１．０から大きく離れると、例えば、図４のシミュレーション結果では、ｘ＜０．７６、及び、ｘ＞１．２の領域では、回路定数設定後の共振周波数（図２のｆｐ＊相当）における伝導ノイズが、特性線ＣＬ０よりも増加することが理解される。従って、図４のシミュレーション結果に照らすと、パラメータｘについては、０．７６≦ｘ≦１．２の範囲内とすることが好ましい。 When the parameter x deviates significantly from 1.0, for example, in the simulation result of FIG. 4, in the region of x <0.76 and x> 1.2, the resonance frequency after setting the circuit constant (fp * in FIG. 2). It is understood that the conduction noise in (corresponding to) increases more than the characteristic line CL0. Therefore, in light of the simulation results of FIG. 4, the parameter x is preferably in the range of 0.76 ≦ x ≦ 1.2.
　言い換えると、パラメータｘ、即ち、Ｌ２・Ｃ２に対するＬ１・Ｃ１の比は、電力変換回路１５０ａ，１５０ｂのノイズ特性に対応したキャパシタンスＣ１，Ｃ２の下での、共振周波数ｆｐ＊における伝導ノイズが、回路定数調整前の並列共振周波数ｆｐ（図２）での伝導ノイズよりも減少する範囲に対応させて、ｘ＝１．０を含む予め定められた範囲内に設定することができる。 In other words, the parameter x, that is, the ratio of L1 and C1 to L2 and C2, is the conduction noise at the resonance frequency fp * under the capacitances C1 and C2 corresponding to the noise characteristics of the power conversion circuits 150a and 150b. It can be set within a predetermined range including x = 1.0 in correspondence with a range in which the conduction noise at the parallel resonance frequency fp (FIG. 2) before the constant adjustment is reduced.
　以上説明したように、実施の形態１に係る電気機器によれば、複数の電力変換回路が共通の入力電源と接続される構成において、複数の電力変換回路に対応した、ノイズフィルタ回路内のコンデンサのキャパシタンスと、配線等の寄生インダクタンスとについての上述の逆比に従った回路定数の設定により、高いノイズ低減効果を実現することができる。 As described above, according to the electric device according to the first embodiment, a capacitor in a noise filter circuit corresponding to a plurality of power conversion circuits in a configuration in which a plurality of power conversion circuits are connected to a common input power supply. A high noise reduction effect can be realized by setting the circuit constant according to the above-mentioned inverse ratio of the capacitance of the above and the parasitic inductance of the wiring or the like.
　実施の形態２．
　実施の形態２では、ノイズフィルタ回路２５ａ，２５ｂのコンデンサ８２ａ，８２ｂのキャパシタンスＣ１，Ｃ２が不一致の下でのノイズ低減効果を更に高める回路構成を説明する。 Embodiment 2.
In the second embodiment, a circuit configuration will be described in which the capacitances C1 and C2 of the capacitors 82a and 82b of the noise filter circuits 25a and 25b further enhance the noise reduction effect under the inconsistency.
　図５は、実施の形態２に係る電気機器の構成例を説明する回路図である。
　図５を参照して、実施の形態２に係る電気機器１０１では、相対的にキャパシタンスが小さいコンデンサを有するノイズフィルタ回路において、入力端子間に、抵抗素子８６（抵抗値Ｒ１）がコンデンサと直列に接続される。 FIG. 5 is a circuit diagram illustrating a configuration example of the electric device according to the second embodiment.
With reference to FIG. 5, in the electric device 101 according to the second embodiment, in a noise filter circuit having a capacitor having a relatively small capacitance, a resistance element 86 (resistance value R1) is connected in series with the capacitor between the input terminals. Be connected.
　図５では、Ｃ１＜Ｃ２のときの回路構成例が示される。従って、抵抗素子８６は、ノイズフィルタ回路２５ａにおいて、入力端子８０ａ，８１ａ間にコンデンサ８２ａと直列に接続される。一方で、コンデンサ８２ｂ（キャパシタンスＣ２）を含むノイズフィルタ回路２５ｂの構成は、実施の形態１（図１）と同様である。 FIG. 5 shows an example of a circuit configuration when C1 <C2. Therefore, the resistance element 86 is connected in series with the capacitor 82a between the input terminals 80a and 81a in the noise filter circuit 25a. On the other hand, the configuration of the noise filter circuit 25b including the capacitor 82b (capacitance C2) is the same as that of the first embodiment (FIG. 1).
　抵抗素子８６の抵抗値Ｒ１は、図６に示される簡易等価回路図に基づいて設定することができる。 The resistance value R1 of the resistance element 86 can be set based on the simple equivalent circuit diagram shown in FIG.
　図６は、電気機器１０１の入力電源１０側に形成される共振回路の並列共振周波数ｆｐ（図２）における簡易等価回路図である。 FIG. 6 is a simple equivalent circuit diagram at the parallel resonance frequency fp (FIG. 2) of the resonance circuit formed on the input power supply 10 side of the electric device 101.
　図６を参照して、実施の形態１と同様に、Ｌ１＞＞Ｌ１ｘ、かつ、Ｌ２＞＞Ｌ２ｘであるので、コンデンサ８２ａ，８２ｂの寄生インダクタンスＬｘ１，Ｌｘ２は無視することができる。更に、Ｃ１＜Ｃ２のときには、周波数上昇に伴って、寄生インダクタンスＬ２又はＬｘ２の影響が支配的になることによりコンデンサ８２ｂ（Ｃ２）が先に容量性のふるまいを失う。このため、並列共振周波数ｆｐでは、コンデンサ８２ａのキャパシタンスＣ１が容量性のふるまいを行う一方で、コンデンサ８２ｂのキャパシタンスＣ２は、共振回路に対して容量として影響しない。 With reference to FIG. 6, since L1 >> L1x and L2 >> L2x as in the first embodiment, the parasitic inductances Lx1 and Lx2 of the capacitors 82a and 82b can be ignored. Further, when C1 <C2, the influence of the parasitic inductance L2 or Lx2 becomes dominant as the frequency rises, so that the capacitor 82b (C2) first loses its capacitive behavior. Therefore, at the parallel resonance frequency fp, the capacitance C1 of the capacitor 82a behaves as a capacitance, while the capacitance C2 of the capacitor 82b does not affect the resonance circuit as a capacitance.
　このため、簡易等価回路では、ノイズフィルタ回路２５ａにおいて、コンデンサ８２ａ（Ｃ１）が容量として作用する一方で、配線７０ａ，７１ａの寄生インダクタンスＬ１は共振回路上では無視できる。一方で、ノイズフィルタ回路２５ｂでは、コンデンサ８２ｂ（Ｃ２）が容量として作用しない一方で、配線７０ａ，７１ａの寄生インダクタンスＬ２が作用する。 Therefore, in the simple equivalent circuit, the capacitor 82a (C1) acts as a capacitance in the noise filter circuit 25a, while the parasitic inductance L1 of the wirings 70a and 71a can be ignored on the resonance circuit. On the other hand, in the noise filter circuit 25b, the capacitor 82b (C2) does not act as a capacitance, while the parasitic inductance L2 of the wirings 70a and 71a acts.
　図６の簡易等価回路において、入力電源１０から見た合成インピーダンスｚ（ω）は、角各周波数ωの関数（ω＝２π・ｆ）として、下記の式（５）により示される。式（５）中において、Ｌｂ＝２・Ｌ１である。 In the simple equivalent circuit of FIG. 6, the combined impedance z (ω) seen from the input power supply 10 is represented by the following equation (5) as a function (ω = 2π · f) of each angular frequency ω. In the formula (5), Lb = 2 · L1.
Figure JPOXMLDOC01-appb-M000004
  
Figure JPOXMLDOC01-appb-M000004
  
　式（５）の実数項及び虚数項に整理することにより、下記の式（６）が得られる。 The following equation (6) can be obtained by arranging the equation (5) into a real number term and an imaginary number term.
Figure JPOXMLDOC01-appb-M000005
  
Figure JPOXMLDOC01-appb-M000005
  
　並列共振周波数ｆｐに対応する角周波数ωｐ（ωｐ＝２π・ｆｐ）において、ｚ（ωｐ）の虚数項はゼロとなり、実数項のみが残る。従って、式（６）の虚数項より、角周波数ωｐについて、下記の式（７）が成立することが理解される。 At the angular frequency ω p (ω p = 2π · fp) corresponding to the parallel resonance frequency fp, the imaginary term of z (ω p ) becomes zero, and only the real term remains. Therefore, from the imaginary term of the equation (6), it is understood that the following equation (7) holds for the angular frequency ω p.
Figure JPOXMLDOC01-appb-M000006
  
Figure JPOXMLDOC01-appb-M000006
  
　式（７）を変形すると、下記の式（８）が得られる。 By transforming equation (7), the following equation (8) can be obtained.
Figure JPOXMLDOC01-appb-M000007
  
Figure JPOXMLDOC01-appb-M000007
  
　更に、式（８）を変形することで、式（９）を得ることができる。 Further, by modifying the equation (8), the equation (9) can be obtained.
Figure JPOXMLDOC01-appb-M000008
  
Figure JPOXMLDOC01-appb-M000008
  
　式（９）において、Ｌｂ≦Ｃ１・Ｒ１2のとき、ωｐが実数ではなくなるので並列共振が消滅することなる。従って、抵抗値Ｒ１について、下記の式（１０）とすることで、図６の簡易等価回路において並列共振が消滅する。 In the formula (9), when Lb ≦ C1 · R1 2, ω p is that parallel resonance disappears because there is no more real numbers. Therefore, by using the following equation (10) for the resistance value R1, the parallel resonance disappears in the simple equivalent circuit of FIG.
Figure JPOXMLDOC01-appb-M000009
  
Figure JPOXMLDOC01-appb-M000009
  
　尚、式（１０）は、抵抗値Ｒ１の下限値のみを規定する。一方で、Ｒ１が過大になるとコンデンサ８２ａ（Ｃ１）によるノイズ低減効果が失われるため、この観点からの上限値を更に用いることで、抵抗値Ｒ１の適正値を定めることができる。 Note that the equation (10) specifies only the lower limit of the resistance value R1. On the other hand, if R1 becomes excessive, the noise reduction effect of the capacitor 82a (C1) is lost. Therefore, by further using the upper limit value from this viewpoint, the appropriate value of the resistance value R1 can be determined.
　図７は、図５に示された電気機器１０１における図２と同様のシミュレーション結果を示すグラフである。 FIG. 7 is a graph showing the same simulation results as in FIG. 2 in the electric device 101 shown in FIG.
　図７を参照して、特性線ＣＬ０は、図２と同様であり、並列共振周波数ｆｐに伝導ノイズの極大ピークが生じている。図７中の特性線ＣＬ２は、抵抗素子８６が配置された電気機器１０２において、実施の形態１と同様に、２・Ｌ１・Ｃ１＝２・Ｌ２・Ｃ２（即ち、Ｌ１・Ｃ１＝Ｌ２・Ｃ２）としたときのシミュレーション結果である。 With reference to FIG. 7, the characteristic line CL0 is the same as that of FIG. 2, and a maximum peak of conduction noise is generated at the parallel resonance frequency fp. The characteristic line CL2 in FIG. 7 is 2 · L1, · C1 = 2, L2 · C2 (that is, L1, · C1 = L2 · C2) in the electrical device 102 in which the resistance element 86 is arranged, as in the first embodiment. ) Is the simulation result.
　特性線ＣＬ２において、特性線ＣＬ０の並列共振周波数ｆｐにおけるノイズ低減効果は、実施の形態１での特性線ＣＬ１と同様である。更に、実施の形態２では、新たに配置された抵抗素子８６の抵抗値Ｒ１を式（１０）に従って設定することにより、並列共振ピークを鈍らせることができる。これにより、伝導ノイズが極大となる並列共振ピークの大きさを、伝導ノイズが極小となる直列共振ピークの大きさより小さくすることができる。 In the characteristic line CL2, the noise reduction effect of the characteristic line CL0 at the parallel resonance frequency fp is the same as that of the characteristic line CL1 in the first embodiment. Further, in the second embodiment, the parallel resonance peak can be blunted by setting the resistance value R1 of the newly arranged resistance element 86 according to the equation (10). As a result, the size of the parallel resonance peak at which the conduction noise is maximized can be made smaller than the size of the series resonance peak at which the conduction noise is at its minimum.
　この結果、実施の形態２に係る電気機器では、Ｌａ・Ｃ１＝Ｌｂ・Ｃ２（Ｌ１・Ｃ１＝Ｌ２・Ｃ２）とする回路定数の設定により、並列共振周波数と直列共振周波数を一致させたときに、直列共振によるノイズ極小ピークが残存するようになる。従って、特性線ＣＬ２では、並列共振周波数ｆｐ、及び、直列共振周波数ｆｓ１及びｆｓ２を一致させた後の共振周波数ｆｐ＊において、図２のような極大ピークが残存していない。 As a result, in the electric device according to the second embodiment, when the parallel resonance frequency and the series resonance frequency are matched by setting the circuit constants such that La · C1 = Lb · C2 (L1 · C1 = L2 · C2). , The noise minimum peak due to series resonance will remain. Therefore, in the characteristic line CL2, the maximum peak as shown in FIG. 2 does not remain at the parallel resonance frequency fp and the resonance frequency fp * after the series resonance frequencies fs1 and fs2 are matched.
　図８は、図５に示された電気機器１０１における図３と同様のシミュレーション結果を示すグラフである。図８には、図３と同様のパラメータｘ（式（４））について、ｘ＝０．７６、ｘ＝１．０、及び、ｘ＝１．２としたときの、特性線ＣＬ２１～ＣＬ２３が示される。 FIG. 8 is a graph showing the same simulation results as in FIG. 3 in the electric device 101 shown in FIG. In FIG. 8, the characteristic lines CL21 to CL23 are shown for the same parameter x (Equation (4)) as in FIG. 3 when x = 0.76, x = 1.0, and x = 1.2. Shown.
　図８を参照して、特性線ＣＬ２１～ＣＬ２３のいずれについても、特性線ＣＬ０と比較すると、並列共振周波数ｆｐでの伝導ノイズは、図３と同様に、３０［ｄＢ］以上低減されている。 With reference to FIG. 8, for all of the characteristic lines CL21 to CL23, the conduction noise at the parallel resonance frequency fp is reduced by 30 [dB] or more as compared with the characteristic line CL0.
　更に、実施の形態２では、パラメータｘが１．０から離れる特性線ＣＬ２１，ＣＬ２３においても、抵抗素子８６の配置によって並列共振ピークを鈍らせることにより、実施の形態１（図３）と比較して、共振周波数ｆｐ＊におけるピーク値が抑制されることが理解される。 Further, in the second embodiment, even in the characteristic lines CL21 and CL23 in which the parameter x is separated from 1.0, the parallel resonance peak is blunted by the arrangement of the resistance element 86, as compared with the first embodiment (FIG. 3). Therefore, it is understood that the peak value at the resonance frequency fp * is suppressed.
　このように、実施の形態２に係る電気機器では、低容量のコンデンサを含むノイズフィルタに抵抗素子８６を配置することによって、ノイズ低減効果を高めることが可能である。特に、実施の形態２では、実施の形態１と比較して、２・Ｌ１・Ｃ１＝２・Ｌ２・Ｃ２（即ち、Ｌ１・Ｃ１＝Ｌ２・Ｃ２）とする回路定数設定が厳密に実行できなくても、高いノイズ低減効果を得ることが可能である。 As described above, in the electric device according to the second embodiment, the noise reduction effect can be enhanced by arranging the resistance element 86 in the noise filter including the low-capacity capacitor. In particular, in the second embodiment, the circuit constant setting of 2, L1, C1 = 2, L2, C2 (that is, L1, C1 = L2, C2) cannot be strictly executed as compared with the first embodiment. However, it is possible to obtain a high noise reduction effect.
　尚、以上では、Ｃ１＜Ｃ２の場合を例示したが、反対に、コンデンサ８２ａのキャパシタンスＣ１の方が、コンデンサ８２ｂのキャパシタンスＣ２よりも大きいとき（Ｃ１＞Ｃ２）にも実施の形態２を適用することができる。この場合には、図５において、抵抗素子８６は、ノイズフィルタ回路２５ｂにおいて、入力端子８０ｂ，８１ｂ間にコンデンサ８２ｂと直列に接続される。一方で、コンデンサ８２ａを含むノイズフィルタ回路２５ａの構成は、実施の形態１（図１）と同様とされる。又、式（１０）において、インダンクタンスＬｂをＬａに置換し、かつ、キャパシタンスＣ１をＣ２に置換することで、抵抗値Ｒ１の範囲を定めることができる。 In the above, the case of C1 <C2 has been illustrated, but conversely, the second embodiment is also applied when the capacitance C1 of the capacitor 82a is larger than the capacitance C2 of the capacitor 82b (C1> C2). be able to. In this case, in FIG. 5, the resistance element 86 is connected in series with the capacitor 82b between the input terminals 80b and 81b in the noise filter circuit 25b. On the other hand, the configuration of the noise filter circuit 25a including the capacitor 82a is the same as that of the first embodiment (FIG. 1). Further, in the equation (10), the range of the resistance value R1 can be determined by substituting La for the inductance Lb and C2 for the capacitance C1.
　実施の形態３．
　図９は、実施の形態３に係る電気機器の構成例を説明する回路図である。 Embodiment 3.
FIG. 9 is a circuit diagram illustrating a configuration example of the electric device according to the third embodiment.
　図９を参照して、実施の形態３に係る電気機器１０２は、実施の形態１に係る電気機器１００（図１）と比較して、ノイズフィルタ回路２５ａ，２５ｂが、調整用インダクタ８７ａ，８８ａ及び調整用インダクタ８７ｂ，８８ｂをさらに備える点で異なる。電気機器１０２のその他の部分の構成は、電気機器１００と同様であるので詳細な説明は繰り返さない。 With reference to FIG. 9, in the electric device 102 according to the third embodiment, the noise filter circuits 25a and 25b have the adjusting inductors 87a and 88a as compared with the electric device 100 (FIG. 1) according to the first embodiment. And the adjustment inductors 87b and 88b are further provided. Since the configuration of the other parts of the electric device 102 is the same as that of the electric device 100, the detailed description will not be repeated.
　ノイズフィルタ回路２５ａにおいて、調整用インダクタ８７ａは、配線７０ａ又は７１ａに直列接続される態様で、コンデンサ８２ａよりも入力電源側に電気的に接続される。調整用インダクタ８８ａは、コンデンサ８２ａと直列接続される。ノイズフィルタ回路２５ａにおいて、調整用インダクタ８７ａは「第１の調整用インダクタ」の一実施例に対応し、調整用インダクタ８８ａは「第２の調整用インダクタ」の一実施例に対応する。 In the noise filter circuit 25a, the adjusting inductor 87a is electrically connected to the input power supply side of the capacitor 82a in a manner of being connected in series with the wiring 70a or 71a. The adjusting inductor 88a is connected in series with the capacitor 82a. In the noise filter circuit 25a, the adjusting inductor 87a corresponds to one embodiment of the "first adjusting inductor", and the adjusting inductor 88a corresponds to one embodiment of the "second adjusting inductor".
　図９の構成では、調整用インダクタ８７ａのインダクタンスＬａ１及び調整用インダクタ８８ａのインダクタンスＬｘａ１を用いると、電源入力ノードＮ０及びＮ１間に、ノイズフィルタ回路２５ａを介して形成される経路のインダクタンスＬａ＝２・Ｌ１＋Ｌａ１＋Ｌｘａ１で示される。 In the configuration of FIG. 9, when the inductance La1 of the adjusting inductor 87a and the inductance Lxa1 of the adjusting inductor 88a are used, the inductance La = 2 of the path formed between the power input nodes N0 and N1 via the noise filter circuit 25a. -Indicated by L1 + La1 + Lxa1.
　同様に、ノイズフィルタ回路２５ｂにおいて、調整用インダクタ８７ｂは、配線７０ｂ又は７１ｂに直列接続される態様で、コンデンサ８２ｂよりも入力電源側に電気的に接続される。調整用インダクタ８８ｂは、コンデンサ８２ｂと直列接続される。ノイズフィルタ回路２５ｂにおいて、調整用インダクタ８７ｂは「第１の調整用インダクタ」の一実施例に対応し、調整用インダクタ８８ｂは「第２の調整用インダクタ」の一実施例に対応する。 Similarly, in the noise filter circuit 25b, the adjusting inductor 87b is electrically connected to the input power supply side of the capacitor 82b in a manner of being connected in series to the wiring 70b or 71b. The adjusting inductor 88b is connected in series with the capacitor 82b. In the noise filter circuit 25b, the adjusting inductor 87b corresponds to one embodiment of the "first adjusting inductor", and the adjusting inductor 88b corresponds to one embodiment of the "second adjusting inductor".
　図９の構成では、調整用インダクタ８７ｂのインダクタンスＬｂ１及び調整用インダクタ８８ｂのインダクタンスＬｘｂ１を用いると、電源入力ノードＮ０及びＮ１間に、ノイズフィルタ回路２５ｂを介して形成される経路のインダクタンスＬｂ＝２・Ｌ２＋Ｌｂ１＋Ｌｘｂ１で示される。 In the configuration of FIG. 9, when the inductance Lb1 of the adjusting inductor 87b and the inductance Lxb1 of the adjusting inductor 88b are used, the inductance Lb = 2 of the path formed between the power input nodes N0 and N1 via the noise filter circuit 25b. -Indicated by L2 + Lb1 + Lxb1.
　この結果、実施の形態３の構成では、伝導ノイズが極大となる並列共振周波数と、伝導ノイズが極小となる直列共振周波数とが一致するための回路定数の設定条件である、Ｌａ・Ｃ１＝Ｌｂ・Ｃ２は、調整用インダクタ８７ａ，８７ｂ，８８ａ，８８ｂのインダクタンスを加味して、下記の式（１１）で示される。 As a result, in the configuration of the third embodiment, La · C1 = Lb, which is a setting condition of the circuit constant for matching the parallel resonance frequency at which the conduction noise is maximum and the series resonance frequency at which the conduction noise is minimum. C2 is represented by the following equation (11) in consideration of the inductances of the adjusting inductors 87a, 87b, 88a, 88b.
Figure JPOXMLDOC01-appb-M000010
  
Figure JPOXMLDOC01-appb-M000010
  
　上述のように、寄生インダクタンスＬ１及びＬ２は、配線７０ａ，７１ａ及び配線７０ｂ，７１ｂの長さ等によってある程度調整可能ではあるが、高精度に調整することは一般的に困難である。或いは、レイアウト面等から配線７０ａ，７１ａ及び配線７０ｂ，７１ｂの長さが制約を受ける可能性も想定される。このため、電力変換回路１５０ａ及び１５０ｂのノイズ特性に対応させて設定されたキャパシタンスＣ１及びＣ２に対して、寄生インダクタンスＬ１，Ｌ２の調整のみによって、伝導ノイズ低減のための回路定数設定（Ｌａ・Ｃ１＝Ｌｂ・Ｃ２）を実現することが困難となる（即ち、パラメータｘの１．０からの乖離が大きくなる）虞がある。 As described above, the parasitic inductances L1 and L2 can be adjusted to some extent by the lengths of the wirings 70a and 71a and the wirings 70b and 71b, but it is generally difficult to adjust them with high accuracy. Alternatively, it is assumed that the lengths of the wirings 70a and 71a and the wirings 70b and 71b may be restricted due to the layout surface and the like. Therefore, for the capacitances C1 and C2 set corresponding to the noise characteristics of the power conversion circuits 150a and 150b, the circuit constants (La and C1) for reducing conduction noise are set only by adjusting the parasitic inductances L1 and L2. = Lb · C2) may be difficult to realize (that is, the deviation of the parameter x from 1.0 becomes large).
　これに対して、実施の形態３に係る電気機器によれば、調整用インダクタ８７ａ，８７ｂ及び８８ａ，８８ｂの追加配置により、伝導ノイズ低減のための回路定数設定（Ｌａ・Ｃ１＝Ｌｂ・Ｃ２）をより高精度に実現すること、即ち、パラメータｘを１．０に近付けることが容易となる。これにより、伝導ノイズの低減効果を高める構成を容易に実現することが可能となる。 On the other hand, according to the electric device according to the third embodiment, the circuit constants for reducing conduction noise are set (La · C1 = Lb · C2) by additionally arranging the adjusting inductors 87a, 87b and 88a, 88b. Is realized with higher accuracy, that is, it becomes easy to bring the parameter x closer to 1.0. This makes it possible to easily realize a configuration that enhances the effect of reducing conduction noise.
　尚、上述した式（１０）の実現のために、調整用インダクタ８７ａ，８７ｂ，８８ａ，８８ｂの一部のみを配置する構成とすることも可能である。即ち、調整用インダクタ８７ａ及び８８ａの一方のみを配置すること、或いは、調整用インダクタ８７ｂ及び８８ｂの一方のみを配置することも可能である。又、ノイズフィルタ回路２５ａ側及びノイズフィルタ回路２５ｂ側の一方のみに、調整用インダクタ８７ａ及び８８ａの少なくとも一方、又は、調整用インダクタ８７ｂ及び８８ｂの少なくとも一方を配置する構成とすることも可能である。 In order to realize the above-mentioned equation (10), it is also possible to arrange only a part of the adjusting inductors 87a, 87b, 88a, 88b. That is, it is possible to arrange only one of the adjusting inductors 87a and 88a, or to arrange only one of the adjusting inductors 87b and 88b. Further, it is also possible to arrange at least one of the adjusting inductors 87a and 88a or at least one of the adjusting inductors 87b and 88b on only one of the noise filter circuit 25a side and the noise filter circuit 25b side. ..
　実施の形態４．
　図１０は、実施の形態４に係る電気機器１０３の構成例を説明する回路図である。 Embodiment 4.
FIG. 10 is a circuit diagram illustrating a configuration example of the electric device 103 according to the fourth embodiment.
　図１０を参照して、実施の形態４に係る電気機器１０３は、実施の形態３に係る電気機器１０２（図９）の構成に加えて、ノイズフィルタ回路２５ａが、図５と同様の抵抗素子８６（抵抗値Ｒ１）をさらに有する点で異なる。即ち、図１０においても、ノイズフィルタ回路２５ａ，２５ｂの間でコンデンサ８２ａ，８２ｂのキャパシタンスは異なっており、図５と同様にＣ１＜Ｃ２のときの回路構成例が示される。 With reference to FIG. 10, in the electric device 103 according to the fourth embodiment, in addition to the configuration of the electric device 102 (FIG. 9) according to the third embodiment, the noise filter circuit 25a has the same resistance element as that of FIG. It differs in that it further has 86 (resistance value R1). That is, also in FIG. 10, the capacitances of the capacitors 82a and 82b are different between the noise filter circuits 25a and 25b, and a circuit configuration example when C1 <C2 is shown as in FIG.
　このような構成とすることにより、実施の形態３と同様に、伝導ノイズが極大ピークとなる並列共振周波数と、極小ピークとなる直列共振周波数が一致するための条件Ｌａ・Ｃ１＝Ｌｂ・Ｃ２の実現が容易になるとともに、実施の形態２と同様に、抵抗素子８６の配置により、並列共振ピークを鈍らせることができる。 With such a configuration, as in the third embodiment, the conditions La · C1 = Lb · C2 for the parallel resonance frequency at which the conduction noise has the maximum peak and the series resonance frequency at which the minimum peak is the same are satisfied. The realization becomes easy, and the parallel resonance peak can be blunted by arranging the resistance element 86 as in the second embodiment.
　従って、実施の形態４に係る電気機器によれば、実施の形態２及び３の効果の組み合わせにより、伝導ノイズの低減効果を更に高めることができる。尚、抵抗素子８６の抵抗値Ｒ１の範囲については、式（１０）において、Ｌｂ＝２・Ｌ２＋（Ｌｂ１＋Ｌｘｂ１）として算出することが可能である。 Therefore, according to the electric device according to the fourth embodiment, the effect of reducing conduction noise can be further enhanced by combining the effects of the second and third embodiments. The range of the resistance value R1 of the resistance element 86 can be calculated as Lb = 2 · L2 + (Lb1 + Lxb1) in the equation (10).
　又、実施の形態４に係る電気機器１０３においても、実施の形態３で説明したように、調整用インダクタ８７ａ，８７ｂ，８８ａ，８８ｂの一部のみを配置する構成とすることも可能である。又、抵抗素子８６についても、実施の形態２で説明したように、Ｃ２＜Ｃ１の場合には、ノイズフィルタ回路２５ｂにおいて、入力端子８０ｂ，８１ｂ間にコンデンサ８２ｂと直列に接続される。 Further, also in the electric device 103 according to the fourth embodiment, as described in the third embodiment, it is possible to arrange only a part of the adjusting inductors 87a, 87b, 88a, 88b. Further, as described in the second embodiment, the resistance element 86 is also connected in series with the capacitor 82b between the input terminals 80b and 81b in the noise filter circuit 25b when C2 <C1.
　実施の形態５．
　図１１は、実施の形態５に係る電気機器の構成例を説明する回路図である。 Embodiment 5.
FIG. 11 is a circuit diagram illustrating a configuration example of the electric device according to the fifth embodiment.
　図１１を参照して、実施の形態４に係る電気機器１０４は、図１に示された電気機器１００と比較して、ノイズフィルタ回路２５ａ，２５ｂの構成が異なる。具体的には、ノイズフィルタ回路２５ａにおいて、コモンモードチョークコイル８５ａは、入力端子８０ａ及び８１ａと、コンデンサ８２ａとの間に接続され、コンデンサ８２ａは、コモンモードチョークコイル８５ａ及び電力変換回路１５０ａの間に接続される。同様に、ノイズフィルタ回路２５ｂにおいて、コモンモードチョークコイル８５ｂは、入力端子８０ｂ及び８１ｂと、コンデンサ８２ｂとの間に接続され、コンデンサ８２ｂは、コモンモードチョークコイル８５ｂ及び電力変換回路１５０ｂの間に接続される。 With reference to FIG. 11, the electric device 104 according to the fourth embodiment has a different configuration of the noise filter circuits 25a and 25b from the electric device 100 shown in FIG. Specifically, in the noise filter circuit 25a, the common mode choke coil 85a is connected between the input terminals 80a and 81a and the capacitor 82a, and the capacitor 82a is between the common mode choke coil 85a and the power conversion circuit 150a. Connected to. Similarly, in the noise filter circuit 25b, the common mode choke coil 85b is connected between the input terminals 80b and 81b and the capacitor 82b, and the capacitor 82b is connected between the common mode choke coil 85b and the power conversion circuit 150b. Will be done.
　図１１の構成では、コモンモードチョークコイル８５ａをコンデンサ８２ａよりも入力電源側に接続することにより、電源入力ノードＮ０及びＮ１間にノイズフィルタ回路２５ａを介して形成される経路のインダクタンスＬａに、コモンモードチョークコイル８５ａの漏れインダクタンスＬｄｍ１が加えられる。この結果、図９では、Ｌａ＝２・Ｌ１＋２・Ｌｄｍ１となる。 In the configuration of FIG. 11, by connecting the common mode choke coil 85a to the input power supply side of the capacitor 82a, it is common to the inductance La of the path formed between the power supply input nodes N0 and N1 via the noise filter circuit 25a. The leakage inductance Ldm1 of the mode choke coil 85a is added. As a result, in FIG. 9, La = 2 · L1 + 2 · Ldm1.
　同様に、電源入力ノードＮ０及びＮ１間に、ノイズフィルタ回路２５ｂを介して形成される経路のインダクタンスＬｂには、コモンモードチョークコイル８５ｂの漏れインダクタンスＬｄｍ２が加えられる。この結果、図９では、Ｌｂ＝２・Ｌ２＋２・Ｌｄｍ２となる。 Similarly, the leakage inductance Ldm2 of the common mode choke coil 85b is added to the inductance Lb of the path formed between the power input nodes N0 and N1 via the noise filter circuit 25b. As a result, in FIG. 9, Lb = 2, L2 + 2, Ldm2.
　従って、実施の形態３では、伝導ノイズが極大となる並列共振周波数と、伝導ノイズが極小となる直列共振周波数が一致するための回路定数の設定条件である、Ｌａ・Ｃ１＝Ｌｂ・Ｃ２は、コモンモードチョークコイル８５ａ，８５ｂの漏れインダクタンスＬｄｍ１，Ｌｄｍ２を加味して、下記の式（１２）で示される。 Therefore, in the third embodiment, La · C1 = Lb · C2, which is a setting condition of the circuit constant for matching the parallel resonance frequency at which the conduction noise is maximized and the series resonance frequency at which the conduction noise is minimal, is It is represented by the following equation (12) in consideration of the leakage inductances Ldm1 and Ldm2 of the common mode choke coils 85a and 85b.
　（Ｌ１＋Ｌｄｍ１）・Ｃ１＝（Ｌ２＋Ｌｄｍ２）・Ｃ２　　…（１２）
　このように、図１１の回路構成では、コモンモードチョークコイル８５ａ，８５ｂをコンデンサ８２ａ，８２ｂよりも入力端子８０ａ，８０ｂ側に接続することにより、ノーマルモードチョークとして機能する漏れインダクタンスＬｄｍ１，Ｌｄｍ２を、伝導ノイズ低減のための回路定数設定Ｌａ・Ｃ１＝Ｌｂ・Ｃ２に組み入れることが可能となる。 (L1 + Ldm1) ・ C1 = (L2 + Ldm2) ・ C2 ... (12)
As described above, in the circuit configuration of FIG. 11, by connecting the common mode choke coils 85a and 85b to the input terminals 80a and 80b side of the capacitors 82a and 82b, the leakage inductances Ldm1 and Ldm2 that function as normal mode chokes are provided. It is possible to incorporate it into the circuit constant setting La · C1 = Lb · C2 for reducing conduction noise.
　この結果、実施の形態３に係る電気機器１０２では、漏れインダクタンスＬｄｍ１，Ｌｄｍ２と、配線７０ａ，７１ａ及び配線７０ｂ，７１ｂの長さの調整との組み合わせによって、伝導ノイズ低減のための回路定数設定（Ｌａ・Ｃ１＝Ｌｂ・Ｃ２）の実現性を向上することができる。 As a result, in the electric device 102 according to the third embodiment, the circuit constants for reducing conduction noise are set by combining the leakage inductances Ldm1 and Ldm2 with the adjustment of the lengths of the wirings 70a and 71a and the wirings 70b and 71b. The feasibility of La · C1 = Lb · C2) can be improved.
　実施の形態５の変形例
　図１２は、実施の形態５の変形例に係る電気機器１０５の構成例を説明する回路図である。 Modification Example of Embodiment 5 FIG. 12 is a circuit diagram illustrating a configuration example of an electric device 105 according to a modification of Embodiment 5.
　図１２を参照して、実施の形態５の変形例に係る電気機器１０５は、実施の形態５に係る電気機器１０４（図１０）の構成に加えて、図９（実施の形態３）と同様の調整用インダクタ８７ａ，８８ａ及び調整用インダクタ８７ｂ，８８ｂをさらに備える点、並びに、ノイズフィルタ回路２５ａが、図５（実施の形態２）と同様の抵抗素子８６（抵抗値Ｒ１）をさらに有する点で異なる。即ち、図１２においても、ノイズフィルタ回路２５ａ，２５ｂの間でコンデンサ８２ａ，８２ｂのキャパシタンスは異なっており、図５と同様にＣ１＜Ｃ２のときの回路構成例が示される。 With reference to FIG. 12, the electric device 105 according to the modified example of the fifth embodiment is the same as that of FIG. 9 (3rd embodiment) in addition to the configuration of the electric device 104 (FIG. 10) according to the fifth embodiment. The point that the adjusting inductors 87a and 88a and the adjusting inductors 87b and 88b are further provided, and the point that the noise filter circuit 25a further has the same resistance element 86 (resistance value R1) as in FIG. 5 (Embodiment 2). Is different. That is, also in FIG. 12, the capacitances of the capacitors 82a and 82b are different between the noise filter circuits 25a and 25b, and a circuit configuration example when C1 <C2 is shown as in FIG.
　この結果、図１２の回路構成では、電源入力ノードＮ０及びＮ１間に、ノイズフィルタ回路２５ａを介して形成される経路のインダクタンスＬａ＝２・Ｌ１＋２・Ｌｄｍ１＋Ｌａ１＋Ｌｘａ１となる。同様に、ノイズフィルタ回路２５ｂを介して形成される経路のインダクタンスＬｂ＝２・Ｌ２＋２・Ｌｄｍ２＋Ｌｂ１＋Ｌｘｂ１となる。 As a result, in the circuit configuration of FIG. 12, the inductance La = 2, L1 + 2, Ldm1 + La1 + Lxa1 of the path formed between the power input nodes N0 and N1 via the noise filter circuit 25a. Similarly, the inductance of the path formed via the noise filter circuit 25b is Lb = 2, L2 + 2, Ldm2 + Lb1 + Lxb1.
　この結果、実施の形態５の変形例では、実施の形態５と比較して、調整用インダクタ８７ａ，８７ｂ，８８ａ，８８ｂの追加配置により、伝導ノイズを低減するための回路定数の条件Ｌａ・Ｃ１＝Ｌｂ・Ｃ２の実現が更に容易になるとともに、抵抗素子８６の配置により、並列共振ピークを鈍らせることができる。 As a result, in the modified example of the fifth embodiment, the conditions of the circuit constants for reducing the conduction noise La · C1 are obtained by additionally arranging the adjusting inductors 87a, 87b, 88a, 88b as compared with the fifth embodiment. = Lb · C2 can be realized more easily, and the parallel resonance peak can be blunted by arranging the resistance element 86.
　尚、実施の形態５の変形例では、実施の形態５に対して、実施の形態２及び３の両方を組み合わせる構成例を説明したが、実施の形態２及び３の一方を実施の形態５と組み合わせることも可能である。又、これらの組み合わせにおいて、実施の形態３で説明したように、調整用インダクタ８７ａ，８７ｂ，８８ａ，８８ｂの一部のみを配置する構成とすることも可能である。更に、実施の形態２で説明したように、抵抗素子８６については、Ｃ２＜Ｃ１の場合には、ノイズフィルタ回路２５ｂにおいて、入力端子８０ｂ，８１ｂ間にコンデンサ８２ｂと直列に接続される。 In the modified example of the fifth embodiment, a configuration example in which both the second and third embodiments are combined with respect to the fifth embodiment has been described, but one of the second and third embodiments is the same as the fifth embodiment. It is also possible to combine them. Further, in these combinations, as described in the third embodiment, it is also possible to arrange only a part of the adjusting inductors 87a, 87b, 88a, 88b. Further, as described in the second embodiment, when C2 <C1, the resistance element 86 is connected in series with the capacitor 82b between the input terminals 80b and 81b in the noise filter circuit 25b.
　実施の形態６．
　実施の形態６では、電気機器が室外機及び室内機を備える空気調和機である場合の構成例を説明する。 Embodiment 6.
In the sixth embodiment, a configuration example will be described in the case where the electric device is an air conditioner including an outdoor unit and an indoor unit.
　図１３は、実施の形態６に係る電気機器の第１の構成例を説明する回路図である。
　図１３を参照して、実施の形態６の第１の構成例に係る電気機器１０６は、入力電源１０と電気的に接続されるプラグ１１と、リレースイッチ２００と、室内機３００ａと、室外機３００ｂとを備える。 FIG. 13 is a circuit diagram illustrating a first configuration example of the electric device according to the sixth embodiment.
With reference to FIG. 13, the electric device 106 according to the first configuration example of the sixth embodiment includes a plug 11, a relay switch 200, an indoor unit 300a, and an outdoor unit that are electrically connected to the input power source 10. It is equipped with 300b.
　室内機３００ａは、実施の形態１と同様のノイズフィルタ回路２５ａ及び電力変換回路１５０ａを含む。室内機３００ａに内設された室内機受電部１１０ａは、ノイズフィルタ回路２５ａと電気的に接続される。例えば、電力変換回路１５０ａは、室内機のファンモータ（図示せず）に対して交流電力を供給する。 The indoor unit 300a includes a noise filter circuit 25a and a power conversion circuit 150a similar to those in the first embodiment. The indoor unit power receiving unit 110a installed internally in the indoor unit 300a is electrically connected to the noise filter circuit 25a. For example, the power conversion circuit 150a supplies AC power to a fan motor (not shown) of an indoor unit.
　室外機３００ｂは、実施の形態１と同様のノイズフィルタ回路２５ｂ及び電力変換回路１５０ｂを含む。室外機３００ｂに内設された室外機受電部１１０ｂは、ノイズフィルタ回路２５ｂと電気的に接続される。例えば、電力変換回路１５０ｂは、室外機の冷媒圧縮機（図示せず）の駆動モータに対して交流電力を供給する。 The outdoor unit 300b includes a noise filter circuit 25b and a power conversion circuit 150b similar to those in the first embodiment. The outdoor unit power receiving unit 110b installed internally in the outdoor unit 300b is electrically connected to the noise filter circuit 25b. For example, the power conversion circuit 150b supplies AC power to the drive motor of the refrigerant compressor (not shown) of the outdoor unit.
　電気機器１０６では、室内機３００ａに内設された室内機受電部１１０ａがプラグ１１と電気的に接続される。室外機３００ｂに内設された室外機受電部１１０ｂは、リレースイッチ２００を経由して室内機受電部１１０ａと接続されることによって、プラグ１１と接続された入力電源１０から給電される。電気機器１０６（空気調和機）の停止時には、リレースイッチ２００をオフすることにより、漏洩電流の抑制が図られる。 In the electric device 106, the indoor unit power receiving unit 110a installed internally in the indoor unit 300a is electrically connected to the plug 11. The outdoor unit power receiving unit 110b installed internally in the outdoor unit 300b is connected to the indoor unit power receiving unit 110a via the relay switch 200, so that power is supplied from the input power source 10 connected to the plug 11. When the electric device 106 (air conditioner) is stopped, the leakage current is suppressed by turning off the relay switch 200.
　図１３の電気機器１０６では、ノイズフィルタ回路２５ａ，２５ｂにそれぞれ対応する室内機受電部１１０ａ及び室外機受電部１１０ｂが入力電源に対して段階的に接続される構成とすることで、電気機器１０６の「受電部」と、ノイズフィルタ回路２５ａ及び２５ｂのそれぞれとの間の配線長の差が大きくなることが理解される。 In the electric device 106 of FIG. 13, the indoor unit power receiving unit 110a and the outdoor unit power receiving unit 110b corresponding to the noise filter circuits 25a and 25b, respectively, are connected stepwise to the input power source, whereby the electric device 106 It is understood that the difference in wiring length between the "power receiving unit" of the above and each of the noise filter circuits 25a and 25b becomes large.
　図１３の構成では、プラグ１１を介して入力電源と接続される室内機受電部１１０ａが「受電部」に対応する。電源入力ノードＮ０及びＮ１間に、ノイズフィルタ回路２５ｂを介して形成される経路のインダクタンスＬｂ（Ｌｂ＝２・Ｌ２）を構成する寄生インダクタンスＬ２には、室外機３００ｂ内の配線長による寄生インダクタンスに加えて、室内機受電部１１０ａ及び室外機受電部１１０ｂの間の配線長による寄生インダクタンスが含まれることになる。 In the configuration of FIG. 13, the indoor unit power receiving unit 110a connected to the input power supply via the plug 11 corresponds to the “power receiving unit”. The parasitic inductance L2 that constitutes the inductance Lb (Lb = 2 · L2) of the path formed between the power input nodes N0 and N1 via the noise filter circuit 25b has a parasitic inductance due to the wiring length in the outdoor unit 300b. In addition, the parasitic inductance due to the wiring length between the indoor unit power receiving unit 110a and the outdoor unit power receiving unit 110b is included.
　一方で、電源入力ノードＮ０及びＮ１間に、ノイズフィルタ回路２５ａを介して形成される経路のインダクタンスＬａ（Ｌａ＝２・Ｌ２）を構成する寄生インダクタンスＬ１は、室内機３００ａ内の配線長による寄生インダクタンスによって形成される。 On the other hand, the parasitic inductance L1 constituting the inductance La (La = 2 · L2) of the path formed between the power input nodes N0 and N1 via the noise filter circuit 25a is parasitic due to the wiring length in the indoor unit 300a. Formed by inductance.
　この結果、図１３の電気機器１０６では、ノイズフィルタ回路２５ａ側の寄生インダクタンスＬ１（インダクタンスＬａ）が、ノイズフィルタ回路２５ｂ側の寄生インダクタンスＬ２（インダクタンスＬｂ）よりも小さくなり（Ｌ１＜Ｌ２）、かつ、その差が比較的大きくなる。 As a result, in the electric device 106 of FIG. 13, the parasitic inductance L1 (inductance La) on the noise filter circuit 25a side is smaller than the parasitic inductance L2 (inductance Lb) on the noise filter circuit 25b side (L1 <L2), and , The difference is relatively large.
　従って、寄生インダクタンスＬ１及びＬ２の差を活用して、伝導ノイズが極大となる並列共振周波数と、伝導ノイズが極小となる直列共振周波数とが一致するための回路定数の設定条件である、Ｌａ・Ｃ１＝Ｌｂ・Ｃ２の実現を図ることができる。 Therefore, by utilizing the difference between the parasitic inductances L1 and L2, the circuit constant setting condition for matching the parallel resonance frequency at which the conduction noise is maximized and the series resonance frequency at which the conduction noise is at its minimum is La. It is possible to realize C1 = Lb · C2.
　即ち、図１３の回路構成では、Ｌ２＞Ｌ１によりＬｂ＞Ｌａとなることを考慮すると、電力変換回路１５０ａ，１５０ｂのノイズ特性から、コンデンサ８２ａ，８２ｂについてＣ１＞Ｃ２であるときに、調整用インダクタの追加配置を最小化して、Ｌａ・Ｃ１＝Ｌｂ・Ｃ２を確保することが可能となる。 That is, in the circuit configuration of FIG. 13, considering that Lb> La due to L2> L1, the adjusting inductor when the capacitors 82a and 82b are C1> C2 due to the noise characteristics of the power conversion circuits 150a and 150b. It is possible to secure La · C1 = Lb · C2 by minimizing the additional arrangement of.
　図１４は、実施の形態６に係る電気機器の第２の構成例を説明する回路図である。
　図１４を参照して、実施の形態６の第２の構成例に係る電気機器１０７は、図１３に示された電気機器１０６と同様の、プラグ１１と、リレースイッチ２００と、室内機３００ａと、室外機３００ｂとを備える。 FIG. 14 is a circuit diagram illustrating a second configuration example of the electric device according to the sixth embodiment.
With reference to FIG. 14, the electric device 107 according to the second configuration example of the sixth embodiment includes a plug 11, a relay switch 200, and an indoor unit 300a similar to the electric device 106 shown in FIG. , The outdoor unit 300b is provided.
　電気機器１０７では、電気機器１０６（図１３）とは反対に、室外機受電部１１０ｂがプラグ１１と電気的に接続されるとともに、室内機受電部１１０ａは、室外機受電部１１０ｂを介して、入力電源に対して段階的に接続される。これにより、電気機器１０７においても、「受電部」と、ノイズフィルタ回路２５ａ及び２５ｂのそれぞれとの間の配線長の差が大きくなる。 In the electric device 107, contrary to the electric device 106 (FIG. 13), the outdoor unit power receiving unit 110b is electrically connected to the plug 11, and the indoor unit power receiving unit 110a is connected to the outdoor unit power receiving unit 110b via the outdoor unit power receiving unit 110b. It is connected in stages to the input power supply. As a result, even in the electric device 107, the difference in wiring length between the “power receiving unit” and each of the noise filter circuits 25a and 25b becomes large.
　具体的には、図１４の構成では、プラグ１１を介して入力電源と接続される室外機受電部１１０ｂが「受電部」に対応する。電源入力ノードＮ０及びＮ１間に、ノイズフィルタ回路２５ａを介して形成される経路のインダクタンスＬａ（Ｌａ＝２・Ｌ１）を構成する寄生インダクタンスＬ１には、室内機３００ａ内の配線長による寄生インダクタンスに加えて、室外機受電部１１０ｂ及び室内機受電部１１０ａの間の配線長による寄生インダクタンスが含まれることになる。 Specifically, in the configuration of FIG. 14, the outdoor unit power receiving unit 110b connected to the input power supply via the plug 11 corresponds to the “power receiving unit”. The parasitic inductance L1 that constitutes the inductance La (La = 2 · L1) of the path formed between the power input nodes N0 and N1 via the noise filter circuit 25a has a parasitic inductance due to the wiring length in the indoor unit 300a. In addition, the parasitic inductance due to the wiring length between the outdoor unit power receiving unit 110b and the indoor unit power receiving unit 110a is included.
　一方で、電源入力ノードＮ０及びＮ１間に、ノイズフィルタ回路２５ｂを介して形成される経路のインダクタンスＬｂ（Ｌｂ＝２・Ｌ２）を構成する寄生インダクタンスＬ２は、室外機３００ｂ内の配線長による寄生インダクタンスによって形成される。 On the other hand, the parasitic inductance L2 forming the inductance Lb (Lb = 2 · L2) of the path formed between the power input nodes N0 and N1 via the noise filter circuit 25b is parasitic due to the wiring length in the outdoor unit 300b. Formed by inductance.
　この結果、図１４の電気機器１０７では、ノイズフィルタ回路２５ｂ側の寄生インダクタンスＬ２（インダクタンスＬｂ）が、ノイズフィルタ回路２５ａ側の寄生インダクタンスＬ１（インダクタンスＬａ）よりも小さくなり（Ｌ２＜Ｌ１）、かつ、その差が比較的大きくなる。 As a result, in the electric device 107 of FIG. 14, the parasitic inductance L2 (inductance Lb) on the noise filter circuit 25b side is smaller than the parasitic inductance L1 (inductance La) on the noise filter circuit 25a side (L2 <L1), and , The difference is relatively large.
　即ち、図１４の回路構成では、Ｌ１＞Ｌ２によりＬａ＞Ｌｂとなることを考慮すると、電力変換回路１５０ａ，１５０ｂのノイズ特性から、コンデンサ８２ａ，８２ｂについてＣ２＞Ｃ１であるときに、調整用インダクタの追加配置を最小化して、Ｌａ・Ｃ１＝Ｌｂ・Ｃ２を確保することが可能となる。 That is, in the circuit configuration of FIG. 14, considering that La> Lb due to L1> L2, from the noise characteristics of the power conversion circuits 150a and 150b, when C2> C1 for the capacitors 82a and 82b, the adjusting inductor It is possible to secure La · C1 = Lb · C2 by minimizing the additional arrangement of.
　このように、実施の形態６に係る電気機器では、ノイズフィルタ回路２５ａ及び２５ｂを段階的に入力電源と接続することによって生じた、配線の寄生インダクタンスの差を利用して、伝導ノイズを低減するための回路定数の条件Ｌａ・Ｃ１＝Ｌｂ・Ｃ２を容易に実現することが可能となる。 As described above, in the electric device according to the sixth embodiment, the conduction noise is reduced by utilizing the difference in the parasitic inductance of the wiring generated by connecting the noise filter circuits 25a and 25b stepwise to the input power supply. It is possible to easily realize the condition La · C1 = Lb · C2 of the circuit constant for the purpose.
　尚、実施の形態６及びその変形例に係る電気機器１０６，１０７に対して、実施の形態２で説明した抵抗素子８６をコンデンサ８２ａ又は８２ｂと直列接続する構成、実施の形態３で説明した、調整用インダクタ８７ａ，８７ｂ，８８ａ，８８ｂの少なくとも一部を追加配置する構成、並びに、実施の形態５で説明した、漏れインダクタンスＬｄｍ１，Ｌｄｍ２を利用するようにコモンモードチョークコイル８５ａ，８５ｂを接続する構成の一部又は全部を組み合わせることも可能である。 The configuration in which the resistance element 86 described in the second embodiment is connected in series with the capacitor 82a or 82b with respect to the electric devices 106 and 107 according to the sixth embodiment and the modified examples thereof is described in the third embodiment. The common mode choke coils 85a and 85b are connected so as to utilize the configuration in which at least a part of the adjusting inductors 87a, 87b, 88a and 88b is additionally arranged and the leakage inductances Ldm1 and Ldm2 described in the fifth embodiment. It is also possible to combine some or all of the configurations.
　又、本実施の形態では、２個の電力変換回路１５０ａ，１５０ｂが共通の受電部１１０（入力電源１０）と接続される構成を説明したが、３個以上の電力変換回路が共通の受電部（入力電源）と接続される構成に対しても、本実施の形態を適用することが可能である。例えば、当該３個以上の電力変換回路のうちのノイズ発生量の多い２個の電力変換回路の間で、入力側のノイズフィルタ回路に関連する回路構成及び回路定数条件を実施の形態１～６のいずれかと同様にすることができる。 Further, in the present embodiment, the configuration in which the two power conversion circuits 150a and 150b are connected to the common power receiving unit 110 (input power supply 10) has been described, but the power receiving unit in which three or more power conversion circuits are common. It is possible to apply this embodiment to a configuration connected to (input power supply). For example, the circuit configuration and circuit constant conditions related to the noise filter circuit on the input side are set between the two power conversion circuits that generate a large amount of noise among the three or more power conversion circuits according to the first to sixth embodiments. Can be similar to any of.
　以上で説明した複数の実施の形態について、明細書内で言及されていない組み合わせを含めて、不整合や矛盾が生じない範囲内で、各実施の形態で説明された構成を適宜組合わせることは出願当初から予定されている点についても、確認的に記載する。 With respect to the plurality of embodiments described above, the configurations described in the respective embodiments may be appropriately combined within a range that does not cause inconsistency or inconsistency, including combinations not mentioned in the specification. The points planned from the beginning of the application will also be described in a confirmatory manner.
　今回開示された実施の形態は、すべての点で例示であって制限的なものではないと考えられるべきである。本発明の範囲は、上記した実施の形態の説明ではなくて請求の範囲によって示され、請求の範囲と均等の意味および範囲内でのすべての変更が含まれることが意図される。 The embodiments disclosed this time should be considered to be exemplary in all respects and not restrictive. The scope of the present invention is shown by the claims rather than the description of the embodiments described above, and is intended to include all modifications within the meaning and scope equivalent to the claims.
　１０　入力電源、１１　プラグ、２５ａ，２５ｂ　ノイズフィルタ回路、７０ａ，７０ｂ，７１ａ，７１ｂ　配線、８０ａ，８０ｂ　入力端子、８２ａ，８２ｂ　コンデンサ、８５ａ，８５ｂ　コモンモードチョークコイル、８６　抵抗素子、８７ａ，８７ｂ，８８ａ，８８ｂ　調整用インダクタ、１００～１０７　電気機器、１１０　受電部、１１０ａ　室内機受電部、１１０ｂ　室外機受電部、１５０ａ，１５０ｂ　電力変換回路、２００　リレースイッチ、３００ａ　室内機、３００ｂ　室外機、Ｎ０，Ｎ１　電源入力ノード、Ｒ１　抵抗値、ｆｐ　並列共振周波数、ｆｐ＊　共振周波数（回路定数条件設定後）、ｆｓ１，ｆｓ２　直列共振周波数。 10 input power supply, 11 plug, 25a, 25b noise filter circuit, 70a, 70b, 71a, 71b wiring, 80a, 80b input terminal, 82a, 82b capacitor, 85a, 85b common mode choke coil, 86 resistance element, 87a, 87b, 88a, 88b Adjustment inductor, 100-107 electrical equipment, 110 power receiving unit, 110a indoor unit power receiving unit, 110b outdoor unit power receiving unit, 150a, 150b power conversion circuit, 200 relay switch, 300a indoor unit, 300b outdoor unit, N0, N1 power input node, R1 resistance value, fp parallel resonance frequency, fp * resonance frequency (after setting circuit constant conditions), fs1, fs2 series resonance frequency.

Claims (8)

  1. 　入力電源と接続された第１及び第２の電源入力ノードを有する受電部と、
    　スイッチング素子を含んで構成された第１及び第２の電力変換回路と、
    　前記受電部及び前記第１の電力変換回路の間に電気的に接続される第１のノイズフィルタ回路と、
    　前記受電部及び前記第２の電力変換回路の間に電気的に接続される第２のノイズフィルタ回路と、
    　前記受電部及び前記第１のノイズフィルタ回路を電気的に接続する第１の配線と、
    　前記受電部及び前記第２のノイズフィルタ回路を電気的に接続する第２の配線とを備え、
    　前記第１のノイズフィルタ回路は、
    　前記第１の配線と接続される１対の第１入力端子と、
    　前記第１入力端子間に、前記第１の電力変換回路の入力電源側に対して並列接続された第１のコンデンサとを含み、
    　前記第２のノイズフィルタ回路は、
    　前記第２の配線と接続される１対の第２入力端子と、
    　前記第２入力端子間に、前記第２の電力変換回路の入力電源側に対して並列接続された第２のコンデンサとを含み、
    　前記第１及び第２の電源入力ノードの間に、前記第１の配線及び前記第１のノイズフィルタ回路を経由して形成される第１の経路の第１のインダクタンス、並びに、前記第２の配線及び前記第２のノイズフィルタ回路を経由して形成される第２の経路の第２のインダクタンスは、前記第２のインダクタンスに対する前記第１のインダクタンスの比が、前記第１のコンデンサの第１のキャパシタンスに対する前記第２のコンデンサの第２のキャパシタンスの比に従うように調整される、電気機器。     A power receiving unit having first and second power input nodes connected to an input power supply,
    A first and second power conversion circuit configured to include a switching element, and
    A first noise filter circuit electrically connected between the power receiving unit and the first power conversion circuit,
    A second noise filter circuit electrically connected between the power receiving unit and the second power conversion circuit, and
    The first wiring that electrically connects the power receiving unit and the first noise filter circuit, and
    The power receiving unit and the second wiring for electrically connecting the second noise filter circuit are provided.
    The first noise filter circuit is
    A pair of first input terminals connected to the first wiring,
    A first capacitor connected in parallel to the input power supply side of the first power conversion circuit is included between the first input terminals.
    The second noise filter circuit is
    A pair of second input terminals connected to the second wiring,
    A second capacitor connected in parallel to the input power supply side of the second power conversion circuit is included between the second input terminals.
    The first inductance of the first path formed between the first and second power input nodes via the first wiring and the first noise filter circuit, and the second The second inductance of the second path formed via the wiring and the second noise filter circuit is such that the ratio of the first inductance to the second inductance is the first of the first capacitor. An electrical device that is adjusted to follow the ratio of the second capacitance of the second capacitor to its capacitance.
  2. 　前記第１及び第２の電力変換回路のノイズ特性に対応してそれぞれ設定された前記第１及び第２のキャパシタンスとは異なる値であり、
    　前記第１の配線及び前記第２の配線は、前記第２の配線のインダクタンスに対する前記第１の配線のインダクタンスの比が、前記第１のキャパシタンスに対する前記第２のキャパシタンスの比に従うように調整される、請求項１記載の電気機器。     It is a value different from the first and second capacitances set corresponding to the noise characteristics of the first and second power conversion circuits, respectively.
    The first wiring and the second wiring are adjusted so that the ratio of the inductance of the first wiring to the inductance of the second wiring follows the ratio of the second capacitance to the first capacitance. The electrical device according to claim 1.
  3. 　前記第２のキャパシタンス及び前記第２の配線のインダクタンスの積に対する、前記第１のキャパシタンス及び前記第１の配線のインダクタンスの積の比が、１．０を含む所定範囲内となるように、前記第１及び第２のインダクタンスは調整される、請求項２記載の電気機器。 The ratio of the product of the first capacitance and the inductance of the first wiring to the product of the inductance of the second capacitance and the second wiring is within a predetermined range including 1.0. The electrical device according to claim 2, wherein the first and second inductances are adjusted.
  4. 　前記第１のキャパシタンスは、前記第２のキャパシタンスよりも小さく、
    　前記第１のノイズフィルタ回路は、
    　前記第１入力端子間に、前記第１のコンデンサと直列に接続された抵抗素子をさらに含む、請求項１～３のいずれか１項に記載の電気機器。     The first capacitance is smaller than the second capacitance,
    The first noise filter circuit is
    The electric device according to any one of claims 1 to 3, further comprising a resistance element connected in series with the first capacitor between the first input terminals.
  5. 　前記第２のキャパシタンスは、前記第１のキャパシタンスよりも小さく、
    　前記第２のノイズフィルタ回路は、
    　前記第２入力端子間に、前記第２のコンデンサと直列に接続された抵抗素子をさらに含む、請求項１～３のいずれか１項に記載の電気機器。     The second capacitance is smaller than the first capacitance,
    The second noise filter circuit is
    The electric device according to any one of claims 1 to 3, further comprising a resistance element connected in series with the second capacitor between the second input terminals.
  6. 　前記第１及び第２のノイズフィルタ回路の少なくとも一方は、
    　前記第１の配線に対して直列に接続される第１の調整用インダクタと、
    　前記第１又は第２のコンデンサに対して直列に接続される第２の調整用インダクタとの少なくとも一方をさらに含む、請求項１～５のいずれか１項に記載の電気機器。     At least one of the first and second noise filter circuits
    A first adjusting inductor connected in series with the first wiring,
    The electrical device according to any one of claims 1 to 5, further comprising at least one of a second adjusting inductor connected in series with the first or second capacitor.
  7. 　前記第１及び第２のノイズフィルタ回路の各々は、
    　前記第１入力端子又は前記第２入力端子と、前記第１又は第２のコンデンサとの間に接続されたコモンモードチョークコイルをさらに含む、請求項１～６のいずれか１項に記載の電気機器。     Each of the first and second noise filter circuits
    The electricity according to any one of claims 1 to 6, further comprising a common mode choke coil connected between the first input terminal or the second input terminal and the first or second capacitor. machine.
  8. 　前記受電部は、前記第１及び第２のノイズフィルタ回路にそれぞれ対応して２個設けられ、
    　前記２個の受電部のうちの一方の受電部は、前記入力電源と接続された他方の受電部を経由して、前記入力電源と電気的に接続される、請求項１～７のいずれか１項に記載の電気機器。     Two power receiving units are provided corresponding to the first and second noise filter circuits, respectively.
    Any one of claims 1 to 7, wherein one of the two power receiving units is electrically connected to the input power source via the other power receiving unit connected to the input power source. The electrical equipment according to item 1.
PCT/JP2019/035937 2019-09-12 2019-09-12 Electric device WO2021048978A1 (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000324696A (en) * 1999-05-14 2000-11-24 Hitachi Ltd Air conditioner
JP2008054287A (en) * 2006-07-27 2008-03-06 Murata Mfg Co Ltd Noise filter array
JP2010220272A (en) * 2009-03-13 2010-09-30 Fuji Electric Holdings Co Ltd Power conversion system, method for calculating constant of filter component of the system, and program
JP2013110580A (en) * 2011-11-21 2013-06-06 Denso Corp Noise filter and electronic apparatus equipped with the same
JP2019047541A (en) * 2017-08-29 2019-03-22 ダイキン工業株式会社 Power conversion system

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000324696A (en) * 1999-05-14 2000-11-24 Hitachi Ltd Air conditioner
JP2008054287A (en) * 2006-07-27 2008-03-06 Murata Mfg Co Ltd Noise filter array
JP2010220272A (en) * 2009-03-13 2010-09-30 Fuji Electric Holdings Co Ltd Power conversion system, method for calculating constant of filter component of the system, and program
JP2013110580A (en) * 2011-11-21 2013-06-06 Denso Corp Noise filter and electronic apparatus equipped with the same
JP2019047541A (en) * 2017-08-29 2019-03-22 ダイキン工業株式会社 Power conversion system

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