WO2021031153A1 - 一种数据处理的设备以及系统 - Google Patents

一种数据处理的设备以及系统 Download PDF

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Publication number
WO2021031153A1
WO2021031153A1 PCT/CN2019/101804 CN2019101804W WO2021031153A1 WO 2021031153 A1 WO2021031153 A1 WO 2021031153A1 CN 2019101804 W CN2019101804 W CN 2019101804W WO 2021031153 A1 WO2021031153 A1 WO 2021031153A1
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WIPO (PCT)
Prior art keywords
data
main control
control board
deviation
channel
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PCT/CN2019/101804
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English (en)
French (fr)
Inventor
黄天强
刘威
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN201980098430.2A priority Critical patent/CN114127767A/zh
Priority to PCT/CN2019/101804 priority patent/WO2021031153A1/zh
Priority to EP19942616.4A priority patent/EP4016428A4/en
Publication of WO2021031153A1 publication Critical patent/WO2021031153A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H04J3/0697—Synchronisation in a packet node

Definitions

  • This application relates to the field of communications, and in particular to a data processing device.
  • a hardware solution with dual main control boards and interface boards is generally adopted.
  • the two main control boards are used to ensure mutual backup of services and ensure the normal transmission of services.
  • the main control board and interface board work together.
  • the interface board completes the switching of the service from the main main control board to the standby main control board, for example, when the interface board determines the main main control board If the board is abnormal, the interface board no longer sends messages to or receives messages from the original active main control board, but sends messages to the original standby main control board or receives messages from the original standby main control board.
  • the transmission delay caused by the active main control board and the standby main control board may be asymmetric when the service is transmitted in the device .
  • the asymmetric transmission delay generated during the active/standby switching may introduce delay jitter or cause service interruption. Therefore, how to reduce the delay and jitter introduced during the active/standby switchover and perform the active/standby switchover without interrupting services needs to be solved urgently.
  • the present application provides a data processing device, which reduces the delay and jitter introduced when the active main control board is switched to the standby main control board, and at the same time solves the problem of service interruption of the peer device when the active and standby main control boards are switched.
  • the first aspect of this application provides a data processing device.
  • the data processing device may be a clock data recovery (CDR) or an interface board, and may include: a first transceiver module for receiving a first master The first data sent by the board.
  • the second transceiver module is used to receive the second data sent by the second main control board.
  • the first main control board and the second main control board are each other's master and standby main control boards, and the first data and the second data are mutually backup data.
  • the deviation measurement module is used to determine the first deviation between the first data and the second data.
  • the data processing device may also include a feedback module for sending a first deviation to the standby main control board in the first main control board and the second main control board, and the first deviation is used for the first main control board to perform the third data
  • the feedback module is the same as or different from the first transceiver module.
  • the first transceiver module is also used to receive the third data sent by the first main control board after receiving the first data.
  • the second transceiver module is also used to receive the fourth data sent by the second main control board, and the fourth data and the third data are mutually backup data.
  • the deviation compensation module is used to perform the second deviation compensation on the third data according to the fourth data.
  • the standby main control board performs the first deviation compensation on the third data according to the first deviation, and the data processing equipment performs the second deviation compensation on the third data. After two deviation compensations, the third The data and the fourth data can be basically aligned.
  • the standby main control board is triggered to switch to the active main control board, the delay jitter is reduced.
  • the first possible implementation manner it may further include: a tracking module, which is used to track when the first main control board is switched from the standby main control board to the active main control board The third data after the second offset compensation.
  • the data processing device may further include a fourth transceiver module, configured to send third data to the opposite device. From the first possible implementation of the first aspect, it can be seen that the tracking module only needs to track one channel of data to ensure that the services of the peer device are not interrupted. For example, the tracking module tracks before the first main control board is switched to the active main control board.
  • the data of the second main control board that is, the tracking module tracks the data of the main main control board.
  • the tracking module only needs to track the third data to ensure that the peer-end business is not interrupted.
  • the first transceiver module may include P channels, and the second transceiver module may include Q channels , P and Q are both positive integers, and the first transceiver module is specifically used to receive the first data through the P channel.
  • the second transceiver module is specifically configured to receive the second data through the Q channel.
  • the deviation measurement module is specifically used to determine the first deviation according to the difference between T1 and T2 and the interface rate of the device. T1 is the arrival time of the last channel in the P channel, and T2 is the arrival time of the last channel in the Q channel.
  • the second possible implementation manner of the first aspect provides a specific manner for determining the first deviation.
  • each of the P channels may include the alignment mark AM, and each of the Q channels may Including AM, T1 is the arrival time of AM in the last channel of the P channel, and T2 is the arrival time of AM in the last channel of the Q channel.
  • the third possible implementation of the first aspect provides a specific way to determine the first deviation.
  • the data processing device can determine the first deviation based on the phase offset between the AM words in the first data and the second data. .
  • the first transceiver module may include P channels, and the second transceiver module may include Q channels.
  • P and Q are both positive integers, and the first transceiver module is specifically used to receive the first data through the P channel.
  • the second transceiver module is specifically configured to receive the second data through the Q channel.
  • the device may also include: a buffer module for buffering the P channel and the Q channel when the data of the first channel is received.
  • the deviation measurement module is specifically configured to determine the first skew according to the first buffer and the second buffer.
  • the first buffer is the buffer accumulated by the P channel when the last channel in the P channel arrives, and the second buffer is the Q channel When the last channel in the Q channel arrives, the accumulated buffer of the Q channel.
  • the fourth possible implementation of the first aspect provides a specific way of determining the first deviation.
  • a second aspect of the present application provides a data processing device, which may include: a first transceiver module, configured to send first data to an interface board.
  • the acquisition module is used to acquire the first deviation, the first deviation is the deviation between the first data and the second data determined by the interface board, the second data is the data sent by the second main control board, and the second data is the same as the first data They are mutually backup data, the second main control board and the first main control board are mutually active and standby main control boards, and the acquisition module is the same or different from the first transceiver module.
  • the processing module is configured to perform deviation compensation on the third data according to the first deviation obtained by the second transceiver module.
  • the first transceiver module is also used to send the third data after deviation compensation.
  • a third aspect of the present application provides a data processing system.
  • the data processing system includes an interface board and a main control board.
  • the interface board is the data described in the first aspect or any one of the possible implementations of the first aspect.
  • the processing equipment, the main control board is the data processing equipment described in the second aspect.
  • a fourth aspect of the present application provides a data processing system.
  • the data processing system includes a clock data recovery CDR chip and a network processor NP chip.
  • the CDR chip is a possible implementation of the first aspect or any one of the first aspect.
  • the NP chip is the data processing equipment described in the second aspect.
  • a fifth aspect of the present application provides a packet transport network (PTN) device.
  • the PTN device includes an interface board and a main control board, where the interface board is the first aspect or any possible implementation of the first aspect
  • the main control board is the data processing equipment described in the second aspect.
  • a sixth aspect of the present application provides a packet transport network (PTN) device.
  • the PTN device includes a clock data recovery CDR chip and a network processor NP chip.
  • the CDR chip is either the first aspect or any one of the first aspect.
  • the NP chip is the data processing equipment described in the second aspect.
  • the embodiment of the application provides a data processing device.
  • the interface board determines the deviation between the data sent by the active main control board and the standby main control board.
  • the standby main control board can adjust the sent data according to the deviation, and the interface board then Perform deviation compensation for the data sent by the main main control board and the standby main control board.
  • the data stream sent by the standby main control board is already aligned with the data sent by the main main control board inside the interface board. Therefore, after the active/standby switchover, the delay jitter introduced by the active/standby switchover is reduced, and at the same time, the problem of service interruption at the opposite end when the active/standby control board is switched.
  • FIG. 1 is a schematic diagram of an application scenario provided by an embodiment of the application
  • Figure 2 is a schematic structural diagram of a data processing device
  • FIG. 3 is a schematic diagram of the structure of a data processing device including a first CDR chip
  • FIG. 4 is a schematic diagram of the structure of a data processing device including a second CDR chip
  • Figure 5 is a schematic diagram of delay jitter caused by the second CDR chip
  • FIG. 6 is a schematic structural diagram of a data processing device provided by this application.
  • FIG. 7 is a schematic structural diagram of another data processing device provided by this application.
  • Fig. 1 is a schematic diagram of an application scenario provided by an embodiment of the present invention.
  • the device 101 is called the local device
  • the device 102 is called the opposite device, or the device 102 is called the local device
  • the device 101 is called the opposite device.
  • the device 101 and the device 102 are box-type devices or frame-type devices.
  • the device 101 and the device 102 may be routers, switches, optical transport network (OTN) equipment, and packet transport network (PTN) Equipment, wavelength-division multiplexing (WDM) equipment.
  • OTN optical transport network
  • PTN packet transport network
  • WDM wavelength-division multiplexing
  • the embodiments of this application do not limit the types of the local device and the opposite device to be the same.
  • the local device may be a PTN device or a router
  • the opposite device may be a router or a switch.
  • the box-type equipment or frame-type equipment mentioned above generally adopts a hardware solution of dual main control boards and interface boards.
  • the main control board may include a media access controller (MAC) and a network processor.
  • the main control board may also include multiple MACs and multiple network processors.
  • the MAC in the main control board can be coupled with the network processor in the main control board.
  • the main control board can be implemented by a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC).
  • FPGA field programmable gate array
  • ASIC application specific integrated circuit
  • FIG 2 it is a schematic diagram of the structure of a data processing device, which includes two main control boards, the main main control board 201 and the standby main control board 202 respectively.
  • the main main control board is referred to as the master main control board below.
  • the standby main control board is called the slave main control board.
  • Two main control boards are used to ensure mutual backup of services.
  • the main main control board 201 in FIG. 2 only shows one MAC 2012 and one network processor 2011, and the standby main control board 202 in FIG. 2 only shows one MAC 2022 and one network processor.
  • the MAC2012 is coupled with the network processor 2011, and the MAC2022 is coupled with the network processor 2021.
  • one MAC and one network processor do not represent a limit on the number, but for the convenience of description. The following description of numbers is not a limit on the number, but for the convenience of description, and will not be repeated below.
  • the network processor on the main control board implements service processing such as packet forwarding and scheduling.
  • the network processor 2011 and the network processor 2021 can be a network processor (NP) or a packet processor (PP). ), or a packet engine (PE), or an application specific integrated circuit (ASIC), the network processor 2011 and the network processor 2021 may be programmable or non-programmable, the implementation of the present invention The example does not limit this. It should be noted that in some scenarios, the main control board is also called the forwarding processing board. As mentioned above, those skilled in the art should understand that hardware manufacturers may use different terms To call the same component. This specification and the following claims do not use differences in names as a way to distinguish components, but use differences in functions of components as a criterion for distinguishing.
  • the interface board 203 adopts a clock data recovery (CDR) chip 2031 with an electronic switch (MUX/DEMUX) function.
  • the electronic switch includes a multiplexer circuit (MUX) and a demultiplexer circuit (DEMUX) to realize the line side
  • the selective sending or dual sending function to the system side and the selective receiving function from the system side to the line side support the switching between the master main control board 201 and the slave main control board 202.
  • the line side refers to the side of the interface board close to the external interface.
  • the line side refers to the side of the interface board close to the external optical fiber
  • the system side refers to the side of the interface board close to the internal interface.
  • the system side refers to the side of the interface board close to the network processor.
  • the selective sending function means that the CDR chip 2031 chooses to send the message to the master main control board 201 or the slave main control board 202.
  • the CDR chip 2031 sends the message to the master main control board 201 and the slave main control board 202.
  • the selective receiving function means that the CDR chip 2031 selects to send the message of the master main control board 201 or the slave main control board 202 to the line side.
  • the main control board and the interface board may also include other components, which are not specifically limited in the embodiment of the application.
  • the interface board 203 may also include an optical module (optical mpdel) 2032, which is used for photoelectric signal conversion. .
  • the master main control board 201 and the interface board work together.
  • the master/backup switchover is triggered.
  • the service is taken over by the slave main control board 202.
  • the interface board CDR chip completes the service switching from the master main control board 201 to the slave main control board 202, for example, when the CDR chip If the master main control board 201 is determined to be abnormal, the CDR chip no longer sends messages to the master main control board 201 or no longer receives messages from the master main control board 201, but sends messages to the slave main control board 202 or from the slave The main control board 202 receives the message.
  • FIG. 3 is a schematic diagram of the structure of the device including the first CDR chip 303, and the first CDR chip 303 shown in FIG. 3 includes a serializer/deserializer (SERializer/DESerializer, serializer) and MUX/DEMUX and other circuits.
  • serializer/deserializer Serializer/DESerializer, serializer
  • MUX/DEMUX MUX/DEMUX and other circuits.
  • the deserializer 3035, serializer/deserializer 3036 and MUX/DEMUX 3033 and MUX/DEMUX 3034, MUX/DEMUX 3033, and MUX/DEMUX 3034 circuits are also called electronic switches.
  • the serdes circuit can convert the parallel physical code into a serial physical code and send it, or convert the serial physical code into a parallel physical code to receive, so that the data can be transmitted in serial form with a higher transmission rate.
  • this application refers to the serdes circuit that can convert parallel physical codes into serial physical codes and then send them as serializers (also called serdes Tx in English), which converts serial physical codes into parallel physical codes
  • the serdes circuit is called deserializer (also called serdes Rx in English).
  • This type of first CDR chip 303 does not support the ethnet physical coding sublayer (ETH PCS).
  • the first CDR chip 303 When the master main control board 301 is abnormal and triggers the master/backup switchover, the first CDR chip 303 is generally at any time The service is switched to the slave main control board 302, but since the processing delays of the two main control boards of the master and slave cannot be consistent, the ETH protocol words of the two main control boards of the master and slave are also difficult to achieve alignment.
  • the network-side protocol words and messages received by the first CDR chip 303 from the master and slave two main control boards are not synchronized, which results in the network-side protocol of the device interface-side message when the device sends out messages Words will be shifted, causing service interruption on the peer device.
  • the main main control board 301 and the standby main control board 302 can be understood with reference to the main main control board 201 and the standby main control board 202 corresponding to FIG. 2.
  • the network processor 3011 and the network processor 3021 can refer to the network processing corresponding to FIG.
  • the device 2011 and the network processor 2021 understand that the media access controller 3012 and the media access controller 3022 can refer to the media access controller 2012 and the media access controller 2022 corresponding to FIG. 2 and will not be repeated here.
  • Fig. 4 is a schematic structural diagram of a device including a second CDR chip 403.
  • the second CDR chip 403 shown in Fig. 4 includes not only serdes and MUX/DEMUX circuits, but also an Ethernet physical encoding sublayer.
  • the second CDR chip 403 supports the Ethernet physical encoding sublayer, and the Ethernet physical encoding sublayer can parse the synchronization headers, alignment markers (alignment markers, AM), etc. of the 8bit/10bit encoding or 64bit/66bit encoding of the ETH protocol.
  • alignment markers alignment markers, AM
  • the master main control board 401 and the slave main control board 402 respectively send data to the second CDR chip 403 through the Ethernet interface.
  • Different Ethernet interfaces correspond to the number of different lanes.
  • the number of lanes can be understood as a parallel link
  • the number of links sending data For example, if the Ethernet interface adopts the 25G Ethernet protocol, the number of corresponding lanes can be 1.
  • the master main control board 401 sending data to the second CDR chip 403 as an example, that is, the master main control board 401 can send data to the first lane through one lane.
  • the two CDR chip 403 sends data; if the Ethernet interface adopts the 40G Ethernet protocol, the number of corresponding lanes can be 2 or 4.
  • the master main control board 401 can convert data to 2 lanes and send data to the second CDR chip 403 through 2 lanes, or master main control board 401 can send data to the second CDR chip 403 through 4 lanes, if the Ethernet interface uses 50G Ethernet protocol, the number of corresponding lanes is 1 or 2.
  • the number of corresponding lanes can be 1 or 2 or 4 or 10, etc., according to the above 25G Ethernet protocol
  • the 40G Ethernet protocol uses an example to understand that the master main control board 401 and the slave main control board 402 send data to the second CDR chip 403 through P lane, P is a positive integer, and the example is not repeated here.
  • the number of lanes corresponds to the number of serdes on the second CDR chip 403, and the lane can correspond to the serdes on the second CDR chip 403.
  • the second CDR chip 403 receives the data on the P lane through the P lane serdes, and the data in each lane in the P lane is sent serially Yes
  • the P road serdes respectively converts the serial data of each lane in the P road lane into parallel data.
  • any serial data in the P road is demultiplexed by the serdes. Multi-bit channels.
  • the second CDR chip 403 After the second CDR chip 403 receives P data streams, it needs to use a clock to process the P data streams in the P physical channels. For example, the second CDR chip 403 is used to process the P data streams to ensure the processed data stream. Time synchronization of P data stream.
  • the Ethernet protocol includes two lanes.
  • the master main control board 401 converts the data stream into two data streams transmitted on the lane, and each data stream includes an AM and a data block group. Each data block in the data stream is obtained by performing physical layer coding on the Ethernet frame stream, and AM is periodically inserted after the physical layer coding on the Ethernet frame stream.
  • the physical layer coding can be 64bit/66bit coding.
  • the first Ethernet physical encoding sublayer 4034 decodes the received data streams in the two lanes sent by the master main control board 401, and then aligns the AM in the two lanes.
  • the second Ethernet physical encoding sublayer 4035 After decoding the received data in the two lanes sent by the slave main control board 402, align the AM in the two lanes. In order to explain the problem clearly, the two lanes sent by the master main control board 401 are called here.
  • the two lanes sent by the slave main control board 402 are called the third lane and the fourth lane.
  • the AM of the first lane and the second lane are aligned, and the AM of the third lane and the fourth lane are also aligned, but As shown in Figure 5, the AM words of the first lane and the second lane and the third lane are not necessarily aligned. In other words, the AM words of the data streams sent by the master main control board 401 and the slave main control board 402 are not It must be aligned.
  • the second CDR chip 403 deletes all the AM of the first lane, the second lane, the third lane, and the fourth lane through the AM deletion module 4039.
  • the third Ethernet physical encoding The sub-layer 4060 re-encodes the physical layer of the first lane, the second lane, the third lane and the fourth lane, and inserts AM periodically, thereby ensuring the first lane, the second lane, the third lane and the fourth lane
  • the AM is aligned.
  • the fourth Ethernet physical encoding sublayer 4070 aligns the AM in the data stream, and then deletes the AM.
  • the fifth Ethernet physical coding sublayer 4036 reinserts the AM into the data stream according to a certain period.
  • the second CDR chip 403 adopts the AM deletion and re-insertion technology.
  • the AM is re-inserted in the third Ethernet physical encoding sublayer 4060, which can ensure that the Ethernet physical encoding sublayer of the peer device will not be The phenomenon of service interruption occurs, so that the switching operation of the local device is not perceived. But this also brings other problems. Because AM is re-inserted in the third Ethernet physical coding sublayer 4060, it is impossible to ensure that the AM position of the data stream sent by the main control board (the main control board and the standby main control board) is maintained.
  • the third Ethernet physical coding sublayer 4060 re-physicalizes the first lane, the second lane, or the second Ethernet physical coding sublayer 4035 re-physicalizes the third lane and the fourth lane.
  • Layer coding and periodically insert AM.
  • the AM position may be different from the original AM positions of the first lane, the second lane, the third lane, and the fourth lane.
  • the data stream passes through the second CDR chip 403 and introduces delay jitter. This delay jitter has little effect on ordinary forwarding services, but has a great impact on the accuracy of 1588.
  • the re-inserted AM is 1280 unit interval (UI) time shift.
  • the main control board completes 1588 stamping and line delay compensation. The smaller the jitter of the data stream on the interface board, the higher the 1588 accuracy of the device.
  • this application provides a data processing device to reduce delay jitter, improve 1588 processing accuracy, and ensure high-precision 1588 system specifications.
  • 1588 is also called Institute of Electrical and Electronics Engineers 1588 (institute of electrical and electronics engineers 1588, IEEE 1588), which is a time synchronization protocol.
  • the current mainstream time synchronization technical solutions also include network time protocol (network time protocol, NTP), synchronous Ethernet, GPS, etc., but these time synchronization solutions have obvious shortcomings compared to IEEE 1588, for example, based on NTP technology IEEE1588 can further improve the synchronization accuracy.
  • FIG. 6 is a schematic structural diagram of a data processing device provided by this application.
  • a data processing device may include: a first main control board 601, a second main control board 602, and an interface board 603, a first main control board 601, and a second main control board 601;
  • the main control board 602 is coupled with the interface board 603 respectively.
  • the first main control board 601 includes a network processor 6011 and a media access controller 6012.
  • the media access controller 6012 includes a processing module 6013.
  • the second main control board includes a network processor 6021 and a media access controller 6022.
  • the media access controller 6022 includes a processing module 6023, where the network processor 6011 and the network processor 6021 can be understood with reference to the network processors described in FIGS. 2 to 4.
  • the interface board 603 includes a third CDR chip 6031, and may also include other components, which are not specifically limited in the embodiment of the present application.
  • the interface board 603 may also include an optical module (optical mpdel) 6032 for photoelectric signals. Conversion.
  • the first main control board 601 is configured to send first data to the interface board 603.
  • the second main control board 602 is configured to send second data to the interface board 603.
  • the first main control board 601 and the second main control board 602 are mutually active and standby main control boards, and the first data and the second data are mutually backup data.
  • the main control board and the interface board 603 work together.
  • the main main control board is abnormal, the main-standby switchover is triggered, and the service is taken over by the standby main control board.
  • the data processing equipment completes the service switching from the main main control board to the standby main control board.
  • the interface board 603 determines the main If the main control board is abnormal, the interface board 603 no longer sends messages to or receives messages from the main main control board, but sends messages to the standby main control board or from the standby main control board. Receive the message.
  • the interface board 603 is used to determine the deviation between the first data and the second data (hereinafter referred to as the first deviation).
  • the first deviation refers to the phase offset difference between the first Ethernet protocol word of the first data and the first Ethernet protocol word of the second data, and the first deviation may be a bit level.
  • the first deviation refers to the phase difference between the AM word in the first data and the AM value in the second data. Due to factors such as differences in the propagation speed of each channel in the medium, the data transmission multi-channel may not be aligned.
  • the interface board 603 receives the first data and the second data, the AM word in the first data and the AM included in the second data Words are generally not aligned.
  • the interface board aligns the AM words of all lanes corresponding to the first data after receiving the first data, and after receiving the second data, the interface board aligns the AM words of all lanes corresponding to the second data. But at this time, the AM words of the first data and the second data are generally not aligned. There are multiple implementation ways of determining the deviation between the first data and the second data, which will be specifically described below in conjunction with FIG. 7.
  • the interface board 603 is also used to send the first deviation to the standby main control board.
  • the first main control board 601 is the standby main control board, and the first main control board 601 is also used to compensate the data sent next time according to the first deviation, where the next data refers to the first main control board 601 receives the most recently sent data after the first deviation (hereinafter referred to as the third data).
  • the first main control board may determine to delay sending the third data according to the first deviation, or the first main control board may determine to send the third data in advance according to the first deviation.
  • the network processor in the first main control board may perform deviation compensation for the third data according to the first deviation, because the network processor in the first main control board is coupled with the sending module in the first main control board, Therefore, the first main control board sending data to the outside can be understood as the network processor in the first main control board directly or indirectly sending data to the outside. It should be noted that it is almost impossible for the first main control board to completely eliminate the first deviation, and the cost and power consumption will increase accordingly. Therefore, in this solution, the first main control board only needs to control the accuracy within the preset range Within.
  • the first main control board 601 is also used to send third data to the interface board 603.
  • the second main control board 602 is also used to send fourth data to the interface board 603, and the third data and the fourth data are mutually backup data.
  • the standby main control board compensates for the sent data according to the first skew, which does not affect the data transmission of the main control board and does not affect the normal operation of services.
  • the interface board 603 is also used to perform deviation compensation for the received third data and fourth data.
  • the interface board 603 determines the first deviation based on the first data and the second data, and the first main control board has performed the first deviation compensation for the data sent next time, that is, the third data based on the first deviation.
  • the deviation between the third data and the fourth data (hereinafter referred to as the second deviation) is within the preset range, such as 100UI.
  • the interface board can minimize or eliminate the deviation between the third data and the fourth data through the deviation compensation circuit.
  • the deviation compensation single circuit in this embodiment can be implemented in any manner, for example, any deviation compensation circuit that can realize the function of the deviation compensation module.
  • the existing deviation compensation circuit is a well-known technology, so it will not be repeated here. It should be noted that if the first interface board 601 does not compensate for the deviation between the third data and the fourth data to the preset range, and only relies on the interface board 603 to compensate for the deviation between the third data and the fourth data, comparison is required Large cache data causes an increase in cost and power consumption. This solution cleverly uses the cooperation of the interface board 603 and the main control board to achieve strict alignment of the data sent by the first main control board and the second main control board through two offset compensations.
  • the downstream transmission direction of the interface board 603 can track the data flow of the main control board to align the output data with the input data.
  • the data flow of the first main control board 601 has been
  • the data flow of the second main control board 602 is aligned, so after switching, the data flow sent by the interface board 603 can still be consistent with the data flow of the second main control board 602.
  • the interface board receives the data stream on the line side, because there is only one data source, that is, the data stream received by the interface board 603 is from the same transmitter, and the interface board 603 can track the input data stream to make the upstream direction.
  • the delay jitter of the message passing through the interface board 603 is close to zero.
  • the second CDR chip 403 uses AM deletion and re-insertion technology, although it can be guaranteed that the main-standby switchover occurs At this time, the peer device will not experience service interruption, but it will cause delay and jitter when the data stream passes through the second CDR chip.
  • the blocks are the first data block and the second data block.
  • the second CDR chip 403 After the second CDR chip 403 receives the first lane, it deletes the first AM and reinserts the second AM.
  • the positions of the second AM and the first AM are usually It is not the same.
  • the interface board only tracks one of the data streams. For example, only the AM in the main control board can be tracked to output data (the interface board sends to the opposite end).
  • the AM word of the input data (the interface board receives the data sent by the main control board) is aligned with the AM word.
  • the main control board is sent, the data flow from the first main control board and the second main control board is processed in advance because of this solution. Therefore, only tracking the AM in the data stream sent by the master main control board after the switch can prevent the data stream from shifting after passing through the interface board, and no delay jitter is introduced.
  • the upstream and downstream data streams do not shift after passing through the interface board 603, so that the delay jitter in the upstream and downstream directions of the message passing through the third CDR chip 6031 is close to 0, and the downstream direction means that the data flow is controlled by the master.
  • the upstream direction refers to the direction of data flow from the interface board to the line side, and the line side is the fiber side.
  • the data processing device provided by the embodiment of the application is described above.
  • the data processing device may be an interface board.
  • the data processing device may also be a CDR chip or a data processing circuit.
  • the following shows a third CDR chip 6031 Schematic.
  • FIG. 7 is a schematic structural diagram of a data processing device provided by this application.
  • a data processing device provided by an embodiment of this application may include:
  • the first transceiver module 7031 is used to receive the first data sent by the first main control board 701 in the downlink direction.
  • the first transceiver module 7031 may include P channels, and P is a positive integer, where the number of P can be 1, 2, or 4, etc.
  • the embodiment of the present application does not limit the number of P, and can be implemented according to actual needs. set up.
  • the first transceiver module 7031 can be regarded as the first communication interface of the third CDR chip.
  • the first transceiver module can be regarded as a serdes circuit.
  • the second transceiver module 7032 when in the downlink direction, is used to receive the second data sent by the second main control board 702.
  • the second transceiver module 7032 may include Q channels, where Q is a positive integer, where P and Q can be equal or Not equal, and the embodiment of the present application does not limit this.
  • the second transceiver module 7032 can be regarded as the second communication interface of the third CDR chip.
  • the second transceiver module can be regarded as a serdes circuit.
  • the first main control board 701 and the second main control board 702 are mutually active and standby main control boards, that is, when the first main control board 701 is the active main control board, the second main control board 702 is the standby main control board.
  • the first main control board 701 is the standby main control board.
  • the main main control board and the third CDR chip 703 work together.
  • the main main control board is abnormal, the main-standby switchover is triggered, and the service is taken over by the standby main control board.
  • the data processing equipment completes the service switching from the main main control board to the standby main control board.
  • the third CDR chip 703 determines If the main main control board is abnormal, the third CDR chip 703 no longer sends messages to the main main control board or no longer receives messages from the main main control board, but sends messages or slaves to the standby main control board.
  • the standby main control board receives the message.
  • the third transceiver module 7070 is used to send data to the line side, or it can also be said to send data to the peer device.
  • the third transceiver module 7070 can be regarded as the third communication interface of the third CDR chip, such as the third transceiver module It can be regarded as a serdes circuit.
  • the fourth transceiver module 7080 is used to receive data from the line side, or it can be said to receive data sent by the peer device.
  • the fourth transceiver module 7080 can be regarded as the fourth communication interface of the third CDR chip, such as the fourth transceiver
  • the module can be regarded as a serdes circuit.
  • the deviation measurement module 7033 which is coupled to the first transceiver module and the second transceiver module, is used to determine the difference between the first data sent by the first main control board 701 and the second data sent by the second main control board 702 Deviation, the first deviation refers to the phase offset difference between the first Ethernet protocol word of the first data and the first Ethernet protocol word of the second data, and the first deviation may be a bit level.
  • the deviation between the data sent by the first main control board 701 and the data sent by the second main control board 702 is simply referred to as the first deviation.
  • the first transceiver module 7031 receives data sent by the first main control board through the P channel, hereinafter referred to as the first data
  • the second transceiver module 7032 receives the second main control board through the Q channel
  • the data sent by the board is hereinafter referred to as the second data for short
  • the first data and the second data are mutually backup data.
  • P and Q are both positive integers
  • the arrival time of the last channel in the P channel is T1
  • the arrival time of the last channel in the Q channel is T2.
  • the deviation measurement module 7033 is based on the difference between T1 and T2 and the third CDR chip
  • the interface rate determines the deviation between the data sent by the first main control board 701 and the data sent by the second main control board 702 to determine the first deviation, and the measurement accuracy reaches the bit level.
  • the first transceiver module 7031 receives the first data through the P channel
  • the second transceiver module 7032 receives the second data through the Q channel.
  • Both P and Q are positive integers.
  • Each channel includes the alignment mark AM
  • each channel in the Q channel includes AM
  • T1 is the arrival time of AM in the last channel in the P channel
  • T2 is the arrival time of AM in the last channel in the Q channel
  • deviation The measurement module 7033 determines the deviation between the data sent by the first main control board 701 and the data sent by the second main control board 702 according to the difference between T1 and T2 and the interface rate of the third CDR chip.
  • the first transceiver module receives the first data through the P channel
  • the second transceiver module receives the second data through the Q channel.
  • P and Q are both positive integers, and a buffer module may also be included. It is not shown in, it is used to buffer the P-channel and Q-channel when the data of the first channel is received.
  • the accumulated buffer of the P-channel is the first buffer
  • the buffer accumulated by the Q channel is the second buffer deviation.
  • the third CDR chip determines the deviation between the data sent by the first main control board 701 and the data sent by the second main control board 702 according to the difference between the first buffer and the second buffer.
  • the third CDR chip may send the first deviation to the first main control board 701 through the first transceiver module 7031. Or send the first deviation to the first main control board 701 through a feedback module (not shown in the figure).
  • the processing module 70121 in the first main control board can adjust the data to be sent next time according to the received deviation.
  • the first main control board can receive the first deviation according to the first transceiver module, or the first main control board can obtain the The module (not shown in the figure) obtains the first deviation.
  • the first main control board can obtain the first deviation from the third CDR chip through software calling.
  • the processing module 70121 in the first main control board can adjust the data to be sent next time according to the received deviation.
  • the processing module can be integrated in the media access controller of the first main control board. It should be noted that the first main control board is not shown in Figure 7 one by one.
  • the control board and the second main control board also include other devices, such as a network processor and a media access controller that may also be included.
  • PMA physical medium attachment
  • the first transceiver module 7031 is also configured to receive the third data adjusted according to the deviation sent by the first main control board.
  • the first main control board 701 compensates the data sent next time according to the first deviation.
  • the next data here refers to the last data sent after the first main control board 701 receives the first deviation (hereinafter referred to as the third data) ).
  • the first main control board may determine to delay sending the third data according to the first deviation, or the first main control board may determine to send the third data in advance according to the first deviation. It should be noted that it is almost impossible for the first main control board to completely eliminate the first deviation, and the cost and power consumption will increase accordingly. Therefore, in this solution, the first main control board only needs to control the accuracy within the preset range Within.
  • the second transceiver module 7032 is also configured to receive fourth data sent by the second main control board, and the third data and the fourth data are mutually backup data.
  • the sixth Ethernet physical encoding sublayer 7037 used to decode the received third data sent by the first main control board 701 and the fourth data sent by the second main control board 702, the sixth Ethernet physical encoding sublayer 7037 Including deviation compensation module 70371.
  • the deviation measurement module 7033 determines the first deviation based on the first data and the second data.
  • the first main control board has already performed deviation compensation for the data sent next time, that is, the third data based on the first deviation, so that The deviation between the third data and the fourth data (hereinafter referred to as the second deviation) is within a preset range, such as 100UI. At this time, there is still a part of the deviation that has not been eliminated, that is, the difference between the first deviation and the second deviation.
  • the interface board can perform deviation compensation processing on the decoded third data and fourth data through the deviation compensation module 70371.
  • the deviation compensation module 70371 can complete the AM words sent by the first main control board and the second main control board.
  • the deviation compensation module 70371 is used to minimize or eliminate the time difference between the third data and the fourth data.
  • the deviation compensation module in this embodiment can be implemented in any manner, for example, any deviation compensation circuit that can realize the function of the deviation compensation module.
  • the existing deviation compensation circuit is a well-known technology, so it will not be repeated here.
  • the first interface board 701 does not compensate the deviation between the third data and the fourth data to the preset range, and only relies on the deviation compensation module 70371 to perform deviation compensation on the third data and the fourth data, you need Larger cache data increases cost and power consumption.
  • This solution cleverly realizes the strict alignment of data sent by the first main control board and the second main control board through the cooperation of the deviation compensation module 70371 and the main control board.
  • the eighth Ethernet physical coding sublayer 7050 encodes the data.
  • the eighth Ethernet physical coding sublayer 7050 is also used to track the third data when sending the active/standby switch, that is, when the downlink transmission direction is , Track the data flow of the main control board, specifically, it can track the AM in the data flow of the main control board. Since the deviation compensation module has performed deviation compensation for the data of the first main control board and the data of the second main control board, the data flow of the standby main control board has been aligned with the data flow of the main main control board, that is, the first main control board The data flow of the control board has been aligned with the data flow of the second main control board.
  • the AM word sent by the first main control board has been aligned with the AM word sent by the second main control board, so the electronic switch 7039 determines the master/backup switch Later, the eighth Ethernet physical encoding sublayer 7050 only tracks the data in the main control board, such as tracking the AM word in the third data mentioned in the embodiment of this application, to ensure that the output data and the input data are Aligned, that is, the AM word sent by the third CDR chip 703 can still be consistent with the AM word of the first main control board, and the third data is sent to the peer device through the third transceiver module.
  • the upstream and downstream data streams do not shift after passing through the third CDR chip 703.
  • the following row direction is taken as an example to illustrate this technical effect.
  • the second CDR chip 403 adopts AM deletion and re-insertion technology. Although it can ensure that the peer device will not experience service interruption when the main-standby switch occurs, it will cause delay and jitter when the data stream passes through the second CDR chip. For example, suppose that the data blocks before and after the first AM in the first lane sent by the master main control board 401 are the first data block and the second data block respectively. Since the second CDR chip 403 receives the first lane, it will Delete the first AM and re-insert the second AM. The positions of the second AM and the first AM are usually different.
  • the interface board only tracks one of the data streams. For example, it only tracks the AM in the active main control board. When sending the active/standby switch, the interface board will The data flow of the control board and the second main control board are aligned. At this time, only the AM in the data flow sent by the master main control board after the switch is tracked so that the data flow does not shift after passing through the interface board, and no delay is introduced. Time jitter.
  • the above description process is the process in which the first main control board is triggered and the standby main control board is switched to the active main control board. If the second main control board is switched from the standby main control board to the active main control board again, It can be understood with reference to the above process.
  • the deviation compensation module 70381 included in the seventh Ethernet physical coding sublayer 7038 performs the compensation for the first main control board and the second main control board.
  • the data sent by the board is strictly aligned, and will not be repeated here. The above describes the processing process of data in the downstream direction.
  • the ninth Ethernet physical encoding sublayer 7060 decodes the data sent by the peer device received by the fourth transceiver module 7080.
  • It may also include a deviation compensation module 70611, which is used to deskew multiple lane data received from the peer device.
  • the tracking module tracks the decoded data, and the tenth Ethernet physical encoding sublayer 7040 encodes the data and sends it to the main control board.
  • the third CDR chip 703 realizes the function of dual data transmission/selective transmission. Since there is only one data source, the tracking module can track the input data flow so that the message can pass through the third CDR chip 703.
  • the uplink delay jitter is close to zero.

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Abstract

一种数据处理的设备，包括：第一收发模块（7031），用于接收第一主控板（701）发送的第一数据。第二收发模块（7032），用于接收第二主控板（702）发送的第二数据。偏差测量模块（7033），用于确定第一数据和第二数据之间的第一偏差。反馈模块，用于向第二主控板（702）发送第一偏差，第一偏差用于第一主控板（701）对第三数据进行第一次偏差补偿。第一收发模块（7031），还用于接收第一数据之后，接收第一主控板（701）发送的第三数据。第二收发模块（7032），还用于接收第二主控板（702）发送的第四数据，第四数据和第三数据互为备份数据。偏差补偿模块（70371），用于根据第四数据对第三数据进行第二次偏差补偿。所述设备使得主备切换时对端业务不中断，且降低延时抖动。

Description

一种数据处理的设备以及系统 技术领域
本申请涉及通信领域，尤其涉及一种数据处理的设备。
背景技术
盒式设备或者框式设备中，一般都采用双主控板以及接口板的硬件方案。两块主控板用于保证业务的互为备份，保证业务的正常传输过程。正常情况下，主用主控板和接口板配合工作。当主用主控板发生异常时触发主备倒换，业务由备用主控板接管，同时接口板完成业务从主用主控板到备用主控板的切换，比如，当接口板确定主用主控板发生异常，则接口板不再向原主用主控板发送报文或者从原主用主控板接收报文，而是向原备用主控板发送报文或者从原备用主控板接收报文。
但是，由于主用主控板和备用主控板对业务的处理时延无法保持一致，业务在设备内传输时，主用主控板和备用主控板所产生的传输时延可能是非对称的。当业务对时延对称性要求较高时，主备倒换时产生的非对称传输时延可能引入延时抖动，或者导致业务中断。因此，如何降低主备倒换时引入的延时抖动、不中断业务进行主备倒换亟待解决。
发明内容
本申请提供一种数据处理的设备，降低了主用主控板切换为备用主控板时引入的延时抖动，同时解决主备主控板倒换时，对端设备业务中断的问题。
为达到上述目的，本申请实施例提供如下技术方案：
本申请第一方面提供一种数据处理的设备，该数据处理的设备可以是时钟数据恢复(clock data recovery，CDR)或者是接口板，可以包括：第一收发模块，用于接收第一主控板发送的第一数据。第二收发模块，用于接收第二主控板发送的第二数据，第一主控板和第二主控板互为主备主控板，第一数据和第二数据互为备份数据。偏差测量模块，用于确定第一数据和第二数据之间的第一偏差。数据处理的设备还可以包括反馈模块，用于向第一主控板和第二主控板中的备用主控板发送第一偏差，第一偏差用于第一主控板对第三数据进行第一次偏差补偿，反馈模块与第一收发模块相同或者不同。第一收发模块，还用于接收第一数据之后，接收第一主控板发送的第三数据。第二收发模块，还用于接收第二主控板发送的第四数据，第四数据和第三数据互为备份数据。偏差补偿模块，用于根据第四数据对第三数据进行第二次偏差补偿。由第一方面可知，备用主控板根据第一偏差对第三数据进行第一次偏差补偿，数据处理的设备再对第三数据进行第二次偏差补偿，经过两次偏差补偿后，第三数据和第四数据可以基本对齐，当备用主控板被触发切换为主用主控板时，降低延时抖动。
可选地，结合上述第一方面，在第一种可能的实现方式中，还可以包括：跟踪模块，用于当第一主控板由备用主控板切换为主用主控板时，跟踪经过第二次偏差补偿后的第三数据。该数据处理的设备还可以包括第四收发模块，用于向对端设备发送第三数据。由第一方面第一种可能的实现方式可知，跟踪模块只需要跟踪一路数据就可以使对端设备的业务不中断，比如第一主控板未切换为主用主控板之前，跟踪模块跟踪第二主控板的数据，即跟踪模块跟踪主用主控板的数据，当第一主控板由备用主控板被切换为主用主控板时， 由于第三数据和第四数据已经对齐，跟踪模块只需要跟踪第三数据，就可以保障对端业务不中断。
可选地，结合上述第一方面或第一方面第一种可能的实现方式，在第二种可能的实现方式中，第一收发模块可以包括P路通道，第二收发模块可以包括Q路通道，P和Q均为正整数，第一收发模块，具体用于通过P路通道接收第一数据。第二收发模块，具体用于通过Q路通道接收第二数据。偏差测量模块，具体用于根据T1和T2的差值以及设备的接口速率确定第一偏差，T1为P路通道中最后一路通道的到达时刻，T2为Q路通道中最后一路通道的到达时刻。第一方面第二种可能的实现方式提供了一种确定第一偏差的具体方式。
可选地，结合上述第一方面第二种可能的实现方式，在第三种可能的实现方式中，P路通道中的每一路通道可以包括对齐标记AM，Q路通道中的每一路通道可以包括AM，T1为P路通道中最后一路通道中AM的到达时刻，T2为Q路通道中最后一路通道中AM的到达时刻。第一方面第三种可能的实现方式提供了一种具体的确定第一偏差的方式，数据处理的设备可以根据第一数据和第二数据中的AM字之间的相位偏移确定第一偏差。
可选地，结合上述第一方面或第一方面第一种可能的实现方式，在第四种可能的实现方式中，第一收发模块可以包括P路通道，第二收发模块可以包括Q路通道，P和Q均为正整数，第一收发模块，具体用于通过P路通道接收第一数据。第二收发模块，具体用于通过Q路通道接收第二数据。该设备还可以包括：缓存模块，用于接收到第一路通道的数据时，对P路通道和Q路通道进行缓存。偏差测量模块，具体用于根据第一缓存和第二缓存确定确定第一skew，第一缓存为P路通道中的最后一路通道到达时，P路通道累积的缓存，第二缓存为Q路通道中的最后一路通道到达时，Q路通道累积的缓存。第一方面第四种可能的实现方式提供了一种具体的确定第一偏差的方式。
本申请第二方面提供一种数据处理的设备，可以包括：第一收发模块，用于向接口板发送第一数据。获取模块，用于获取第一偏差，第一偏差是接口板确定的第一数据和第二数据之间的偏差，第二数据是第二主控板发送的数据，第二数据与第一数据互为备份数据，第二主控板与第一主控板互为主备主控板，获取模块与第一收发模块相同或者不同。处理模块，用于根据第二收发模块获取的第一偏差对第三数据进行偏差补偿。第一收发模块，还用于发送偏差补偿后的第三数据。
本申请第三方面提供一种数据处理的系统，该数据处理的系统包括接口板和主控板，其中，接口板为第一方面或第一方面任意一种可能的实现方式中所描述的数据处理的设备，主控板为第二方面所描述的数据处理的设备。
本申请第四方面提供一种数据处理的系统，该数据处理的系统包括包括时钟数据恢复CDR芯片和网络处理器NP芯片，其中，CDR芯片为第一方面或第一方面任意一种可能的实现方式中所描述的数据处理的设备，NP芯片为第二方面所描述的数据处理的设备。
本申请第五方面提供一种分组传送网(packet transport network，PTN)设备，该PTN设备包括接口板和主控板，其中，接口板为第一方面或第一方面任意一种可能的实现方式中所描述的数据处理的设备，主控板为第二方面所描述的数据处理的设备。
本申请第六方面提供一种分组传送网(packet transport network，PTN)设备，该PTN设备包括时钟数据恢复CDR芯片和网络处理器NP芯片，其中，CDR芯片为第一方面或第一 方面任意一种可能的实现方式中所描述的数据处理的设备，NP芯片为第二方面所描述的数据处理的设备。
本申请实施例提供了一种数据处理的设备，接口板确定主用主控板和备用主控板发送的数据之间的偏差，备用主控板可以根据该偏差调整发送的数据，接口板再对主用主控板和备用主控板发送的数据进行偏差补偿，当发生主备切换时，由于备用主控板发送的数据流已经在接口板内部和主用主控板发送的数据对齐了，因此主备切换后，降低了主备切换引入的延时抖动，同时解决主备主控板倒换时，对端业务中断的问题。
附图说明
图1为本申请实施例提供的一种应用场景示意图；
图2为一种数据处理设备的结构示意图；
图3为包含第一CDR芯片的数据处理设备的结构示意图；
图4为包含第二CDR芯片的数据处理设备的结构示意图；
图5为第二CDR芯片引起的延时抖动示意图；
图6为本申请提供的一种数据处理设备的结构示意图；
图7为本申请提供的另一种数据处理设备的结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”、“第三”、“第四”等(如果存在)是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的实施例能够以除了在这里图示或描述的内容以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
在说明书及权利要求当中使用了某些词汇来指称特定的组件。本领域技术人员应可理解，硬件制造商可能会用不同的名词来称呼同一个组件。本说明书及后权利要求并不以名称的差异来作为区分组件的方式，而是以组件在功能上的差异来作为区分的准则。在说明书及权利要求当中所提及的包含或者包括是为一开放式的用语，故应解释成包含但不限定于或者包括但不限于。此外，耦接或者耦合在此是包含任何直接及间接的电气连接手段，因此，若文中描述第一设备耦接于一第二设备，或者第一设备与第二设备耦合，则代表该第一设备可直接电气连接于该第二设备，或者通过其他设备或连接手段间接地电气连接至该第二设备。
图1为本发明实施例提供的一种应用场景示意图。如图1中所示，设备101称为本端设备，设备102称为对端设备，或者设备102称为本端设备，设备101称为对端设备。其中，设备101和设备102是盒式设备或者框式设备，比如设备101和设备102可以是路由器、交换机、光传送网(optical transport network，OTN)设备、分组传送网(packet transport network，PTN)设备、波分复用(wavelength-division multiplexing，WDM) 设备。本申请实施例不限定本端设备和对端设备的类型要相同，比如本端设备可以是PTN设备或者路由器，对端设备可以是路由器或者交换机。
目前，上述提到的盒式设备或者框式设备中，一般都采用双主控板以及接口板的硬件方案。主控板可以包括1个媒体访问控制器(media access controller，MAC)和1个网络处理器。该主控板也可以包括多个MAC和多个网络处理器。主控板中的MAC可以与主控板中的网络处理器耦合。主控板可以通过现场可编程门阵列(field programmable gate array，FPGA)或者专用集成电路(application specific integrated circuit，ASIC)实现。如图2所示，为一种数据处理设备的结构示意图，其中包括两块主控板，分别为主用主控板201和备用主控板202，以下将主用主控板称为master主控板，将备用主控板称为slave主控板。两块主控板用于保证业务的互为备份。为了简化说明，图2中的主用主控板201仅示出了1个MAC2012和1个网络处理器2011，图2中的备用主控板202仅示出了1个MAC2022和1个网络处理器2021，其中MAC2012和网络处理器2011耦合，MAC2022和网络处理器2021耦合。需要说明的是，1个MAC和1个网络处理器不代表数量的限制，只是为了说明的方便，以下关于数字的描述都不是对数量的限制，只是为了方便说明，以下不再重复赘述。主控板上的网络处理器实现报文的转发调度等业务处理，例如网络处理器2011和网络处理器2021可以为网络处理器(network processor，NP)，或者报文处理器(packet processor，PP)，或者报文引擎(packet engine，PE)，或者专用集成电路(application specific integrated circuit，ASIC)，该网络处理器2011和网络处理器2021可以为可编程的，或者不可编程的，本发明实施例对此不作限定，需要说明的是，在一些场景中也将主控板称为转发处理板，正如上文提到的，本领域技术人员应可理解，硬件制造商可能会用不同的名词来称呼同一个组件。本说明书及后权利要求并不以名称的差异来作为区分组件的方式，而是以组件在功能上的差异来作为区分的准则。接口板203上采用带电子开关(MUX/DEMUX)功能的时钟数据恢复(clock data recovery，CDR)芯片2031，其中电子开关包括复用器电路(MUX)和解复用电路(DEMUX)，实现线路侧到系统侧的选发或者双发功能，以及系统侧到线路侧的选收功能，来支持master主控板201和slave主控板202之间的倒换。在本申请实施例中，线路侧是指接口板靠近外部接口的一侧，换句话说，线路侧是指接口板靠近外部光纤的一侧，系统侧是指接口板靠近内部接口的一侧，换句话说，系统侧是指接口板靠近网络处理器的一侧，选发功能是指CDR芯片2031选择将报文发送给master主控板201或者slave主控板202，双发功能是使指CDR芯片2031将报文发送给master主控板201和slave主控板202，选收功能是指CDR芯片2031选择将master主控板201或者slave主控板202的报文发送至线路侧。此外，主控板和接口板还可以包括其他的组成部分，本申请实施例对此并不做具体的限定，比如接口板203还可以包括光模块(optical mpdel)2032，用于光电信号的转换。
正常情况下，master主控板201和接口板配合工作。当master主控板201发生异常时触发主备倒换，业务由slave主控板202接管，同时接口板CDR芯片完成业务从master主控板201到slave主控板202的切换，比如，当CDR芯片确定master主控板201发生异常，则CDR芯片不再向master主控板201发送报文或者不再从master主控板201接收报文，而是向slave主控板202发送报文或者从slave主控板202接收报文。
针对不同的场景，CDR芯片的结构可能不同，如图3所示为包含第一CDR芯片303的设备的结构示意图，如图3所示的第一CDR芯片303包括串行器/解串行器(SERializer/DESerializer，serdes)和MUX/DEMUX等电路，为了说明的方便，图3中仅示出了串行器/解串行器3031、串行器/解串行器3032、串行器/解串行器3035、串行器/解串行器3036和MUX/DEMUX3033以及MUX/DEMUX3034，MUX/DEMUX3033以及MUX/DEMUX3034电路也被称为电子开关。serdes电路可以将并行的物理编码转化为串行的物理编码后发送，或者将串行的物理编码转化为并行的物理编码接收，这样数据就能够以串行的形式传输，传输速率较高，为了区分，本申请把可以将并行的物理编码转化为串行的物理编码后发送的serdes电路称为串行器(英文又称serdes Tx)，把可以将串行的物理编码转化为并行的物理编码的serdes电路称为解串行器(英文又称serdes Rx)。此种第一CDR芯片303不支持以太网物理编码子层(ethnet physical coding sublayer，ETH PCS)，当master主控板301发生异常，触发主备倒换时，第一CDR芯片303一般在任意一个时刻将业务切换到slave主控板302，但是由于master和slave两路主控板对业务的处理时延无法保持一致，master和slave两路主控板的ETH协议字也很难实现对齐。第一CDR芯片303从master和slave两路主控板接收到的网络侧协议字以及报文都不是同步的，由此导致当设备向外发送报文时，设备接口侧报文的网络侧协议字会发生移位，从而造成对端设备的出现业务中断的现象。主用主控板301以及备用主控板302可以参照图2对应的主用主控板201以及备用主控板202进行理解，网络处理器3011和网络处理器3021可以参照图2对应的网络处理器2011和网络处理器2021进行理解，媒体访问控制器3012和媒体访问控制器3022可以参照图2对应的媒体访问控制器2012和媒体访问控制器2022此处不再重复赘述。
如图4所示为包含第二CDR芯片403的设备的结构示意图，如图4所示的第二CDR芯片403除了包括serdes和MUX/DEMUX电路，还包括以太网物理编码子层等。第二CDR芯片403支持以太网物理编码子层，以太网物理编码子层可以解析ETH协议的8bit/10bit编码或者64bit/66bit编码的同步头、对齐标记(alignment marker，AM)等。采用该技术方案，当发生主备倒换时，可以实现系统侧到线路侧方向协议层无损切换。下面结合图4和图5对此进行具体的说明。master主控板401和slave主控板402分别通过以太网接口向第二CDR芯片403发送数据，不同的以太网接口对应不同的通道(lane)的数量，可以将lane的数量理解为并行链路发送数据的链路数。比如若以太网接口采用25G以太网协议，对应的lane的数量可以为1，以master主控板401向第二CDR芯片403发送数据为例，即master主控板401可以通过1条lane向第二CDR芯片403发送数据；若以太网接口采用40G以太网协议，对应的lane的数量可以为2或者4，以master主控板401向第二CDR芯片403发送数据为例，即master主控板401可以将数据转化到2条lane上，通过2条lane向第二CDR芯片403发送数据，或者master主控板401可以通过4条lane向第二CDR芯片403发送数据，若以太网接口采用50G以太网协议，对应的lane的数量为1或者2，若以太网接口采用100G以太网协议，对应的lane的数量可以为1或者2或者4或者10，等等，可以按照上述对25G以太网协议以及40G以太网协议举的例子理解master主控板401和slave主控板402通过P路lane向第二CDR芯片403发送数据，P为正整数，这里不再重复举例 说明。
lane的数量与第二CDR芯片403上的serdes的数量对应，P路lane可以对应第二CDR芯片403上的P路serdes。举例说明，master主控板401通过P路lane发送数据后，第二CDR芯片403通过P路serdes接收该P路lane上的数据，P路lane中的每一路lane中的数据都是串行发送的，经过P路serdes后，P路serdes分别将P路lane中的每一路lane的串行数据转换为并行数据，举例说明，P路中的任意一路串行数据通过serdes被解复用成多个多比特通道。第二CDR芯片403接收到P路数据后，需要使用一个时钟对这P路物理通道中的P路数据流进行处理，例如使用第二CDR芯片403对P路数据流进行处理，保证处理后的P路数据流的时间同步。为了简化说明，以下针对以太网协议对应包括2个lane的情况进行举例说明。master主控板401将数据流转换为2个lane上传输的数据流，每个数据流均包括AM以及数据块组。数据流中的每个数据块是对以太网帧流进行物理层编码得到的，在对以太网帧流进行物理层编码后会周期性的插入AM。物理层编码可以是64bit/66bit编码。当物理层编码是64bit/66bit编码时，1个数据块中包含的比特的数量是66。66个比特的数据块中，2个比特可以是同步头，当然任意比特可以是同步头，这里的2个比特并不代表数目的限制，只是为了举例说明。第一以太网物理编码子层4034将接收到的master主控板401发送的两个lane中的数据流解码后，对两个lane中的AM进行对齐处理，第二以太网物理编码子层4035将接收到的slave主控板402发送的两个lane中的数据解码后，对两个lane中的AM进行对齐处理，为了清楚的说明问题，这里将master主控板401发送的两个lane称为第一lane和第二lane，将slave主控板402发送的两个lane称为第三lane和第四lane。经过第一以太网物理编码子层4034和第二以太网物理编码子层4035的处理，第一lane和第二lane的AM是对齐的，第三lane和第四lane的AM也是对齐的，但是如图5所示，第一lane和第二lane与第三lane的AM不一定是对齐的，换句话说，master主控板401和slave主控板402两路发送的数据流的AM字不一定是对齐的。所以经过电子开关4037后，第二CDR芯片403通过AM删除模块4039将第一lane、第二lane、第三lane和第四lane的AM全部删除，经过缓存器4050之后，第三以太网物理编码子层4060对第一lane、第二lane、第三lane和第四lane重新进行物理层编码，并周期性的插入AM，由此保证第一lane、第二lane、第三lane和第四lane的AM是对齐的。对于第二CDR芯片403接收线路侧发送的数据流的过程，数据流经过解串行器之后，第四以太网物理编码子层4070对数据流中的AM进行对齐处理后，再将AM进行删除，经过缓存器4038后，由第五以太网物理编码子层4036对数据流按照一定的周期重新插入AM。
第二CDR芯片403采用了AM删除和重新插入的技术，在第三以太网物理编码子层4060中重新插入AM，可以保证在发生主备倒换时，对端设备以太网物理编码子层不会出现业务中断的现象，从而感知不到本端设备的倒换操作。但是这也带来了其他问题，由于第三以太网物理编码子层4060中重新插入AM，无法保证和主控板(主用主控板和备用主控板)发送的数据流的AM位置保持一致，如图5所示，举例说明，第三以太网物理编码子层4060对第一lane、第二lane、或者第二以太网物理编码子层4035对第三lane和第四lane重新进行物理层编码，并周期性的插入AM，AM的位置可能与第一lane、第二lane、第三lane以及第四lane原来的AM的位置都是不同的。从而导致数据流经过第二CDR芯片403后引 入延时抖动。该延时抖动对普通转发业务影响不大，但是对1588的精度却有很大影响，比如当以太网接口为100GE，重新插入的AM为1280单元间隔(unit interval，UI)时移，第二CDR因接收和发送AM字的位置存在偏移，导致单向的延时抖动约为12.8纳秒(1280/100Gbps＝12.8ns)。当盒式设备或者框式设备，由主控板完成1588打戳以及线路时延补偿等处理。数据流在接口板上的抖动越小，设备的1588精度越高。
为了解决上述技术问题，本申请提供了一种数据处理的设备，减小延时抖动，提高1588处理精度，确保高精度1588系统规格。在介绍本申请提供的技术方案之前，先对1588进行简要的介绍。1588也称为电气电子工程师学会1588(institute of electrical and electronics engineers 1588，IEEE 1588)，是一种时间同步协议。目前主流的时间同步技术方案还包括网络时间协议(network time protocol，NTP)，同步以太网，GPS等，但是这些时间同步方案相比于IEEE 1588都有明显的缺点，比如在NTP技术的基础上，IEEE1588可以进一步提高同步精度，在同样基于以太网、适用于分布式网络中，相比于NTP技术毫秒级的同步精度，1588 V2协议的精度提高到了纳秒级别，但是需要说明的是，本申请提供的技术方案以IEEE 1588为例进行说明，本领域技术人员在本申请提供的技术方案的基础上，可以当然的将本申请提供的技术方案应用到其他时间同步技术方案上。
图6为本申请提供的一种数据处理设备的结构示意图。
如图6所示，为本申请实施例提供的一种数据处理的设备，可以包括：第一主控板601，第二主控板602以及接口板603，第一主控板601以及第二主控板602分别与接口板603耦合。其中第一主控板601包括网络处理器6011以及媒体访问控制器6012，媒体访问控制器6012包括处理模块6013，第二主控板包括网络处理器6021以及媒体访问控制器6022，媒体访问控制器6022包括处理模块6023，其中网络处理器6011和网络处理器6021可以参考图2至图4中描述的网络处理器进行理解。接口板603包括第三CDR芯片6031，还可以包括其他的组成部分，本申请实施例对此并不做具体的限定，比如接口板603还可以包括光模块(optical mpdel)6032，用于光电信号的转换。
第一主控板601，用于向接口板603发送第一数据。
第二主控板602，用于向接口板603发送第二数据。第一主控板601和第二主控板602互为主备主控板，第一数据和第二数据互为备份数据。通常情况下，主用主控板和接口板603配合工作。当主用主控板发生异常时触发主备倒换，业务由备用主控板接管，同时数据处理设备完成业务从主用主控板到备用主控板的切换，比如，当接口板603确定主用主控板发生异常，则接口板603不再向主用主控板发送报文或者不再从主用主控板接收报文，而是向备用主控板发送报文或者从备用主控板接收报文。
接口板603，用于确定第一数据和第二数据之间的偏差(以下简称为第一偏差)。第一偏差是指第一数据的第一以太网协议字和第二数据的第一以太网协议字之间的相位偏移差值，该第一偏差可以是比特级别。比如该第一以太网协议字是AM字时，第一偏差是指第一数据中的AM字和第二数据中的AM值之间的相位差值。因为各个通道在媒介中传播速度差异等因素，可能造成数据传输多通道不对齐，接口板603接收到第一数据和第二数据时，第一数据中的AM字和第二数据中包括的AM字一般不是对齐的。举例说明，假设接口板接收到第一数据后，对第一数据对应的所有lane的AM字进行对齐，接口板接收到第二数据 后，对第二数据对应的所有lane的AM字进行对齐。但此时，第一数据和第二数据的AM字一般不是对齐的。关于如何确定第一数据和第二数据之间的偏差有多种实现方式，将在下面结合图7进行具体的说明。
接口板603，还用于将第一偏差向备用主控板发送。
假设此时，第一主控板601为备用主控板，第一主控板601还用于根据第一偏差对下一次发送的数据进行补偿，这里的下一次数据是指第一主控板601接收到第一偏差后最近一次发送的数据(以下简称为第三数据)。举例说明，第一主控板根据第一偏差可能确定要延迟发送第三数据，或者第一主控板根据第一偏差可能确定要提前发送第三数据。具体的，可以是第一主控板中的网络处理器根据第一偏差对第三数据进行偏差补偿，因为第一主控板中的网络处理器与第一主控板中的发送模块耦合，所以第一主控板对外发送数据可以理解为第一主控板中的网络处理器直接或者间接对外发送数据。需要说明的是，第一主控板完全消除第一偏差几乎是不可能的，成本和功耗会随之增加，所以在本方案中，第一主控板只需要将精度控制在预设范围内即可。
第一主控板601，还用于向接口板603发送第三数据。
第二主控板602，还用于向接口板603发送第四数据，第三数据和第四数据互为备份数据。在本申请实施例中，由备用主控板根据第一skew对发送的数据进行补偿，不影响主控板的数据传输，不影响业务的正常进行。
接口板603，还用于对接收到的第三数据和第四数据进行偏差补偿。
上述已经介绍了接口板603根据第一数据和第二数据确定了第一偏差，第一主控板根据该第一偏差已经将下一次发送的数据，即第三数据进行了第一次偏差补偿，使得第三数据和第四数据之间的偏差(以下简称为第二偏差)在预设范围内，比如100UI，此时还有一部分偏差还没有消除，即第一偏差和第二偏差的差值，此时接口板可以通过偏差补偿电路来最小化或消除第三数据和第四数据之间的偏差。本实施例中的偏差补偿单路可以任何方式实施之，比如任何一个可以实现偏差补偿模块的功能的偏差补偿电路都可以。现有偏差补偿电路为公知技术，故在此不予赘述。需要说明的是，如果第一接口板601不将第三数据和第四数据之间的偏差补偿到预设范围，只依靠接口板603对第三数据和第四数据进行偏差补偿，则需要比较大的缓存数据，造成成本和功耗的增加。本方案巧妙的通过接口板603和主控板的配合，通过两次偏差补偿实现第一主控板和第二主控板发送数据的严格对齐。
在此基础上，接口板603下行发送方向跟踪主用主控板的数据流即可使输出的数据与输入的数据对齐，当发生主备倒换，由于第一主控板601的数据流已经和第二主控板602的数据流对齐了，因此倒换后，接口板603发送的数据流依然能和第二主控板602的数据流保持一致。接口板接收线路侧的数据流时，由于数据源头只有一份，即接口板603接收到的数据流是来自于同一个发送器的，接口板603跟踪输入的数据流即可使上行方向时，报文经过接口板603的延时抖动接近0。下面以下行方向为例，对这一技术效果进行说明，上文中介绍第二CDR芯片403时提到，第二CDR芯片403采用了AM删除和重新插入的技术，虽然可以保证在发生主备倒换时，对端设备不会出现业务中断的现象，但是导致数据流经过第二CDR芯片时会引起延时抖动，举例说明，假设master主控板401发送的第一lane 中第一AM的前后数据块分别是第一数据块和第二数据块，由于第二CDR芯片403接收到第一lane后，会将第一AM删除，重新插入第二AM，第二AM与第一AM的位置通常是不相同的，假设第二AM插入的位置是第二数据块之后，那么插入第二AM后的第二数据块在第一lane中的位置和删除第一AM前的第二数据块在第一lane中的位置是不同的，但是插入第二AM不会对第一数据块在第一lane中的位置产生很大影响，可见，由于AM的删除和插入使得数据流进入第二CDR芯片后引入延时抖动。而本申请提供的技术方案，因为不需要删除AM和插入AM，接口板只跟踪其中一路数据流，比如只跟踪主用主控板中的AM，就可以实现输出数据(接口板向对端发送的数据)和输入数据(接口板接收主控板发送的数据)的AM字对齐，当发送主备倒换时，由于本方案预先将来自第一主控板和第二主控板的数据流进行了对齐，所以只跟踪切换后的主用主控板发送的数据流中的AM就可以使数据流经过接口板后不发生位移，不引入延时抖动。
通过以上方案，可以实现上下行数据流经过接口板603后都不发生位移，从而使报文经过第三CDR芯片6031的上下行方向的延时抖动都接近0，下行方向是指数据流由主控板到接口板的方向，上行方向是指数据流由接口板到线路侧的方向，线路侧为光纤侧。
以上对本申请实施例提供的数据处理设备进行了说明，该数据处理设备可以是接口板，当然该数据处理设备还可以是CDR芯片或者是数据处理电路，下面给出一种第三CDR芯片6031的结构示意图。
图7为本申请提供的一种数据处理设备的结构示意图。
如图7所示，为本申请实施例提供的一种数据处理的设备，可以包括：
第一收发模块7031，当下行方向时，用于接收第一主控板701发送的第一数据。第一收发模块7031可以包括P路通道，P为正整数，其中P的数量可以为1个、2个或4个等等，本申请实施例并不对P的数量进行限制，可以按照实际需求进行设定。可以将第一收发模块7031视为第三CDR芯片的第一通信接口，比如该第一收发模块可以视为是serdes电路。
第二收发模块7032，当下行方向时，用于接收第二主控板702发送的第二数据，第二收发模块7032可以包括Q路通道，Q为正整数，其中P和Q可以相等也可以不相等，本申请实施例对此不进行限定。可以将该第二收发模块7032视为第三CDR芯片的第二通信接口，比如该第二收发模块可以视为是serdes电路。第一主控板701和第二主控板702互为主备主控板，也就是说，第一主控板701为主用主控板时，则第二主控板702为备用主控板，第二主控板702为主用主控板时，则第一主控板701为备用主控板。通常情况下，主用主控板和第三CDR芯片703配合工作。当主用主控板发生异常时触发主备倒换，业务由备用主控板接管，同时数据处理设备完成业务从主用主控板到备用主控板的切换，比如，当第三CDR芯片703确定主用主控板发生异常，则第三CDR芯片703不再向主用主控板发送报文或者不再从主用主控板接收报文，而是向备用主控板发送报文或者从备用主控板接收报文。
第三收发模块7070，用于向线路侧发送数据，或者也可以说向对端设备发送数据，可以将第三收发模块7070视为第三CDR芯片的第三通信接口，比如该第三收发模块可以视为是serdes电路。
第四收发模块7080，用于从线路侧接收数据，或者也可以说接收对端设备发送的数据，可以将第四收发模块7080视为第三CDR芯片的第四通信接口，比如该第四收发模块可以视为是serdes电路。
偏差测量模块7033，偏差测量模块7033与第一收发模块和第二收发模块耦合，用于确定第一主控板701发送的第一数据以及第二主控板702发送的第二数据之间的偏差，第一偏差是指第一数据的第一以太网协议字和第二数据的第一以太网协议字之间的相位偏移差值，该第一偏差可以是比特级别。以下将第一主控板701发送的数据以及第二主控板702发送的数据之间的偏差简称为第一偏差。
在一个具体的实施方式中，假设第一收发模块7031通过P路通道接收第一主控板发送的数据，以下简称为第一数据，第二收发模块7032通过Q路通道接收第二主控板板发送的数据，以下简称为第二数据，第一数据和第二数据互为备份数据。P和Q均为正整数，P路通道中最后一路通道的到达时刻为T1，Q路通道中最后一路通道的到达时刻为T2，偏差测量模块7033根据T1和T2的差值以及第三CDR芯片的接口速率确定第一主控板701发送的数据以及第二主控板702发送的数据之间的偏差确定第一偏差，测量精度达到bit级别。
在一个具体的实施方式中，假设第一收发模块7031通过P路通道接收第一数据，第二收发模块7032通过Q路通道接收第二数据，P和Q均为正整数，P路通道中的每一路通道包括对齐标记AM，Q路通道中的每一路通道包括AM，T1为P路通道中最后一路通道中AM的到达时刻，T2为Q路通道中最后一路通道中AM的到达时刻，偏差测量模块7033根据T1和T2的差值以及第三CDR芯片的接口速率确定第一主控板701发送的数据以及第二主控板702发送的数据之间的偏差。
在一个具体的实施方式中，假设第一收发模块通过P路通道接收第一数据，第二收发模块通过Q路通道接收第二数据，P和Q均为正整数，还可以包括缓存模块，图中并未示出，用于接收到第一路通道的数据时，对P路通道和Q路通道进行缓存，P路通道中的最后一路通道到达时，P路通道累积的缓存为第一缓存，Q路通道中的最后一路通道到达时，Q路通道累积的缓存为第二缓存偏差。第三CDR芯片根据第一缓存和第二缓存的差值确定第一主控板701发送的数据以及第二主控板702发送的数据之间的偏差。
第三CDR芯片可以通过第一收发模块7031将第一偏差向第一主控板701发送。或者通过反馈模块(图中未示出)将第一偏差向第一主控板701发送。第一主控板中的处理模块70121可以根据接收到的偏差调整下一次发送的数据，其中，第一主控板可以根据第一收发模块接收第一偏差，或者第一主控板可以通过获取模块(图中并未示出)获取第一偏差，比如，第一主控板可以通过软件调用的方式从第三CDR芯片获取第一偏差。第一主控板中的处理模块70121可以根据接收到的偏差调整下一次发送的数据，比如可以根据接收到的偏差，对发送的数据中包括的AM字进行时延补偿，重新调整AM字发送的位置，调整精度控制在较小范围内(如100UI)，其中处理模块可以集成在第一主控板的媒体访问控制器中，需要说明的是，图7中没有一一示出第一主控板和第二主控板还包括的其他器件，比如还可以包括的网络处理器以及媒体访问控制器。
在一个具体的实施方式中，还可以包括物理媒介连接子层(physical medium attachment，PMA)7034和7035，PMA对数据总线位宽和时钟域进行转换处理，经过PMA 后，将接口的时钟转换到内部统一的时钟进行处理，有利于提升处理精度。
第一收发模块7031，还用于接收第一主控板发送的根据偏差调整后的第三数据。第一主控板701根据第一偏差对下一次发送的数据进行补偿，这里的下一次数据是指第一主控板701接收到第一偏差后最近一次发送的数据(以下简称为第三数据)。举例说明，第一主控板根据第一偏差可能确定要延迟发送第三数据，或者第一主控板根据第一偏差可能确定要提前发送第三数据。需要说明的是，第一主控板完全消除第一偏差几乎是不可能的，成本和功耗会随之增加，所以在本方案中，第一主控板只需要将精度控制在预设范围内即可。
第二收发模块7032，还用于接收第二主控板发送的第四数据，第三数据和第四数据互为备份数据。
第六以太网物理编码子层7037，用于对接收到的第一主控板701发送的第三数据以及第二主控板702发送的第四数据解码，第六以太网物理编码子层7037包括偏差补偿模块70371。上述已经介绍了偏差测量模块7033根据第一数据和第二数据确定了第一偏差，第一主控板根据该第一偏差已经将下一次发送的数据，即第三数据进行了偏差补偿，使得第三数据和第四数据之间的偏差(以下简称为第二偏差)在预设范围内，比如100UI，此时还有一部分偏差还没有消除，即第一偏差和第二偏差的差值，此时接口板可以通过偏差补偿模块70371将解码后的第三数据和第四数据进行偏差补偿处理，比如通过偏差补偿模块70371完成第一主控板和第二主控板发送的AM字实现严格对齐，采用偏差补偿模块70371来最小化或消除第三数据和第四数据之间的时间差。本实施例中的偏差补偿模块可以任何方式实施之，比如任何一个可以实现偏差补偿模块的功能的偏差补偿电路都可以。现有偏差补偿电路为公知技术，故在此不予赘述。需要说明的是，如果第一接口板701不将第三数据和第四数据之间的偏差补偿到预设范围，只依靠偏差补偿模块70371对第三数据和第四数据进行偏差补偿，则需要比较大的缓存数据，造成成本和功耗的增加。本方案巧妙的通过偏差补偿模块70371和主控板的配合，实现第一主控板和第二主控板发送数据的严格对齐。在此基础上，第八以太网物理编码子层7050对数据进行编码，此外，第八以太网物理编码子层7050还用于在发送主备倒换时，跟踪第三数据，即下行发送方向时，跟踪主用主控板的数据流，具体的，可以跟踪主用主控板的数据流中的AM。由于偏差补偿模块已经对第一主控板的数据和第二主控板的数据进行了偏差补偿，备用主控板的数据流已经和主用主控板的数据流对齐了，即第一主控板的数据流已经和第二主控板的数据流对齐了，比如第一主控板发送的AM字已经和第二主控板发送的AM字对齐了，因此电子开关7039确定主备倒换后，第八以太网物理编码子层7050只跟踪主用主控板中的数据，比如跟踪本申请实施例提到的第三数据中的AM字，就可以保证输出的数据和输入的数据是对齐的，也就是说第三CDR芯片703发送的AM字依然能和第一主控板的AM字保持一致，第三数据通过第三收发模块发送到对端设备。通过以上方案，可以实现上下行数据流经过第三CDR芯片703后都不发生位移，下面以下行方向为例，对这一技术效果进行说明，上文中介绍第二CDR芯片403时提到，第二CDR芯片403采用了AM删除和重新插入的技术，虽然可以保证在发生主备倒换时，对端设备不会出现业务中断的现象，但是导致数据流经过第二CDR芯片时会引起延时抖动，举例说明，假设master主控板401发送的第一lane中第一AM的 前后数据块分别是第一数据块和第二数据块，由于第二CDR芯片403接收到第一lane后，会将第一AM删除，重新插入第二AM，第二AM与第一AM的位置通常是不相同的，假设第二AM插入的位置是第二数据块之后，那么插入第二AM后的第二数据块在第一lane中的位置和删除第一AM前的第二数据块在第一lane中的位置是不同的，但是插入第二AM不会对第一数据块在第一lane中的位置产生影响，可见，由于AM的删除和插入使得数据流进入第二CDR芯片后引入延时抖动。而本方案中，不需要删除AM和插入AM，接口板只跟踪其中一路数据流，比如只跟踪主用主控板中的AM，当发送主备倒换时，由于本方案预先将来自第一主控板和第二主控板的数据流进行了对齐，此时只跟踪切换后的主用主控板发送的数据流中的AM就可以使数据流经过接口板后不发生位移，不引入延时抖动。
需要说明的，上述说明过程是第一主控板被触发由备用主控板切换为主用主控板的过程，若第二主控板由备用主控板再次切换为主用主控板，可以参照上述过程进行理解，比如，当第二主控板为备用主控板时，由第七以太网物理编码子层7038中包括的偏差补偿模块70381对第一主控板和第二主控板发送的数据实现严格对齐，此处不再重复赘述。以上对下行方向数据的处理过程进行了介绍，当上行方向时，第九以太网物理编码子层7060对第四收发模块7080接收到的对端设备发送的数据进行解码，在一个具体的实施方式中，还可以包括偏差补偿模块70611，用于对接收到的来自对端设备的多条lane的数据进行deskew。跟踪模块跟踪解码后的数据，第十以太网物理编码子层7040对数据进行编码后向主用主控板发送。上行(线路侧到系统侧)方向，第三CDR芯片703实现数据双发/选发功能，由于数据源头只有一份，跟踪模块跟踪输入的数据流即可使报文经过第三CDR芯片703的上行延时抖动接近0。
以上对本申请实施例所提供的数据处理的设备以及系统进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的一般技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (10)

  1. 一种数据处理的设备，其特征在于，包括：
    第一收发模块，用于接收第一主控板发送的第一数据；
    第二收发模块，用于接收第二主控板发送的第二数据，所述第一数据和所述第二数据互为备份数据；
    偏差测量模块，用于确定所述第一数据和所述第二数据之间的第一偏差；
    所述数据处理的设备还包括反馈模块，用于向所述第一主控板和所述第二主控板中的备用主控板发送所述第一偏差，所述第一偏差用于所述第一主控板对第三数据进行第一次偏差补偿，所述反馈模块与所述第一收发模块相同或者不同；
    所述第一收发模块，还用于接收所述第一数据之后，接收所述第一主控板发送的第三数据；
    所述第二收发模块，还用于接收所述第二主控板发送的第四数据，所述第四数据和所述第三数据互为备份数据；
    偏差补偿模块，用于根据所述第四数据对所述第三数据进行第二次偏差补偿。
  2. 根据权利要求1所述的设备，其特征在于，还包括：
    跟踪模块，用于当所述第一主控板由备用主控板切换为主用主控板时，跟踪经过第二次偏差补偿后的所述第三数据；
    第四收发模块，用于向对端设备发送所述第三数据。
  3. 根据权利要求1或2所述的设备，其特征在于，所述第一收发模块包括P路通道，所述第二收发模块包括Q路通道，所述P和所述Q均为正整数，
    所述第一收发模块，具体用于通过所述P路通道接收所述第一数据；
    所述第二收发模块，具体用于通过所述Q路通道接收所述第二数据；
    所述偏差测量模块，具体用于根据T1和T2的差值以及所述设备的接口速率确定所述第一偏差，所述T1为所述P路通道中最后一路通道的到达时刻，所述T2为所述Q路通道中最后一路通道的到达时刻。
  4. 根据权利要求3所述的设备，其特征在于，所述P路通道中的每一路通道包括对齐标记AM，所述Q路通道中的每一路通道包括AM，所述T1为所述P路通道中最后一路通道中AM的到达时刻，所述T2为所述Q路通道中最后一路通道中AM的到达时刻。
  5. 根据权利要求1或2所述的设备，其特征在于，所述第一收发模块包括P路通道，所述第二收发模块包括Q路通道，所述P和所述Q均为正整数，
    所述第一收发模块，具体用于通过所述P路通道接收所述第一数据；
    所述第二收发模块，具体用于通过所述Q路通道接收所述第二数据；
    所述设备还包括：
    缓存模块，用于接收到第一路通道的数据时，对所述P路通道和所述Q路通道进行缓存；
    所述偏差测量模块，具体用于根据第一缓存和第二缓存确定确定所述第一skew，所述第一缓存为所述P路通道中的最后一路通道到达时，所述P路通道累积的缓存，所述第二缓存为所述Q路通道中的最后一路通道到达时，所述Q路通道累积的缓存。
  6. 一种数据处理的设备，其特征在于，包括：
    第一收发模块，用于向接口板发送第一数据；
    获取模块，用于获取第一偏差，所述第一偏差是所述接口板确定的所述第一数据和第二数据之间的偏差，所述第二数据是第二主控板发送的数据，所述第二数据与所述第一数据互为备份数据，所述第二主控板与所述第一主控板互为主备主控板，所述第二收发模块与所述第一收发模块相同或者不同；
    处理模块，用于根据所述第二收发模块获取的所述第一偏差对第三数据进行偏差补偿；
    所述第一收发模块，还用于发送偏差补偿后的所述第三数据。
  7. 一种数据处理的系统，其特征在于，所述数据处理的系统包括接口板和主控板，其中，
    所述接口板为权利要求1至5中任一项所描述的数据处理的设备；
    所述主控板为权利要求6所描述的数据处理的设备。
  8. 一种数据处理的系统，其特征在于，所述数据处理的系统包括时钟数据恢复CDR芯片和网络处理器NP芯片，其中，
    所述CDR芯片为权利要求1至5中任一项所描述的数据处理的设备；
    所述NP芯片为权利要求6所描述的数据处理的设备。
  9. 一种分组传送网PTN设备，其特征在于，所述PTN设备包括接口板和主控板，其中，
    所述接口板为权利要求1至5中任一项所描述的数据处理的设备；
    所述主控板为权利要求6所描述的数据处理的设备。
  10. 一种分组传送网PTN设备，其特征在于，所述PTN设备时钟数据恢复CDR芯片和网络处理器NP芯片，其中，
    所述CDR芯片为权利要求1至5中任一项所描述的数据处理的设备；
    所述NP芯片为权利要求6所描述的数据处理的设备。
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