WO2021030941A1

WO2021030941A1 - Ssb design for v2x communication

Info

Publication number: WO2021030941A1
Application number: PCT/CN2019/101010
Authority: WO
Inventors: Zhixun Tang; Tao Chen; Min LEI
Original assignee: Mediatek Singapore Pte. Ltd.
Priority date: 2019-08-16
Filing date: 2019-08-16
Publication date: 2021-02-25

Abstract

For NR V2X sidelink synchronization signal block (SL-SSB), SL-SSB can be composed of 2 PSS, 2 SSS and 8 PBCH symbols. 8 symbols of PBCH is formed by repetition of 4 symbols of PBCH so that they can be decoded separately or combined for decoding with joint or independent channel estimation. PBCH DMRS pattern could be sparse in both frequency and time domain with different cyclic shift. V2X UE could also utilize the SSS sequence for combing channel estimation. Some information bits can also inherently be carried by PBCH DMRS sequence. Moreover, the GP length in the end of the slot could be changed based on different configuration.

Description

SSB DESIGN FOR V2X COMMUNICATION

FIELD OF INVENTION

This disclosure relates generally to wireless communications, and, more particularly, to methods and apparatus for the synchronization signal block of V2X sidelink communications.

BACKGROUND OF THE INVENTION

In 5G new radio, V2X sidelink (SL) communication may be supported by the unicast, groupcast and broadcast communications. However, there are several issues to be addressed, e.g., how to synchronize between each other and obtain the timing information.

SUMMARY OF THE INVENTION

For NR V2X sidelink synchronization signal block (SL-SSB) , SL-SSB can be composed of 2 PSS, 2 SSS and 8 PBCH symbols. 8 symbols of PBCH is formed by repetition of 4 symbols of PBCH so that they can be decoded separately or combined for decoding with joint or independent channel estimation. PBCH DMRS pattern could be sparse in both frequency and time domain with different cyclic shift. V2X UE could also utilize the SSS sequence for combing channel estimation. Some information bits can also inherently be carried by PBCH DMRS sequence. Moreover, the GP length in the end of the slot could be changed based on different (pre-) configuration in V2X SL-SSB.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:

FIG. 1 shows an example of SL-SSB composition.

FIG. 2 shows the PBCH DMRS pattern S-SSB.

FIG. 3 shows an exemplary block diagram of a UE (a.k.a device) according to an embodiment of the disclosure.

DETAILED DESCRIPTION

Certain terms are used throughout the description and following claims to refer to particular components. As one skilled in the art will appreciate, manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to ... " . Also, the term "couple" is intended to mean either an indirect or direct electrical connection. Accordingly, if one device is coupled to another device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections. The making and using of the embodiments of the disclosure are discussed in detail below. It should be appreciated, however, that the embodiments can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative, and do not limit the scope of the disclosure. Some variations of the embodiments are described. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements.

The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. Note that the 3GPP specifications described herein are used to teach the spirit of the invention, and the invention is not limited thereto.

FIG. 1 shows an example of SL-SSB composition. One S-SSB with 11 RBs by 14 symbols is composed of 1 AGC symbol (e.g., based on SSS) , 2 PSS symbols, 2 SSS symbol, 4-8 PBCH symbols by repetition of 2 PBCH channels and 1-5 symbols for guard period (GP) in order.

PSS and SSS are generated with length-127 m-sequence located in the center 127 subcarriers of the 11 RBs (RB, 1RB=12 subcarriers) . PSS and SSS can be used to carry sidelink synchronization ID (SLSS ID) which is used to identify the sync source type and priority. For example, the UEs synced to eNB and gNB can be assigned with different set of sequences for PSS/SSS generation corresponding to the different SLSS ID. Upon the detection of SLSS ID of the directly synced UE, the other UEs synced to the synced UEs (a.k.a indirectly synced UE) can know the sync source of the synced UE (or original sync source) for proper synchronization prioritization if needed. The unused resource in the frequency domain in PSS/SSS symbols can be set as zero power. Another option is SSS symbols could be before PSS symbols. The S-SSB by 14 symbols is composed of 1 AGC symbol (e.g., based on SSS) , 2 SSS symbols, 2 PSS symbol, 4-8 PBCH symbols by repetition of 2 PBCH channels and 1-5 symbols for guard period (GP) in order.

For repetition of PBCH symbols, there are several options as shown in Figure 1. Option 1 is to transmit PBCH-1 with 4 symbols and then repeat it in PBCH-2 with another 4 symbols (i.e., channel by channel repetition) . The GP length is one symbol in option 1. In option 2, the GP symbols are three. The PBCH symbols will be 6 with two repetition PBCH pattern. Three PBCH symbols is occupied in each PBCH pattern. In option 3, the GP symbols are five. The PBCH symbols will be 4 with two repetition PBCH pattern. Two PBCH symbols is occupied in each PBCH pattern.

There are several methods to configure the flexible S-SSB PBCH and GP length. One option is to pre-configure the S-SSB pattern in sidelink UE’s memory. Another option is to configure the S-SSB pattern by network configuration, such as RRC reconfiguration, SCI indication etc.

PBCH symbol will be transmitted over 11 RBs including sparse PBCH-DMRS in frequency and time domain.

As shown in Figure 2. In option 1, the PBCH DMRS are occupied in symbol #1, #3, #5, #7 which numbered from the first PBCH symbol as symbol #0 in time domain. The DMRS signals are occupied resource element (RE) #0, #4, #8 which numbered from the first PBCH RE as #0 in frequency domain. PBCH could use its DMRS to obtain the channel estimation. Another optional is to combing SSS sequence to obtain the better channel estimation.

In option 2, the PBCH DMRS are occupied in symbol #1, #3, #5, #7 which numbered from the first PBCH symbol as symbol #0 in time domain. The DMRS signals are occupied resource element (RE) #1, #5, #9 which numbered from the first PBCH RE as #0 in frequency domain. The DMRS has a shift in frequency to obtain the better performance in PBCH edge.

In option 3, the PBCH DMRS are occupied in symbol #1, #3, #5, #7 which numbered from the first PBCH symbol as symbol #0 in time domain. The DMRS signals are occupied resource element (RE) #2, #6, #10 which numbered from the first PBCH RE as #0 in frequency domain.

In option 4, the PBCH DMRS are occupied in symbol #0, #2, #4, #6 which numbered from the first PBCH symbol as symbol #0 in time domain. The DMRS signals are occupied resource element (RE) #0, #4, #8 which numbered from the first PBCH RE as #0 in frequency domain.

In option 5, the PBCH DMRS are occupied in symbol #0, #2, #4, #6 which numbered from the first PBCH symbol as symbol #0 in time domain. The DMRS signals are occupied resource element (RE) #1, #5, #9 which numbered from the first PBCH RE as #0 in frequency domain.

In option 6, the PBCH DMRS are occupied in symbol #0, #2, #4, #6 which numbered from the first PBCH symbol as symbol #0 in time domain. The DMRS signals are occupied resource element (RE) #2, #6, #10 which numbered from the first PBCH RE as #0 in frequency domain.

The DMRS pattern location can be fixed in the time/frequency domain without any cyclic shift to ensure the better channel estimation or cancellation in case of collision with other PBCHs from other UEs.

Which DMRS pattern or S-SSB structure is used can be indicated by network configuration or pre-configuration at UE.

Some information bits can be carried in DMRS. In option 1, the basic DMRS sequence could be same for these two DMRS patterns. And it could introduce an OVSF sequence {1, 1} and {1, -1} for these two DMRS patterns to indicate the information bit, such as in-Coverage bit for UE whether directly sync. to GNSS/gNB/eNB. The UE don’t had to decode the PSBCH contents but know the in-Coverage indication immediately after channel estimation and DMRS cross-correlation. For example, the information bit could be given by

inCoverage	OVSF
0	{+1, +1}
1	{+1, -1}

In option 2, it could use a longer OVSF sequence, such as 4 bit for these four DMRS patterns in indicate more information bits.

Fig. 3 shows an exemplary block diagram of a UE according to an embodiment of the disclosure. The UE 800 can be configured to implement various embodiments of the disclosure described herein. The UE 800 can include a processor 810, a memory 820, and a radio frequency (RF) module 830 that are coupled together as shown in Fig. 3. In different examples, the UE 800 can be a mobile phone, a tablet computer, a desktop computer, a vehicle carried device, and the like.

The processor 810 can be configured to perform various functions of the UE 800 described above with reference to Figs. 1-2. The processor 810 can include signal processing circuitry to process received or to be transmitted data according to communication protocols specified in, for example, LTE and NR standards. Additionally, the processor 810 may execute program instructions, for example, stored in the memory 820, to perform functions related with different communication protocols. The processor 810 can be implemented with suitable hardware, software, or a combination thereof. For example, the processor 810 can be implemented with application specific integrated circuits (ASIC) , field programmable gate arrays (FPGA) , and the like, that includes circuitry. The circuitry can be configured to perform various functions of the processor 810.

In one example, the memory 820 can store program instructions that, when executed by the processor 810, cause the processor 810 to perform various functions as described herein. The memory 820 can include a read only memory (ROM) , a random access memory (RAM) , a flash memory, a solid state memory, a hard disk drive, and the like.

The RF module 830 can be configured to receive a digital signal from the processor 810 and accordingly transmit a signal to a base station in a wireless communication network via an antenna 840. In addition, the RF module 830 can be configured to receive a wireless signal from a base station and accordingly generate a digital signal which is provided to the processor 810. The RF module 830 can include digital to analog/analog to digital converters (DAC/ADC) , frequency down/up converters, filters, and amplifiers for reception and transmission operations. For example, the RF module 830 can include converter circuits, filter circuits, amplification circuits, and the like, for processing signals on different carriers or bandwidth parts.

The UE 800 can optionally include other components, such as input and output devices, additional CPU or signal processing circuitry, and the like. Accordingly, the UE 800 may be capable of performing other additional functions, such as executing application programs, and processing alternative communication protocols.

The processes and functions described herein can be implemented as a computer program which, when executed by one or more processors, can cause the one or more processors to perform the respective processes and functions. The computer program may be stored or distributed on a suitable medium, such as an optical storage medium or a solid-state medium supplied together with, or as part of, other hardware. The computer program may also be distributed in other forms, such as via the Internet or other wired or wireless telecommunication systems. For example, the computer program can be obtained and loaded into an apparatus, including obtaining the computer program through physical medium or distributed system, including, for example, from a server connected to the Internet.

The computer program may be accessible from a computer-readable medium providing program instructions for use by or in connection with a computer or any instruction execution system. A computer readable medium may include any apparatus that stores, communicates, propagates, or transports the computer program for use by or in connection with an instruction execution system, apparatus, or device. The computer-readable medium can be magnetic, optical, electronic, electromagnetic, infrared, or semiconductor system (or apparatus or device) or a propagation medium. The computer-readable medium may include a computer-readable non-transitory storage medium such as a semiconductor or solid state memory, magnetic tape, a removable computer diskette, a random access memory (RAM) , a read-only memory (ROM) , a magnetic disk and an optical disk, and the like. The computer-readable non-transitory storage medium can include all types of computer readable medium, including magnetic storage medium, optical storage medium, flash medium and solid state storage medium.

While aspects of the present disclosure have been described in conjunction with the specific embodiments thereof that are proposed as examples, alternatives, modifications, and variations to the examples may be made. Accordingly, embodiments as set forth herein are intended to be illustrative and not limiting. There are changes that may be made without departing from the scope of the claims set forth below.

Claims

A method, comprising:

receiving a configuration or pre-configuration for V2X sidelink synchronization signal block; and

performing time/frequency synchronization based on the the corresponding DMRS pattern.
The method of claim 1, wherein a configuration or pre-configuration for V2X sidelink synchronization signal block is SSB composition including PSS/SSS, PBCH and/or the additional front-loaded symbol (s) for AGC tuning and/or the additional symbol (s) for guard period.
The method of claim 1, wherein performing time/frequency synchronization including reception/transmission of PSS/SSS and PBCH.
The method of claim 2, wherein PBCH can be constructed with the same number of REs for data and the DMRS for each PBCH pattern, and wherein two PBCH pattern symbol number is flexiable.
The method of claim 2, wherein the GP symbol number is flexible.
The method of claim 2, wherein the DMRS pattern in PBCH is occupied symbol index #1, #3, #5, #7 in time domain and resource element index #0, #4, #8 in frequency domain.
The method of claim 2, wherein the DMRS pattern in PBCH is occupied symbol index #1, #3, #5, #7 in time domain and resource element index #1, #5, #9 in frequency domain.
The method of claim 2, wherein the DMRS pattern in PBCH is occupied symbol index #1, #3, #5, #7 in time domain and resource element index #2, #6, #10 in frequency domain.
The method of claim 2, wherein the DMRS pattern in PBCH is occupied symbol index #0, #2, #4, #6 in time domain and resource element index #0, #4, #8 in frequency domain.
The method of claim 2, wherein the DMRS pattern in PBCH is occupied symbol index #0, #2, #4, #6 in time domain and resource element index #1, #5, #9 in frequency domain.
The method of claim 2, wherein the DMRS pattern in PBCH is occupied symbol index #0, #2, #4, #6 in time domain and resource element index #2, #6, #10 in frequency domain.
The method of claim 2, wherein the DMRS pattern in PBCH carry some information bits by spreading with the OVSF sequence.