WO2021027354A1

WO2021027354A1 - Set module based on rram memristor unit, and forming method therefor

Info

Publication number: WO2021027354A1
Application number: PCT/CN2020/090988
Authority: WO
Inventors: 李琛; 段杰斌; 郭令仪
Original assignee: 上海集成电路研发中心有限公司
Priority date: 2019-08-09
Filing date: 2020-05-19
Publication date: 2021-02-18
Also published as: CN110619905A

Abstract

A set module based on an RRAM memristor unit, and a forming method therefor. The module comprises: N RRAM memristor units used for storing weight values and a weight generation unit, wherein the N RRAM memristor units comprise M variable RRAM memristor units; each variable RRAM memristor unit comprises an original RRAM memristor where a weight value is not written, a control transistor, an excitation voltage generator and an output end, where N and M are positive integers greater than or equal to two, and M is less than or equal to N; and when the weight generation unit determines a weight value needing to be stored by each variable RRAM memristor unit, the excitation voltage generator generates a voltage corresponding to the weight value, and inputs a fixed weight value into each variable RRAM memristor unit by means of the control transistor, so as to form a whole set of weight value combinations of the N RRAM memristor units.

Description

An integrated module based on RRAM memristor unit and its forming method

cross reference

This application claims the priority of the Chinese patent application with application number 201910742298.6 filed on August 9, 2019. The content of the above application is included here by reference.

Technical field

The present invention relates to the technical field of artificial intelligence chip design, in particular to an assembly module based on RRAM memristor units and a forming method thereof.

technical background

Embedded memory is one of the important components of system-level chips, and it is also the development trend of future memory technology. The architecture of existing embedded memory is mainly based on traditional memory architecture, such as static random access memory (SRAM) or flash memory (Flash). At present, the research of embedded memory based on various new memory architectures has attracted wide attention at home and abroad, including phase change memory (PCRAM), magnetic memory (MRAM) and resistive random access memory (RRAM). Among them, resistive random access memory is due to its simultaneous With the advantages of high speed, low power consumption, non-volatility, high integration and compatibility with CMOS technology, it has always been a research hotspot in the field of new embedded memory.

In recent years, the research on resistive random access memory represented by RRAM has made many breakthroughs. Its device structure has evolved from the initial 2D planar structure to the high-density 3D vertical structure. The cell area has been significantly reduced, and the read and write speed, durability and retention The characteristics and so on have all been significantly improved, and the capacity of the resistive memory chip has also grown from 2Mb to the largest 32Gb. At the same time, many international memory manufacturers have begun to develop embedded resistive random access memory, including Hewlett-Packard, Sony, Micron, Panasonic and Crossbar. In terms of foundry, TSMC, UMC and SMIC have also begun to provide Customers provide specialized resistive random access memory production technology. Among them, Panasonic is the leader in the industrialization of resistive random access memory. In 2013, embedded resistive random access memory was first used in single-chip microcomputer (Single Chip Microcomputer, referred to as MCU) products; in 2016, Panasonic also cooperated with Fujitsu, Launched the first memory product based on the 180nm process with a 4Mb capacity. Recently, Panasonic is developing embedded resistive random access memory on the 40nm process line.

In the application process of the storage-calculation integrated chip, RRAM, as a storage medium with variable weights for matrix operations, not only plays the role of multi-valued weight storage, but also plays a role of storage-calculation integration in matrix network operations. However, RRAM exists as a single device or a single array. In the actual storage-computing chip, the neural network algorithm usually requires various possible RRAM sizes (such as 1024*1024 or 1048*1048 are possible). The current foundry The provided RRAM cannot satisfy such functions. That is to say, the industry needs that the RRAM array scale can be customized according to the algorithm and can be changed according to the depth of the hierarchy; at the same time, the foundry is required to provide a set of RRAM devices with different resistance combinations.

Summary of the invention

In order to achieve the above objective, the present invention aims to provide an RRAM memristor unit-based assembly module and a method for forming the same. To achieve the above objective, the technical solution of the present invention is as follows:

A weight logic library module based on an RRAM memristor; it includes: N RRAM memristor units for storing weight values and a weight generation unit, wherein the N RRAM memristor units include M variable RRAMs Memristor unit; each of the variable RRAM memristor units includes an original RRAM memristor without a written weight value, a control transistor, an excitation voltage generator and an output terminal; wherein, the N and M are A positive integer greater than or equal to 2, and M is less than or equal to N; when the weight generation unit determines the weight value that each variable RRAM memristor unit needs to store, the excitation voltage generator generates a value corresponding to the For the voltage of the weight value, a fixed weight value is input to each of the variable RRAM memristor units through the control transistor to form a complete set of weight value combinations of the N RRAM memristor units.

Preferably, the M is less than N, and the N RRAM memristor units include N-M fixed RRAM memristor units.

Preferably, the weight value in the set of weight value combinations of the N RRAM memristor units is formed in an arithmetic sequence, or a geometric sequence.

Preferably, the number of the weights in the set of weight value combinations of the N RRAM memristor units is at most 256.

Preferably, the number of the weights in the set of weight value combinations of the N RRAM memristor units is 11.

Preferably, the RRAM memristor unit-based assembly module further includes a digital synthesis tool, and the set of weight values of the N RRAM memristor units are combined to form an X*Y underlying basic weight logic matrix. The digital synthesis tool Directly call the X*Y underlying basic weight logic matrix according to user requirements; wherein the value of X*Y is greater than or equal to the N.

Preferably, in order to achieve the above objective, another technical solution of the present invention is as follows:

A method for forming a collective module based on the RRAM memristor unit described above includes:

Step S1: Determine, according to the weight generating unit, a complete set of weight value combinations to be stored in the N RRAM memristor units;

Step S2: Fabricate the N RRAM memristor units, where the M variable RRAM memristor units are original RRAM memristors without storing any weight values;

Step S3: The excitation voltage generator generates a voltage corresponding to the weight value, and inputs a fixed weight value to each variable RRAM memristor unit through the control transistor to form the M RRAM memories The weight value combination of the resistor unit;

Step S4: forming a set of weight value combinations of the N RRAM memristor units.

Preferably, the forming method further includes step S5: the entire set of weight values of the N RRAM memristor units are combined to form an X*Y underlying basic weight logic matrix, and the digital synthesis tool directly calls X*Y according to user needs Basic weight logic matrix

Preferably, the number of the weights in the set of weight value combinations of the N RRAM memristor units is 11, and the N is equal to M, and the step S3 specifically includes the following steps:

Step S31: The excitation voltage generator generates 11 voltage values, where the 11 voltage values are respectively V1, V2, ... V11;

Step S32: Respectively receive the 11 voltage values V1, V2,...V11 through the 11 control transistors to the 11 variable RRAM memristor units to complete the 11 variable RRAM memristor units The input of the fixed weight value, wherein the fixed weight values of the 11 variable RRAM memristor units are respectively Z1, Z2, ... Z11.

Preferably, the step S4 specifically includes the following steps:

Step S41: If the M is less than N, execute step S42, if the M is equal to N, execute step S43;

Step S42: the set of weight value combinations of the N RRAM memristor units is the weight value combination of the M RRAM memristor units plus (N-M) weight value combinations of the fixed RRAM memristor unit;

Step S43: The whole set of weight value combinations of the N RRAM memristor units is the weight value combination of the M RRAM memristor units.

It can be seen from the above technical solutions that the present invention provides an RRAM memristor unit-based assembly module and its forming method, which has the following technical advantages:

① Form a complete set of weight value combinations according to user needs, that is, weight values can be set arbitrarily;

②. Since the weight network has been trained and fixed when the user is using it, the combination of the above set of weight values can directly call the underlying basic weight logic through the digital synthesis tool;

③ The RRAM memristor-based unit has a non-volatile storage function, that is to say, after the weight is made and written, the weight value is permanently retained.

Description of the drawings

Figure 1 is a schematic diagram of a weighted logic library module based on an RRAM memristor in an embodiment of the present invention

Figure 2 is a schematic diagram of a typical RRAM memristor unit in an embodiment of the invention

Figure 3 is a flow chart of the use of the RRAM memristor-based weight logic library module in an embodiment of the present invention

4 is a schematic diagram of the weight logic library of the RRAM memristor unit with 11 weights in an embodiment of the present invention

Figure 5 is a schematic diagram of the process in the application of the present invention to the neural network inference chip embodiment

FIG. 6 is a schematic diagram of an array finally formed by a typical RRAM memristor unit set in an embodiment of the present invention after fabricating and writing weights

Summary of the invention

Hereinafter, the RRAM memristor-based cell set and its formation method of the present invention will be further described in detail through specific embodiments in conjunction with FIGS. 1-6. It should be noted that the drawings all adopt a very simplified form and use imprecise proportions, and are only used to facilitate and clearly achieve the purpose of assisting in describing the embodiments of the present invention.

Please refer to FIG. 1. FIG. 1 is a schematic diagram of a weighted logic library module based on an RRAM memristor in an embodiment of the present invention. As shown in the figure, the RRAM memristor-based weight logic library module includes N RRAM memristor units for storing weight values and a weight generation unit. Among them, N is a positive integer greater than or equal to 2. The N RRAM memristor units include M variable RRAM memristor units, where M is a positive integer greater than or equal to 2, and M is less than or equal to N. That is to say, when M is equal to N, the N RRAM memristor units are variable RRAM memristor units; when M is less than N, the N RRAM memristor units additionally include NM storage weights. Fixed RRAM memristor unit.

In the embodiment of the present invention, each variable RRAM memristor unit includes an original RRAM memristor without a written weight value, a control transistor, an excitation voltage generator and an output terminal. It should be noted that the original RRAM memristor cannot store any value, and the weight value can only be input through subsequent voltage forming.

When the weight generation unit (or the user) determines the weight value that each variable RRAM memristor unit needs to store, the excitation voltage generator generates a voltage corresponding to the weight value, and through the control transistor (used to control the RRAM memory Resistor read and write operations) Input a fixed weight value to each variable RRAM memristor unit to form a complete set of weight value combinations of N RRAM memristor units.

In the embodiment of the present invention, the weight values in the set of weight value combinations of the N RRAM memristor units can be formed in an arithmetic sequence or can be formed in a geometric sequence. In addition, the maximum number of weights in the set of weight value combinations of N RRAM memristor units is usually 256 at most. Preferably, the number of weights in the set of weight value combinations of N RRAM memristor units is 11.

For the sake of simplicity, the following embodiment uses the case where M is equal to N as an example.

Example one

In this embodiment, assuming that N=11, that is, after a set of weight values of N RRAM memristor units are combined, each RRAM memristor unit stores a weight value, and the RRAM memristor-based unit has a non- Volatile storage function, that is, after the weight is created and written, the weight value can be retained.

Please refer to FIG. 2. FIG. 2 is a schematic diagram of a typical RRAM memristor unit in an embodiment of the present invention. As shown in the figure, for each stored RRAM memristor unit (equivalent to a fixed RRAM memristor unit), the digital synthesis tool calls the control transistor to receive the input value, and the input value is calculated together with the weight value to obtain the calculation result.

Please refer to FIG. 3, which is a flowchart of the use of the weight logic library module based on the RRAM memristor in an embodiment of the present invention. The method for forming a collective module based on the RRAM memristor unit of the present invention includes the following steps:

Step S1: Determine a set of weight value combinations to be stored in the N RRAM memristor units according to user requirements.

Please refer to FIG. 4, which is a schematic diagram of a weight logic library of an RRAM memristor unit with 11 types of weights in an embodiment of the present invention. As shown in the figure, the logic library with different weights required by the foundry in advance includes the following devices:

i. An RRAM device with a weight of 1.0 and a control transistor;

ii. RRAM device with a weight of 0.9 and 1 control transistor;

...

x, RRAM device with a weight of 0.1, and 1 control transistor;

xi, RRAM device with a weight of 0.0, and 1 control transistor.

Step S2: Fabricate the N RRAM memristor units, wherein the M variable RRAM memristor units are original RRAM memristors without storing any weight values.

Step S3: The excitation voltage generator generates a voltage corresponding to the weight value, and a fixed weight value is input to each of the variable RRAM memristor units through a control transistor to form the weight value of M RRAM memristor units combination.

In the embodiment of the present invention, the number of the weights in the set of weight value combinations of N RRAM memristor units is 11, and the N is equal to M, and the step S3 specifically includes the following steps:

Step S31: The excitation voltage generator generates 11 voltage values, where the 11 voltage values are respectively V1, V2, ... V11; wherein, the 11 voltage values can be generated by an excitation voltage generator or Generated by multiple excitation voltage generators.

Step S32: Respectively receive the 11 voltage values V1, V2,...V11 through the 11 control transistors to the 11 variable RRAM memristor units to complete the 11 variable RRAM memristor units The input of the fixed weight value, wherein the fixed weight values of the 11 variable RRAM memristor units are respectively Z1, Z2, ... Z11. In this embodiment, Z1, Z2, ... Z11 are 1.0, 0.9, 0.8, 0.7, 0.6, 0.5, 0.4, 0.3, 0.2, 0.1, and 0.0, respectively.

Step S4 specifically includes the following steps (it should be noted that the following examples include not only the case where M is equal to N, but also the case where M is less than N):

Step S41: If the M is less than N, perform step S42, if the M is equal to N, perform step S43;

Step S5: The entire set of weight values of the N RRAM memristor units are combined to form an X*Y bottom-level basic weight logic matrix, and the digital synthesis tool directly calls the X*Y bottom-level basic weight logic matrix according to user requirements.

Example two

Neural Networks (NNs), or Connection Models, are an algorithmic mathematical model that imitates the behavioral characteristics of animal neural networks and performs distributed and parallel information processing. This kind of network relies on the complexity of the system and achieves the purpose of processing information by adjusting the interconnection between a large number of internal nodes.

At present, the three important operational features of neural network chips are as follows:

① Neural network has the characteristics of multi-layer perception and hierarchical convolution operation. The multiplication and addition MAC matrix (Modal Assurance Criterion, modal confidence matrix) has a huge amount of calculation, and the network scale and level need to be dynamically changed with the algorithm;

② When training calculations, the classic ASIC (Application Specific Integrated Circuit) architecture built by general logic gates does not have storage characteristics itself. Because the weights are repeatedly refreshed during training, a large amount of interaction data with the memory unit (Memory) is required;

③. In the inference operation, there are a large number of data operations that are moved. To overcome the bottleneck of bandwidth and storage, multiple cache interfaces (such as LPDDR4) are needed, which wastes a lot of power consumption.

In the embodiment of the present invention, the collective module based on the RRAM memristor unit and the forming method thereof are adopted, so that the above-mentioned problems are well solved. Please refer to FIG. 5, which is a schematic diagram of a process in an embodiment of a neural network inference chip according to the present invention. As shown in the figure, the operational characteristics of AI and neural network chips determine: the multiplication and addition network based on multi-value weights can significantly accelerate the multi-layer perception and hierarchical convolution operation, and the most basic single-value/multi-value multiplication and addition of the network matrix Operators are made into a basic unit library, which can effectively decompose the hierarchical convolutional network operation to the underlying basic weight logic operation. For the inference chip, the weight network has been trained and fixed, and the underlying basic weight logic can be directly called through the digital synthesis tool.

That is to say, for the neural network inference chip, the weight network has been trained and fixed, and a certain layer of neural network needs a specific multiplication and addition matrix to achieve. The multiplication-addition matrix can be decomposed into each monomial. The α, β, γ, δ in the monomial A are the required weights. There are three kinds of weights, α=1, β=0.5, γ=0, and δ is available. The variable weight can be any value of α, β, and γ; the underlying basic weight logic can be directly called by the digital synthesis tool to form the array shown in Figure 6, and the final weight array can be formed through the previous manufacturing process.

The above are only the preferred embodiments of the present invention, and the described embodiments are not used to limit the scope of patent protection of the present invention. Therefore, any equivalent structural changes made using the contents of the description and drawings of the present invention should be included in the same reasoning Within the protection scope of the appended claims of the present invention.

6. The RRAM memristor unit-based assembly module according to claim 1, further comprising a digital synthesis tool, and the combination of the entire set of weight values of the N RRAM memristor units forms the underlying basic weight of X*Y Logical matrix, the digital synthesis tool directly calls the X*Y underlying basic weight logical matrix according to user requirements; wherein the value of X*Y is greater than or equal to the N.

7. A method for forming an aggregate module based on RRAM memristor units according to claim 1, characterized in that it comprises the following steps:

Step S2: Fabricate the N RRAM memristor units, wherein the M variable RRAM memristor units are original RRAM memristors without storing any weight values;

Step S4: forming a complete set of weight value combinations of the N RRAM memristor units.

8. The forming method according to claim 7, further comprising step S5: the entire set of weight values of the N RRAM memristor units are combined to form an X*Y underlying basic weight logic matrix, and the digital synthesis tool Directly call the underlying basic weight logic matrix of X*Y according to user needs.

9. The method of claim 7, wherein the number of weights in the set of weight value combinations of the N RRAM memristor units is 11, and the N is equal to M, and the step S3 It includes the following steps:

10. The forming method according to claim 7, wherein the step S4 specifically includes the following steps:

Claims

A weighted logic library module based on RRAM memristor, which is characterized in that it comprises: N RRAM memristor units for storing weight values and a weight generating unit, and the N RRAM memristor units include M Variable RRAM memristor unit; each of the variable RRAM memristor units includes an original RRAM memristor without a written weight value, a control transistor, an excitation voltage generator and an output terminal; wherein, the N And M is a positive integer greater than or equal to 2, and M is less than or equal to N; when the weight generation unit determines the weight value that each variable RRAM memristor unit needs to store, the excitation voltage generator generates a corresponding For the voltage of the weight value, a fixed weight value is input to each of the variable RRAM memristor units through the control transistor to form a set of weight value combinations of the N RRAM memristor units.
The assembly module based on RRAM memristor units according to claim 1, wherein the M is less than N, and the N RRAM memristor units include N-M fixed RRAM memristor units.
The assembly module based on RRAM memristor units according to claim 1, wherein the weight values in the set of weight value combinations of the N RRAM memristor units are formed in an arithmetic sequence, or in an equal ratio The sequence is formed.
The assembly module based on RRAM memristor units according to claim 1, wherein the number of the weights in the set of weight value combinations of the N RRAM memristor units is at most 256.
The assembly module based on RRAM memristor units according to claim 4, wherein the number of the weights in the set of weight value combinations of the N RRAM memristor units is 11.
The assembly module based on RRAM memristor units according to claim 1, characterized in that it further comprises a digital synthesis tool, the set of weight values of the N RRAM memristor units are combined to form an X*Y underlying basic weight logic matrix , The digital synthesis tool directly calls the underlying basic weight logic matrix of X*Y according to user requirements; wherein the value of X*Y is greater than or equal to the N.
A method for forming a collective module based on RRAM memristor units according to claim 1, characterized in that it comprises the following steps:

Step S1: Determine, according to the weight generating unit, a complete set of weight value combinations to be stored in the N RRAM memristor units;

Step S2: Fabricate the N RRAM memristor units, wherein the M variable RRAM memristor units are original RRAM memristors without storing any weight values;

Step S3: The excitation voltage generator generates a voltage corresponding to the weight value, and inputs a fixed weight value to each variable RRAM memristor unit through the control transistor to form the M RRAM memories The weight value combination of the resistor unit;

Step S4: forming a complete set of weight value combinations of the N RRAM memristor units.
The formation method according to claim 7, further comprising step S5: the entire set of weight values of the N RRAM memristor units are combined to form an X*Y underlying basic weight logic matrix, and the digital synthesis tool is based on the user Need to directly call the underlying basic weight logic matrix of X*Y.
The method of claim 7, wherein the number of the weights in the set of weight value combinations of the N RRAM memristor units is 11, and the N is equal to M, and the step S3 specifically includes The following steps:

Step S31: The excitation voltage generator generates 11 voltage values, where the 11 voltage values are respectively V1, V2, ... V11;

Step S32: Respectively receive the 11 voltage values V1, V2,...V11 through the 11 control transistors to the 11 variable RRAM memristor units to complete the 11 variable RRAM memristor units The input of the fixed weight value, wherein the fixed weight values of the 11 variable RRAM memristor units are respectively Z1, Z2, ... Z11.
The forming method according to claim 7, wherein the step S4 specifically includes the following steps:

Step S41: If the M is less than N, execute step S42, if the M is equal to N, execute step S43;

Step S42: the set of weight value combinations of the N RRAM memristor units is the weight value combination of the M RRAM memristor units plus (N-M) weight value combinations of the fixed RRAM memristor unit;

Step S43: The whole set of weight value combinations of the N RRAM memristor units is the weight value combination of the M RRAM memristor units.