WO2021027050A1 - Wear-leveling garbage collection accelerating device supporting two bit widths - Google Patents

Wear-leveling garbage collection accelerating device supporting two bit widths Download PDF

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WO2021027050A1
WO2021027050A1 PCT/CN2019/111412 CN2019111412W WO2021027050A1 WO 2021027050 A1 WO2021027050 A1 WO 2021027050A1 CN 2019111412 W CN2019111412 W CN 2019111412W WO 2021027050 A1 WO2021027050 A1 WO 2021027050A1
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data
module
maximum value
data reading
clock
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Chinese (zh)
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王运哲
刘大铕
朱苏雁
刘奇浩
刘尚
孙中琳
王资川
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山东华芯半导体有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0253—Garbage collection, i.e. reclamation of unreferenced memory
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • the invention relates to a wear-leveling garbage collection acceleration device supporting two bit widths, which uses hardware to accelerate the search and comparison of entries in FTL (Flash translation layer), and adopts different hardware designs for different FTL tables and different bus bit widths , To help achieve flash wear leveling and garbage collection.
  • FTL Flash translation layer
  • Flash memory has the characteristics of limited erasing times and erasing first and then writing. Therefore, it is necessary to balance the erasing frequency of each block in the flash to extend the life of the flash memory, which is called wear leveling. Copying the "valid" page data in a flash block to a "blank" block, and then completely erasing this block is called garbage collection.
  • garbage collection In order to achieve wear leveling and garbage collection, the software needs to establish a table (block information table) containing the erase information of the block, the number of valid pages in the block, and the average number of erases, to determine the subsequent erase and write operations of the Flash, and Update the block lookup table (the mapping table of LBA and PBA).
  • the technical problem to be solved by the present invention is to provide a wear-leveling garbage collection acceleration device supporting two bit widths, and improve the efficiency of erasing and writing Flash.
  • a wear-leveling garbage collection acceleration device supporting two bit widths which is characterized in that it includes:
  • Configuration module used to give data reading information and maximum value generation information, initiate data reading, wait for maximum value generation, and feed back the comparison result to the system bus.
  • the data read information includes the address and length of the block information table, the maximum value
  • the generated information includes working mode, comparison items and path selection.
  • the configuration module determines the path selection according to the data bus bit width and the size of the firmware structure, and the size of the firmware structure determines the bit width recorded in the block information table;
  • the data reading module reads the content of the block information table of the corresponding address from the data bus according to the data reading information from the configuration module;
  • the maximum value generation module according to the maximum value generation information given by the configuration module, iteratively compares the data entered from the data reading module and finally obtains the maximum value index and outputs it to the configuration module;
  • the maximum value generation module includes a data path, a clock and a comparator.
  • the data path includes a normal data path, a 2 times frequency data path and a 2 frequency data path
  • the clock includes a normal clock, a 2 frequency clock and a frequency divider clock;
  • the firmware structure size is 16byte or the data bus bit width is 256bit, and the firmware structure size is 32byte, the data read by the data reading module is transmitted to the comparator through the normal data path for comparison. Use normal clock in this process;
  • the data read by the data reading module is transmitted to the comparator through the 2 times frequency data path for comparison, and the 2 times frequency clock is used in this process;
  • the data read by the data reading module is transmitted to the comparator through the divide-by-2 data path for comparison, and the divide-by-2 clock is used in this process.
  • the 2 times frequency data path receives two 128bit data from the data bus in one clock cycle, divides the two 128bit data into high 16byte and low 16byte, and then superimposes the high 16byte and low 16byte into 32byte for transmission.
  • divide-by-2 data path splits the 256bit data transmitted from the data bus into two 16bytes for transmission.
  • the working mode of the maximum value generating module includes single item comparison and multiple weighted comparison
  • the comparator of the maximum value generating module includes single item comparator and multiple item weighted comparator.
  • the comparison item includes the number of erasing times and the number of valid pages.
  • the present invention adopts a hardware acceleration strategy to help achieve wear leveling and garbage collection.
  • the advantage of the present invention is that it can support free combinations of two bus bit widths and two firmware structure sizes. Make full use of the speed advantage of the hardware and cooperate with the software to reduce the time it takes for each flash to erase and write, and to improve the efficiency and service life of the flash.
  • Figure 1 is a schematic block diagram of the present invention.
  • This embodiment discloses a wear-leveling garbage collection acceleration device supporting two bit widths, as shown in FIG. 1, including a block information table, a data reading module, a maximum value generation module, a configuration module, and a data bus control bus.
  • the block information table is stored in the cache after the system is powered on, and stored in the Flash after power off.
  • the block information table stores the erase information of the block, the number of valid pages in the block and the average number of erases. This method can Find the index value of the most value of one or several comparison items in the block information table of the specified type, and improve the software's efficiency of erasing and writing Flash by using the wear leveling and garbage collection candidate block information given by the index value.
  • the configuration module is used to give data reading information and maximum value generation information, initiate data reading, and wait for the maximum value to be generated and then feedback the comparison result to the system bus.
  • the data read information includes the address and length of the block information table, and the maximum value is generated
  • the information includes working mode, comparison items and path selection.
  • the configuration module determines the path selection according to the data bus bit width and the size of the firmware structure.
  • the size of the firmware structure determines the bit width recorded in the block information table.
  • the data reading module reads the content of the block information table of the corresponding address from the data bus according to the data reading information from the configuration module.
  • the maximum value generation module according to the maximum value generation information given by the configuration module, iteratively compares the data entered from the data reading module and finally obtains the maximum value index and outputs it to the configuration module.
  • the maximum value generation module includes a data path, a clock and a comparator.
  • the data path includes a normal data path, a 2 times frequency data path and a 2 frequency data path
  • the clock includes a normal clock, a 2 frequency clock and a frequency divider clock;
  • the firmware structure size is 16byte or the data bus bit width is 256bit, and the firmware structure size is 32byte
  • the data read by the data reading module is transmitted to the comparator through the normal data path for comparison.
  • the normal clock is used in this process.
  • the data read by the data reading module is transmitted to the comparator through the 2 times frequency data path for comparison, and the 2 times frequency clock is used in this process.
  • the data read by the data reading module is transmitted to the comparator through the divide-by-2 data path for comparison, and the divide-by-2 clock is used in this process.
  • the double frequency data path receives two 128bit data from the data bus in one clock cycle, divides the two 128bit data into high 16byte and low 16byte, and then superimposes the high 16byte and low 16byte into 32byte. transmission.
  • the divide-by-2 data path splits the 256-bit data transmitted from the data bus into two 16-byte data for transmission.
  • B stands for byte and b stands for bit.
  • the working mode of the maximum value generating module includes single comparison and multiple weighted comparison
  • the comparator of the maximum value generating module includes a single comparator and a multiple weighted comparator.
  • the comparison items include the number of erasures and the number of valid pages.
  • the maximum value generation module compares the number of erasures and/or the number of valid pages according to the comparison item information, and generates a corresponding maximum value.
  • the CPU (firmware) in the system will need to request the address and length of the most valuable block information table, working mode (weighting parameter register is required for multiple weighting modes), comparison items, data bit width information and structure size information Write to the corresponding register in the configuration module through the control bus.
  • the configuration module passes the address and length of the block information table to the data reading module and starts the data reading module. At the same time, the configuration module passes the path selection (clock selection, data path selection, comparator selection) determined by the data bus bit width and the size of the firmware structure to the maximum value comparison module and starts its comparison operation.
  • path selection clock selection, data path selection, comparator selection
  • the data reading module reads data from the data bus and transmits it to the maximum value generation module.
  • the maximum value generation module compares data according to the path selection given by the configuration module to obtain the maximum value index. Steps 3 and 4 are pipelined, that is, as long as the external data bus is not busy, the data reading module can send burst transmission to read all the data in uninterruptedly, and the maximum value generation module continuously iteratively compares. When the data reading is completed You can get the most value index. Due to the 2 times frequency clock and the 2 frequency divider clock, for each clock cycle of the maximum value generation module, one beat of data is performed and a data comparison is completed.
  • step 4 Store the most value index obtained in step 4 into the register of the configuration module for CPU (firmware) access.
  • the software uses multiple (a few to a dozen) clock cycles to use the CPU to perform a calculation.
  • the hardware can Each clock cycle can perform an operation, that is, when the frequency is the same, the efficiency of the hardware accelerator can be several times or more than ten times that of the CPU; 2.
  • the bit width of the CPU is limited to 64bit, and the bit width of the hardware acceleration module can be customized.
  • the data bus bit width is generally 128bit or 256bit, so if the frequency is the same, the amount of data processed per clock cycle is also 2 or 4 times that of the CPU.
  • This device can achieve: 1. Select the appropriate data path according to the system bus bit width and the size of the firmware structure; 2. Find the most index value of a comparison item in the specified type block; 3. Calculate several according to the weight information Compare the weighted calculation results of the items, and compare the results to get the index value corresponding to the maximum value. These index values give the candidate block information for wear leveling and garbage collection, which improves the efficiency of software erasing and writing to Flash.

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Abstract

Disclosed in the present invention is a wear-leveling garbage collection accelerating device supporting two bit widths, comprising: a data reading module, an extreme value generation module, a configuration module, a data bus, and a control bus. The configuration module gives out data reading information and extreme value generation information, initiates data reading, and after the extreme value is generated, feeds a comparison result back to a system bus. The data reading module reads content of a block information table of a corresponding address from the data bus according to the data reading information from the configuration module, and the extreme value generation module iteratively compares data entering from the data reading module according to the extreme value generation information given by the configuration module to finally obtain an extreme value index. The device adopts a hardware acceleration strategy to help realize wear leveling and garbage collection, can support free combination of two bus bit widths and two firmware structure sizes, reduces the time consumed by Flash erasing each time, improves the use efficiency of a flash memory, and prolongs the service life of the flash memory.

Description

支持两种位宽的磨损均衡垃圾回收加速装置Support two bit width wear leveling garbage collection acceleration devices 技术领域Technical field
本发明涉及一种支持两种位宽的磨损均衡垃圾回收加速装置，使用硬件加速对FTL(Flash translation layer)中表项的搜索比较，通过对不同FTL表和不同总线位宽采用不同的硬件设计，帮助实现闪存的磨损均衡和垃圾回收。The invention relates to a wear-leveling garbage collection acceleration device supporting two bit widths, which uses hardware to accelerate the search and comparison of entries in FTL (Flash translation layer), and adopts different hardware designs for different FTL tables and different bus bit widths , To help achieve flash wear leveling and garbage collection.
背景技术Background technique
闪存具有擦除次数有限、先擦后写的特点，因此需要均衡flash中每个块的擦写频率来延长闪存的使用寿命，即所谓的磨损均衡。把一个闪存块里的‘有效’页数据复制到一个“空白”块里，然后把这个块完全擦除即所谓的垃圾回收。为实现磨损均衡和垃圾回收，软件需要建立包含块的擦除信息及块中有效页个数及平均擦除次数等信息的表(块信息表)，以此决定Flash后续的擦写操作，并更新块查询表(LBA和PBA的映射表)。这些表存储在闪存的特殊地址单元中，系统上电后cpu将其读入内存中实时更新。然而单纯通过软件将块信息表中的信息逐一读取比对耗时较长，使得闪存的擦写操作变慢。Flash memory has the characteristics of limited erasing times and erasing first and then writing. Therefore, it is necessary to balance the erasing frequency of each block in the flash to extend the life of the flash memory, which is called wear leveling. Copying the "valid" page data in a flash block to a "blank" block, and then completely erasing this block is called garbage collection. In order to achieve wear leveling and garbage collection, the software needs to establish a table (block information table) containing the erase information of the block, the number of valid pages in the block, and the average number of erases, to determine the subsequent erase and write operations of the Flash, and Update the block lookup table (the mapping table of LBA and PBA). These tables are stored in a special address unit of the flash memory, and the cpu will read them into the memory and update them in real time after the system is powered on. However, it takes longer to read and compare the information in the block information table one by one by software alone, which slows down the erasing and writing operations of the flash memory.
发明内容Summary of the invention
本发明要解决的技术问题是提供一种支持两种位宽的磨损均衡垃圾回收加速装置，提高对Flash的擦写效率。The technical problem to be solved by the present invention is to provide a wear-leveling garbage collection acceleration device supporting two bit widths, and improve the efficiency of erasing and writing Flash.
为了解决所述技术问题，本发明采用的技术方案是：支持两种位宽的磨损均衡垃圾回收加速装置，其特征在于：包括：In order to solve the technical problem, the technical solution adopted by the present invention is: a wear-leveling garbage collection acceleration device supporting two bit widths, which is characterized in that it includes:
配置模块，用于给出数据读取信息和最值生成信息，发起数据读取，等待最值生成后将比较结果反馈给系统总线，数据读取信息包括块信息表的地址和长度，最值生成信息包括工作模式、比较项目和通路选择，配置模块根据数据总线位宽和固件结构体的大小决定通路选择，固件结构体的大小决定块信息表中记录的位宽；Configuration module, used to give data reading information and maximum value generation information, initiate data reading, wait for maximum value generation, and feed back the comparison result to the system bus. The data read information includes the address and length of the block information table, the maximum value The generated information includes working mode, comparison items and path selection. The configuration module determines the path selection according to the data bus bit width and the size of the firmware structure, and the size of the firmware structure determines the bit width recorded in the block information table;
数据读取模块，根据来自配置模块的数据读取信息从数据总线读取相应地址的块信息表的内容；The data reading module reads the content of the block information table of the corresponding address from the data bus according to the data reading information from the configuration module;
最值生成模块，根据配置模块给出的最值生成信息将从数据读取模块进入的数据迭代比较最终得到最值索引并输出给配置模块；The maximum value generation module, according to the maximum value generation information given by the configuration module, iteratively compares the data entered from the data reading module and finally obtains the maximum value index and outputs it to the configuration module;
最值生成模块包括数据通路、时钟和比较器，数据通路包括正常数据通路、2倍频数据通路和2分频数据通路，时钟包括正常时钟、2倍频时钟和2分频时钟；The maximum value generation module includes a data path, a clock and a comparator. The data path includes a normal data path, a 2 times frequency data path and a 2 frequency data path, and the clock includes a normal clock, a 2 frequency clock and a frequency divider clock;
当数据总线位宽为128bit、固件结构体大小为16byte或者数据总线位宽为256bit、固件结构 体大小为32byte时，数据读取模块读取的数据通过正常数据通路传送给比较器进行比较，在此过程中使用正常时钟；When the data bus bit width is 128bit, the firmware structure size is 16byte or the data bus bit width is 256bit, and the firmware structure size is 32byte, the data read by the data reading module is transmitted to the comparator through the normal data path for comparison. Use normal clock in this process;
当数据总线位宽为128bit、固件结构体大小为32byte时，数据读取模块读取的数据通过2倍频数据通路传送给比较器进行比较，在此过程中使用2倍频时钟；When the data bus bit width is 128bit and the firmware structure size is 32byte, the data read by the data reading module is transmitted to the comparator through the 2 times frequency data path for comparison, and the 2 times frequency clock is used in this process;
当数据总线位宽为256bit，固件结构体大小为16byte时，数据读取模块读取的数据通过2分频数据通路传送给比较器进行比较，在此过程中使用2分频时钟。When the data bus bit width is 256bit and the firmware structure size is 16byte, the data read by the data reading module is transmitted to the comparator through the divide-by-2 data path for comparison, and the divide-by-2 clock is used in this process.
进一步的，2倍频数据通路在一个时钟周期内接收数据总线传来的两个128bit数据，将此两个128bit数据分成高16byte和低16byte，然后将高16byte和低16byte叠加成32byte进行传输。Furthermore, the 2 times frequency data path receives two 128bit data from the data bus in one clock cycle, divides the two 128bit data into high 16byte and low 16byte, and then superimposes the high 16byte and low 16byte into 32byte for transmission.
进一步的，2分频数据通路将数据总线传输来的256bit数据拆分成两个16byte进行传输。Further, the divide-by-2 data path splits the 256bit data transmitted from the data bus into two 16bytes for transmission.
进一步的，最值生成模块的工作模式包括单项比较和多项加权比较，最值生成模块的比较器包括单项比较器和多项加权比较器。Further, the working mode of the maximum value generating module includes single item comparison and multiple weighted comparison, and the comparator of the maximum value generating module includes single item comparator and multiple item weighted comparator.
进一步的，比较项包括擦除次数和有效页个数。Further, the comparison item includes the number of erasing times and the number of valid pages.
本发明的有益效果：本发明采用硬件加速策略帮助实现磨损均衡和垃圾回收，本发明的优点在于可支持两种总线位宽和两种固件结构体大小的自由组合。充分利用硬件的速度优势配合软件减少Flash每次擦写所耗时间，提高闪存的使用效率和使用寿命。The beneficial effects of the present invention: the present invention adopts a hardware acceleration strategy to help achieve wear leveling and garbage collection. The advantage of the present invention is that it can support free combinations of two bus bit widths and two firmware structure sizes. Make full use of the speed advantage of the hardware and cooperate with the software to reduce the time it takes for each flash to erase and write, and to improve the efficiency and service life of the flash.
附图说明Description of the drawings
图1为本发明的原理框图。Figure 1 is a schematic block diagram of the present invention.
具体实施方式detailed description
下面结合附图和具体实施例对本发明作进一步的说明。The present invention will be further described below with reference to the drawings and specific embodiments.
本实施例公开一种支持两种位宽的磨损均衡垃圾回收加速装置，如图1所示，包括块信息表、数据读取模块、最值生成模块、配置模块、数据总线控制总线。This embodiment discloses a wear-leveling garbage collection acceleration device supporting two bit widths, as shown in FIG. 1, including a block information table, a data reading module, a maximum value generation module, a configuration module, and a data bus control bus.
块信息表在系统上电后存放在缓存中，掉电后存放在Flash当中，块信息表内存储有块的擦除信息、块中有效页个数及平均擦除次数等信息，本方法能找到指定类型块信息表中某个或者某几个比较项目的最值之索引值，根据索引值给出的磨损均衡和垃圾回收的备选块信息，提高软件对Flash的擦写效率。The block information table is stored in the cache after the system is powered on, and stored in the Flash after power off. The block information table stores the erase information of the block, the number of valid pages in the block and the average number of erases. This method can Find the index value of the most value of one or several comparison items in the block information table of the specified type, and improve the software's efficiency of erasing and writing Flash by using the wear leveling and garbage collection candidate block information given by the index value.
配置模块用于给出数据读取信息和最值生成信息，发起数据读取，等待最值生成后将比较结果反馈给系统总线，数据读取信息包括块信息表的地址和长度，最值生成信息包括工作模式、比较项目和通路选择，配置模块根据数据总线位宽和固件结构体的大小决定通路 选择，固件结构体的大小决定块信息表中记录的位宽。The configuration module is used to give data reading information and maximum value generation information, initiate data reading, and wait for the maximum value to be generated and then feedback the comparison result to the system bus. The data read information includes the address and length of the block information table, and the maximum value is generated The information includes working mode, comparison items and path selection. The configuration module determines the path selection according to the data bus bit width and the size of the firmware structure. The size of the firmware structure determines the bit width recorded in the block information table.
数据读取模块，根据来自配置模块的数据读取信息从数据总线读取相应地址的块信息表的内容。The data reading module reads the content of the block information table of the corresponding address from the data bus according to the data reading information from the configuration module.
最值生成模块，根据配置模块给出的最值生成信息将从数据读取模块进入的数据迭代比较最终得到最值索引并输出给配置模块。The maximum value generation module, according to the maximum value generation information given by the configuration module, iteratively compares the data entered from the data reading module and finally obtains the maximum value index and outputs it to the configuration module.
最值生成模块包括数据通路、时钟和比较器，数据通路包括正常数据通路、2倍频数据通路和2分频数据通路，时钟包括正常时钟、2倍频时钟和2分频时钟；The maximum value generation module includes a data path, a clock and a comparator. The data path includes a normal data path, a 2 times frequency data path and a 2 frequency data path, and the clock includes a normal clock, a 2 frequency clock and a frequency divider clock;
当数据总线位宽为128bit、固件结构体大小为16byte或者数据总线位宽为256bit、固件结构体大小为32byte时，数据读取模块读取的数据通过正常数据通路传送给比较器进行比较，在此过程中使用正常时钟。When the data bus bit width is 128bit, the firmware structure size is 16byte or the data bus bit width is 256bit, and the firmware structure size is 32byte, the data read by the data reading module is transmitted to the comparator through the normal data path for comparison. The normal clock is used in this process.
当数据总线位宽为128bit、固件结构体大小为32byte时，数据读取模块读取的数据通过2倍频数据通路传送给比较器进行比较，在此过程中使用2倍频时钟。When the data bus bit width is 128bit and the firmware structure size is 32byte, the data read by the data reading module is transmitted to the comparator through the 2 times frequency data path for comparison, and the 2 times frequency clock is used in this process.
当数据总线位宽为256bit，固件结构体大小为16byte时，数据读取模块读取的数据通过2分频数据通路传送给比较器进行比较，在此过程中使用2分频时钟。When the data bus bit width is 256bit and the firmware structure size is 16byte, the data read by the data reading module is transmitted to the comparator through the divide-by-2 data path for comparison, and the divide-by-2 clock is used in this process.
本实施例中，2倍频数据通路在一个时钟周期内接收数据总线传来的两个128bit数据，将此两个128bit数据分成高16byte和低16byte，然后将高16byte和低16byte叠加成32byte进行传输。In this embodiment, the double frequency data path receives two 128bit data from the data bus in one clock cycle, divides the two 128bit data into high 16byte and low 16byte, and then superimposes the high 16byte and low 16byte into 32byte. transmission.
本实施例中，2分频数据通路将数据总线传输来的256bit数据拆分成两个16byte进行传输。在图1中，B代表byte(字节)，b代表bit(比特)。In this embodiment, the divide-by-2 data path splits the 256-bit data transmitted from the data bus into two 16-byte data for transmission. In Figure 1, B stands for byte and b stands for bit.
本实施例中，最值生成模块的工作模式包括单项比较和多项加权比较，最值生成模块的比较器包括单项比较器和多项加权比较器。比较项包括擦除次数和有效页个数。最值生成模块根据比较项信息进行擦除次数和/或有效页个数的比较，生成相应的最值。In this embodiment, the working mode of the maximum value generating module includes single comparison and multiple weighted comparison, and the comparator of the maximum value generating module includes a single comparator and a multiple weighted comparator. The comparison items include the number of erasures and the number of valid pages. The maximum value generation module compares the number of erasures and/or the number of valid pages according to the comparison item information, and generates a corresponding maximum value.
利用本实施例所述装置提供块信息表最值的步骤为：The steps of using the device of this embodiment to provide the most value of the block information table are:
1、系统中的CPU(固件)将需要求最值的块信息表的地址及长度、工作模式(多项加权模式时需要配置加权参数寄存器)、比较项、数据位宽信息和结构体大小信息通过控制总线写入到配置模块中相应的寄存器。1. The CPU (firmware) in the system will need to request the address and length of the most valuable block information table, working mode (weighting parameter register is required for multiple weighting modes), comparison items, data bit width information and structure size information Write to the corresponding register in the configuration module through the control bus.
2、配置模块将块信息表的地址及长度传递给数据读取模块并启动数据读取模块。同时配置模块根据数据总线位宽和固件结构体大小决定的通路选择(时钟选择，数据通路选择，比较器选择)传递给最值比较模块并启动其比较操作。2. The configuration module passes the address and length of the block information table to the data reading module and starts the data reading module. At the same time, the configuration module passes the path selection (clock selection, data path selection, comparator selection) determined by the data bus bit width and the size of the firmware structure to the maximum value comparison module and starts its comparison operation.
3、数据读取模块从数据总线读取数据并传递给最值生成模块。3. The data reading module reads data from the data bus and transmits it to the maximum value generation module.
4、最值生成模块根据配置模块给出的通路选择进行数据比较得到最值索引。步骤三和步骤四是流水进行，即只要外部数据总线不忙，数据读取模块可以发送burst传输不间断地将所有数据读入，同时最值生成模块不间断地迭代比较，数据读取完成时即可得到最值索引。因有2倍频时钟和2分频时钟，对于最值生成模块每个时钟周期进一拍数据并完成一次数据比较。4. The maximum value generation module compares data according to the path selection given by the configuration module to obtain the maximum value index. Steps 3 and 4 are pipelined, that is, as long as the external data bus is not busy, the data reading module can send burst transmission to read all the data in uninterruptedly, and the maximum value generation module continuously iteratively compares. When the data reading is completed You can get the most value index. Due to the 2 times frequency clock and the 2 frequency divider clock, for each clock cycle of the maximum value generation module, one beat of data is performed and a data comparison is completed.
5、将步骤4得到的最值索引存入配置模块的寄存器，以备CPU(固件)访问。5. Store the most value index obtained in step 4 into the register of the configuration module for CPU (firmware) access.
本装置实现的是硬件加速查找最值的功能，硬件加速之所以比软件快，是基于以下两点：1、软件使用CPU运算一次需要多个(几个到十几个)时钟周期，硬件可以每一个时钟周期都可以进行一次运算，即频率相同时硬件加速器的效率可以几倍或者十几倍于CPU；2、CPU的位宽受限于64bit，而硬件加速模块的位宽可以自定义，并且数据总线位宽一般为128bit或者256bit，因此如果频率相同的情况下每个时钟周期处理的数据量也2或4倍于CPU。This device realizes the function of hardware acceleration to find the most value. The reason why hardware acceleration is faster than software is based on the following two points: 1. The software uses multiple (a few to a dozen) clock cycles to use the CPU to perform a calculation. The hardware can Each clock cycle can perform an operation, that is, when the frequency is the same, the efficiency of the hardware accelerator can be several times or more than ten times that of the CPU; 2. The bit width of the CPU is limited to 64bit, and the bit width of the hardware acceleration module can be customized. And the data bus bit width is generally 128bit or 256bit, so if the frequency is the same, the amount of data processed per clock cycle is also 2 or 4 times that of the CPU.
本装置可以实现：1、根据系统总线位宽和固件结构体大小选择合适的数据通路；2、找到指定类型块中某个比较项目的最值之索引值；3、根据权重信息计算出几个比较项目的加权运算结果，比较该结果得到其最值所对应的索引值。这些索引值给出了磨损均衡和垃圾回收的备选块信息，提高了软件对Flash的擦写效率。This device can achieve: 1. Select the appropriate data path according to the system bus bit width and the size of the firmware structure; 2. Find the most index value of a comparison item in the specified type block; 3. Calculate several according to the weight information Compare the weighted calculation results of the items, and compare the results to get the index value corresponding to the maximum value. These index values give the candidate block information for wear leveling and garbage collection, which improves the efficiency of software erasing and writing to Flash.
以上描述的仅是本发明的基本原理和优选实施例，本领域技术人员根据本发明做出的改进和替换，属于本发明的保护范围。What has been described above is only the basic principles and preferred embodiments of the present invention. Improvements and replacements made by those skilled in the art according to the present invention belong to the protection scope of the present invention.

Claims (5)

  1. 支持两种位宽的磨损均衡垃圾回收加速装置，其特征在于：包括：Two bit-width wear-leveling garbage collection acceleration devices are supported, which are characterized by: including:
    配置模块，用于给出数据读取信息和最值生成信息，发起数据读取，等待最值生成后将比较结果反馈给系统总线，数据读取信息包括块信息表的地址和长度，最值生成信息包括工作模式、比较项目和通路选择，配置模块根据数据总线位宽和固件结构体的大小决定通路选择，固件结构体的大小决定块信息表中记录的位宽；Configuration module, used to give data reading information and maximum value generation information, initiate data reading, wait for maximum value generation, and feed back the comparison result to the system bus. The data read information includes the address and length of the block information table, the maximum value The generated information includes working mode, comparison items and path selection. The configuration module determines the path selection according to the data bus bit width and the size of the firmware structure, and the size of the firmware structure determines the bit width recorded in the block information table;
    数据读取模块，根据来自配置模块的数据读取信息从数据总线读取相应地址的块信息表的内容；The data reading module reads the content of the block information table of the corresponding address from the data bus according to the data reading information from the configuration module;
    最值生成模块，根据配置模块给出的最值生成信息将从数据读取模块进入的数据迭代比较最终得到最值索引并输出给配置模块；The maximum value generation module, according to the maximum value generation information given by the configuration module, iteratively compares the data entered from the data reading module and finally obtains the maximum value index and outputs it to the configuration module;
    最值生成模块包括数据通路、时钟和比较器，数据通路包括正常数据通路、2倍频数据通路和2分频数据通路，时钟包括正常时钟、2倍频时钟和2分频时钟；当数据总线位宽为128bit、固件结构体大小为16byte或者数据总线位宽为256bit、固件结构体大小为32byte时，数据读取模块读取的数据通过正常数据通路传送给比较器进行比较，在此过程中使用正常时钟；The maximum value generation module includes a data path, a clock, and a comparator. The data path includes a normal data path, a frequency-multiplied 2 data path, and a frequency-divided 2 data path. The clock includes a normal clock, a frequency-multiplied 2 clock, and a frequency-divided 2 clock. When the bit width is 128bit, the firmware structure size is 16byte, or the data bus bit width is 256bit, and the firmware structure size is 32byte, the data read by the data reading module is transmitted to the comparator through the normal data path for comparison. In this process Use normal clock;
    当数据总线位宽为128bit、固件结构体大小为32byte时，数据读取模块读取的数据通过2倍频数据通路传送给比较器进行比较，在此过程中使用2倍频时钟；When the data bus bit width is 128bit and the firmware structure size is 32byte, the data read by the data reading module is transmitted to the comparator through the 2 times frequency data path for comparison, and the 2 times frequency clock is used in this process;
    当数据总线位宽为256bit，固件结构体大小为16byte时，数据读取模块读取的数据通过2分频数据通路传送给比较器进行比较，在此过程中使用2分频时钟。When the data bus bit width is 256bit and the firmware structure size is 16byte, the data read by the data reading module is transmitted to the comparator through the divide-by-2 data path for comparison, and the divide-by-2 clock is used in this process.
  2. 根据权利要求1所述的支持两种位宽的磨损均衡垃圾回收加速装置，其特征在于：2倍频数据通路在一个时钟周期内接收数据总线传来的两个128bit数据，将此两个128bit数据分成高16byte和低16byte，然后将高16byte和低16byte叠加成32byte进行传输。The wear leveling garbage collection acceleration device supporting two bit widths according to claim 1, characterized in that: the 2 times frequency data path receives two 128bit data from the data bus in one clock cycle, and the two 128bit data The data is divided into high 16byte and low 16byte, and then the high 16byte and low 16byte are superimposed into 32byte for transmission.
  3. 根据权利要求1所述的支持两种位宽的磨损均衡垃圾回收加速装置，其特征在于：2分频数据通路将数据总线传输来的256bit数据拆分成两个16byte进行传输。The wear-leveling garbage collection acceleration device supporting two bit widths according to claim 1, characterized in that the 256-bit data transmitted from the data bus is split into two 16-byte data for transmission by the 2-frequency data path.
  4. 根据权利要求1所述的支持两种位宽的磨损均衡垃圾回收加速装置，其特征在于：最值生成模块的工作模式包括单项比较和多项加权比较，最值生成模块的比较器包括单项比较器和多项加权比较器。The wear leveling garbage collection acceleration device supporting two bit widths according to claim 1, wherein the working mode of the maximum value generating module includes single item comparison and multiple weighted comparison, and the comparator of the maximum value generating module includes single item comparison And multiple weighted comparators.
  5. 根据权利要求1所述的支持两种位宽的磨损均衡垃圾回收加速装置，其特征在于：比较项包括擦除次数和有效页个数。The wear-leveling garbage collection acceleration device supporting two bit widths according to claim 1, wherein the comparison item includes the number of erasing times and the number of valid pages.
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