WO2021026521A1

WO2021026521A1 - Reduced resistivity traces in multilayered printed circuit boards and methods of forming

Info

Publication number: WO2021026521A1
Application number: PCT/US2020/045569
Authority: WO
Inventors: Aviram IANCOVICI
Original assignee: Nano-Dimension Technologies, Ltd.; The IP Law Firm of Guy Levi, LLC
Priority date: 2019-08-08
Filing date: 2020-08-10
Publication date: 2021-02-11

Abstract

The disclosure relates to methods for forming multilayered printed circuit boards (PCBs), flexible printed circuits (FPCs) and high-density interconnect (HD I) printed circuits and methods of forming these. Specifically, the disclosure relates to methods for direct inkjet printing of traces having predetermined resistivity for use in multilayered printed circuit boards (PCBs), flexible printed circuits (FPCs) and high-density interconnect (HDI) printed circuits, by printing intermediate traces coupled to the external trace with a plurality of blind and/or buried vias.

Description

REDUCED RESISTIVITY TRACES IN MULTILAYERED PRINTED CIRCUIT BOARDS AND

METHODS OF FORMING

BACKGROUND

[0001] The disclosure is directed to methods for forming multilayered printed circuit boards (PCBs), flexible printed circuits (FPCs) and high-density interconnect (HDI) printed circuits, collectively additively manufactured electronics (AME) and methods of forming these. Specifically, the disclosure is directed to methods for inkjet printing of traces having predetermined resistivity for use in multilayered printed circuit boards (PCBs), flexible printed circuits (FPCs) and high-density interconnect (HDI) printed circuits.

[0002] High power electronic components such as central processing units (CPU) and graphics processing units (GPU), as well as power supply units (PSU), generate a large amount of heat during operation. To increase computing performance for example by overclocking (in other words increasing clock frequency above the standard frequency that the manufacturer used) in stringent packaging constraint, many of these components generate extra heat that cannot be adequately dissipated by the cooling systems provided (e.g., cooling fans).

[0003] In addition, electronic devices with small form factor are increasingly in demand in all areas of, for example: manufacture, business, consumer goods, military, aeronautics, internet of things, and others. Products having these smaller form factors rely on compact PCBs with tightly spaced digital and analog circuits placed in close proximity on external surfaces. Increased device complexity, can also lead to a substantial increase in PCB layer count, to account for example, for increased functionality requirement combined with the demand for smaller footprint and form factor, such as those requirements in mobile communication devices and computing devices.

[0004] Moreover, because active devices that are shrinking in size and are packaged in advanced packaging and chip scale packaging (CSP), add to the complexity and issues associated with small form factor PCBs, OEMs demand lower ‘parasitic’ or ‘bleeding’ interconnects, and better yields associated with these (small form factor) designs. All these requirements need to minimize the length of the connectivity between these active devices, without compromising resistivity as well as robustness to widely varying temperature changes during operation.

[0005] The following disclosure addresses these shortcomings. SUMMARY

[0006] Disclosed, in various exemplary implementations, are methods and systems for forming multilayered printed circuit boards (PCBs), flexible printed circuits (FPCs) and high-density interconnect (HDI) printed circuits, collectively, potentially with additional integrated circuits - additively manufactured electronics (AME) and methods of forming these AMEs. Specifically, the disclosure is directed to methods for inkjet printing of traces having predetermined resistivity for use in multilayered AMEs.

[0007] In an exemplary implementation, provided herein is a method of reducing trace resistivity between at least two connected components in a multilayer additively manufactured electronic (AME) comprising: forming at least one trace on an intermediate layer, thereby forming an intermediate trace; forming a trace sized and configured to operably couple the at least two components on at least one of: an external apical layer, and external basal layer of the multilayer AME, thereby forming at least one external trace; and forming a predetermined number of at least one of: a blind via, and a buried via, the predetermined number of vias sized and configured to electrically couple the at least one intermediate trace and a corresponding external trace of the multilayer AME.

[0008] In another embodiment, provided herein is a multilayered AME comprising: at least one intermediate trace on an intermediate layer; an external trace sized and configured to operably couple the at least two components on at least one of: an external apical, and an external basal layer of the multilayer AME; and a predetermined number of at least one of: a blind via, and a buried via, electrically coupling the at least one intermediate trace and the external trace.

[0009] In yet another embodiment, provided herein is a computerized method for fabricating a trace having reduced resistivity between at least two connected components in a multilayer printed circuit board (PCB), using inkjet printer comprising: providing an inkjet printing system comprising: a first print head, operable to dispense a dielectric ink composition; a second print head operable to dispense a conductive ink composition; a conveyor, operably coupled to the first, and the second print heads configured to convey a substrate to each of the first, and the second print heads; and a computer aided manufacturing (“CAM”) module including a central processing module (CPM), the CAM being in communication with each of the first, and second print heads, wherein the CPM further comprising: at least one processor in communication with a non-transitory storage medium, storing thereon a set of executable instructions configured, when executed to cause the CPM to perform the steps of: receiving a 3D visualization file representing the multilayer AME having the reduced resistivity traces; and generating a file library having a plurality of files, each file representing a substantially 2D layer for printing the LPF and a metafile representing at least the printing order; wherein the CAM module is configured to control each of the conveyer, the first, and the second print heads; providing the dielectric ink composition, and the conductive ink composition; using the CAM module, obtaining from the library a first file representative of the first layer for printing the multilayer AME having the reduced resistivity traces, the first file comprising printing instructions for a pattern representative of at least one of: the dielectric ink, and the conductive ink; using the first print head, forming the pattern corresponding to the dielectric ink; using electromagnetic radiation source, curing the pattern corresponding to the dielectric ink representation in the 2D layer of the multilayer PCB; using the second print head, forming the pattern corresponding to the conductive ink; using heat, sintering the pattern corresponding to the conductive ink; using the CAM module, obtaining from the library a subsequent file representative of a subsequent layer for printing the multilayer AME having the reduced resistivity traces; the subsequent file comprising printing instructions for a pattern representative of at least one of: the dielectric ink, and the conductive ink; repeating the steps of: using the first print head, forming the pattern corresponding to the dielectric ink to the step of using the CAM module, obtaining from the 2D file library the subsequent, substantially 2D layer, wherein upon sintering of the conductive ink pattern in the final substantially 2D layer, the multilayered AME is configured to comprise: at least one intermediate trace on an intermediate layer; at least one external trace sized and configured to operably couple the at least two components on at least one of: an external apical and external basal layer of the multilayered AME; and a predetermined number of at least one of: a blind via, and a buried via, electrically coupling the intermediate trace with the external trace; and removing the substrate.

[00010] These and other features of the methods for forming traces with selectably reduced resistivity in multilayered printed circuit boards, will become apparent from the following detailed description when read in conjunction with the figures and examples, which are exemplary, not limiting.

BRIEF DESCRIPTION OF THE FIGURES

[00011] For a better understanding of the methods for forming traces with selectably reduced resistivity in multilayered printed circuit boards, using for example, direct ink jet printing of multilayered printed circuit boards (PCBs) flexible printed circuits (FPCs) and high density interconnect printed circuits (HDI circuits, with regard to the exemplary implementations thereof, reference is made to the accompanying examples and figures, in which:

[00012] FIG. 1 illustrates a perspective view schematic of traces with fixed area;

[00013] FIG. 2, illustrates a perspective view schematic of traces with reduced resistivity formed using the disclosed methods; and

[00014] FIG. 3, illustrates top plan of a wiring board formed using prior art.

DETAILED DESCRIPTION

[00015] Provided herein are exemplary implementations of methods for forming traces with selectably reduced resistivity in multilayered printed circuit boards.

[00016] Typically, calculating PCB trace resistance is as simple as using the Ohms law (V=I/R) with known parameters. Moreover, estimating the resistance of the final trace on the board can be done by providing the required manufacturing profiles while using a standard formula to calculate the resistance:

Where - R is resistivity in ohm-m;

- p is the material- specific resistivity coefficient;

- L is the trace length;

- h is the trace thickness;

- W is the trace width;

- a is the (material- specific) resistivity temperature coefficient; and

- DT is the temperature differential between the operating temperature and a reference temperature, typically 25 °C.

[00017] Table I provides example of r and a for some commonly used trace materials:

TABLE I: MATERIAL- SPECIFIC RESISTIVITY PARAMETERS:

[00018] Accordingly, under circumstances of high component density, combined at times with high-temperature-generating components such as, for example PSUs and GPUs, as well as shortened trace length requirements, it is reasonable to expect higher trace resistivity. In addition, these calculations can only determine an approximate value. Actual value after production will vary to a degree.

[00019] High-power components, such as converters (A/D, D/A e.g.) and circuits coupling these components will be greatly affected by these constraints and any unanticipated variation in resistivity, potentially resulting in power loss. In such power circuits an uncompensated AME trace resistance may act as a fuse in case of a power surge and burn the trace, leaving the circuit with a permanent damage. Furthermore, in high-speed digital boards PCB, trace resistance, along with parasitic capacitance may create oscillation and cause electromagnetic (EM) interference to the circuitry.

[00020] The methods described herein can be used to form the multilayered AMEs with traces having selectably reduced resistivity in a continuous process, using an inkjet printing device, or using several passes. Typically, the dielectric material used to form the board, is formed separately and is provided as a substrate for further printing of the conductive and dielectric layers on top of it. Using the printing methods described herein, it is possible to achieve traces with selectably reduced resistivity, allowing higher component density, as well as increased flexibility in design.

[00021 ] Traditional methods for forming the multilayer AMEs disclosed herein, are well known methods used to produce electronic components such as RFID antennae and circuit boards and involve multi-step subtractive processes involving etching or stamping of copper/silver films. Additionally, or alternatively, the systems, methods and compositions described herein can be used to form/fabricate the multilayered AMEs with selectably (in other words, pre-calculated without affecting other components in external or intermediate layers) reduced-resistivity traces, using a combination of print heads with conductive and dielectric ink compositions in a continuous (in other words, in a single pass) or semi-continuous additive manufacturing (AM) process using inkjet printing device, or using several passes.

[00022] While reference is made to inkjet inks and their dispensing systems, other additive manufacturing (AM) methods are also contemplated in the implementation of the disclosed methods. In the exemplary embodiment, the multilayered PCBs with selectably reduced-resistivity traces can likewise be fabricated by a selective laser sintering (SLS) process, although any other suitable additive manufacturing process (also known as rapid prototyping, rapid manufacturing, and 3D printing methods) may also be used, either alone or in combination. These can be, for example, direct metal laser sintering (DMLS), electron beam melting (EBM), selective heat sintering (SHS), or stereolithography (SLA).

[00023] The multilayered PCBs with selectably reduced-resistivity traces may be fabricated from any suitable additive manufacturing material, such as metal powder(s) (e.g., silver, gold, cobalt chrome, steels, aluminum, titanium and/or nickel alloys), gas atomized metal powder(s), thermoplastic powder(s) (e.g., polylactic acid (PLA), acrylonitrile butadiene styrene (ABS), and/or high-density polyethylene (HDPE)), photopolymer resin(s) (e.g., UV-curable photopolymers such as, for example PMMA), thermoset resin(s), thermoplastic resin(s), or any other suitable material that enables the functionality as described herein.

[00024] Depending on the metal particles’ type (e.g., silver, copper, gold, platinum, aluminum, etc.) and aspect ratio (referring to the ratio between the metal particle’s length and its respective thickness or diameter), in conductive ink compositions used for inkjet printing, maximum theoretical conductivity attainable may be a fraction of the same metal’s bulk conductivity, for example, between about 10% and about 90%, or between about 20% and about 80%, or, in yet another example, between about 30% and about 70%, or 50%, when compared to pure bulk metal.

[00025] For example, the conductive material used to form the traces is a silver nanoparticle. Silver (Ag) has the highest conductivity amongst conductive metals such as silver, copper, gold, aluminium and nickel (see e.g., Table I). Furthermore, silver remains conductive when oxidized, whereas copper does not. In the context of the disclosure, nanoparticles are defined particles with a volume average particle size (D3_,2, which can be central to obtaining the proper aspect ratio), below 1 micrometer, for example below about 0.5 micrometer, or below about 0.2 micrometer. Nanoparticles may be advantageous for ink jet printing applications, enabling low ink viscosities even with a very high conductive material content or loading (thus ensuring exceeding the 2D (on a single layer) and 3D (for trace-on-trace) bond percolation thresholds), as well as preventing clogging of nozzles on the inkjet print-head dispenser.

[00026] In practice, it was observed that obtaining the particle- specific (in other words, metal type [e.g., silver] and geometry [e.g., aspect ratio of at least 2:1]) theoretical conductivity is harder to obtain, the thicker the trace sought to be printed. In an example, a typical trace was formed using conductive ink with silver nanoparticles achieving 30% conductivity (relative to bulk silver) at a layer thickness (h) of 17pm (for a trace length resulting in total bulk silver weight of 0.5 Oz.), and the trace was measured having 1.0 Ohm in resistance. Using the same geometry and EQU. 1, to reduce the resistance to 0.25 Ohm or lower, typically, the trace thickness would be increased by a factor of at least 4 to roughly 68-71 pm (2.0 Oz silver, for the same trace length). However, when the trace thickness was increased to a thickness of 68-7 lpm, the observed resistance was higher than the calculated (using EQU 1), 0.25 ohm (W>0.25 Ohm).

[00027] Without being bound by theory, it is assumed that nanoparticles’ geometry, especially when the aspect ratio r is » 1 (r»l) affect the 2D bond percolation threshold (distinguishable from the hole percolation threshold), such that the higher the aspect ratio, the lower the 2D bond percolation threshold would be. For example the 2D bond percolation threshold for silver nanoparticles (having aspect ratio of, for example between about 2:1, to 5:1, or 10:1), is about 80 wt % based on total solids in the sintered trace (which corresponds to a fractional concentration of about 28% (v/v) in the ink), whereas for carbon nanotubes/nanoribbons (much higher aspect ratio - e.g., in the range of from 15:1 to 1,000: 1) the percolation threshold may already be at a few wt % (and even lower fractional volume). When the 2D bond percolation threshold is reached (or exceeded), the resistivity of the sintered trace decreases drastically and levels off even with further increases in conductive material loading (e.g., increase in nanoparticles fractional volume concentration). In the context of the disclosure, the 2D bond percolation threshold is defined as the point where the conductive materials in the trace come into contact and form a continuous trace in a X-Y plane of the trace.

[00028] Again without being bound by theory, while at a given trace thickness, exceeding the 2D bond percolation threshold will be enough to reduce resistivity to a given value (e.g., 30% of bulk metal conductivity), increasing the thickness will create a trace where the fractional volume concentration of metal nanoparticles is larger than the 2D bond percolation threshold, yet lower than the fractional volume concentration of the 3D bond percolation threshold (defined as the fractional volume concentration where conductive materials (particles) in the trace come into contact and form a continuous bulk in any direction in the trace).

[00029] Accordingly and in an exemplary implementation, and to cure some of the deficiencies in the current state of affairs, whether in multilayered AMEs formed by reductive methods or additive manufacturing methods, provided herein is a method of reducing trace resistivity between at least two connected components in an AME comprising: forming at least one trace on an intermediate layer (thereby forming an intermediate trace); forming at least one trace sized and configured to operably couple the at least two components on at least one of: an external apical, and external basal layer of the AME; and forming a predetermined number of at least one of: a blind via, and a buried via, the predetermined number of the vias, sized and configured to electrically couple the at least one trace on the intermediate layer (the intermediate trace), with the trace (in other words, the corresponding external trace), formed on at least one of: the external apical and external basal layer of the AME. To the extent that the AME has components coupled to any side facet, wall or aspect of the AME, the methods and systems disclosed can be utilized to likewise reduce trace reistivity coupling these side- mounted components with the rest of the AME topology.

[00030] In typical, extractive methods, a through hole is formed at first, in, for example, a copper-laminated laminate board bearing a copper foil and successively, the substrate is subjected to electroless copper (or other metals’, e.g., silver) plating treatment to form a plated-through hole. Next, a trace pattern is formed by etching the surface of the metal plated substrate in a predetermined pattern and then the surface of the trace pattern is roughened by electroless plating or etching and the like. Continuously, a resin insulating layer is formed on the trace pattern having a roughened surface and then subjected to exposure and development treatment to form an opening part for a via-hole (either through hole, buried, or blind vias) and after that, the interlaminar resin insulating layer is formed by depositing the dielectric resin, UV curing and optionally, main curing following the interlaminar resin insulating layer (in other words, intermediate layer) is typically subjected to roughening treatment by an acid or an oxidizing agent, a thin electroless plating film is formed on the electroless plating film, followed by thickening the thin electroless plating film by electroplating. After the plating resist is parted, etching can be carried out to form a trace pattern connected with a under-level trace pattern through the via-hole. When all intermediate layers are finally thus formed, a solder resist layer for protecting the conductor circuit is formed and the parts exposing the trace pattern for connection with electronic parts, e.g. an IC chip, or a mother board and the like, are plated and then a solder bump is formed by depositing (e.g., by printing, or otherwise dispensing) a solder paste to complete the manufacture of a built-up multilayered PCB .

[00031] Alternatively, in another example, through holes can be formed in a metal-clad laminate carrying metal foil thereon and, then, subjected to electroless metal plating to provide plated- through holes therein. The surface of the substrate board is then etched imagewise (in other words, according to a raster file), to provide a trace pattern thereon. This trace pattern is provided with a roughened surface by electroless plating or etching on this trace pattern and an intermediate layer resin insulating layer comprising epoxy resin, acrylic resin, fluoro-resin or a mixed resin thereof is constructed on said roughened surface. Then, via holes are formed by light exposure and development or laser processing and the resin is UV-cured and optionally post-cured to provide the objective intermediate layer resin insulating layer. This intermediate layer resin insulating layer is also subjected to surface roughening treatment and, then, a thin electroless plated metal layer is formed thereon. Thereafter, a plating resist is disposed on the electroless plated metal layer and a thick electroplated layer is then formed. The plating resist is then stripped off and etching is performed to provide a trace pattern connected to the lower-layer trace pattern by way of via holes. Here too, the sequence of the abovementioned steps is repeated and, then, as the outermost layer (in other words, the external apical layer, or external basal layer), a solder resist layer for protection of the trace pattern is formed. This solder resist layer is formed with openings and the conducting trace layer, in the areas corresponding to the openings is plated to provide contact pads. Solder bumps can then formed, or otherwise deposited on and/or around the contact pads to complete the manufacture of this example of buildup multilayer AME.

[00032] In another embodiment, inkjet printing is used to form the multilayer AMEs having traces with selectably lower resistivity. For example, disclosed herein is a computerized method for fabricating a trace having reduced resistivity between at least two connected components in a multilayer AME, using inkjet printer comprising: providing an inkjet printing system comprising: a first print head, operable to dispense a dielectric ink composition; a second print head operable to dispense a conductive ink composition; a conveyor, operably coupled to the first, and the second print heads configured to convey a substrate to each of the first, and the second print heads; and a computer aided manufacturing (“CAM”) module including a central processing module (CPM), the CAM being in communication with each of the first, and second print heads, wherein the CPM further comprising: at least one processor in communication with a non-transitory storage medium, storing thereon a set of executable instructions configured, when executed to cause the CPM to perform the steps of: receiving a 3D visualization file representing the multilayer AME having the reduced resistivity traces; and generating a file library having a plurality of files, each file representing a substantially 2D layer for printing the LPF and a metafile representing at least the printing order; wherein the CAM module is configured to control each of the conveyer, the first, and the second print heads; providing the dielectric ink composition, and the conductive ink composition; using the CAM module, obtaining from the library a first file representative of the first layer for printing the multilayer AME having the reduced resistivity traces, the first file comprising printing instructions for a pattern representative of at least one of: the dielectric ink, and the conductive ink; using the first print head, forming the pattern corresponding to the dielectric ink; using electromagnetic radiation source, curing the pattern corresponding to the dielectric ink representation in the 2D layer of the multilayer PCB; using the second print head, forming the pattern corresponding to the conductive ink; using heat, sintering the pattern corresponding to the conductive ink; using the CAM module, obtaining from the library a subsequent file representative of a subsequent layer for printing the multilayer AME having the reduced resistivity traces; the subsequent file comprising printing instructions for a pattern representative of at least one of: the dielectric ink, and the conductive ink; repeating the steps of: using the first print head, forming the pattern corresponding to the dielectric ink to the step of using the CAM module, obtaining from the 2D file library the subsequent, substantially 2D layer, wherein upon sintering of the conductive ink pattern in the final substantially 2D layer, the multilayered AME is configured to comprise: at least one intermediate trace on an intermediate layer; at least one external trace sized and configured to operably couple the at least two components on at least one of: an external apical and external basal layer of the multilayered AME; and a predetermined number of at least one of: a blind via, and a buried via, electrically coupling the intermediate trace with the external trace; and removing the substrate.

[00033] In an exemplary implementation, the term “dispensing” is used to designate the operation of the device from which the ink drops are dispensed, such as the print head acting as a dispenser. The dispenser can be, for example an apparatus for dispensing small quantities of liquid including micro-valves, piezoelectric dispensers, continuous-jet print-heads, boiling (bubble-jet) dispensers, and others affecting the temperature and properties of the fluid flowing through the dispenser. In an exemplary implementation, the term “print head” and the term “dispenser” are interchangeable.

[00034] Furthermore, also provided herein are exemplary implementations of multilayered AMEs comprising: at least one trace on an intermediate layer; a trace sized and configured to operably couple the at least two components on at least one of: an external apical and external basal layer of the PCB; and a predetermined number of at least one of: a blind via, and a buried via, electrically coupling the at least one trace on the intermediate layer with the trace on at least one of: the external apical and the external basal layer of the multilayered AME.

[00035] In the context of the disclosure, it is to be understood that via hole spanning the multilayered AME, across all the layers, e.g., from the apical external layer to the external basal layer (e.g., “the Z-direction”), is referred to as a “through-hole via”, which can be plated or filled (with a conductive metal used, for example, silver, copper, gold, aluminum, nickel, etc.), while via hole initiating at either the apical external layer, or the basal external layer; and terminate at any intermediate layer, is referred to as a “blind via”; and via hole between any two intermediate layers (regardless of being adjacent to each other), is referred to as a “buried via”.

[00036] A more complete understanding of the components, methods, and devices disclosed herein can be obtained by reference to the accompanying drawings. These figures (also referred to herein as “FIG.”) are merely schematic representations based on convenience and the ease of demonstrating the present disclosure, and are, therefore, not intended to indicate relative size and dimensions of the devices or components thereof, their relative size relationship and/or to define or limit the scope of the exemplary implementations. Although specific terms are used in the following description for the sake of clarity, these terms are intended to refer only to the particular structure of the exemplary implementations selected for illustration in the drawings, and are not intended to define or limit the scope of the disclosure. In the drawings and the following description below, it is to be understood that like numeric designations refer to components of like function. Likewise, cross sections are referred to on normal orthogonal coordinate apparatus having XYZ axis, such that Y axis refers to front-to-back, X axis refers to side-to-side, and Z axis refers to up-and-down.

[00037] Turning now to FIG.s 1, and 2, illustrating in FIG. 1, the current state of affairs when two conductive external traces 103i above a ground external basal plane 101 of multilayered PCB 100. Also illustrated are contact pads 104j, coupled to external basal (ground) plane 101 with plurality of through-hole vias 107k. It is noted, that dielectric/insulating intermediate layers are not shown in FIG.s 1 and 2, therefore the number of intermediate layers that would result in thickness h of multilayered PCB 100, in the Z direction (see e.g., FIG. 2), is implied and external traces 103i (FIG. 1), and 203i (FIG. 2) are assumed to be deposited on the external apical layer 102, 202 and/or the external basal layer 101, 201. Also, conductive external traces 103i are each illustrated as terminating in coupled contact pads 104j, where solder bumps can be disposed. As indicated (see e.g., EQU 1), in traditional fabrication processes, reducing resistivity can be done by increasing the surface area of traces 103i, by either increasing the width W of traces 103i (see e.g., FIG. 1), or increasing their length as illustrated in 303i, FIG. 3. Likewise, separate contact pads 106q, are also illustrated at close proximity to terminating contact pads 104j, and are coupled with through hole vias 107k, to basal external layer 102. [00038] There are however circumstances where neither option (increasing length and/or width of the trace) is viable, for example, where it is necessary to maintain as short a trace between components as possible (for example, in placing a bypass capacitor as close as possible to its corresponding IC), eliminating increasing length as in FIG. 3, and/or when high-density components’ surface is a requirement, such as in cell phones or high-density interconnect PCBs (HDI) where portability (requiring miniaturization), performance (requiring increased process speeds thus shorter traces) and components (requiring more leads in smaller footprint), all which create a demand for denser interconnect, with shorter track and gap dimensions, smaller diameter vias, and more buried vias.

[00039] Therefore, the methods provided herein for forming multilayer AMEs 200 having traces with selectably lower resistivity (when compared to the same length trace not fabricated using the methods disclosed herein), comprise (see e.g., FIG. 2) forming at least one intermediate trace 213i on an intermediate layer; forming external trace 203i sized and configured to operably couple the at least two components on at least one of: an external apical 202 (not shown - implied) and external basal layer 201 of the multilayer AME 200; and forming a predetermined number of at least one of: a blind via 224k, 233k and a buried via 225k, 226k , the predetermined number of vias sized and configured to electrically couple the at least one intermediate trace 213i with external trace 203i, formed on at least one of: the external apical 202 and external basal 201 layer of the multilayer AME 200.

[00040] Further, the method comprises forming at least one contact pad 204j, adapted, sized and configured to operably couple to component 500n at the terminus (end) of external trace 203 i sized and configured to operably couple the at least two components 500n, (not shown). Component 500n can be, for example one of: a Quad Flat Pack (QFP) package, a Thin Small Outline Package (TSOP), a Small Outline Integrated Circuit (SOIC) package, a Small Outline J-Lead (SOJ) package, a Plastic Leaded Chip Carrier (PLCC) package, a Wafer Level Chip Scale Package (WLCSP), a Mold Array Process-Ball Grid Array (MAPBGA) package, a Quad Flat No-Lead (QFN) package, a Land Grid Array (LGA) package, and a bypass capacitor.

[00041] Therefore, the combined resistivity W of: the predetermined number of at least one of: blind via 224k, 233k and buried via 225k, 226k; at least one intermediate trace 213i; and external trace 203i, is configured to provide resistivity W that is a predetermined fraction of the resistivity W of external trace(s) 103i, 203i alone, without the coupled predetermined number of at least one of: blind via(s) 224k, 233k and buried via(s) 225k, 226k; and at least one intermediate trace(s) 213i. Without being bound by theory, it is estimated, that initial thickness of external trace(s) 103i, 203i, would lead to a fixed and known resistivity for a given length, which, when substantially duplicated in intermediate trace(s) 213i and coupled with blind via 224k, 233k and a buried via 225k, 226k, would lead to a selectable and predictable resistivity of the resulting augmented trace 253i.

[00042] For example, the methods provided herein for forming multilayer PCBs 200 having traces with selectably lower resistivity further comprise forming plurality (2 or more) intermediated traces 213i, each intermediate trace disposed in a separate layer along vertical axis Z of multilayer PCB 200. Moreover, each intermediate trace 213i of the plurality of intermediated traces is coupled to an adjacent intermediate trace, forming plurality of buried vias 225k, 226k, between the immediately adjacent intermediate traces 213i. It is noted, that intermediate traces 213i can have width W that is different than any adjacent intermediate trace 213i and be wider or narrower, based on other parameters and factors associated with trace packing. Moreover, buried vias 225k, 226k, and blind vias 224k, 233k, do not necessarily need to be vertical, and can be slanted at an angle off vertical (e.g., the Z direction, see FIG. 2). Likewise, trellis 253 (also referred to, under certain examples as lattice) formed by the coupled traces does not form even opening throughout.

[00043] As illustrated in FIG. 2, intermediate traces 213i each terminate in a terminal buried via 226k, while intermediate trace 213i, immediately coupled to external trace 203i, with terminal blind via 233k. When there are large number of intermediate traces 213i, and in order not to impede conductivity to contact pad 204j or external trace 203i, it may be advantageous to have terminal blind via 233k (an/or non-terminal blind vias 224k) formed to have a cross section with an area that is larger (e.g., having a larger diameter) than each non-terminal buried via 225k. Similarly, in an example, terminal buried via 226k will likewise formed to have a cross section with an area that is larger (e.g., having a larger diameter) than each non-terminal buried via 225k. Furthermore, in another example, the cross section of each non-terminal buried via 225k will increase the closer the intermediate trace 213i is to external trace 203i, in effect forming a single conical blind via with the base external trace 203 i.

[00044] As illustrated in FIG. 2, the methods provided herein for forming multilayer PCBs 200 having traces with selectably lower resistivity are configured, when finished to have external trace 203i, the at least one of: predetermined number of at least one of: the non-terminal blind via 224k, non-terminal buried via 225k, terminal buried vias 226k, and terminal blind vias 233k and plurality of intermediate traces 213i form lattice 253i extending vertically (in the Z direction) from external trace 203i. The term “lattice” as used herein refers to open framework made of strips of metal (e.g., intermediate traces 213i and external trace(s) 203i), overlapped or overlaid in a regular pattern, connected by a regular pattern of vertical members (for example, buried vias 225k, 226k and blind vias 224k, 233k).

[00045] The method of forming the PCB’s using the computerized ink jet printing systems disclosed herein can comprise a step of providing a substrate (e.g., a peelable substrate such as a film). The print head (and derivatives thereof; are to be understood to refer to any device or technique that deposits, transfers or creates material on a surface in a controlled manner) depositing the dielectric ink, can be configured to provide the ink droplet(s) upon demand, in other words, as a function of various process parameters such as conveyor speed, desired PCB sub-layer thickness, whether the via, or heat pipe is filled or plated, or their combination. It is noted, that intermediate trace(s) 213i is (are) not disposed at the same thickness of the PCB sub-layer determined by the process-specific sub-layer thickness, and can be disposed at the same or variable thickness as the sub-layer thickness.

[00046] In an exemplary implementation, a software feature is added that will allow the selection of a conductive trace in, for example, a Gerber file prior to initiation of fabrication. The software feature will create an additional, embedded blank signal layers with the selected external trace(s) and a buried/blind via drill(s) (e.g, in Excellon format) file with vias that connects the copied layers containing the duplicated traces with the original trace(s) layer on the external signal layer. The input parameters for forming the traces having reduced resistivity can be, for example at least one of: conductive layer height of the embedded traces; dielectric layer height between embedded layers (copies); number of copies (in other words, number of embedded blank signal layers; via diameter, width of embedded traces in the copies (referring to traces that are disposed on internal, embedded signal layers with coupled traces that are substantially wider than the external trace(s) to which they are coupled), and via pitch (in other words, vias that are not normal to the surface of the PCB, but are rather slanted in a predetermined angle to compensate for other component routing vias or other parameters). The copies can then be configured as internal signal layers and internal vias at the print job.

[00047] The substrate, used in the computerized ink jet printing systems disclosed herein can be, for example removable or peelable, can also be a relatively rigid material, for example, glass or crystal (e.g., sapphire), Alternatively, the substrate may be a flexible (e.g., Tollable) substrate (or film) to allow for an easy peeling of the substrate from the PCB, for example, poly(ethylenenaphthalate) (PEN), polyimide (e.g. KAPTONE^® by DuPont), silicon polymers, poly(ethyleneterphtalate) (PET), poly(tetrafluoroethylene) (PTFE) films etc. [00048] Other functional steps (and therefore means for affecting these steps) may be taken when using the computerized ink jet printing systems disclosed herein before or after the first or second print heads (e.g., for sintering the conductive layer). These steps may include (but not limited to): a heating step (affected by a heating element such as a chuck, and/or hot air); photobleaching (using e.g., a UV light source and a photo mask); drying (e.g., using vacuum region, or heating element); (reactive) plasma deposition (e.g., using pressurized plasma gun and a plasma beam controller); cross linking (e.g., by selectively initiated through the addition of a photoacid such as {4- [(2- hydroxy tetradecyl)-oxyl] -phenyl }-phenyliodonium hexafluoro antimonate to a polymer solutions prior to coating or used as dispersant with the metal precursor or nanoparticles); annealing, or facilitating redox reactions.

[00049] Formulating the conductive and/or dielectric ink composition(s), when using the computerized inkjet printing systems disclosed herein may take into account the requirements, if any, imposed by the deposition tool and the surface characteristics (e.g., at least one of hydrophilic or hydrophobic, and the surface energy) of the (optionally removable) substrate. Using ink-jet printing with a piezo head for example, the viscosity of either the conductive ink and/or dielectric ink (measured at 20°C) can be, for example, not lower than about 5 cP, e.g., not lower than about 8 cP, or not lower than about 10 cP, and not higher than about 30 cP, e.g., not higher than about 20 cP, or not higher than about 15 cP. The conductive ink, and/or dielectric ink can each be configured (e.g., formulated) to have a dynamic surface tension (referring to a surface tension when an ink-jet ink droplet is formed at the print-head aperture) of between about 25 mN/m and about 35 mN/m, for example between about 29 mN/m and about 31 mN/m measured by maximum bubble pressure tensiometry at a surface age of 50 ms and at 25°C. The dynamic surface tension can be formulated to provide a contact angle with the peelable substrate or the dielectric layer(s) of between about 100 ⁰ and about 165°.

[00050] In an exemplary implementation, the ink-jet ink systems compositions and methods for forming a multilayer AME having traces with selectably lower resistivity, can be patterned by expelling droplets of the liquid ink-jet ink provided herein from an orifice one-at-a-time, as the print- head (or the substrate/chuck) is maneuvered, for example in two (X-Y) (it should be understood that the print head can also move in the Z axis) dimensions at a predetermined distance above the substrate or any subsequent layer. The ink-jet print heads provided used in the methods described herein can provide a minimum layer film thickness equal to or less than about 3 pm- 10,000 pm [00051] In an exemplary implementation, the volume of each droplet of the conductive ink, and/or the dielectric ink, can range from 0.5 to 300 picoLiter (pL), for example 1-4 pL and depended on the strength of the driving pulse and the properties of the ink. The waveform to expel a single droplet can be a 10V to about 70 V pulse, or about 16V to about 20V, and can be expelled at frequencies between about 5 kHz and about 500 kHz.

[00052] The dielectric ink compositions described herein can have in addition, a continuous phase comprising: a cross-linking agent, a co-monomer, a co-oligomer, co-polymer or a composition comprising one or more of the foregoing. Likewise, the oligomer and/or polymer backbone can be induced to form cross links by contacting the polymer with an agent that will form free radicals on the backbone, thereby allowing for cross-linking sites. In an exemplary implementation, the cross- linking agent, co-monomer, co-oligomer, co-polymer or a composition comprising one or more of the foregoing can be a part, or configured to form a solution, emulsion, gel or suspension within the continuous phase.

[00053] In an exemplary implementation, the continuous phase used in the AMEs (PCBs, FPCs and HDI circuits) fabricated using the disclosed methods for forming a multilayer AME having traces with selectably lower resistivity, can comprise: multifunctional acrylate monomer, oligomer, polymer or their combination; a cross-linking agent; and a radical photoinitiator, and can be partially or entirely soluble in the continuous phase.

[00054] Initiating the dielectric resin backbone polymerization can be done using an initiator, for example benzoyl peroxide (BP) and other peroxide-containing compounds. The term "initiator" as used herein generally refers to a substance that initiates a chemical reaction, specifically any compound which initiates polymerization, or produces a reactive species which initiates polymerization, including, for example and without limitation, co-initiators and/or photoinitiator(s).

[00055] In another embodiment, the dielectric resin used in the ink compositions described, comprises active and/or live components of a polymer capable of undergoing photoinitiation using a photoinitiator. Such live monomer, live oligomer, live polymer or their combination capable of undergoing photoinitiation can be for example, multifunctional acrylates, for example a multifunctional acrylate that can be multifunctional acrylate is selected from the group consisting of 1,2-ethanediol diacrylate, 1,3-propanediol diacrylate, 1,4-butanediol diacrylate, 1,6-hexanediol diacrylate, dipropylene glycol diacrylate, neopentyl glycol diacrylate, ethoxylated neopentyl glycol diacrylate, propoxylated neopentyl glycol diacrylate, tripropylene glycol diacrylate, bisphenol-A- diglycidyl ether diacrylate, hydroxypivalic acid neopentanediol diacrylate, ethoxylated bisphenol-A- diglycidyl ether diacrylate, polyethylene glycol diacrylate, trimethylolpropane triacrylate, ethoxylated trimethylolpropane triacrylate, propoxylated trimethylolpropane triacrylate, propoxylated glycerol triacrylate, tris(2-acryloyloxyethyl)isocyanurate, pentaerythritol triacrylate, ethoxylated pentaerythritol triacrylate, pentaerythritol tetraacrylate, ethoxylated pentaerythritol tetraacrylate, ditrimethylolpropane tetraacrylate, dipentaerythritol pentaacrylate and dipentaerythritol hexaacrylate.

[00056] Photoinitiators that can be used with the multifunctional acrylates described herein can be, for example radical photoinitiator. These radical photoinitiators can be, for example Irgacure® 500 from CIBA SPECIALTY CHEMICAL and Darocur® 1173, Irgacure® 819, Irgacure® 184, TPO- L (ethyl(2,4,6, trimethyl benzoil) phenyl phosphinate) benzophenone and acetophenone compounds and the like. For example, the radical photoinitiator can be cationic photo-initiator, such as mixed triarylsulfonium hexafluoroantimonate salts. Another example of the radical photoinitiator used in the active continuous phase described herein, can be 2-ispropylthioxanthone.

[00057] The terms “live monomer”, “live oligomer”, “polymer” or their counterparts (co monomer e.g., ) combination refers in an exemplary implementation to a monomer, a short group of monomers or a polymer having at least one functional group capable of forming a radical reaction (in other words, the reaction can be continued and is not otherwise terminated by an end-group).

[00058] The cross-linking agent used in the compositions, systems and methods described herein, for forming a multilayer AME having traces with selectably lower resistivity, can be, for example, a primary or secondary polyamine and adducts thereof, or in another example, an anhydride, a polyamide, a C4-C30 polyoxyalkylene in which the alkylene groups each independently comprise 2 to 6 carbon atoms, or a composition comprising one or more of the foregoing.

[00059] The conductive and/or the dielectric ink compositions, may each require the presence of a surfactant and optionally a cosurfactants. The surfactants and/or cosurfactants may be cationic surfactants, anionic surfactants, non-ionic surfactant and amphiphilic copolymers, such as block copolymers.

[00060] Moreover, the dielectric (insulating) layer portion can have a substantially uniform thickness throughout, thereby creating a substantially planar (e.g., flat) surface for receiving an additional conductive circuit pattern. The dielectric layer may be an UV curable adhesive or other polymer material. For example, the dielectric ink comprises a UV curable polymer. Other dielectric polymers such as, for example, polyester (PES), polyethylene (PE), polyvinyl alcohol (PVOH) and poly-methyl methacrylate (PMMA), Poly(vinylpirrolidone) (PVP, water soluble and may be beneficial not to clog the print head orifice). Other dielectric materials can be photoresistive polymers, for example, SU-8 based polymers, polymer-derived ceramics or their combination and copolymers can also be used.

[00061] The ink-jet systems used to implement the methods provided herein, can further comprises a computer aided manufacturing (“CAM”) module, the module comprising a data processor, a non-volatile memory, and a set of executable instructions stored on the non-volatile memory, which when executed are configured to cause the at least one processor to: receive a 3D visualization file representing the printed circuit board comprising the infrastructure elements; generate a library of files, each file represents at least one, substantially 2D layer for printing the multilayered AME having traces with selectably lower resistivity, creating a substantially 2D representation image; receive a selection of parameters related to the multilayered AME having traces with selectably lower resistivity; and alter the file representing the at least one, substantially 2D layer based on at least one of the selection of parameters, wherein the CAM module is configured to control each of the first and second print heads. Accordingly, the set of executable instructions are further configured, when executed to cause the processor to generate a library of a plurality of subsequent layers’ files from the 3D visualization file. Each subsequent file represents a substantially two dimensional (2D) subsequent layer for printing a subsequent portion of the PCB comprising the plurality of embedded passive and active components, wherein each subsequent layer file is indexed by printing order. Furthermore, the set of executable instructions can be configured to parse out the conductive and dielectric portions of each 2D layer, and create a unique pattern per each layer from the first and on, that will instruct the proper print head to print that portion of the 2D layer.

[00062] The CAM module can therefore comprise: a 2D file library storing the files converted from the 3D visualization files of the printed circuit boards including built-in passive and embedded active components. The term “library, as used herein, refers to the collection of 2D layer files derived from the 3D visualization file, containing the information necessary to print each conductive and dielectric pattern, which is accessible and used by the data collection application, which can be executed by the computer-readable media. Each file comprises at least a printing order for the conductive ink (Cl) and the dielectric ink (DI). The layer files in the library will have the printing instructions for both the Cl and DI in the same layer, however, the printing order of each pattern corresponding to the Cl and BI may change from layer to layer, and form a part of the file library. The CAM further comprises a processor in communication with the library; a non-transitory storage device storing a set of operational instructions for execution by the processor; a micromechanical inkjet print head or heads in communication with the processor and with the library; and a print head (or, heads’) interface circuit in communication with the 2D file library, the non-transitory storage device and the micromechanical inkjet print head or heads , the 2D file library configured to provide operation parameters to the printer, specific to a functional (printed) layer.

[00063] Accordingly, the step of using the first print head is preceded by a step of: using the CAM module, obtaining a generated file from the library, the first file representing a first, substantially 2D layer of the multilayered AME having traces with selectably lower resistivity for printing, the 2D layer comprising a pattern representative of the dielectric ink, and the conductive ink, wherein the parameters used in the selection of parameters related to the multilayered AME having traces with selectably lower resistivity comprise, for example: the desired resistivity, the number of intermediate traces 213i, the number of terminal blind vias 233k (relating to the number of the coupled contact pads 204j), the number of non-terminal buried vias 225k, the number of terminal buried vias 226k, their respective diameter and a combination thereof.

[00064] The 3D visualization file representing the multilayered AME having traces with selectably lower resistivity, can be: an an ODB, an ODB++, an. asm, an STL, an IGES, a STEP, a Catia, a SolidWorks, a Autocad, a ProE, a 3D Studio, a Gerber, a Rhino a Altium, an Oread, an or a file comprising one or more of the foregoing; and wherein file that represents at least one, substantially 2D layer (and uploaded to the library) can be, for example, a JPEG, a GIF, a TIFF, a BMP, a PDF file, or a combination comprising one or more of the foregoing.

[00065] In addition, the computer program, can comprise program code means for carrying out the steps of the methods described herein, as well as a computer program product comprising program code means stored on a medium that can be read by a computer. Non-transitory storage device(s) as used in the methods described herein can be any of various types of non-volatile memory devices or storage devices (in other words, memory devices that do not lose the information thereon in the absence of power). The term “memory device” is intended to encompass an installation medium, e.g., a CD-ROM, floppy disks, or tape device or a non-volatile memory such as a magnetic media, e.g., a hard drive, optical storage, or ROM, EPROM, FLASH, etc. The memory device may comprise other types of memory as well, or combinations thereof. In addition, the memory medium may be located in a first computer in which the programs are executed (e.g., the 3D inkjet printer provided), and/or may be located in a second different computer which connects to the first computer over a network, such as the Internet. In the latter instance, the second computer may further provide program instructions to the first computer for execution. The term “memory device” can also include two or more memory devices which may reside in different locations, e.g., in different computers that are connected over a network. Accordingly, for example, the bitmap library can reside on a memory device that is remote from the CAM module coupled to the 3D inkjet printer provided, and be accessible by the 3D inkjet printer provided (for example, by a wide area network)

[00066] The use of the term “module” does not imply that the components or functionality described or claimed as part of the module are all configured in a (single) common package. Indeed, any or all of the various components of a module, whether control logic or other components, can be combined in a single package or separately maintained and can further be distributed in multiple groupings or packages or across multiple (remote) locations and devices. Furthermore, in certain exemplary implementations, the term “module” refers to a monolithic or distributed hardware unit.

[00067] The term "comprising" and its derivatives, as used herein, are intended to be open ended terms that specify the presence of the stated features, elements, components, groups, integers, and/or steps, but do not exclude the presence of other unstated features, elements, components, groups, integers and/or steps. The foregoing also applies to words having similar meanings such as the terms, "including", "having" and their derivatives.

[00068] Unless specifically stated otherwise, as apparent from the following discussions, it is appreciated that throughout the specification discussions utilizing terms such as “processing,” “loading,” “in communication,” “detecting,” “calculating,” “determining”, “analyzing,” or the like, refer to the action and/or processes of a computer or computing system, or similar electronic computing device, that manipulate and/or transform data represented as physical, such as a transistor architecture into other data similarly represented as physical structural (in other words, resin or metal/metallic) layers.

[00069] The Computer-Aided Design/Computer- Aided Manufacturing (CAD/CAM) generated information associated with the AME including traces having reduced resistivity herein to be fabricated, which is used in the methods, programs and libraries can be based on converted CAD/CAM data packages can be, for example, IGES, DXF, DWG, DMIS, NC files, GERBER® files, EXCELLON®, STL, EPRT files, an ODB, an ODB++, an.asm, an STL, an IGES, a STEP, a Catia, a SolidWorks, a Autocad, a ProE, a 3D Studio, a Gerber, a Rhino a Altium, an Oread, an Eagle file or a package comprising one or more of the foregoing. Additionally, attributes attached to the graphics objects transfer the meta-information needed for fabrication and can precisely define the PCBs. Accordingly and in an exemplary implementation, using pre-processing algorithm, GERBER®, EXCELLON®, DWG, DXF, STL, EPRT ASM, and the like as described herein, are converted to 2D files.

[00070] All ranges disclosed herein are inclusive of the endpoints, and the endpoints are independently combinable with each other. “Combination” is inclusive of blends, mixtures, alloys, reaction products, and the like. The terms “a”, “an” and “the” herein do not denote a limitation of quantity, and are to be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. The suffix “(s)” as used herein is intended to include both the singular and the plural of the term that it modifies, thereby including one or more of that term (e.g., the trace(s) includes one or more trace). Reference throughout the specification to “one embodiment”, “another embodiment”, “an exemplary implementation”, and so forth, when present, means that a particular element (e.g., feature, structure, and/or characteristic) described in connection with the embodiment is included in at least one embodiment described herein, and may or may not be present in other exemplary implementations. In addition, it is to be understood that the described elements may be combined in any suitable manner in the various exemplary implementations.

[00071] All ranges disclosed herein are inclusive of the endpoints, and the endpoints are independently combinable with each other. Furthermore, the terms “first,” “second,” and the like, herein do not denote any order, quantity, or importance, but rather are used to denote one element from another.

[00072] Likewise, the term "about" means that amounts, sizes, formulations, parameters, and other quantities and characteristics are not and need not be exact, but may be approximate and/or larger or smaller, as desired, reflecting tolerances, conversion factors, rounding off, measurement error and the like, and other factors known to those of skill in the art. In general, an amount, size, formulation, parameter or other quantity or characteristic is "about" or "approximate" whether or not expressly stated to be such.

[00073] Accordingly, in an exemplary implementation, provided herein is a method of reducing trace resistivity between at least two connected components in a multilayer additively manufactured electronic (AME) comprising: forming at least one trace on an intermediate layer, thereby forming an intermediate trace; forming a trace sized and configured to operably couple the at least two components on at least one of: an external apical layer, and external basal layer of the multilayer AME, thereby forming at least one external trace; and forming a predetermined number of at least one of: a blind via, and a buried via, the predetermined number of vias sized and configured to electrically couple the at least one intermediate trace and a corresponding external trace of the multilayer AME, wherein the method further (i) comprising: forming at least one contact pad, adapted, sized and configured to operably couple to a component at one of the terminus of the external trace, wherein (ii) the combined resistivity of: the predetermined number of at least one of: the blind via, and the buried via; the at least one intermediate trace; and the external trace is configured to provide resistivity that is a predetermined fraction of the resistivity of the external trace without the intermediate traces, further (iii) comprising forming a plurality of intermediated traces, each intermediate trace disposed in a separate layer along a vertical axis of the multilayer AME, (iv) coupling each intermediate trace of the plurality of intermediated traces to an adjacent intermediate trace forming a plurality of buried vias between adjacent intermediate traces, (v) forming a terminal buried via at the terminus of each of the intermediate traces, each terminal buried via formed to have a cross section with an area that is larger than each of a non-terminal buried via, (vi) forming a terminal blind via at each terminus of the intermediate trace immediately adjacent to the external trace, the terminal blind via formed to have a cross section with an area that is larger than each of a non-terminal buried via, wherein (vii) the external trace, the at least one of: predetermined number of at least one of: the blind via, and the buried via, the terminal buried vias, the terminal blind vias and the plurality of intermediate traces form a lattice extending vertically from the external trace, into the multilayered AME, wherein (viii) the formed intermediate traces have a width that is wider than the width of the external trace, and wherein (ix) at least one of the plurality of buried vias between the adjacent intermediate traces is slanted.

[00074] In another exemplary implementation, provided herein is a multilayered additively manufactured electronics (AME) comprising: at least one intermediate trace on an intermediate layer; at least one external trace sized and configured to operably couple the at least two components on at least one of: an external apical and external basal layer of the AME; and a predetermined number of at least one of: a blind via, and a buried via, electrically coupling the intermediate trace with the external trace, wherein (x) the external trace terminates on at least one end in a contact pad, adapted, sized and configured to operably couple to a component, (xi) the predetermined number of at least one of: the blind via, and the buried via are configured to provide resistivity that is fraction of the resistivity of the external trace without the at least one intermediate trace, wherein (xii) the multilayer AME comprises a plurality of intermediated traces, each intermediate trace disposed in a separate intermediate layer along a vertical axis of the multilayer AME, (xiii) each intermediate trace of the plurality of intermediated traces is coupled to an adjacent intermediate trace with a plurality of buried vias between the immediately adjacent intermediate traces, (xiv) each intermediate trace of the plurality of intermediated traces terminates in a terminal buried via, the terminal buried via having a cross section with an area that is larger than each of a non-terminal buried via (xv) the intermediate layer immediately adjacent to the external trace, terminates in a terminal blind via formed to have a cross section with an area that is larger than each of a non-terminal buried vias, and wherein (xvi) the external trace, the at least one of: predetermined number of at least one of: the blind via, and the buried via, the terminal buried vias, the terminal blind vias and the plurality of intermediate traces form a lattice extending vertically from the external trace, into the multilayered AME.

[00075] In yet another exemplary implementation, provided herein is a computerized method for fabricating a trace having reduced resistivity between at least two connected components in a multilayer additively manufactured electronics (AME), using inkjet printer comprising: providing an inkjet printing system comprising: a first print head, operable to dispense a dielectric ink composition; a second print head operable to dispense a conductive ink composition; a conveyor, operably coupled to the first, and the second print heads configured to convey a substrate to each of the first, and the second print heads; and a computer aided manufacturing (“CAM”) module including a central processing module (CPM), the CAM being in communication with each of the first, and second print heads, wherein the CPM further comprising: at least one processor in communication with a non- transitory storage medium, storing thereon a set of executable instructions configured, when executed to cause the CPM to perform the steps of: receiving a 3D visualization file representing the multilayer AME having the reduced resistivity traces; and generating a file library having a plurality of files, each file representing a substantially 2D layer for printing the LPF and a metafile representing at least the printing order; wherein the CAM module is configured to control each of the conveyer, the first, and the second print heads; providing the dielectric ink composition, and the conductive ink composition; using the CAM module, obtaining from the library a first file representative of the first layer for printing the multilayer AME having the reduced resistivity traces, the first file comprising printing instructions for a pattern representative of at least one of: the dielectric ink, and the conductive ink; using the first print head, forming the pattern corresponding to the dielectric ink; using electromagnetic radiation source, curing the pattern corresponding to the dielectric ink representation in the 2D layer of the multilayer AME; using the second print head, forming the pattern corresponding to the conductive ink; using heat, sintering the pattern corresponding to the conductive ink; using the CAM module, obtaining from the library a subsequent file representative of a subsequent layer for printing the multilayer AME having the reduced resistivity traces; the subsequent file comprising printing instructions for a pattern representative of at least one of: the dielectric ink, and the conductive ink; repeating the steps of: using the first print head, forming the pattern corresponding to the dielectric ink to the step of using the CAM module, obtaining from the 2D file library the subsequent, substantially 2D layer, wherein upon sintering of the conductive ink pattern in the final substantially 2D layer, the multilayered AME is configured to comprise: at least one intermediate trace on an intermediate layer; at least one external trace sized and configured to operably couple the at least two components on at least one of: an external apical and external basal layer of the multilayered AME; and a predetermined number of at least one of: a blind via, and a buried via, electrically coupling the intermediate trace with the external trace; and removing the substrate, wherein (xvii) the external trace terminates on at least one end in a contact pad, adapted, sized and configured to operably couple to a component, (xviii) the predetermined number of at least one of: the blind via, and the buried via are configured to provide resistivity that is fraction of the resistivity of the external trace, wherein upon sintering of the conductive ink in the final substantially 2D layer (xix), the multilayered AME is configured to comprise a plurality of intermediated traces, each intermediate trace disposed in a separate layer along a vertical axis of the multilayer AME, (xx) each intermediate trace of the plurality of intermediated traces is coupled to an adjacent intermediate trace with a plurality of buried vias between the immediately adjacent intermediate traces (xxi) each intermediate trace of the plurality of intermediated traces terminates in a terminal buried via, the terminal buried via having a cross section with an area that is larger than each of a non-terminal buried via, (xxii) the intermediate layer immediately adjacent to the external trace, terminates in a terminal blind via formed to have a cross section with an area that is larger than each the non-terminal buried vias, (xxiii) the external trace, the at least one of: predetermined number of at least one of: the blind via, and the buried via, the terminal buried vias, the terminal blind vias and the plurality of intermediate traces from a lattice extending vertically from the external trace, into the multilayered AME, (xxiv) the formed intermediate traces have a width that is wider than the width of the external trace, and (xxv) whereupon sintering of the conductive ink pattern in the final substantially 2D layer, at least one of the plurality of buried vias between the adjacent intermediate traces is slanted.

[00076] The above examples and description have of course been provided only for the purpose of illustration, and are not intended to limit the disclosed technology in any way. As will be appreciated by the skilled person, the disclosed technology can be carried out in a great variety of ways, employing more than one technique from those described above, all without exceeding the scope of the invention.

Claims

What is claimed:

1. A method of reducing trace resistivity between at least two connected components in a multilayer additively manufactured electronic (AME) comprising: a. forming at least one trace on an intermediate layer, thereby forming an intermediate trace; b. forming a trace sized and configured to operably couple the at least two components on at least one of: an external apical layer, and external basal layer of the multilayer AME, thereby forming at least one external trace; and c. forming a predetermined number of at least one of: a blind via, and a buried via, the predetermined number of vias sized and configured to electrically couple the at least one intermediate trace and a corresponding external trace of the multilayer AME.

2. The method of claim 1, further comprising: forming at least one contact pad, adapted, sized and configured to operably couple to a component at the terminus of the external trace.

3. The method of claim 2, wherein the combined resistivity of: the predetermined number of at least one of: the blind via, and the buried via; the at least one intermediate trace; and the external trace is configured to provide resistivity that is a predetermined fraction of the resistivity of the external trace without the intermediate traces.

4. The method of claim 3, further comprising forming a plurality of intermediated traces, each intermediate trace disposed in a separate layer along a vertical axis of the multilayer AME.

5. The method of claim 4, further comprises coupling each intermediate trace of the plurality of intermediated traces to an adjacent intermediate trace forming a plurality of buried vias between adjacent intermediate traces.

6. The method of claim 5, further comprising forming a terminal buried via at the terminus of each of the intermediate traces, each terminal buried via formed to have a cross section with an area that is larger than each of a non-terminal buried via.

7. The method of claim 6, further comprising forming a terminal blind via at each terminus of the intermediate trace immediately adjacent to the external trace, the terminal blind via formed to have a cross section with an area that is larger than each of a non-terminal buried via.

8. The method of claim 7, wherein: the external trace, the at least one of: predetermined number of at least one of: the blind via, and the buried via, the terminal buried vias, the terminal blind vias and the plurality of intermediate traces form a lattice extending vertically from the external trace, into the multilayered AME.

9. The method of claim 4, wherein the formed intermediate traces have a width that is wider than the width of the external trace.

10. The method of claim 5, wherein at least one of the plurality of buried vias between the adjacent intermediate traces is slanted.

11. A multilayered AME comprising: a. at least one intermediate trace on an intermediate layer; b. at least one external trace sized and configured to operably couple the at least two components on at least one of: an external apical and external basal layer of the AME; and c. a predetermined number of at least one of: a blind via, and a buried via, electrically coupling the intermediate trace with the external trace.

12. The multilayered AME of claim 11, wherein the external trace terminates on at least one end in a contact pad, adapted, sized and configured to operably couple to a component.

13. The multilayered AME of claim 12, wherein the predetermined number of at least one of: the blind via, and the buried via are configured to provide resistivity that is fraction of the resistivity of the external trace without the at least one intermediate trace.

14. The multilayered AME of claim 13, wherein the multilayer AME comprises a plurality of intermediated traces, each intermediate trace disposed in a separate intermediate layer along a vertical axis of the multilayer AME.

15. The multilayered AME of claim 14, wherein each intermediate trace of the plurality of intermediated traces is coupled to an adjacent intermediate trace with a plurality of buried vias between the immediately adjacent intermediate traces.

16. The multilayered AME of claim 15, wherein each intermediate trace of the plurality of intermediated traces terminates in a terminal buried via, the terminal buried via having a cross section with an area that is larger than each of a non-terminal buried via.

17. The multilayered AME of claim 16, wherein the intermediate layer immediately adjacent to the external trace, terminates in a terminal blind via formed to have a cross section with an area that is larger than each of a non-terminal buried vias.

18. The multilayered AME of claim 17, wherein the external trace, the at least one of: predetermined number of at least one of: the blind via, and the buried via, the terminal buried vias, the terminal blind vias and the plurality of intermediate traces form a lattice extending vertically from the external trace, into the multilayered AME.

19. A computerized method for fabricating a trace having reduced resistivity between at least two connected components in a multilayer additively manufactured electronics (AME), using inkjet printer comprising: a. providing an inkjet printing system comprising: i. a first print head, operable to dispense a dielectric ink composition; ii. a second print head operable to dispense a conductive ink composition; iii. a conveyor, operably coupled to the first, and the second print heads configured to convey a substrate to each of the first, and the second print heads; and iv. a computer aided manufacturing (“CAM”) module including a central processing module (CPM), the CAM being in communication with each of the first, and second print heads, wherein the CPM further comprising: at least one processor in communication with a non-transitory storage medium, storing thereon a set of executable instructions configured, when executed to cause the CPM to perform the steps of: receiving a 3D visualization file representing the multilayer AME having the reduced resistivity traces; and generating a file library having a plurality of files, each file representing a substantially 2D layer for printing the LPF and a metafile representing at least the printing order; wherein the CAM module is configured to control each of the conveyer, the first, and the second print heads; b. providing the dielectric ink composition, and the conductive ink composition; c. using the CAM module, obtaining from the library a first file representative of the first layer for printing the multilayer AME having the reduced resistivity traces, the first file comprising printing instructions for a pattern representative of at least one of: the dielectric ink, and the conductive ink; d. using the first print head, forming the pattern corresponding to the dielectric ink; e. using electromagnetic radiation source, curing the pattern corresponding to the dielectric ink representation in the 2D layer of the multilayer AME; f. using the second print head, forming the pattern corresponding to the conductive ink; g. using heat, sintering the pattern corresponding to the conductive ink; h. using the CAM module, obtaining from the library a subsequent file representative of a subsequent layer for printing the multilayer AME having the reduced resistivity traces; the subsequent file comprising printing instructions for a pattern representative of at least one of: the dielectric ink, and the conductive ink; i. repeating the steps of: using the first print head, forming the pattern corresponding to the dielectric ink to the step of using the CAM module, obtaining from the 2D file library the subsequent, substantially 2D layer, wherein upon sintering of the conductive ink pattern in the final substantially 2D layer, the multilayered AME is configured to comprise: i. at least one intermediate trace on an intermediate layer; ii. at least one external trace sized and configured to operably couple the at least two components on at least one of: an external apical and external basal layer of the multilayered AME; and iii. a predetermined number of at least one of: a blind via, and a buried via, electrically coupling the intermediate trace with the external trace; and j. removing the substrate.

20. The method of claim 19, wherein the external trace terminates on at least one end in a contact pad, adapted, sized and configured to operably couple to a component.

21. The method of claim 20, wherein the predetermined number of at least one of: the blind via, and the buried via are configured to provide resistivity that is fraction of the resistivity of the external trace.

22. The method of claim 19, whereupon sintering of the conductive ink in the final substantially 2D layer, the multilayered AME is configured to comprise a plurality of intermediated traces, each intermediate trace disposed in a separate layer along a vertical axis of the multilayer AME.

23. The method of claim 22, whereupon sintering of the conductive ink pattern in the final substantially 2D layer, each intermediate trace of the plurality of intermediated traces is coupled to an adjacent intermediate trace with a plurality of buried vias between the immediately adjacent intermediate traces.

24. The method of claim 23, whereupon sintering of the conductive ink pattern in the final substantially 2D layer, each intermediate trace of the plurality of intermediated traces terminates in a terminal buried via, the terminal buried via having a cross section with an area that is larger than each of a non-terminal buried via.

25. The method of claim 24, whereupon sintering of the conductive ink pattern in the final substantially 2D layer, the intermediate layer immediately adjacent to the external trace, terminates in a terminal blind via formed to have a cross section with an area that is larger than each the non terminal buried vias.

26. The method of claim 25, whereupon sintering of the conductive ink pattern in the final substantially 2D layer, the external trace, the at least one of: predetermined number of at least one of: the blind via, and the buried via, the terminal buried vias, the terminal blind vias and the plurality of intermediate traces from a lattice extending vertically from the external trace, into the multilayered AME.

27. The method of claim 22, whereupon sintering of the conductive ink pattern in the final substantially 2D layer, the formed intermediate traces have a width that is wider than the width of the external trace.

28. The method of claim 23, whereupon sintering of the conductive ink pattern in the final substantially 2D layer, at least one of the plurality of buried vias between the adjacent intermediate traces is slanted.