WO2021017369A1 - Insulated gate bipolar transistor and manufacturing method therefor - Google Patents

Insulated gate bipolar transistor and manufacturing method therefor Download PDF

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Publication number
WO2021017369A1
WO2021017369A1 PCT/CN2019/124857 CN2019124857W WO2021017369A1 WO 2021017369 A1 WO2021017369 A1 WO 2021017369A1 CN 2019124857 W CN2019124857 W CN 2019124857W WO 2021017369 A1 WO2021017369 A1 WO 2021017369A1
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Prior art keywords
region
emitter
type
carriers
bipolar transistor
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PCT/CN2019/124857
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French (fr)
Chinese (zh)
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刘利书
冯宇翔
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广东美的白色家电技术创新中心有限公司
美的集团股份有限公司
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Publication of WO2021017369A1 publication Critical patent/WO2021017369A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395Vertical transistors, e.g. vertical IGBT
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0804Emitter regions of bipolar transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234Bipolar junction transistors [BJT]
    • H01L29/66325Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333Vertical insulated gate bipolar transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]

Definitions

  • the embodiments of the present disclosure relate to the field of semiconductor technology but are not limited to the field of semiconductor technology, and in particular to an insulated gate bipolar transistor and a manufacturing method thereof.
  • Insulated Gate Bipolar Transistor is a composite fully controlled voltage-driven power semiconductor device composed of a bipolar transistor (BJT) and an insulated gate field effect transistor (MOSFET), which also has a MOSFET
  • BJT bipolar transistor
  • MOSFET insulated gate field effect transistor
  • the high input impedance of the device and the low turn-on voltage drop of the power transistor (giant transistor, GTR for short) have the advantages of low driving power and reduced saturation voltage, and are widely used in various fields.
  • the latch-up effect is one of the important reasons affecting the reliability of insulated gate bipolar transistors.
  • the existing insulated gate bipolar transistor has poor latch-up resistance, which reduces the reliability of the insulated gate bipolar transistor.
  • the embodiments of the present disclosure provide an insulated gate bipolar transistor and a manufacturing method thereof.
  • the first aspect of the embodiments of the present disclosure provides an insulated gate bipolar transistor, including:
  • the body region is located between the drift region and the emitter region, and is in contact with the drift region, the emitter region, the emitter metal, and the gate region;
  • the emitter metal is located above the body region and is in contact with the emitter region;
  • the emitter region is located between the emitter metal and the gate region; wherein the width of the contact interface between the bottom of the emitter region and the body region is smaller than that of the top of the emitter region width;
  • the gate region is located above the drift region and is in contact with the emitter region.
  • the doping concentration of the first type of carriers in the body region is greater than the doping concentration of the second type of carriers in the body region; wherein, the first type of carriers The charged type of is different from the charged type of the second type of carrier;
  • the gate region in addition to forming an inversion channel under pressure to make the insulated gate bipolar transistor work normally, can also be configured to be in contact with the emitter metal when the insulated gate bipolar transistor is turned on. An electric field is formed between them to promote the movement of the first-type carriers in the body region to the emitter metal.
  • the insulated gate bipolar transistor further includes: a collector region located below the drift region, the doping concentration of the collector region is greater than the doping concentration of the body region.
  • the doping concentration of the first type of carrier in the collector region is greater than the doping concentration of the second type of carrier in the collector region; wherein the doping concentration of the first type of carrier The charging type is different from the charging type of the second type of carrier;
  • the doping concentration of the first type of carriers in the collector region is greater than the doping concentration of the second type of carriers in the drift region; wherein the second type of carriers in the drift region The doping concentration of carriers is greater than the doping concentration of the first type carriers in the drift region.
  • the insulated gate bipolar transistor further includes a gate metal located above the gate region, and the gate metal forms an ohmic contact with the gate region.
  • the width of the contact interface is greater than or equal to 0.5 ⁇ m.
  • a second aspect of the embodiments of the present disclosure provides a method for manufacturing an insulated gate bipolar transistor, including:
  • the emitter region is formed between the emitter metal and the gate region; wherein the width of the contact interface between the bottom of the emitter region and the body region is smaller than that of the top of the emitter region width;
  • the gate region is formed above the drift region; wherein the gate region is in contact with the emitter region.
  • the manufacturing method of the insulated gate bipolar transistor further includes: forming a collector region under the drift region; wherein the doping concentration of the collector region is greater than that of the body region. concentration.
  • the doping concentration of the first type of carriers in the collector region is greater than the doping concentration of the second type of carriers in the drift region; wherein the charge type of the first type of carriers Different from the charging type of the second type of carrier;
  • the doping concentration of the first type of carriers in the collector region is greater than the doping concentration of the second type of carriers in the drift region; wherein the second type of carriers in the drift region The doping concentration of is greater than the doping concentration of the first type of carriers in the drift region.
  • the manufacturing method of the insulated gate bipolar transistor further includes: forming a gate metal above the gate region; wherein the gate metal forms an ohmic contact with the gate region.
  • the above-mentioned insulated gate bipolar transistor and its manufacturing method provided by the embodiments of the present disclosure, by arranging the emitter metal, the emitter region and the gate region in parallel, the body region in contact with the gate region is arranged on the emitter Below the metal and the emitter region, the contact area between the body region and the emitter region is reduced, thereby reducing the contact resistance between the body region and the emitter region, and reducing the voltage drop of the PN junction formed by the body region and the emitter region. The probability of forward bias of the PN junction is reduced, and the latch-up resistance of the insulated gate bipolar transistor is improved.
  • the emitter metal and the gate region can be separated
  • the transverse electric field formed between the body region acts on the body region, and the direction of the transverse electric field can accelerate the movement of the majority carriers in the body region to the emitter metal, and shorten the majority of the carriers in the body region between the body region and the emitter region.
  • the staying time at the contact interface further reduces the probability of the PN junction being forward biased, and improves the latch-up resistance of the insulated gate bipolar transistor.
  • FIG. 1 is a schematic diagram of an insulated gate bipolar transistor provided by an embodiment of the disclosure
  • FIG. 2 is a schematic structural diagram of an insulated gate bipolar transistor provided by an embodiment of the disclosure.
  • FIG. 3 is a schematic structural diagram of another insulated gate bipolar transistor provided by an embodiment of the disclosure.
  • FIG. 4 is a schematic structural diagram of another insulated gate bipolar transistor provided by an embodiment of the disclosure.
  • the directional indications are only used to explain each in a certain posture (such as shown in the drawings). If the relative positional relationship between the components, the movement situation, etc., change the specific posture, the directional indication will change accordingly.
  • the term "A is above/under B" means to include a situation where A and B are in contact with each other and one is above/under the other, or between A and B. A situation in which other components are interposed and one is located above/under the other without contact.
  • an embodiment of the present disclosure provides an insulated gate bipolar transistor, including:
  • the body region 10 is located between the drift region 20 and the emitter region 30, and is in contact with the drift region 20, the emitter region 30, the emitter metal 40 and the gate region 50;
  • the emitter metal 40 is located above the body region 10 and is in contact with the emitter region 30;
  • the emitter region 30 is located between the emitter metal 40 and the gate region 50; wherein the width of the contact interface between the bottom of the emitter region 30 and the body region 10 is smaller than that of the The width of the top of the emitter region 30;
  • the gate region 50 is located above the drift region 20 and is in contact with the emitter region 30.
  • the latch-up resistance performance of the insulated gate bipolar transistor can be further improved.
  • the preset width threshold may be 0.5 ⁇ m, 0.8 ⁇ m, 1 ⁇ m, etc.
  • the doping type of the emitter region 30 and the drift region 20 are the same, and the doping type may be acceptor doping or donor doping.
  • the body region 10 is the same as the emitter doping.
  • the doping type of the region 30 is different.
  • the majority carriers in the emitter region 30 and the drift region 20 are holes, and the doping type of the body region 10 is donor doped.
  • the majority carriers in the body region 10 are electrons; when the emitter region 30 and the drift region 20 are donor-doped, the majority carriers in the emitter region 30 and the drift region 20 are electrons, and the body region 10 is doped
  • the type is acceptor doping, and the majority carriers in the body region 10 are holes.
  • the majority carrier here is: a larger number of carriers per unit volume.
  • the doping concentration is the concentration of carriers generated by doping.
  • the doping concentration of the first type of carrier in the body region 10 is greater than the doping concentration of the second type of carrier in the body region 10; wherein, the first type of carrier The charge type of the current carrier is different from the charge type of the second type of carrier;
  • the gate region in addition to forming an inversion channel under pressure to make the insulated gate bipolar transistor work normally, can also be configured to be in contact with the emitter metal when the insulated gate bipolar transistor is turned on. An electric field is formed between them to promote the movement of the first-type carriers in the body region to the emitter metal.
  • the charge type of the first type of carrier may be positively charged or negatively charged.
  • the first type of carriers When the first type of carriers are positively charged, the first type of carriers can be holes, and the second type of carriers can be electrons; when the first type of carriers are negatively charged, The first type of carriers may be electrons, and the second type of carriers may be holes.
  • the shape of the emitter metal 40 may also be a trapezoidal structure as shown in FIG. 1, a triangular structure as shown in FIG. 2, a fan-shaped structure as shown in FIG. 3 or any other shape.
  • the shape of the gate region 50 may also be a trapezoidal structure as shown in FIG. 1, a fan-shaped structure as shown in FIG. 3 or any other shape.
  • the width of the contact interface between the emitter region 30 and the body region 10 can be reduced to reduce the body region.
  • the contact resistance with the emitter region reduces the voltage drop between the body region and the emitter region, thereby reducing the probability of the PN junction formed by the body region and the emitter region being positively biased.
  • the lateral electric field formed between the emitter metal and the gate region can be applied to the body region.
  • the direction of the lateral electric field can accelerate the movement of the majority carriers in the body region to the emitter metal, shorten the time that the majority carriers in the body region stay at the contact interface between the body region and the emitter region, and reduce the body region
  • the probability of the PN junction formed with the emitter region being forward biased improves the latch-up resistance of the insulated gate bipolar transistor.
  • the insulated gate bipolar transistor further includes a collector region 60 located below the drift region 20, and the doping concentration of the collector region 60 is greater than that of the body. Doping concentration of the zone.
  • the structure of the bipolar transistor includes an N-type insulated gate field effect transistor, a PNP bipolar transistor T1 composed of body region-drift region-collector region, and parasitic NPN composed of emitter region-body region-drift region Bipolar transistor T2; among them, transistor T1 and transistor T2 form an NPNP four-layer three-junction thyristor structure. Therefore, when the current density in the insulated gate bipolar transistor is greater than the preset current density threshold, the thyristor is turned on, causing permanent damage to the insulated gate bipolar transistor.
  • the thyristor When the insulated gate bipolar transistor is working normally, the thyristor will not turn on. This is because the short-circuit emitter structure formed by the emitter and the body under normal operating current ensures that the emitter junction of the transistor T2 does not turn on.
  • the insulated gate bipolar transistor The current of the type transistor is controlled by the gate voltage and has saturation characteristics.
  • the current density in the insulated gate bipolar transistor is greater than the preset current density threshold, an excessively high hole current flows through the body region under the emitter, and this current generates a voltage drop on the body region path resistance.
  • the PN junction formed by the body region and the emitter region is positively biased, and the upper NPN transistor T2 enters the amplifying region to work and drives the lower PNP transistor T1.
  • the upper NPN transistor T2 is driven to form a positive feedback.
  • the regenerative feedback effect causes the gate of the insulated gate bipolar transistor to lose control of the current, so that the current in the insulated gate bipolar transistor increases rapidly.
  • the insulated gate bipolar transistor may be overheated and burned. Therefore, the latch-up phenomenon limits the maximum safe operating current of the insulated gate bipolar transistor.
  • the structure of insulated gate bipolar transistor includes P-type Insulated gate field effect transistor, NPN bipolar transistor T3 composed of body region-drift region-collector region and parasitic PNP bipolar transistor T4 composed of emitter region-body region-drift region.
  • the transistor T3 and the transistor T4 form a P-N-P-N four-layer three-junction thyristor structure. Therefore, when the current density in the insulated gate bipolar transistor is greater than the preset current density threshold, the thyristor is turned on, causing permanent damage to the insulated gate bipolar transistor.
  • the thyristor When the insulated gate bipolar transistor is working normally, the thyristor will not turn on. This is because the short-circuit emitter structure formed by the emitter and the body under normal operating current ensures that the emitter junction of the transistor T4 does not turn on.
  • the insulated gate bipolar transistor The current of the type transistor is controlled by the gate voltage and has saturation characteristics.
  • the current density in the insulated gate bipolar transistor is greater than the preset current density threshold, an excessively high electron current flows through the body region under the emitter, and this current generates a voltage drop on the body region path resistance.
  • the PN junction formed by the body region and the emitter region is positively biased, and the upper PNP transistor T4 enters the amplification region to work, and drives the lower NPN transistor T3.
  • the NPN transistor T3 is turned on In turn, the upper PNP transistor T4 is driven to form a positive feedback.
  • the regenerative feedback effect causes the gate of the insulated gate bipolar transistor to lose control of the current, so that the current in the insulated gate bipolar transistor increases rapidly.
  • the insulated gate bipolar transistor may be overheated and burned. Therefore, the latch-up phenomenon limits the maximum safe operating current of the insulated gate bipolar transistor.
  • the emitter can be reduced.
  • the width of the contact interface between the bottom of the region and the body region thereby reducing the parasitic resistance of the body region, reducing the voltage drop of the current on the path resistance of the body region, and reducing the positive bias of the PN junction formed by the body region and the emitter region.
  • the insulated gate bipolar transistor provided by the embodiments of the present disclosure can act on the lateral electric field formed between the emitter metal and the gate region by extending the emitter region and the gate region in the direction from the gate region to the drift region.
  • the direction of the transverse electric field can accelerate the movement of the majority carriers in the body region to the emitter metal, and shorten the time that the majority carriers in the body region stay at the contact interface between the body region and the emitter region , Further reduce the probability of forward bias of the PN junction formed by the emitter and the body region, and improve the latch-up resistance of the insulated gate bipolar transistor.
  • the doping concentration of the first type carrier in the collector region 60 is greater than the doping concentration of the second type carrier in the collector region 60; wherein, the first type carrier The charging type of the carrier is different from the charging type of the second type of carrier;
  • the doping concentration of the first type of carrier in the collector region 60 is greater than the doping concentration of the second type of carrier in the drift region 20; wherein, the first type of carrier in the drift region 20
  • the doping concentration of the second type of carrier is greater than the doping concentration of the first type of carrier in the drift region 20.
  • the insulated gate bipolar transistor further includes a gate metal 70 located above the gate region 50, and the gate metal 70 forms an ohmic contact with the gate region 50.
  • the contact resistance between the gate metal and the gate region can be reduced, and the gate metal and the gate region can be equipotential. Increase the controllability of grid voltage.
  • the insulated gate bipolar transistor further includes: a collector metal 80 located under the collector region 60, and the collector metal 80 forms an ohmic contact with the collector region 60.
  • the contact resistance between the collector metal and the collector region can be reduced, the energy dissipation caused by the contact resistance can be reduced, and the insulation can be improved.
  • the width of the contact interface is greater than or equal to 0.5 ⁇ m.
  • the width of the contact interface is greater than or equal to a preset width threshold, and the preset width threshold may be 0.5 ⁇ m, 0.6 ⁇ m, 0.8 ⁇ m, or the like.
  • the width of the contact interface is less than the preset width threshold, the probability of breakdown between the emitter metal and the gate layer under the action of an electric field increases, resulting in the failure of the insulated gate bipolar transistor and reducing the insulated gate bipolar transistor. Reliability of type transistors.
  • the embodiment of the present disclosure also provides a manufacturing method of an insulated gate bipolar transistor, including:
  • the emitter region is formed between the emitter metal and the gate region; wherein the width of the contact interface between the bottom of the emitter region and the body region is smaller than that of the top of the emitter region width;
  • the gate region is formed above the drift region; wherein the gate region is in contact with the emitter region.
  • the gate region and the emitter metal with a special structure can be fabricated separately by thermal oxidation or thin film deposition.
  • the doped body region, emitter region, and drift region can be separately prepared by ion implantation.
  • the width of the contact interface between the bottom of the emitter region and the body region can be reduced by means of self-aligned ion implantation, thereby reducing the parasitic resistance of the body region and reducing the current in the body region.
  • the voltage drop on the path resistance improves the latch-up resistance of the insulated gate bipolar transistor.
  • the emitter metal, the emitter region, and the gate region are formed in parallel, and the body region in contact with the gate region is arranged under the emitter metal and the emitter region.
  • the transverse electric field formed between the polar regions acts on the body region. The direction of the transverse electric field can accelerate the movement of majority carriers in the body region to the emitter metal, shortening the majority of carriers in the body region at the contact interface. The staying time reduces the probability that the PN junction formed by the emitter and the body region will be positively biased, and further improves the latch-up resistance of the insulated gate bipolar transistor.
  • the manufacturing method of the insulated gate bipolar transistor further includes: forming a collector region under the drift region; wherein the doping concentration of the collector region is greater than that of the body region. concentration.
  • the doping concentration of the first type of carriers in the collector region is greater than the doping concentration of the second type of carriers in the drift region; wherein the charge type of the first type of carriers Different from the charging type of the second type of carriers, the doping concentration of the first type of carriers in the collector region is greater than the doping concentration of the second type of carriers in the collector region, The doping concentration of the second type of carriers in the drift region is greater than the doping concentration of the first type of carriers in the drift region.
  • the manufacturing method of the insulated gate bipolar transistor further includes: forming a gate metal above the gate region; wherein the gate metal forms an ohmic contact with the gate region.
  • the structure of the insulated gate bipolar transistor includes the N-type insulated gate field effect transistor, which is composed of body region-drift region-collector region PNP bipolar transistor T1 and a parasitic NPN bipolar transistor T2 composed of emitter region-body region-drift region.
  • the transistor T1 and the transistor T2 form an N-P-N-P four-layer triple junction thyristor structure. Therefore, when the current density in the insulated gate bipolar transistor is greater than the preset current density threshold, the thyristor can be turned on, which can cause permanent damage to the insulated gate bipolar transistor.
  • the necessary condition for the latch-up of the insulated gate bipolar transistor is that the transistor T2 is turned on, that is, the PN junction formed by the body region of the insulated gate bipolar transistor and the emitter is forward biased. Since the N-emitter and P-body region of the cathode of the IGBT are at the same potential, the base-emitter forward bias of T2 can only appear when holes in the body region flow along the N-emitter to the cathode contact surface.
  • this example provides a schematic structural diagram of an insulated gate bipolar transistor.
  • the insulated gate bipolar transistor includes a P-type body region 10, an N-type drift region 20, an N+ type emitter region 30, and an emitter metal 40.
  • a positive sign (+) indicates a higher doping concentration
  • a negative sign (-) indicates a lower doping concentration
  • E indicates an emitter section
  • G indicates a gate terminal
  • C indicates a collector terminal.
  • the contact surface between the gate region 50 and the N+ type emitter region 30, the P type body region 10, and the N- type drift region 20 is a thin insulating oxide layer (not labeled in FIG. 4).
  • the gate region 50 and the emitter metal 40 have a trapezoidal structure, and the distance between the bottom of the gate region and the bottom of the emitter metal is smaller than the distance between the top of the gate region and the top of the emitter metal. distance.
  • the shape of the gate region and the emitter metal can also be a triangular structure, a sector structure or other arbitrary shapes. It is only necessary to ensure that the distance between the bottom of the gate region and the bottom of the emitter metal is as small as possible to reduce emission.
  • the width of the contact interface between the pole region and the body region can reduce the contact resistance between the body region and the emitter region, reduce the voltage drop of the PN junction formed by the body region and the emitter region, and reduce the PN junction
  • the probability of occurrence of forward bias improves the latch-up resistance of the insulated gate bipolar transistor.
  • the insulated gate bipolar transistor provided in this example also extends the emitter region and the gate region in the direction from the gate region to the drift region, so that the lateral electric field formed between the emitter metal and the gate region acts on the body region.
  • the direction of the transverse electric field can accelerate the movement of the majority carriers in the body region to the emitter metal, shorten the time that the majority carriers in the body region stay at the contact interface between the body region and the emitter region, and further reduce the body region.
  • the probability that the PN junction formed by the region and the emitter region is positively biased improves the latch-up resistance of the insulated gate bipolar transistor.
  • the insulated gate bipolar transistor may be a conventional planar gate structure, a trench gate structure, a punch-through structure (PT structure), a field stop-trench structure (FS-Trench structure), etc.
  • the gate region and the emitter metal with a special structure can be fabricated separately by thermal oxidation or thin film deposition.
  • the body region and drift region can be doped by ion implantation.
  • the disclosed device and method may be implemented in other ways.
  • the device embodiments described above are merely illustrative.
  • the division of the units is only a logical function division, and there may be other divisions in actual implementation, such as: multiple units or components can be combined, or It can be integrated into another system, or some features can be ignored or not implemented.
  • the coupling, or direct coupling, or communication connection between the components shown or discussed may be indirect coupling or communication connection through some interfaces, devices or units, and may be electrical, mechanical or other forms of.
  • the units described above as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units; Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • the functional units in the embodiments of the present disclosure can be all integrated into one processing module, or each unit can be individually used as a unit, or two or more units can be integrated into one unit;
  • the unit can be implemented in the form of hardware, or in the form of hardware plus software functional units.
  • a person of ordinary skill in the art can understand that all or part of the steps in the above method embodiments can be implemented by a program instructing relevant hardware.
  • the foregoing program can be stored in a computer readable storage medium. When the program is executed, it is executed. Including the steps of the foregoing method embodiment; and the foregoing storage medium includes: removable storage devices, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disks or optical disks, etc.

Abstract

Disclosed are an insulated gate bipolar transistor and a manufacturing method therefor. The insulated gate bipolar transistor comprises: a body region that is located between a drift region and an emitter region and in contact with the drift region, the emitter region, an emitter metal and a gate region; the emitter metal that is located above the body region and in contact with the emitter region; the emitter region located between the emitter metal and the gate region, wherein the width of a contact interface between the bottom of the emitter region and the body region is less than the width of the top of the emitter region; and the gate region that is located above the drift region and in contact with the emitter region.

Description

绝缘栅双极型晶体管及其制作方法Insulated gate bipolar transistor and manufacturing method thereof
相关申请的交叉引用Cross references to related applications
本申请基于申请号为201910684437.4、申请日为2019年07月26日的中国专利申请提出,并要求该中国专利申请的优先权,该中国专利申请的全部内容在此引入本申请作为参考。This application is filed based on a Chinese patent application with application number 201910684437.4 and an application date of July 26, 2019, and claims the priority of the Chinese patent application. The entire content of the Chinese patent application is hereby incorporated into this application by reference.
技术领域Technical field
本公开实施例涉及半导体技术领域但不限于半导体技术领域,特别涉及一种绝缘栅双极型晶体管及其制作方法。The embodiments of the present disclosure relate to the field of semiconductor technology but are not limited to the field of semiconductor technology, and in particular to an insulated gate bipolar transistor and a manufacturing method thereof.
背景技术Background technique
绝缘栅双极型晶体管(Insulated Gate Bipolar Transistor,简称IGBT)是由双极型三极管(BJT)和绝缘栅型场效应管(MOSFET)组成的复合全控型电压驱动式功率半导体器件,兼有MOSFET器件的高输入阻抗和电力晶体管(即巨型晶体管,简称GTR)的低导通压降两方面的优点,且驱动功率小而饱和压降低,被广泛应用到各个领域。Insulated Gate Bipolar Transistor (IGBT) is a composite fully controlled voltage-driven power semiconductor device composed of a bipolar transistor (BJT) and an insulated gate field effect transistor (MOSFET), which also has a MOSFET The high input impedance of the device and the low turn-on voltage drop of the power transistor (giant transistor, GTR for short) have the advantages of low driving power and reduced saturation voltage, and are widely used in various fields.
闩锁效应是影响绝缘栅双极型晶体管可靠性的重要原因之一。现有的绝缘栅双极型晶体管抗闩锁能力较差,降低了绝缘栅双极型晶体管的可靠性。The latch-up effect is one of the important reasons affecting the reliability of insulated gate bipolar transistors. The existing insulated gate bipolar transistor has poor latch-up resistance, which reduces the reliability of the insulated gate bipolar transistor.
发明内容Summary of the invention
本公开实施例提供一种绝缘栅双极型晶体管及其制作方法。The embodiments of the present disclosure provide an insulated gate bipolar transistor and a manufacturing method thereof.
本公开实施例的第一方面提供一种绝缘栅双极型晶体管,包括:The first aspect of the embodiments of the present disclosure provides an insulated gate bipolar transistor, including:
体区,位于漂移区与发射极区之间,与所述漂移区、所述发射极区、 发射极金属及栅极区接触;The body region is located between the drift region and the emitter region, and is in contact with the drift region, the emitter region, the emitter metal, and the gate region;
所述发射极金属,位于所述体区上方,与所述发射极区接触;The emitter metal is located above the body region and is in contact with the emitter region;
所述发射极区,位于所述发射极金属与所述栅极区之间;其中,所述发射极区底部和所述体区之间的接触界面的宽度,小于所述发射极区顶部的宽度;The emitter region is located between the emitter metal and the gate region; wherein the width of the contact interface between the bottom of the emitter region and the body region is smaller than that of the top of the emitter region width;
所述栅极区,位于所述漂移区上方,与所述发射极区接触。The gate region is located above the drift region and is in contact with the emitter region.
在一些实施例中,所述体区中的第一类载流子的掺杂浓度大于所述体区中的第二类载流子的掺杂浓度;其中,所述第一类载流子的带电荷类型和所述第二类载流子的带电荷类型不同;In some embodiments, the doping concentration of the first type of carriers in the body region is greater than the doping concentration of the second type of carriers in the body region; wherein, the first type of carriers The charged type of is different from the charged type of the second type of carrier;
所述栅极区,除了加压形成反型沟道,使绝缘栅双极型晶体管正常工作外,还可配置为当所述绝缘栅双极型晶体管导通时,与所述发射极金属之间形成电场,促进所述体区中的所述第一类载流子向所述发射极金属移动。The gate region, in addition to forming an inversion channel under pressure to make the insulated gate bipolar transistor work normally, can also be configured to be in contact with the emitter metal when the insulated gate bipolar transistor is turned on. An electric field is formed between them to promote the movement of the first-type carriers in the body region to the emitter metal.
在一些实施例中,所述绝缘栅双极型晶体管还包括:集电极区,位于所述漂移区下方,所述集电极区的掺杂浓度大于所述体区的掺杂浓度。In some embodiments, the insulated gate bipolar transistor further includes: a collector region located below the drift region, the doping concentration of the collector region is greater than the doping concentration of the body region.
在一些实施例中,所述集电极区中第一类载流子的掺杂浓度大于所述集电极区中第二类载流子掺杂浓度;其中,所述第一类载流子的带电类型和所述第二类载流子的带电类型不同;In some embodiments, the doping concentration of the first type of carrier in the collector region is greater than the doping concentration of the second type of carrier in the collector region; wherein the doping concentration of the first type of carrier The charging type is different from the charging type of the second type of carrier;
所述集电极区中所述第一类载流子的掺杂浓度大于所述漂移区中所述第二类载流子的掺杂浓度;其中,所述漂移区中所述第二类载流子的掺杂浓度大于所述漂移区中所述第一类载流子的掺杂浓度。The doping concentration of the first type of carriers in the collector region is greater than the doping concentration of the second type of carriers in the drift region; wherein the second type of carriers in the drift region The doping concentration of carriers is greater than the doping concentration of the first type carriers in the drift region.
在一些实施例中,所述绝缘栅双极型晶体管还包括:栅极金属,位于所述栅极区上方,所述栅极金属与所述栅极区形成欧姆接触。In some embodiments, the insulated gate bipolar transistor further includes a gate metal located above the gate region, and the gate metal forms an ohmic contact with the gate region.
在一些实施例中,所述接触界面的宽度大于或等于0.5μm。In some embodiments, the width of the contact interface is greater than or equal to 0.5 μm.
本公开实施例第二方面提供一种绝缘栅双极型晶体管的制作方法,包 括:A second aspect of the embodiments of the present disclosure provides a method for manufacturing an insulated gate bipolar transistor, including:
形成位于漂移区和发射极区之间的体区;其中,所述体区与所述漂移区、所述发射极区、发射极金属、栅极区接触;Forming a body region located between the drift region and the emitter region; wherein the body region is in contact with the drift region, the emitter region, the emitter metal, and the gate region;
在所述体区上方形成与所述发射极区接触的所述发射极金属;Forming the emitter metal in contact with the emitter region above the body region;
在所述发射极金属和所述栅极区之间形成所述发射极区;其中,所述发射极区底部与所述体区之间的接触界面的宽度,小于所述发射极区顶部的宽度;The emitter region is formed between the emitter metal and the gate region; wherein the width of the contact interface between the bottom of the emitter region and the body region is smaller than that of the top of the emitter region width;
在所述漂移区上方形成所述栅极区;其中,所述栅极区与所述发射极区接触。The gate region is formed above the drift region; wherein the gate region is in contact with the emitter region.
在一些实施例中,所述绝缘栅双极型晶体管的制作方法还包括:在所述漂移区下方形成集电极区;其中,所述集电极区的掺杂浓度大于所述体区的掺杂浓度。In some embodiments, the manufacturing method of the insulated gate bipolar transistor further includes: forming a collector region under the drift region; wherein the doping concentration of the collector region is greater than that of the body region. concentration.
在一些实施例中,所述集电极区中第一类载流子掺杂浓度大于所述漂移区中第二类载流子掺杂浓度;其中,所述第一类载流子的带电类型和所述第二类载流子的带电类型不同;In some embodiments, the doping concentration of the first type of carriers in the collector region is greater than the doping concentration of the second type of carriers in the drift region; wherein the charge type of the first type of carriers Different from the charging type of the second type of carrier;
所述集电极区中所述第一类载流子掺杂浓度大于所述漂移区区中所述第二类载流子掺杂浓度;其中,所述漂移区中所述第二类载流子的掺杂浓度大于所述漂移区中所述第一类载流子的掺杂浓度。The doping concentration of the first type of carriers in the collector region is greater than the doping concentration of the second type of carriers in the drift region; wherein the second type of carriers in the drift region The doping concentration of is greater than the doping concentration of the first type of carriers in the drift region.
在一些实施例中,所述绝缘栅双极型晶体管的制作方法还包括:在所述栅极区上方形成栅极金属;其中,所述栅极金属与所述栅极区形成欧姆接触。In some embodiments, the manufacturing method of the insulated gate bipolar transistor further includes: forming a gate metal above the gate region; wherein the gate metal forms an ohmic contact with the gate region.
一方面,本公开实施例提供的上述绝缘栅双极型晶体管及其制作方法,通过将发射极金属、发射极区以及栅极区并列设置,将与栅极区接触的体区设置在发射极金属与发射极区下方,减小了体区与发射极区的接触面积,进而减小体区与发射极区的接触电阻,降低了体区与发射极区形成的PN结 的压降,减小了所述PN结发生正偏的几率,提高了绝缘栅双极型晶体管的抗闩锁性能。On the one hand, the above-mentioned insulated gate bipolar transistor and its manufacturing method provided by the embodiments of the present disclosure, by arranging the emitter metal, the emitter region and the gate region in parallel, the body region in contact with the gate region is arranged on the emitter Below the metal and the emitter region, the contact area between the body region and the emitter region is reduced, thereby reducing the contact resistance between the body region and the emitter region, and reducing the voltage drop of the PN junction formed by the body region and the emitter region. The probability of forward bias of the PN junction is reduced, and the latch-up resistance of the insulated gate bipolar transistor is improved.
另一方面,本公开实施例提供的绝缘栅双极型晶体管及其制作方法,通过沿栅极区向漂移区的方向延伸发射极区和栅极区,可将发射极金属与栅极区之间形成的横向电场作用于体区中,所述横向电场的方向可加速体区中的多数载流子向发射极金属运动,缩短体区中多数载流子在体区与发射极区之间的接触界面处停留的时间,进一步降低所述PN结发生正偏的几率,提高绝缘栅双极型晶体管的抗闩锁性能。On the other hand, in the insulated gate bipolar transistor and its manufacturing method provided by the embodiments of the present disclosure, by extending the emitter region and the gate region along the gate region to the drift region, the emitter metal and the gate region can be separated The transverse electric field formed between the body region acts on the body region, and the direction of the transverse electric field can accelerate the movement of the majority carriers in the body region to the emitter metal, and shorten the majority of the carriers in the body region between the body region and the emitter region. The staying time at the contact interface further reduces the probability of the PN junction being forward biased, and improves the latch-up resistance of the insulated gate bipolar transistor.
附图说明Description of the drawings
图1为本公开实施例提供的一种绝缘栅双极晶体管的示意图;FIG. 1 is a schematic diagram of an insulated gate bipolar transistor provided by an embodiment of the disclosure;
图2为本公开实施例提供的一种绝缘栅双极晶体管的结构示意图;2 is a schematic structural diagram of an insulated gate bipolar transistor provided by an embodiment of the disclosure;
图3为本公开实施例提供的另一种绝缘栅双极型晶体管的结构示意图;3 is a schematic structural diagram of another insulated gate bipolar transistor provided by an embodiment of the disclosure;
图4为本公开实施例提供的又一种绝缘栅双极型晶体管的结构示意图。FIG. 4 is a schematic structural diagram of another insulated gate bipolar transistor provided by an embodiment of the disclosure.
具体实施方式Detailed ways
以下结合说明书附图及具体实施例对本公开的技术方案进一步详细阐述。虽然附图中显示了本公开的示例性实施方法,然而应当理解,可以以各种形式实现本公开而不应被这里阐述的实施方式所限制。相反,提供这些实施方式是为了能够更透彻的理解本公开,并且能够将本公开的范围完整的传达给本领域的技术人员。The technical solutions of the present disclosure will be further described in detail below in conjunction with the drawings and specific embodiments of the specification. Although the drawings show exemplary implementation methods of the present disclosure, it should be understood that the present disclosure may be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.
在下列段落中参照附图以举例方式更具体的描述本公开。根据下面说明和权利要求书,本公开的优点和特征将更清楚。需说明的是,附图均采用非常简化的形式且均使用非精准的比例,仅用以方便、明晰地辅助说明本公开实施方式的目的。除非特别说明或者指出,否则本公开实施例中的术语“第一”、“第二”等描述仅用于区分本公开中的各个组件、元素、步 骤等,而不是用于表示各个组件、元素、步骤之间的逻辑关系或者顺序关系等。In the following paragraphs, the present disclosure is described in more detail by way of example with reference to the drawings. According to the following description and claims, the advantages and features of the present disclosure will be clearer. It should be noted that the drawings all adopt a very simplified form and all use imprecise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present disclosure. Unless otherwise specified or pointed out, the terms "first", "second" and other descriptions in the embodiments of the present disclosure are only used to distinguish each component, element, step, etc. in the present disclosure, rather than to indicate each component or element , The logical relationship or sequence relationship between steps, etc.
若本公开实施例中涉及方向性指示(诸如上、下、左、右、前、后……),则该方向性指示仅用于解释在某一特定姿态(诸如附图所示)下各部件之间的相对位置关系、运动情况等,如果该特定姿态发生改变,则该方向性指示也相应的随之改变。在本公开实施例中,术语“A在B之上/下”意味着包含A、B两者相互接触地一者在另一者之上/下的情形,或者A、B两者之间还间插有其他部件而一者非接触地位于另一者之上/下的情形。If the embodiments of the present disclosure involve directional indications (such as up, down, left, right, front, back...), then the directional indications are only used to explain each in a certain posture (such as shown in the drawings). If the relative positional relationship between the components, the movement situation, etc., change the specific posture, the directional indication will change accordingly. In the embodiments of the present disclosure, the term "A is above/under B" means to include a situation where A and B are in contact with each other and one is above/under the other, or between A and B. A situation in which other components are interposed and one is located above/under the other without contact.
如图1所示,本公开实施例提供一种绝缘栅双极型晶体管,包括:As shown in FIG. 1, an embodiment of the present disclosure provides an insulated gate bipolar transistor, including:
体区10,位于漂移区20与发射极区30之间,与所述漂移区20、所述发射极区30、发射极金属40及栅极区50接触;The body region 10 is located between the drift region 20 and the emitter region 30, and is in contact with the drift region 20, the emitter region 30, the emitter metal 40 and the gate region 50;
所述发射极金属40,位于所述体区10上方,与所述发射极区30接触;The emitter metal 40 is located above the body region 10 and is in contact with the emitter region 30;
所述发射极区30,位于所述发射极金属40与所述栅极区50之间;其中,所述发射极区30底部和所述体区10之间的接触界面的宽度,小于所述发射极区30顶部的宽度;The emitter region 30 is located between the emitter metal 40 and the gate region 50; wherein the width of the contact interface between the bottom of the emitter region 30 and the body region 10 is smaller than that of the The width of the top of the emitter region 30;
所述栅极区50,位于所述漂移区20上方,与所述发射极区30接触。The gate region 50 is located above the drift region 20 and is in contact with the emitter region 30.
在一些实施例中,可以通过减小发射极区底部和所述体区之间的接触界面的宽度至预设宽度阈值,进一步提高绝缘栅双极型晶体管的抗闩锁性能。其中,所述预设宽度阈值可为0.5μm、0.8μm、1μm等。In some embodiments, by reducing the width of the contact interface between the bottom of the emitter region and the body region to a predetermined width threshold, the latch-up resistance performance of the insulated gate bipolar transistor can be further improved. Wherein, the preset width threshold may be 0.5 μm, 0.8 μm, 1 μm, etc.
在本公开实施例中,所述发射极区30和所述漂移区20的掺杂类型相同,其掺杂类型可为受主掺杂或施主掺杂,所述体区10与所述发射极区30的掺杂类型不同。In the embodiment of the present disclosure, the doping type of the emitter region 30 and the drift region 20 are the same, and the doping type may be acceptor doping or donor doping. The body region 10 is the same as the emitter doping. The doping type of the region 30 is different.
在本公开实施例中,当发射极区30和漂移区20为受主掺杂时,发射极区30和漂移区20的多数载流子为空穴,体区10的掺杂类型为施主掺杂,体区10的多数载流子为电子;当发射极区30和漂移区20为施主掺杂时, 发射极区30和漂移区20的多数载流子为电子,体区10的掺杂类型为受主掺杂,体区10的多数载流子为空穴。此处的多数载流子为:单位体积内数量更多的载流子。在本公开实施例中,所述掺杂浓度为掺杂产生的载流子的浓度。In the embodiment of the present disclosure, when the emitter region 30 and the drift region 20 are acceptor doped, the majority carriers in the emitter region 30 and the drift region 20 are holes, and the doping type of the body region 10 is donor doped. In addition, the majority carriers in the body region 10 are electrons; when the emitter region 30 and the drift region 20 are donor-doped, the majority carriers in the emitter region 30 and the drift region 20 are electrons, and the body region 10 is doped The type is acceptor doping, and the majority carriers in the body region 10 are holes. The majority carrier here is: a larger number of carriers per unit volume. In the embodiment of the present disclosure, the doping concentration is the concentration of carriers generated by doping.
在一些实施例中,所述体区10中的第一类载流子的掺杂浓度大于所述体区10中的第二类载流子的掺杂浓度;其中,所述第一类载流子的带电荷类型和所述第二类载流子的带电荷类型不同;In some embodiments, the doping concentration of the first type of carrier in the body region 10 is greater than the doping concentration of the second type of carrier in the body region 10; wherein, the first type of carrier The charge type of the current carrier is different from the charge type of the second type of carrier;
所述栅极区,除了加压形成反型沟道,使绝缘栅双极型晶体管正常工作外,还可配置为当所述绝缘栅双极型晶体管导通时,与所述发射极金属之间形成电场,促进所述体区中的所述第一类载流子向所述发射极金属移动。The gate region, in addition to forming an inversion channel under pressure to make the insulated gate bipolar transistor work normally, can also be configured to be in contact with the emitter metal when the insulated gate bipolar transistor is turned on. An electric field is formed between them to promote the movement of the first-type carriers in the body region to the emitter metal.
在本公开实施例中,所述第一类载流子的带电荷类型可为带正电荷或带负电荷。当第一类载流子带正电荷时,所述第一类载流子可为空穴,所述第二类载流子为可为电子;当第一类载流子带负电荷时,所述第一类载流子可为电子,所述第二类载流子为可为空穴。In the embodiment of the present disclosure, the charge type of the first type of carrier may be positively charged or negatively charged. When the first type of carriers are positively charged, the first type of carriers can be holes, and the second type of carriers can be electrons; when the first type of carriers are negatively charged, The first type of carriers may be electrons, and the second type of carriers may be holes.
在一些实施例中,发射极金属40的形状也可如图1所示为梯形结构,可如图2所示为三角形结构,可如图3所示为扇形结构或其他任意形状。In some embodiments, the shape of the emitter metal 40 may also be a trapezoidal structure as shown in FIG. 1, a triangular structure as shown in FIG. 2, a fan-shaped structure as shown in FIG. 3 or any other shape.
在一些实施例中,栅极区50的形状也可如图1所示为梯形结构,可如图3所示为扇形结构或其他任意形状。In some embodiments, the shape of the gate region 50 may also be a trapezoidal structure as shown in FIG. 1, a fan-shaped structure as shown in FIG. 3 or any other shape.
在本公开实施例中,只需保证栅极区50底部与发射极金属40底部的距离尽量较小,减小发射极区30与体区10之间的接触界面的宽度,可减小体区与发射极区的接触电阻,降低体区与发射极区之间的压降,进而降低体区与发射极区形成的PN结发生正偏的几率。In the embodiment of the present disclosure, it is only necessary to ensure that the distance between the bottom of the gate region 50 and the bottom of the emitter metal 40 is as small as possible, and the width of the contact interface between the emitter region 30 and the body region 10 can be reduced to reduce the body region. The contact resistance with the emitter region reduces the voltage drop between the body region and the emitter region, thereby reducing the probability of the PN junction formed by the body region and the emitter region being positively biased.
此外,通过沿栅极区向漂移区方向延伸发射极金属和栅极区,可将发射极金属与栅极区之间形成的横向电场作用于体区中。所述横向电场的方 向可加速体区中的多数载流子向发射极金属运动,缩短体区中多数载流子在体区与发射极区之间的接触界面处停留的时间,降低体区与发射极区形成的PN结发生正偏的几率,提高绝缘栅双极型晶体管的抗闩锁性能。In addition, by extending the emitter metal and the gate region along the gate region toward the drift region, the lateral electric field formed between the emitter metal and the gate region can be applied to the body region. The direction of the lateral electric field can accelerate the movement of the majority carriers in the body region to the emitter metal, shorten the time that the majority carriers in the body region stay at the contact interface between the body region and the emitter region, and reduce the body region The probability of the PN junction formed with the emitter region being forward biased improves the latch-up resistance of the insulated gate bipolar transistor.
在一些实施例中,如图1所示,所述绝缘栅双极型晶体管还包括:集电极区60,位于所述漂移区20下方,所述集电极区60的掺杂浓度大于所述体区的掺杂浓度。In some embodiments, as shown in FIG. 1, the insulated gate bipolar transistor further includes a collector region 60 located below the drift region 20, and the doping concentration of the collector region 60 is greater than that of the body. Doping concentration of the zone.
以体区和集电极区为受主掺杂(P型掺杂)、漂移区和发射极区为施主掺杂(N型掺杂)的N型绝缘栅双极型晶体管器件为例,绝缘栅双极型晶体管的结构包括了N型绝缘栅型场效应管、由体区-漂移区-集电极区构成的PNP双极型晶体管T1及由发射极区-体区-漂移区构成的寄生NPN双极型晶体管T2;其中,晶体管T1和晶体管T2组成了N-P-N-P的四层三结的晶闸管结构。因此,当绝缘栅双极性晶体管中的电流密度大于预设电流密度阈值时,所述晶闸管导通,造成绝缘栅双极型晶体管永久性损坏。Take the N-type insulated gate bipolar transistor device with the body region and the collector region as the acceptor doping (P-type doping) and the drift region and the emitter region as the donor doping (N-type doping) as an example. The structure of the bipolar transistor includes an N-type insulated gate field effect transistor, a PNP bipolar transistor T1 composed of body region-drift region-collector region, and parasitic NPN composed of emitter region-body region-drift region Bipolar transistor T2; among them, transistor T1 and transistor T2 form an NPNP four-layer three-junction thyristor structure. Therefore, when the current density in the insulated gate bipolar transistor is greater than the preset current density threshold, the thyristor is turned on, causing permanent damage to the insulated gate bipolar transistor.
当绝缘栅双极型晶体管正常工作时,晶闸管不会开启,这是由于正常工作电流下发射极和体区形成的短路发射极结构保证了晶体管T2的发射结不发生导通,绝缘栅双极型晶体管的电流受到栅极电压的控制,具有饱和特性。When the insulated gate bipolar transistor is working normally, the thyristor will not turn on. This is because the short-circuit emitter structure formed by the emitter and the body under normal operating current ensures that the emitter junction of the transistor T2 does not turn on. The insulated gate bipolar transistor The current of the type transistor is controlled by the gate voltage and has saturation characteristics.
当绝缘栅双极性晶体管中的电流密度大于预设电流密度阈值时,过高的空穴电流流过发射极下方的体区,该电流在体区路径电阻上产生压降。当所述压降大于预设压降阈值时,体区与发射极区形成的PN结发生正偏,上层的NPN晶体管T2进入放大区工作,并驱动下层的PNP晶体管T1,PNP晶体管T1开启后又反过来驱动上层NPN晶体管T2,如此形成正反馈。再生反馈效应使得绝缘栅双极型晶体管的栅极失去对电流的控制,使得绝缘栅双极型晶体管中的电流迅速增大。当电流大于预设电流阈值后,可能使绝缘栅双极型晶体管过热烧毁,因此闩锁现象限制了绝缘栅双极型晶体管 的最大安全工作电流。When the current density in the insulated gate bipolar transistor is greater than the preset current density threshold, an excessively high hole current flows through the body region under the emitter, and this current generates a voltage drop on the body region path resistance. When the voltage drop is greater than the preset voltage drop threshold, the PN junction formed by the body region and the emitter region is positively biased, and the upper NPN transistor T2 enters the amplifying region to work and drives the lower PNP transistor T1. After the PNP transistor T1 is turned on In turn, the upper NPN transistor T2 is driven to form a positive feedback. The regenerative feedback effect causes the gate of the insulated gate bipolar transistor to lose control of the current, so that the current in the insulated gate bipolar transistor increases rapidly. When the current is greater than the preset current threshold, the insulated gate bipolar transistor may be overheated and burned. Therefore, the latch-up phenomenon limits the maximum safe operating current of the insulated gate bipolar transistor.
以体区和集电极区为施主掺杂(N型掺杂)、漂移区和发射极区为受主掺杂(P型掺杂)为例,绝缘栅双极型晶体管的结构包括了P型绝缘栅型场效应管、由体区-漂移区-集电极区构成的NPN双极型晶体管T3及由发射极区-体区-漂移区构成的寄生PNP双极型晶体管T4。其中晶体管T3和晶体管T4组成了P-N-P-N的四层三结的晶闸管结构。因此,当绝缘栅双极性晶体管中的电流密度大于预设电流密度阈值时,所述晶闸管导通,造成绝缘栅双极型晶体管永久性损坏。Taking body region and collector region as donor doping (N-type doping), drift region and emitter region as acceptor doping (P-type doping) as an example, the structure of insulated gate bipolar transistor includes P-type Insulated gate field effect transistor, NPN bipolar transistor T3 composed of body region-drift region-collector region and parasitic PNP bipolar transistor T4 composed of emitter region-body region-drift region. Among them, the transistor T3 and the transistor T4 form a P-N-P-N four-layer three-junction thyristor structure. Therefore, when the current density in the insulated gate bipolar transistor is greater than the preset current density threshold, the thyristor is turned on, causing permanent damage to the insulated gate bipolar transistor.
当绝缘栅双极型晶体管正常工作时,晶闸管不会开启,这是由于正常工作电流下发射极和体区形成的短路发射极结构保证了晶体管T4的发射结不发生导通,绝缘栅双极型晶体管的电流受到栅极电压的控制,具有饱和特性。When the insulated gate bipolar transistor is working normally, the thyristor will not turn on. This is because the short-circuit emitter structure formed by the emitter and the body under normal operating current ensures that the emitter junction of the transistor T4 does not turn on. The insulated gate bipolar transistor The current of the type transistor is controlled by the gate voltage and has saturation characteristics.
当绝缘栅双极性晶体管中的电流密度大于预设电流密度阈值时,过高的电子电流流过发射极下方的体区,该电流在体区路径电阻上产生压降。当所述压降大于预设压降阈值时,体区与发射极区形成的PN结发生正偏,上层的PNP晶体管T4进入放大区工作,并驱动下层的NPN晶体管T3,NPN晶体管T3开启后又反过来驱动上层PNP晶体管T4,如此形成正反馈。再生反馈效应使得绝缘栅双极型晶体管的栅极失去对电流的控制,使得绝缘栅双极型晶体管中的电流迅速增大。当电流大于预设电流阈值后,可能使绝缘栅双极型晶体管过热烧毁,因此闩锁现象限制了绝缘栅双极型晶体管的最大安全工作电流。When the current density in the insulated gate bipolar transistor is greater than the preset current density threshold, an excessively high electron current flows through the body region under the emitter, and this current generates a voltage drop on the body region path resistance. When the voltage drop is greater than the preset voltage drop threshold, the PN junction formed by the body region and the emitter region is positively biased, and the upper PNP transistor T4 enters the amplification region to work, and drives the lower NPN transistor T3. After the NPN transistor T3 is turned on In turn, the upper PNP transistor T4 is driven to form a positive feedback. The regenerative feedback effect causes the gate of the insulated gate bipolar transistor to lose control of the current, so that the current in the insulated gate bipolar transistor increases rapidly. When the current is greater than the preset current threshold, the insulated gate bipolar transistor may be overheated and burned. Therefore, the latch-up phenomenon limits the maximum safe operating current of the insulated gate bipolar transistor.
在本公开实施例中,通过将发射极金属、发射极区以及栅极区并列设置,将与栅极区接触的体区设置在发射极金属与发射极区下方,可减小所述发射极区底部与所述体区之间的接触界面的宽度,从而减少体区的寄生电阻,降低电流在体区路径电阻上的压降,减小体区与发射极区形成的PN 结发生正偏的几率,提高绝缘栅双极型晶体管的抗闩锁性能。In the embodiments of the present disclosure, by arranging the emitter metal, the emitter region, and the gate region in parallel, and the body region in contact with the gate region is arranged under the emitter metal and the emitter region, the emitter can be reduced. The width of the contact interface between the bottom of the region and the body region, thereby reducing the parasitic resistance of the body region, reducing the voltage drop of the current on the path resistance of the body region, and reducing the positive bias of the PN junction formed by the body region and the emitter region The probability of improving the latch-up resistance of insulated gate bipolar transistors.
此外,本公开实施例提供的绝缘栅双极型晶体管通过沿栅极区向漂移区的方向延伸发射极区和栅极区,可将发射极金属与栅极区之间形成的横向电场作用于体区中,所述横向电场的方向可加速体区中的多数载流子向发射极金属运动,缩短体区中多数载流子在体区与发射极区之间的接触界面处停留的时间,进一步降低发射极与体区形成的PN结发生正偏的几率,提高绝缘栅双极型晶体管的抗闩锁性能。In addition, the insulated gate bipolar transistor provided by the embodiments of the present disclosure can act on the lateral electric field formed between the emitter metal and the gate region by extending the emitter region and the gate region in the direction from the gate region to the drift region. In the body region, the direction of the transverse electric field can accelerate the movement of the majority carriers in the body region to the emitter metal, and shorten the time that the majority carriers in the body region stay at the contact interface between the body region and the emitter region , Further reduce the probability of forward bias of the PN junction formed by the emitter and the body region, and improve the latch-up resistance of the insulated gate bipolar transistor.
在一些实施例中,所述集电极区60中第一类载流子的掺杂浓度大于所述集电极区60中第二类载流子掺杂浓度;其中,所述第一类载流子的带电类型和所述第二类载流子的带电类型不同;In some embodiments, the doping concentration of the first type carrier in the collector region 60 is greater than the doping concentration of the second type carrier in the collector region 60; wherein, the first type carrier The charging type of the carrier is different from the charging type of the second type of carrier;
所述集电极区60中所述第一类载流子的掺杂浓度大于所述漂移区20中所述第二类载流子的掺杂浓度;其中,所述漂移区20中所述第二类载流子的掺杂浓度大于所述漂移区20中所述第一类载流子的掺杂浓度。The doping concentration of the first type of carrier in the collector region 60 is greater than the doping concentration of the second type of carrier in the drift region 20; wherein, the first type of carrier in the drift region 20 The doping concentration of the second type of carrier is greater than the doping concentration of the first type of carrier in the drift region 20.
在一些实施例中,所述绝缘栅双极型晶体管还包括:栅极金属70,位于所述栅极区50上方,所述栅极金属70与所述栅极区50形成欧姆接触。In some embodiments, the insulated gate bipolar transistor further includes a gate metal 70 located above the gate region 50, and the gate metal 70 forms an ohmic contact with the gate region 50.
在本公开实施例中,通过在栅极金属与栅极区之间形成欧姆接触,可减小栅极金属与栅极区之间的接触电阻,使栅极金属与栅极区形成等电位,增加栅压的调控性。In the embodiments of the present disclosure, by forming an ohmic contact between the gate metal and the gate region, the contact resistance between the gate metal and the gate region can be reduced, and the gate metal and the gate region can be equipotential. Increase the controllability of grid voltage.
在一些实施例中,所述绝缘栅双极型晶体管还包括:集电极金属80,位于所述集电极区60下方,所述集电极金属80与所述集电极区60形成欧姆接触。In some embodiments, the insulated gate bipolar transistor further includes: a collector metal 80 located under the collector region 60, and the collector metal 80 forms an ohmic contact with the collector region 60.
在本公开实施例中,通过在集电极金属与集电极区之间形成欧姆接触,可可减小集电极金属与集电极区之间的接触电阻,降低该接触电阻引起的能量耗散,提高绝缘栅双极型晶体管在高温状态下工作的稳定性。In the embodiments of the present disclosure, by forming an ohmic contact between the collector metal and the collector region, the contact resistance between the collector metal and the collector region can be reduced, the energy dissipation caused by the contact resistance can be reduced, and the insulation can be improved. The stability of gate bipolar transistors at high temperatures.
在一些实施例中,所述接触界面的宽度大于或等于0.5μm。In some embodiments, the width of the contact interface is greater than or equal to 0.5 μm.
在本公开实施例中,所述接触界面的宽度大于或等于预设宽度阈值,所述预设宽度阈值可为0.5μm、0.6μm、0.8μm等。当所述接触界面的宽度小于预设宽度阈值时,在电场作用下发射极金属与栅极层之间发生击穿的几率增大,导致绝缘栅双极型晶体管失效,降低了绝缘栅双极型晶体管的可靠性。In the embodiment of the present disclosure, the width of the contact interface is greater than or equal to a preset width threshold, and the preset width threshold may be 0.5 μm, 0.6 μm, 0.8 μm, or the like. When the width of the contact interface is less than the preset width threshold, the probability of breakdown between the emitter metal and the gate layer under the action of an electric field increases, resulting in the failure of the insulated gate bipolar transistor and reducing the insulated gate bipolar transistor. Reliability of type transistors.
本公开实施例还提供一种绝缘栅双极型晶体管的制作方法,包括:The embodiment of the present disclosure also provides a manufacturing method of an insulated gate bipolar transistor, including:
形成位于漂移区和发射极区之间的体区;其中,所述体区与所述漂移区、所述发射极区、发射极金属、栅极区接触;Forming a body region located between the drift region and the emitter region; wherein the body region is in contact with the drift region, the emitter region, the emitter metal, and the gate region;
在所述体区上方形成与所述发射极区接触的所述发射极金属;Forming the emitter metal in contact with the emitter region above the body region;
在所述发射极金属和所述栅极区之间形成所述发射极区;其中,所述发射极区底部与所述体区之间的接触界面的宽度,小于所述发射极区顶部的宽度;The emitter region is formed between the emitter metal and the gate region; wherein the width of the contact interface between the bottom of the emitter region and the body region is smaller than that of the top of the emitter region width;
在所述漂移区上方形成所述栅极区;其中,所述栅极区与所述发射极区接触。The gate region is formed above the drift region; wherein the gate region is in contact with the emitter region.
在本公开实施例中,可通过热氧化或者薄膜沉积的方法,分别制作特殊结构的栅极区和发射极金属。In the embodiments of the present disclosure, the gate region and the emitter metal with a special structure can be fabricated separately by thermal oxidation or thin film deposition.
在本公开实施例中,可通过离子注入的方法分别制备掺杂的体区、发射极区、漂移区。In the embodiments of the present disclosure, the doped body region, emitter region, and drift region can be separately prepared by ion implantation.
在本公开实施例中,可通过自对准离子注入的方式减小所述发射极区底部与所述体区之间的接触界面的宽度,从而减少体区的寄生电阻,降低电流在体区路径电阻上的压降,提高绝缘栅双极型晶体管的抗闩锁性能。In the embodiments of the present disclosure, the width of the contact interface between the bottom of the emitter region and the body region can be reduced by means of self-aligned ion implantation, thereby reducing the parasitic resistance of the body region and reducing the current in the body region. The voltage drop on the path resistance improves the latch-up resistance of the insulated gate bipolar transistor.
此外,本公开实施例通过形成并列设置的发射极金属、发射极区以及栅极区,将与栅极区接触的体区设置在发射极金属与发射极区下方,可将发射极金属与栅极区之间形成的横向电场作用于体区中,所述横向电场的方向可加速体区中的多数载流子向发射极金属运动,缩短体区中多数载流 子在所述接触界面处停留的时间,降低发射极与体区形成的PN结发生正偏的几率,进一步提高绝缘栅双极型晶体管的抗闩锁性能。In addition, in the embodiments of the present disclosure, the emitter metal, the emitter region, and the gate region are formed in parallel, and the body region in contact with the gate region is arranged under the emitter metal and the emitter region. The transverse electric field formed between the polar regions acts on the body region. The direction of the transverse electric field can accelerate the movement of majority carriers in the body region to the emitter metal, shortening the majority of carriers in the body region at the contact interface. The staying time reduces the probability that the PN junction formed by the emitter and the body region will be positively biased, and further improves the latch-up resistance of the insulated gate bipolar transistor.
在一些实施例中,所述绝缘栅双极型晶体管的制作方法还包括:在所述漂移区下方形成集电极区;其中,所述集电极区的掺杂浓度大于所述体区的掺杂浓度。In some embodiments, the manufacturing method of the insulated gate bipolar transistor further includes: forming a collector region under the drift region; wherein the doping concentration of the collector region is greater than that of the body region. concentration.
在一些实施例中,所述集电极区中第一类载流子掺杂浓度大于所述漂移区中第二类载流子掺杂浓度;其中,所述第一类载流子的带电类型和所述第二类载流子的带电类型不同,所述集电极区中所述第一类载流子掺杂浓度大于所述集电极区中所述第二类载流子掺杂浓度,所述漂移区中所述第二类载流子的掺杂浓度大于所述漂移区中所述第一类载流子的掺杂浓度。In some embodiments, the doping concentration of the first type of carriers in the collector region is greater than the doping concentration of the second type of carriers in the drift region; wherein the charge type of the first type of carriers Different from the charging type of the second type of carriers, the doping concentration of the first type of carriers in the collector region is greater than the doping concentration of the second type of carriers in the collector region, The doping concentration of the second type of carriers in the drift region is greater than the doping concentration of the first type of carriers in the drift region.
在一些实施例中,所述绝缘栅双极型晶体管的制作方法还包括:在所述栅极区上方形成栅极金属;其中,所述栅极金属与所述栅极区形成欧姆接触。In some embodiments, the manufacturing method of the insulated gate bipolar transistor further includes: forming a gate metal above the gate region; wherein the gate metal forms an ohmic contact with the gate region.
示例1Example 1
以漂移区为施主掺杂的N型绝缘栅双极型晶体管器件为例,绝缘栅双极型晶体管的结构包括了N型绝缘栅型场效应管、由体区-漂移区-集电极区构成的PNP双极型晶体管T1及由发射极区-体区-漂移区构成的寄生NPN双极型晶体管T2。其中晶体管T1和晶体管T2组成了N-P-N-P的四层三结的晶闸管结构。因此,当绝缘栅双极型晶体管中的电流密度大于预设电流密度阈值时,所述晶闸管可以导通,可造成绝缘栅双极型晶体管永久性损坏。Take the N-type insulated gate bipolar transistor device doped with the drift region as the donor as an example. The structure of the insulated gate bipolar transistor includes the N-type insulated gate field effect transistor, which is composed of body region-drift region-collector region PNP bipolar transistor T1 and a parasitic NPN bipolar transistor T2 composed of emitter region-body region-drift region. Among them, the transistor T1 and the transistor T2 form an N-P-N-P four-layer triple junction thyristor structure. Therefore, when the current density in the insulated gate bipolar transistor is greater than the preset current density threshold, the thyristor can be turned on, which can cause permanent damage to the insulated gate bipolar transistor.
绝缘栅双极型晶体管发生闩锁的必要条件为晶体管T2导通,即绝缘栅双极型晶体管的体区与发射极形成的PN结发生正偏。由于IGBT的阴极N发射极和P体区在同一电位上,因此T2的基极-发射极正偏只可能在体区 中的空穴沿着N发射极流向阴极接触面时出现。由于P体区存在一定的导通电阻,这样的空穴电流将导致一定的电压降,从而打开T2的基极-发射极PN结,最终与PNP型晶体管T1形成正反馈,使绝缘栅双极型晶体管器件过热烧毁。The necessary condition for the latch-up of the insulated gate bipolar transistor is that the transistor T2 is turned on, that is, the PN junction formed by the body region of the insulated gate bipolar transistor and the emitter is forward biased. Since the N-emitter and P-body region of the cathode of the IGBT are at the same potential, the base-emitter forward bias of T2 can only appear when holes in the body region flow along the N-emitter to the cathode contact surface. Since there is a certain on-resistance in the P body region, such hole current will cause a certain voltage drop, thereby opening the base-emitter PN junction of T2, and finally forming a positive feedback with the PNP transistor T1, making the insulated gate bipolar Type transistor device is overheated and burned.
要抑制寄生晶闸管的闩锁效应,就必须减小上层T2管和下层T1管的开基极电流增益,由于宽基区的下层T1管在绝缘栅双极型晶体管正常工作时需要传导通态电流,减小其电流增益会增大绝缘栅双极型晶体管的导通压降,而上层T2管通常不参与绝缘栅双极型晶体管导通态电流的传导。因此,最好是降低上层T2管的电流增益。可以通过增加体区的掺杂浓度降低T2管的电流增益,以防止闩锁效应发生。但该方法会增加绝缘栅双极型晶体管的阈值电压并降低反向耐压性能。To suppress the latch-up effect of the parasitic thyristor, it is necessary to reduce the open base current gain of the upper T2 tube and the lower T1 tube, because the lower T1 tube with a wide base area needs to conduct the on-state current when the insulated gate bipolar transistor is working normally , Reducing its current gain will increase the on-voltage drop of the insulated gate bipolar transistor, and the upper T2 tube usually does not participate in the conduction of the on-state current of the insulated gate bipolar transistor. Therefore, it is best to reduce the current gain of the upper T2 tube. The current gain of the T2 tube can be reduced by increasing the doping concentration of the body region to prevent the latch-up effect. However, this method increases the threshold voltage of the insulated gate bipolar transistor and reduces the reverse withstand voltage performance.
如图4所示,本示例提供了一种绝缘栅双极型晶体管的结构示意图。所述绝缘栅双极型晶体管包括:P型体区10、N-型漂移区20、N+型发射极区30、发射极金属40。栅极区50、P+型集电极区60、栅极金属70、集电极金属80。其中,正号(+)表示掺杂浓度较高,负号(-)表示掺杂浓度较低,E表示发射极段,G表示栅极端,C表示集电极端。栅极区50与N+型发射极区30、P型体区10、N-型漂移区20的接触面为一层薄的绝缘氧化层(图4中未标注)。As shown in FIG. 4, this example provides a schematic structural diagram of an insulated gate bipolar transistor. The insulated gate bipolar transistor includes a P-type body region 10, an N-type drift region 20, an N+ type emitter region 30, and an emitter metal 40. The gate region 50, the P+ type collector region 60, the gate metal 70, and the collector metal 80. Among them, a positive sign (+) indicates a higher doping concentration, a negative sign (-) indicates a lower doping concentration, E indicates an emitter section, G indicates a gate terminal, and C indicates a collector terminal. The contact surface between the gate region 50 and the N+ type emitter region 30, the P type body region 10, and the N- type drift region 20 is a thin insulating oxide layer (not labeled in FIG. 4).
在本示例中,栅极区50和发射极金属40为梯形结构,且栅极区的底部与发射极金属的底部之间的距离,小于栅极区的顶部与发射极金属的顶部之间的距离。In this example, the gate region 50 and the emitter metal 40 have a trapezoidal structure, and the distance between the bottom of the gate region and the bottom of the emitter metal is smaller than the distance between the top of the gate region and the top of the emitter metal. distance.
在一些实施例中,栅极区和发射极金属的形状也可为三角形结构、扇形结构或其他任意形状,只需保证栅极区底部与发射极金属底部的距离尽量较小,以减小发射极区与体区之间的接触界面的宽度,可实现减小体区与发射极区的接触电阻,降低了体区与发射极区形成的PN结的压降,减小 了所述PN结发生正偏的几率,提高了绝缘栅双极型晶体管的抗闩锁性能。In some embodiments, the shape of the gate region and the emitter metal can also be a triangular structure, a sector structure or other arbitrary shapes. It is only necessary to ensure that the distance between the bottom of the gate region and the bottom of the emitter metal is as small as possible to reduce emission. The width of the contact interface between the pole region and the body region can reduce the contact resistance between the body region and the emitter region, reduce the voltage drop of the PN junction formed by the body region and the emitter region, and reduce the PN junction The probability of occurrence of forward bias improves the latch-up resistance of the insulated gate bipolar transistor.
本示例提供的绝缘栅双极性晶体管还通过沿栅极区向漂移区的方向延伸发射极区和栅极区,将发射极金属与栅极区之间形成的横向电场作用于体区中,所述横向电场的方向可加速体区中的多数载流子向发射极金属运动,缩短体区中多数载流子在体区与发射极区之间的接触界面处停留的时间,进一步降低体区与发射极区形成的PN结发生正偏的几率,提高绝缘栅双极型晶体管的抗闩锁性能。The insulated gate bipolar transistor provided in this example also extends the emitter region and the gate region in the direction from the gate region to the drift region, so that the lateral electric field formed between the emitter metal and the gate region acts on the body region. The direction of the transverse electric field can accelerate the movement of the majority carriers in the body region to the emitter metal, shorten the time that the majority carriers in the body region stay at the contact interface between the body region and the emitter region, and further reduce the body region. The probability that the PN junction formed by the region and the emitter region is positively biased improves the latch-up resistance of the insulated gate bipolar transistor.
在一些实施例中,所述绝缘栅双极型晶体管可为常规平面栅结构、沟槽栅结构、穿通结构(PT结构)、场终止-沟槽结构(FS-Trench结构)等。In some embodiments, the insulated gate bipolar transistor may be a conventional planar gate structure, a trench gate structure, a punch-through structure (PT structure), a field stop-trench structure (FS-Trench structure), etc.
在本示例中,可通过热氧化或者薄膜沉积的方法,分别制作特殊结构的栅极区和发射极金属。In this example, the gate region and the emitter metal with a special structure can be fabricated separately by thermal oxidation or thin film deposition.
在本示例中,可通过离子注入的方法实现体区和漂移区的掺杂。In this example, the body region and drift region can be doped by ion implantation.
在本公开所提供的几个实施例中,应该理解到,所揭露的设备和方法,可以通过其它的方式实现。以上所描述的设备实施例仅仅是示意性的,例如,所述单元的划分,仅仅为一种逻辑功能划分,实际实现时可以有另外的划分方式,如:多个单元或组件可以结合,或可以集成到另一个系统,或一些特征可以忽略,或不执行。另外,所显示或讨论的各组成部分相互之间的耦合、或直接耦合、或通信连接可以是通过一些接口,设备或单元的间接耦合或通信连接,可以是电性的、机械的或其它形式的。In the several embodiments provided in the present disclosure, it should be understood that the disclosed device and method may be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division, and there may be other divisions in actual implementation, such as: multiple units or components can be combined, or It can be integrated into another system, or some features can be ignored or not implemented. In addition, the coupling, or direct coupling, or communication connection between the components shown or discussed may be indirect coupling or communication connection through some interfaces, devices or units, and may be electrical, mechanical or other forms of.
上述作为分离部件说明的单元可以是、或也可以不是物理上分开的,作为单元显示的部件可以是、或也可以不是物理单元,即可以位于一个地方,也可以分布到多个网络单元上;可以根据实际的需要选择其中的部分或全部单元来实现本实施例方案的目的。The units described above as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units; Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
另外,在本公开各实施例中的各功能单元可以全部集成在一个处理模块中,也可以是各单元分别单独作为一个单元,也可以两个或两个以上单 元集成在一个单元中;上述集成的单元既可以采用硬件的形式实现,也可以采用硬件加软件功能单元的形式实现。本领域普通技术人员可以理解:实现上述方法实施例的全部或部分步骤可以通过程序指令相关的硬件来完成,前述的程序可以存储于一计算机可读取存储介质中,该程序在执行时,执行包括上述方法实施例的步骤;而前述的存储介质包括:移动存储设备、只读存储器(ROM,Read-Only Memory)、随机存取存储器(RAM,Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。In addition, the functional units in the embodiments of the present disclosure can be all integrated into one processing module, or each unit can be individually used as a unit, or two or more units can be integrated into one unit; The unit can be implemented in the form of hardware, or in the form of hardware plus software functional units. A person of ordinary skill in the art can understand that all or part of the steps in the above method embodiments can be implemented by a program instructing relevant hardware. The foregoing program can be stored in a computer readable storage medium. When the program is executed, it is executed. Including the steps of the foregoing method embodiment; and the foregoing storage medium includes: removable storage devices, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disks or optical disks, etc. A medium that can store program codes.
本申请所提供的几个方法实施例中所揭露的方法,在不冲突的情况下可以任意组合,得到新的方法实施例。The methods disclosed in the several method embodiments provided in this application can be combined arbitrarily without conflict to obtain new method embodiments.
本申请所提供的几个产品实施例中所揭露的特征,在不冲突的情况下可以任意组合,得到新的产品实施例。The features disclosed in the several product embodiments provided in this application can be combined arbitrarily without conflict to obtain new product embodiments.
本申请所提供的几个方法或设备实施例中所揭露的特征,在不冲突的情况下可以任意组合,得到新的方法实施例或设备实施例。The features disclosed in the several method or device embodiments provided in this application can be combined arbitrarily without conflict to obtain a new method embodiment or device embodiment.
以上所述,仅为本公开的具体实施方式,但本公开的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本公开揭露的技术范围内,可轻易想到变化或替换,都应涵盖在本公开的保护范围之内。因此,本公开的保护范围应以所述权利要求的保护范围为准。The above are only specific implementations of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present disclosure. It should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims (10)

  1. 一种绝缘栅双极型晶体管,包括:An insulated gate bipolar transistor including:
    体区,位于漂移区与发射极区之间,与所述漂移区、所述发射极区、发射极金属及栅极区接触;The body region is located between the drift region and the emitter region and is in contact with the drift region, the emitter region, the emitter metal and the gate region;
    所述发射极金属,位于所述体区上方,与所述发射极区接触;The emitter metal is located above the body region and is in contact with the emitter region;
    所述发射极区,位于所述发射极金属与所述栅极区之间;其中,所述发射极区底部和所述体区之间的接触界面的宽度,小于所述发射极区顶部的宽度;The emitter region is located between the emitter metal and the gate region; wherein the width of the contact interface between the bottom of the emitter region and the body region is smaller than that of the top of the emitter region width;
    所述栅极区,位于所述漂移区上方,与所述发射极区接触。The gate region is located above the drift region and is in contact with the emitter region.
  2. 根据权利要求1所述的绝缘栅双极型晶体管,其中,The insulated gate bipolar transistor according to claim 1, wherein:
    所述体区中的第一类载流子的掺杂浓度大于所述体区中的第二类载流子的掺杂浓度;其中,所述第一类载流子的带电荷类型和所述第二类载流子的带电荷类型不同;The doping concentration of the first type of carriers in the body region is greater than the doping concentration of the second type of carriers in the body region; wherein the charge type and the charge type of the first type of carriers The charge types of the second type of carriers are different;
    所述栅极区,除了加压形成反型沟道,使绝缘栅双极型晶体管正常工作外,还可配置为当所述绝缘栅双极型晶体管导通时,与所述发射极金属之间形成电场,促进所述体区中的所述第一类载流子向所述发射极金属移动。The gate region, in addition to forming an inversion channel under pressure to make the insulated gate bipolar transistor work normally, can also be configured to be in contact with the emitter metal when the insulated gate bipolar transistor is turned on. An electric field is formed between them to promote the movement of the first-type carriers in the body region to the emitter metal.
  3. 根据权利要求1所述的绝缘栅双极型晶体管,其中,还包括:The insulated gate bipolar transistor according to claim 1, further comprising:
    集电极区,位于所述漂移区下方,所述集电极区的掺杂浓度大于所述体区的掺杂浓度。The collector region is located below the drift region, and the doping concentration of the collector region is greater than the doping concentration of the body region.
  4. 根据权利要求3所述的绝缘栅双极型晶体管,其中,The insulated gate bipolar transistor according to claim 3, wherein:
    所述集电极区中第一类载流子的掺杂浓度大于所述集电极区中第二类载流子掺杂浓度;其中,所述第一类载流子的带电类型和所述第二类载流子的带电类型不同;The doping concentration of the first type of carriers in the collector region is greater than the doping concentration of the second type of carriers in the collector region; wherein, the charging type of the first type of carriers and the The charge types of the two types of carriers are different;
    所述集电极区中所述第一类载流子的掺杂浓度大于所述漂移区中所述第二类载流子的掺杂浓度;其中,所述漂移区中所述第二类载流子的掺杂浓度大于所述漂移区中所述第一类载流子的掺杂浓度。The doping concentration of the first type of carriers in the collector region is greater than the doping concentration of the second type of carriers in the drift region; wherein the second type of carriers in the drift region The doping concentration of carriers is greater than the doping concentration of the first type carriers in the drift region.
  5. 根据权利要求1所述的绝缘栅双极型晶体管,其中,还包括:The insulated gate bipolar transistor according to claim 1, further comprising:
    栅极金属,位于所述栅极区上方,所述栅极金属与所述栅极区形成欧姆接触;Gate metal located above the gate region, and the gate metal forms an ohmic contact with the gate region;
    所述栅极层与所述发射极区、所述体区、所述漂移区之间由一层很薄的绝缘氧化层隔开。The gate layer is separated from the emitter region, the body region, and the drift region by a thin insulating oxide layer.
  6. 根据权利要求1至5任一项所述的绝缘栅双极型晶体管,其中,The insulated gate bipolar transistor according to any one of claims 1 to 5, wherein:
    所述接触界面的宽度大于或等于0.5μm。The width of the contact interface is greater than or equal to 0.5 μm.
  7. 一种绝缘栅双极型晶体管的制作方法,包括:A method for manufacturing an insulated gate bipolar transistor includes:
    形成位于漂移区和发射极区之间的体区;其中,所述体区与所述漂移区、所述发射极区、发射极金属、栅极区接触;Forming a body region located between the drift region and the emitter region; wherein the body region is in contact with the drift region, the emitter region, the emitter metal, and the gate region;
    在所述体区上方形成与所述发射极区接触的所述发射极金属;Forming the emitter metal in contact with the emitter region above the body region;
    在所述发射极金属和所述栅极区之间形成所述发射极区;其中,所述发射极区底部与所述体区之间的接触界面的宽度,小于所述发射极区顶部的宽度;The emitter region is formed between the emitter metal and the gate region; wherein the width of the contact interface between the bottom of the emitter region and the body region is smaller than that of the top of the emitter region width;
    在所述漂移区上方形成所述栅极区;其中,所述栅极区与所述发射极区接触。The gate region is formed above the drift region; wherein the gate region is in contact with the emitter region.
  8. 根据权利要求7所述的制作方法,其中,还包括:The production method according to claim 7, further comprising:
    在所述漂移区下方形成集电极区;其中,所述集电极区的掺杂浓度大于所述体区的掺杂浓度。A collector region is formed under the drift region; wherein the doping concentration of the collector region is greater than the doping concentration of the body region.
  9. 根据权利要求8所述的制作方法,其中,The manufacturing method according to claim 8, wherein:
    所述集电极区中第一类载流子掺杂浓度大于所述漂移区中第二类载流子掺杂浓度;其中,所述第一类载流子的带电类型和所述第二类载流子的 带电类型不同;The doping concentration of the first type of carriers in the collector region is greater than the doping concentration of the second type of carriers in the drift region; wherein the charging type of the first type of Different types of charge carriers;
    所述集电极区中所述第一类载流子掺杂浓度大于所述漂移区中所述第二类载流子掺杂浓度;其中,所述漂移区中所述第二类载流子的掺杂浓度大于所述漂移区中所述第一类载流子的掺杂浓度。The doping concentration of the first type of carriers in the collector region is greater than the doping concentration of the second type of carriers in the drift region; wherein, the second type of carriers in the drift region The doping concentration of is greater than the doping concentration of the first type of carriers in the drift region.
  10. 根据权利要求8所述的制作方法,其中,还包括:The production method according to claim 8, further comprising:
    在所述栅极区上方形成栅极金属;其中,所述栅极金属与所述栅极区形成欧姆接触。A gate metal is formed above the gate region; wherein, the gate metal forms an ohmic contact with the gate region.
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CN208077983U (en) * 2018-04-23 2018-11-09 广东美的制冷设备有限公司 The insulated gate bipolar transistor of 4H-SiC

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