WO2021017232A1 - 一种灵活调配且易于cpld管理背板的方法与系统 - Google Patents

一种灵活调配且易于cpld管理背板的方法与系统 Download PDF

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WO2021017232A1
WO2021017232A1 PCT/CN2019/114524 CN2019114524W WO2021017232A1 WO 2021017232 A1 WO2021017232 A1 WO 2021017232A1 CN 2019114524 W CN2019114524 W CN 2019114524W WO 2021017232 A1 WO2021017232 A1 WO 2021017232A1
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cpld
eeprom
backplane
easy
connection
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唐传贞
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Suzhou Wave Intelligent Technology Co Ltd
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Suzhou Wave Intelligent Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/60—Software deployment
    • G06F8/65—Updates
    • G06F8/654—Updates using techniques specially adapted for alterable solid state memories, e.g. for EEPROM or flash memories
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0016—Inter-integrated circuit (I2C)

Definitions

  • the invention relates to the technical field of storage design, in particular to a method and system for flexible deployment and easy CPLD management backplane.
  • NVME interface SSDs use PCIE bus to directly connect to the PCIE port of the CPU. Since the hard disk needs to have an indicator to show the working status of the hard disk when it is working, when the industry launched the NVME hard disk, the hard disk lighting service was also developed. When the current NVME hard disk is directly connected to the CPU, the hard disk control comes from the CPU, and the lighting function is the same Comes from the CPU.
  • the current lighting channel of Intel's CPU to NVME hard disk is connected to the CPLD of the backplane where the hard disk is located through the VPP bus.
  • the CPLD parses out specific lighting signals to control the physical lights The light off.
  • NVME hard disks Current servers are mostly multi-channel servers, that is, they contain multiple CPUs inside.
  • the NVME hard disk connected to each CPU needs to be controlled by the CPU’s VPP to control the lighting.
  • the NVME hard disk backplane is a multi-interface backplane, for example, it supports 4 NVME hard disk interface, or 8 NVME hard disk interfaces
  • CPLD needs to identify the connection method of the hard disk backplane and the motherboard CPU when analyzing the VPP bus protocol, and also need to know which CPU it is Which PCIE interface is connected, and then perform analysis and lighting.
  • 4 NVME hard disks connected to two CPUs as an example, there are as many as 5 connection methods.
  • the current method is to use the DIP switch, at least 3 pairs of DIP switches are required, and 3 signals need to be connected to the CPLD.
  • the number of hard disks increases and the number of CPUs increases, the number of DIP switch signals increases exponentially, occupying a large number of CPLD pins and a large amount of PCB area to place DIP switches.
  • the purpose of the present invention is to provide a method and system for flexible deployment and easy CPLD management of the backplane, which aims to solve the problem that the multi-port number backplane occupies too many CPLD pins and the dial switch is prone to error in the prior art, and realizes occupation CPLD has fewer pins and saves a lot of DIP switches.
  • the present invention provides a flexible deployment and easy CPLD management backplane method, the method includes the following operations:
  • the CPLD reads the connection relationship information in the EEPROM, and analyzes the VPP protocol bus to obtain the corresponding lighting mode.
  • the EEPROM is connected with CPLD and BMC through I2C respectively.
  • the number of pins occupied in the CPLD is two.
  • the method further includes:
  • the BMC updates the connection information content in the EEPROM through the I2C bus, and then shuts down the whole machine and powers on again.
  • the CPLD reads the new connection information from the EEPROM to complete the new connection. VPP bus analysis.
  • the present invention also provides a flexible deployment and easy CPLD management backplane system, the system includes:
  • EEPROM add module used to add EEPROM on the backplane, connect EEPROM with CPLD and BMC respectively;
  • the configuration information burning module is used to burn the connection relationship information between the backplane hard disk interface and the motherboard CPU in the EEPROM;
  • Protocol analysis module used for CPLD to read the connection relationship information in EEPROM after power-on, and analyze the VPP protocol bus to get the corresponding lighting mode.
  • the EEPROM is connected with CPLD and BMC through I2C respectively.
  • the number of pins occupied in the CPLD is two.
  • the system further includes:
  • connection relationship update module is used to update the connection relationship information content in the EEPROM through the I2C bus when the connection mode of the CPU and the hard disk interface changes, and then power off the whole machine again, and the CPLD reads the new one from the EEPROM Connection relationship information, complete new VPP bus analysis.
  • the present invention adds an EEPROM module on the backplane, stores the connection configuration mode of the hard disk backplane and the motherboard-side controller in the EEPROM module, and CPLD reads the connection relationship information from the EEPROM through I2C to perform Lighting function and other similar control functions.
  • the BMC management module on the motherboard when the configuration changes, the BMC directly upgrades the stored information in the EEPROM module through the I2C bus without disassembling.
  • the invention only needs to occupy two pins of the CPLD, and there is no need to consider that more CPLD pins are required for more complicated configurations.
  • the DIP switches need to be manually set, when there are many DIP switches, the operator is prone to errors, resulting in products Configuration errors and abnormal product functions directly affect product quality.
  • the present invention can effectively avoid such problems.
  • FIG. 1 is a flow chart of a method for flexible deployment and easy CPLD management backplane provided in an embodiment of the present invention
  • FIG. 2 is a schematic diagram of the connection between a dual CPU and four NVME hard disks provided in an embodiment of the present invention
  • FIG. 3 is a schematic diagram of a CPLD and dial-up connection method provided in an embodiment of the present invention
  • FIG. 4 is a schematic diagram of the connection between an EEPROM and CPLD and BMC provided in an embodiment of the present invention
  • FIG. 5 is a system block diagram of a flexible deployment and easy CPLD management backplane provided in an embodiment of the present invention.
  • the embodiment of the present invention discloses a method for flexible deployment and easy CPLD management backplane, and the method includes the following operations:
  • the CPLD reads the connection relationship information in the EEPROM, and analyzes the VPP protocol bus to obtain the corresponding lighting mode.
  • an EEPROM is added to the backplane, and the interconnection and connection relationship information between the backplane and the main board system is burned in the EEPROM.
  • the CPLD and the EEPROM are interconnected, and the connection relationship information is read from the EEPROM when the power is turned on, and the BMC is connected to the EEPROM on the backplane.
  • the BMC can update the connection relationship information in the EEPROM in real time as required after power-on, thereby eliminating the use of a large number of DIP switches.
  • the CPLD For the five combinations in the table, the CPLD must recognize which combination it is. In the past, the CPLD needs to add several pins. Connect these pins to the DIP switch, and the DIP switch can be set to high level. , You can also dial to low level. CPLD judges the different combinations of CPU and NVME hard disk interface by detecting the different levels of these pins, as shown in Figure 3 and Table 2. CPLD connects three pins to the three DIP switches of the DIP switch. Five combinations are formed by the different high and low levels of three dial codes, corresponding to the five combinations of CPU connected to hard disk.
  • the backplane CPLD By adding an EEPROM on the backplane, connect the backplane CPLD and this EEPROM through the I2C bus, and connect the BMC on the motherboard to the EEPROM on the backplane through I2C. Burn the backplane port number information and the connection information between the backplane and the motherboard CPU in the EEPROM. After power-on, the CPLD reads the connection relationship information from the EEPROM. According to the identified connection relationship information, the CPLD parses the VPP protocol bus and lights the hard disk with The actual CPU control corresponds well, as shown in Figure 4.
  • the CPLD in Figure 4 is the CPLD on the hard disk backplane described above, and the BMC is a management module.
  • the module is a storage module, and the connection relationship information can be burned into this storage module.
  • the CPLD will read the configuration relationship between the backplane hard disk interface and the CPU on the motherboard from the EEPROM, and then send the CPU to the CPLD's VPP bus for analysis into the corresponding lighting method.
  • connection mode of the CPU and the hard disk interface is changed, only the BMC needs to update the configuration content in the EEPROM through the I2C bus, and then power off the whole machine again, and the CPLD reads the new connection relationship information from the EEPROM to complete the new VPP bus analysis. Therefore, this solution only needs to occupy two pins of the CPLD. Even if it is a complicated connection method, this connection method can be maintained. At the same time, even if the BMC module on the motherboard is abnormal, it will not affect the CPLD on the backplane to capture from the EEPROM. ⁇ .
  • an EEPROM module is added to the backplane, and the connection configuration mode of the hard disk backplane and the motherboard-side controller is stored in the EEPROM module.
  • the CPLD reads the connection relationship information from the EEPROM through I2C, thereby performing lighting functions and other similar Control function, in addition, by adding the connection of the BMC management module on the motherboard to this EEPROM module, when the configuration changes, the BMC directly upgrades the stored information in the EEPROM module through the I2C bus without disassembling.
  • the invention only needs to occupy two pins of the CPLD, and there is no need to consider that more CPLD pins are required for more complicated configurations.
  • the DIP switches need to be manually set, when there are many DIP switches, the operator is prone to errors, resulting in products Configuration errors and abnormal product functions directly affect product quality.
  • the present invention can effectively avoid such problems.
  • the embodiment of the present invention also discloses a system for flexible deployment and easy CPLD management backplane, the system includes:
  • EEPROM add module used to add EEPROM on the backplane, connect EEPROM with CPLD and BMC respectively;
  • the configuration information burning module is used to burn the connection relationship information between the backplane hard disk interface and the motherboard CPU in the EEPROM;
  • Protocol analysis module used for CPLD to read the connection relationship information in EEPROM after power-on, and analyze the VPP protocol bus to get the corresponding lighting mode.
  • the backplane CPLD By adding an EEPROM on the backplane, connect the backplane CPLD and this EEPROM through the I2C bus, and connect the BMC on the motherboard to the EEPROM on the backplane through I2C. Burn the backplane port number information and the connection information between the backplane and the motherboard CPU in the EEPROM. After power-on, the CPLD reads the connection relationship information from the EEPROM. According to the identified connection relationship information, the CPLD parses the VPP protocol bus and lights the hard disk with The actual CPU control corresponds well.
  • the EPPROM module is a storage module, and the connection relationship information can be burned into this storage module.
  • the CPLD When the backplane is powered on, the CPLD will read the configuration relationship between the backplane hard disk interface and the CPU on the motherboard from the EEPROM, and then send the CPU to the CPLD's VPP bus for analysis into the corresponding lighting method.
  • the connection mode of the CPU and the hard disk interface is changed, only the BMC needs to update the configuration content in the EEPROM through the I2C bus, and then power off the whole machine again, and the CPLD reads the new connection relationship information from the EEPROM to complete the new VPP bus analysis. Therefore, this solution only needs to occupy two pins of the CPLD. Even if it is a complicated connection method, this connection method can be maintained.
  • the BMC module on the motherboard is abnormal, it will not affect the CPLD on the backplane to capture from the EEPROM. Take information.

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  • General Engineering & Computer Science (AREA)
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  • General Physics & Mathematics (AREA)
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Abstract

一种灵活调配且易于CPLD管理背板的方法与系统，该方法和系统通过在背板上增加EEPROM模块（S1），在EEPROM模块中存储硬盘背板与主板端控制器的连接配置方式（S2），CPLD通过I2C从EEPROM中读取连接关系信息，从而进行点灯功能以及其他类似控制功能（S3），另外通过增加主板上BMC管理模块到此EEPROM模块的连接，当配置发生改变时，BMC通过I2C总线直接对EEPROM模块中的存储信息进行升级，而无需拆机。该方法和系统只需占用CPLD的两个管脚，无需考虑较复杂配置时需要更多的CPLD管脚，另外由于拨码开关需要人为手动设置，当拨码开关较多时，操作人员容易出错，造成产品配置错误，产品功能异常，直接影响产品质量，通过该方法和系统可有效避免此类问题发生。

Description

一种灵活调配且易于CPLD管理背板的方法与系统
本申请要求于2019年7月29日提交中国专利局、申请号为201910686459.4、发明名称为“一种灵活调配且易于CPLD管理背板的方法与系统”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及存储设计技术领域，特别是一种灵活调配且易于CPLD管理背板的方法与系统。
背景技术
随着云计算持续发展，各大互联网厂商对服务器产品性能要求越来越高，为提高存储性能，各大硬盘厂商陆续推出NVME接口SSD，NVME接口使用PCIE总线可与CPU的PCIE端口直连。由于硬盘在工作时需要有指示灯显示硬盘的工作状态，当业界推出NVME硬盘时，硬盘的点灯服务也随之开发出来，当前NVME硬盘与CPU直连时，硬盘控制来源于CPU，点灯功能同样来源于CPU。以Intel为典型代表，随着Intel的CPU迭代演进，当前Intel的CPU对NVME硬盘的点灯通道是通过VPP总线连接到硬盘所在的背板的CPLD内，由CPLD解析出具体的点灯信号控制实体灯的亮灭。
当前服务器多为多路服务器，也即内部包含多个CPU，每个CPU连接的NVME硬盘需要由此CPU的VPP控制点灯，同样，当NVME硬盘背板为多接口背板时，比如支持4个NVME硬盘接口，或者8个NVME硬盘接口，当多接口背板与多路服务器连接，CPLD在解析VPP总线协议时，需要识别出硬盘背板与主板CPU的连接方式，同时也需知道是哪个CPU的哪个PCIE接口连接，然后进行解析点灯。以4个NVME硬盘连接两路CPU为例，连接方式有多达5种方案。目前的方式是用拨码开关的方式，至少需要3联的拨码开关，需要有3个信号连接到CPLD。随着硬盘数量增加，CPU数量增加，拨码开关信号数量成指数上升，既占用大量CPLD管脚，也占用大量的PCB面积摆放拨码开关，同时在维护时也存在 拨码开关拨错的情况，影响产品功能。
发明内容
本发明的目的是提供一种灵活调配且易于CPLD管理背板的方法与系统，旨在解决现有技术中多端口数量背板占用CPLD管脚过多且拨码开关易出错的问题，实现占用CPLD管脚少且省去大量拨码开关。
为达到上述技术目的，本发明提供了一种灵活调配且易于CPLD管理背板的方法，所述方法包括以下操作：
S1、在背板上增加EEPROM，将EEPROM分别与CPLD和BMC互联；
S2、在EEPROM中烧录背板硬盘接口与主板CPU的连接关系信息；
S3、上电后CPLD读取EEPROM中的连接关系信息，并解析VPP协议总线得到对应的点灯方式。
优选地，所述EEPROM分别与CPLD和BMC通过I2C连接。
优选地，所述CPLD中占用的管脚数量为2。
优选地，所述方法还包括：
当CPU与硬盘接口的连接方式发生改变时，BMC通过I2C总线更新EEPROM中的连接关系信息内容，然后将整机重新关机开机上电，CPLD从EEPROM中读取新的连接关系信息，完成新的VPP总线解析。
本发明还提供了一种灵活调配且易于CPLD管理背板的系统，所述系统包括：
EEPROM添加模块，用于在背板上增加EEPROM，将EEPROM分别与CPLD和BMC互联；
配置信息烧录模块，用于在EEPROM中烧录背板硬盘接口与主板CPU连接的连接关系信息；
协议解析模块，用于上电后CPLD读取EEPROM中的连接关系信息，并解析VPP协议总线得到对应的点灯方式。
优选地，所述EEPROM分别与CPLD和BMC通过I2C连接。
优选地，所述CPLD中占用的管脚数量为2。
优选地，所述系统还包括：
连接关系更新模块，用于当CPU与硬盘接口的连接方式发生改变时，BMC通过I2C总线更新EEPROM中的连接关系信息内容，然后将整机重新关机开机上电，CPLD从EEPROM中读取新的连接关系信息，完成新的VPP总线解析。
发明内容中提供的效果仅仅是实施例的效果，而不是发明所有的全部效果，上述技术方案中的一个技术方案具有如下优点或有益效果：
与现有技术相比，本发明通过在背板上增加EEPROM模块，在EEPROM模块中存储硬盘背板与主板端控制器的连接配置方式，CPLD通过I2C从EEPROM中读取连接关系信息，从而进行点灯功能以及其他类似控制功能，另外通过增加主板上BMC管理模块到此EEPROM模块的连接，当配置发生改变时，BMC通过I2C总线直接对EEPROM模块中的存储信息进行升级，而无需拆机。本发明只需占用CPLD的两个管脚，无需考虑较复杂配置时需要更多的CPLD管脚，另外由于拨码开关需要人为手动设置，当拨码开关较多时，操作人员容易出错，造成产品配置错误，产品功能异常，直接影响产品质量，通过本发明可有效避免此类问题发生。
附图说明
图1为本发明实施例中所提供的一种灵活调配且易于CPLD管理背板的方法流程图；
图2为本发明实施例中所提供的一种双路CPU与四个NVME硬盘连接示意图；
图3为本发明实施例中所提供的一种CPLD与拨码联连接方式示意图；
图4为本发明实施例中所提供的一种EEPROM与CPLD和BMC之间的连接示意图；
图5为本发明实施例中所提供的一种灵活调配且易于CPLD管理背板的系统框图。
具体实施方式
为了能清楚说明本方案的技术特点，下面通过具体实施方式，并结合其附图，对本发明进行详细阐述。下文的公开提供了许多不同的实施例或例子用来实现本发明的不同结构。为了简化本发明的公开，下文中对特定例子的部件和设置进行描述。此外，本发明可以在不同例子中重复参考数字和/或字母。这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施例和/或设置之间的关系。应当注意，在附图中所图示的部件不一定按比例绘制。本发明省略了对公知组件和处理技术及工艺的描述以避免不必要地限制本发明。
下面结合附图对本发明实施例所提供的一种灵活调配且易于CPLD管理背板的方法与系统进行详细说明。
如图1所示，本发明实施例公开了一种灵活调配且易于CPLD管理背板的方法，所述方法包括以下操作：
S1、在背板上增加EEPROM，将EEPROM分别与CPLD和BMC互联；
S2、在EEPROM中烧录背板硬盘接口与主板CPU的连接关系信息；
S3、上电后CPLD读取EEPROM中的连接关系信息，并解析VPP协议总线得到对应的点灯方式。
本发明实施例通过在背板上增加一个EEPROM，并在EEPROM中烧录背板与主板系统互联连接关系信息，CPLD与EEPROM互联，开机上电时从EEPROM中读取连接关系信息，同时将主板BMC连接到背板上EEPROM。根据不同的出货配置，BMC可以上电后根据需求实时更新EEPROM中的连接关系信息，从而省去大量的拨码开关的使用。
如图2所示，以4口NVME硬盘接口背板和两路CPU主板为例，两路CPU连接到硬盘背板上的4个NVME硬盘接口，每个硬盘只有一个CPU连接连接方式如表1所示。
表1
  硬盘1 硬盘2 硬盘3 硬盘4
组合1 CPU1 CPU1 CPU1 CPU1
组合2 CPU1 CPU1 CPU1 CPU2
组合3 CPU1 CPU1 CPU2 CPU2
组合4 CPU1 CPU2 CPU2 CPU2
组合5 CPU2 CPU2 CPU2 CPU2
针对表中5种组合，CPLD必须识别到是哪种组合，以往的方案是CPLD需要增加几个管脚，将这些管脚连接到拨码开关上，拨码开关可以拨到高电平准位，也可以拨到低电平准位。CPLD通过侦测这几个管脚的不同准位来判断CPU与NVME硬盘接口的不同组合方式，如图3以及表2，CPLD连接三个管脚到拨码开关的三个拨码联上，通过三个拨码联的不同高低准位组成5种组合方式，对应CPU连接硬盘的5种组合方式。
表2
  拨码联1 拨码联2 拨码联3
组合1 0 0 0
组合2 0 0 1
组合3 0 1 0
组合4 1 0 0
组合5 0 1 1
通过在背板上增加一个EEPROM，将背板CPLD与此EEPROM通过I2C总线连接，将主板上的BMC通过I2C与背板上EEPROM连接。在EEPROM中烧录背板端口数量信息和背板与主板CPU的连接信息，上电后CPLD从EEPROM中读取连接关系信息，根据识别的连接关系信息，CPLD解析VPP协议总线，将硬盘点灯与实际CPU控制对应好，如图4所示。
图4中CPLD即为前文所述的硬盘背板上的CPLD，BMC是个管理模块。通过在硬盘背板上增加一个EPPROM，该模块为存储模块，可将连接关系信息烧录到此存储模块。背板在上电开机时，CPLD会从EEPROM中将背板硬盘接口与主板上CPU连接的配置关系读出来，然后将CPU发送至CPLD的VPP总线进行解析为对应的点灯方式。当CPU与硬盘接口的连接方式发生改变时，只需要BMC通过I2C总线更新EEPROM中的配置内容，然后将整机重新关机开机上电，CPLD从EEPROM中读取新的连接 关系信息，完成新的VPP总线解析。因此该方案只需占用CPLD的两个管脚，即使是再复杂的连接方式，都可以维持此连接方式不变，同时即使主板上BMC模块异常，也不会影响背板上CPLD从EEPROM中抓取信息。
本发明实施例通过在背板上增加EEPROM模块，在EEPROM模块中存储硬盘背板与主板端控制器的连接配置方式，CPLD通过I2C从EEPROM中读取连接关系信息，从而进行点灯功能以及其他类似控制功能，另外通过增加主板上BMC管理模块到此EEPROM模块的连接，当配置发生改变时，BMC通过I2C总线直接对EEPROM模块中的存储信息进行升级，而无需拆机。本发明只需占用CPLD的两个管脚，无需考虑较复杂配置时需要更多的CPLD管脚，另外由于拨码开关需要人为手动设置，当拨码开关较多时，操作人员容易出错，造成产品配置错误，产品功能异常，直接影响产品质量，通过本发明可有效避免此类问题发生。
如图5所示，本发明实施例还公开了一种灵活调配且易于CPLD管理背板的系统，所述系统包括：
EEPROM添加模块，用于在背板上增加EEPROM，将EEPROM分别与CPLD和BMC互联；
配置信息烧录模块，用于在EEPROM中烧录背板硬盘接口与主板CPU连接的连接关系信息；
协议解析模块，用于上电后CPLD读取EEPROM中的连接关系信息，并解析VPP协议总线得到对应的点灯方式。
通过在背板上增加一个EEPROM，将背板CPLD与此EEPROM通过I2C总线连接，将主板上的BMC通过I2C与背板上EEPROM连接。在EEPROM中烧录背板端口数量信息和背板与主板CPU的连接信息，上电后CPLD从EEPROM中读取连接关系信息，根据识别的连接关系信息，CPLD解析VPP协议总线，将硬盘点灯与实际CPU控制对应好。
EPPROM模块为存储模块，可将连接关系信息烧录到此存储模块。背板在上电开机时，CPLD会从EEPROM中将背板硬盘接口与主板上CPU连接的配置关系读出来，然后将CPU发送至CPLD的VPP总线进行解析为对应的点灯方式。当CPU与硬盘接口的连接方式发生改变时，只需要 BMC通过I2C总线更新EEPROM中的配置内容，然后将整机重新关机开机上电，CPLD从EEPROM中读取新的连接关系信息，完成新的VPP总线解析。因此该方案只需占用CPLD的两个管脚，即使是再复杂的连接方式，都可以维持此连接方式不变，同时即使主板上BMC模块异常，也不会影响背板上CPLD从EEPROM中抓取信息。
以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (8)

  1. 一种灵活调配且易于CPLD管理背板的方法，其特征在于，所述方法包括以下操作：
    S1、在背板上增加EEPROM，将EEPROM分别与CPLD和BMC互联；
    S2、在EEPROM中烧录背板硬盘接口与主板CPU的连接关系信息；
    S3、上电后CPLD读取EEPROM中的连接关系信息，并解析VPP协议总线得到对应的点灯方式。
  2. 根据权利要求1所述的一种灵活调配且易于CPLD管理背板的方法，其特征在于，所述EEPROM分别与CPLD和BMC通过I2C连接。
  3. 根据权利要求1所述的一种灵活调配且易于CPLD管理背板的方法，其特征在于，所述CPLD中占用的管脚数量为2。
  4. 根据权利要求1-3任意一项所述的一种灵活调配且易于CPLD管理背板的方法，其特征在于，所述方法还包括：
    当CPU与硬盘接口的连接方式发生改变时，BMC通过I2C总线更新EEPROM中的连接关系信息内容，然后将整机重新关机开机上电，CPLD从EEPROM中读取新的连接关系信息，完成新的VPP总线解析。
  5. 一种灵活调配且易于CPLD管理背板的系统，其特征在于，所述系统包括：
    EEPROM添加模块，用于在背板上增加EEPROM，将EEPROM分别与CPLD和BMC互联；
    配置信息烧录模块，用于在EEPROM中烧录背板硬盘接口与主板CPU连接的连接关系信息；
    协议解析模块，用于上电后CPLD读取EEPROM中的连接关系信息，并解析VPP协议总线得到对应的点灯方式。
  6. 根据权利要求5所述的一种灵活调配且易于CPLD管理背板的系统，其特征在于，所述EEPROM分别与CPLD和BMC通过I2C连接。
  7. 根据权利要求5所述的一种灵活调配且易于CPLD管理背板的系统，其特征在于，所述CPLD中占用的管脚数量为2。
  8. 根据权利要求5-7任意一项所述的一种灵活调配且易于CPLD管理背板的系统，其特征在于，所述系统还包括：
    连接关系更新模块，用于当CPU与硬盘接口的连接方式发生改变时，BMC通过I2C总线更新EEPROM中的连接关系信息内容，然后将整机重新关机开机上电，CPLD从EEPROM中读取新的连接关系信息，完成新的VPP总线解析。
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