WO2021016918A1 - 接收卡和显示控制卡组件 - Google Patents

接收卡和显示控制卡组件 Download PDF

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Publication number
WO2021016918A1
WO2021016918A1 PCT/CN2019/098574 CN2019098574W WO2021016918A1 WO 2021016918 A1 WO2021016918 A1 WO 2021016918A1 CN 2019098574 W CN2019098574 W CN 2019098574W WO 2021016918 A1 WO2021016918 A1 WO 2021016918A1
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WO
WIPO (PCT)
Prior art keywords
electrically connected
differential signal
interfaces
logic device
programmable logic
Prior art date
Application number
PCT/CN2019/098574
Other languages
English (en)
French (fr)
Inventor
王雪
梁伟
韦桂锋
Original Assignee
西安诺瓦星云科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 西安诺瓦星云科技股份有限公司 filed Critical 西安诺瓦星云科技股份有限公司
Priority to PCT/CN2019/098574 priority Critical patent/WO2021016918A1/zh
Priority to EP19934384.9A priority patent/EP3813047A4/en
Priority to US17/057,706 priority patent/US11829678B2/en
Priority to CN201980033518.6A priority patent/CN112673413B/zh
Publication of WO2021016918A1 publication Critical patent/WO2021016918A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G06F3/1423—Digital output to display device ; Cooperation and interconnection of the display device with other functional units controlling a plurality of local displays, e.g. CRT and flat panel display
    • G06F3/1446—Digital output to display device ; Cooperation and interconnection of the display device with other functional units controlling a plurality of local displays, e.g. CRT and flat panel display display composed of modules, e.g. video walls
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/006—Details of the interface to the display terminal
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/02—Composition of display devices
    • G09G2300/026—Video wall, i.e. juxtaposition of a plurality of screens to create a display screen of bigger dimensions
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/02—Networking aspects
    • G09G2370/025—LAN communication management
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/14—Use of low voltage differential signaling [LVDS] for display data communication
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]

Definitions

  • This application relates to the field of display technology, and in particular to a receiving card and a display control card assembly.
  • the LED display screen is composed of a splicing of display boxes configured with receiving cards one by one, and the receiving cards configured in the display box are connected by a network cable to transmit image data signals.
  • the LED display industry has been developing for many years, but as far as the current market is concerned, products generally still stay at the 1Gbps transmission rate; as the LED display develops towards small-pitch displays, the 1Gbps transmission rate is obviously not enough.
  • the embodiments of the present application provide a receiving card and a display control card assembly.
  • a receiving card proposed in an embodiment of the present application includes: a circuit board and a programmable logic device, a storage device, a plug-in assembly, a physical layer transceiver group and multiple Ethernet interfaces arranged on the circuit board .
  • the storage device and the plug-in assembly are electrically connected to the programmable logic device;
  • the multiple Ethernet interfaces are respectively electrically connected to multiple SerDes configured by the programmable logic device through the physical layer transceiver group Channel; each of the SerDes channels includes two pairs of differential signal lines, and one of the two pairs of differential signal lines is used for data transmission and the other pair of differential signal lines is used for data reception.
  • the Ethernet interface is connected to the SerDes channel of the programmable logic device and the number and function of the differential signal lines in the SerDes channel are defined.
  • the SerDes channel is a high-speed serial data channel, which can increase the transmission rate of the entire receiving card .
  • the physical layer transceiver group includes two 5Gbase-T or 10GBASE-T Ethernet physical layer transceivers, the number of the multiple Ethernet interfaces is two, and the Two Ethernet interfaces are respectively electrically connected to the two SerDes channels configured by the programmable logic device through the two 5Gbase-T or 10GBASE-T Ethernet physical layer transceivers.
  • the plug-in component includes a display data single-ended signal pin group, a display control signal single-ended signal pin group, and a display data differential signal pin group; the programmable logic device is electrically connected The display data single-ended signal pin group and the display data differential signal pin group are used to output display data in a single-ended signal and LVDS differential signal mode; and the programmable logic device is electrically connected to the display control signal
  • the single-ended signal pin group is used to output the display control signal with a single-ended signal.
  • the receiving card further includes: a DC power supply circuit and a plurality of first type interfaces provided on the circuit board, and the first type interface is different from the Ethernet interface;
  • the plurality of first-type interfaces are respectively electrically connected to other plurality of SerDes channels configured by the programmable logic device, and the plurality of first-type interfaces are also electrically connected to the DC power supply circuit for obtaining power signals to the outside Transmit.
  • the plurality of first-type interfaces are two USB3.0 interfaces, and each of the USB3.0 interfaces is electrically connected to one SerDes channel configured by the programmable logic device.
  • another receiving card includes: a circuit board and a programmable logic device, a storage device, a plug-in component, a DC power supply circuit, and a plurality of first types provided on the circuit board Interface; wherein the storage device and the plug-in assembly are electrically connected to the programmable logic device; the plurality of first type interfaces are respectively electrically connected to the plurality of SerDes channels configured by the programmable logic device, and also power Connect the DC power supply circuit for obtaining power signals for external transmission; each of the SerDes channels includes two pairs of differential signal lines, and one pair of the two pairs of differential signal lines is used for data transmission and the other A pair of differential signal lines are used for data reception.
  • the first type interface is connected to the SerDes channel of the programmable logic device and the number and functions of the differential signal lines in the SerDes channel are defined.
  • the SerDes channel is a high-speed serial data channel, which can improve the transmission of the entire receiving card. Speed; Moreover, the first type of interface can also transmit power signals to the outside, so it can simplify the connection between the receiving card and other devices.
  • the multiple first-type interfaces are two USB3.0 interfaces, and each of the USB3.0 interfaces is electrically connected to one SerDes channel configured by the programmable logic device.
  • the plurality of first-type interfaces are four USB3.0 interfaces, and each of the USB3.0 interfaces is electrically connected to one SerDes channel configured by the programmable logic device.
  • the plug-in component includes a display data single-ended signal pin group, a display control signal single-ended signal pin group, and a display data differential signal pin group; the programmable logic device is electrically connected The display data single-ended signal pin group and the display data differential signal pin group are used to output display data in a single-ended signal and LVDS differential signal mode; and the programmable logic device is electrically connected to the display control signal
  • the single-ended signal pin group is used to output the display control signal with a single-ended signal.
  • a display control card assembly provided by an embodiment of the present application includes: the aforementioned receiving card and at least one daughter card. Wherein, each of the daughter cards is connected to one of the first type interfaces of the plurality of first type interfaces of the receiving card through a cable for transmitting data signals and power signals.
  • the at least one daughter card includes a wireless transmission daughter card
  • the wireless transmission daughter card includes: a second circuit board and a DC-to-DC circuit provided on the second circuit board, A wireless transmitting chip and a wireless receiving chip
  • the second circuit board is provided with a pad group, and the pad group is electrically connected to one end of the cable
  • the DC-to-DC circuit is electrically connected to the pad group
  • the wireless transmitting chip and the wireless receiving chip are used to obtain a power signal from the pad group and provide working voltage to the wireless transmitting chip and the wireless receiving chip
  • the wireless transmitting chip and the wireless receiving chip The receiving chips are arranged at intervals and are electrically connected to the pad group through a second SerDes channel.
  • the second SerDes channel includes two pairs of second differential signal lines, and a pair of second differential signals among the two pairs of second differential signal lines.
  • the signal line is used for data transmission, and the other pair of second differential signal lines are used for data reception; and the working frequencies of the wireless transmitting chip and the wireless receiving chip are located in the millimeter wave frequency band.
  • the at least one daughter card includes a wired network transmission daughter card
  • the wired network transmission daughter card includes: a third circuit board and a second type provided on the third circuit board Interface, DC-to-DC circuit, physical layer transceiver, and Ethernet interface
  • the second-type interface and the first-type interface are the same type of interface and are connected to one end of the cable
  • the DC-to-DC circuit is electrically connected
  • the second type interface and the physical layer transceiver are used to obtain a power signal from the second type interface and provide a working voltage to the physical layer transceiver
  • the physical layer transceiver passes through a third SerDes channel
  • the second type interface is electrically connected, and the Ethernet interface is electrically connected to the physical layer transceiver
  • the third SerDes channel includes two pairs of third differential signal lines, and the two pairs of third differential signal lines A pair of third differential signal lines is used for data transmission, and the other pair of third differential signal lines is used for data reception.
  • the above technical solutions of the embodiments of the present application may have one or more of the following beneficial effects: connecting the Ethernet interface and/or the first type interface (such as the USB3.0 interface) to the SerDes channel of the programmable logic device and Define the number and functions of the differential signal lines in the SerDes channel.
  • the SerDes channel is a high-speed serial data channel, which can increase the transmission rate of the entire receiving card.
  • the first type interface can also transmit power signals to the outside, so the connection between the receiving card and other devices can be simplified.
  • the structure of the display control card assembly can be diversified.
  • FIG. 1 is a schematic structural diagram of a receiving card provided by an embodiment of the application.
  • FIG. 2 is a schematic diagram of the receiving card shown in FIG. 1 from another perspective.
  • Fig. 3 is a schematic diagram of the pin functions of the plug-in assembly of the receiving card shown in Fig. 1.
  • Fig. 4 is a schematic structural diagram of another receiving card provided by an embodiment of the application.
  • Fig. 5 is a structural diagram of a display control card assembly using the receiving card shown in Fig. 4.
  • FIG. 6 is a schematic diagram of the structure of the wireless transmission daughter card shown in FIG. 5.
  • FIG. 7 is a schematic structural diagram of still another receiving card provided by an embodiment of the application.
  • Fig. 8 is a schematic structural diagram of a display control card assembly using the receiving card shown in Fig. 7.
  • Fig. 9 is a schematic structural diagram of another display control card assembly using the receiving card shown in Fig. 7.
  • FIG. 10 is a schematic diagram of the structure of the wired network transmission daughter card shown in FIG. 9.
  • Fig. 11 is a schematic structural diagram of another display control card assembly using the receiving card shown in Fig. 7.
  • a receiving card 10 provided by an embodiment of the present application includes: a circuit board 11 and a plug-in assembly 12 arranged on the circuit board 11, a programmable logic device 13, a storage device 14, Physical layer transceiver groups 15a and 15b, and a plurality of, for example, two Ethernet interfaces 16a and 16b.
  • the connector assembly 12 is electrically connected to the programmable logic device 13, which is, for example, composed of two connectors 12a, 12b with the same number of pins.
  • the connectors 12a, 12b here are, for example, 120Pin high-density connectors.
  • the embodiments of the present application are not limited to this. Furthermore, it can be seen from FIG.
  • the connector assembly 12 is located on one side of the circuit board 11 (for example, the bottom side of the circuit board 11), and the programmable logic device 13, the storage device 14, the physical layer transceiver groups 15a and 15b, and The Ethernet interfaces 16a and 16b are located on the other side of the circuit board 11 (for example, the top surface side of the circuit board 11); this arrangement facilitates the insertion and fixation of the receiving card 11 and the adapter board (not shown).
  • the plug-in assembly 12 includes a display data single-ended signal pin group 121, a display control signal single-ended signal pin group 123, and a display data differential signal pin group 125.
  • the programmable logic device 13 is electrically connected to the display
  • the data single-ended signal pin group 121 and the display data differential signal pin group 125 are used to output display data such as RGB data in a single-ended signal and LVDS (Low Voltage Differential Signaling) differential signal mode.
  • the programmable logic device 13 is electrically connected to the single-ended signal pin group of the display control signal for outputting display control signals such as line decoding signals, enable signals, latch signals, clock signals, and even line blanking with single-ended signals signal.
  • the receiving card 11 can not only use RGB data single-ended signal transmission, but also directly use LVDS differential signal transmission when supplying LED module display data.
  • the LVDS differential signal has the following advantages: (1) Strong anti-interference ability, the interference noise is generally equal in value and loaded on the two signal lines at the same time, and the difference is 0, that is Noise has no effect on the logical meaning of the signal; (2) It can effectively suppress electromagnetic interference (EMI). Because the two wires are close together and the signal amplitude is equal, the amplitude of the coupled electromagnetic field between the two wires and the ground wire The values are also equal, and their signal polarities are opposite, their electromagnetic fields will cancel each other, so the electromagnetic interference to the outside world is also small.
  • EMI electromagnetic interference
  • the programmable logic device 13 is, for example, an FPGA (Field Programmable Gate Array) device.
  • FPGA Field Programmable Gate Array
  • the storage device 14 is electrically connected to the programmable logic device 13, which is, for example, DDR4, DDR3, DDR2, LPDDR2, SDRAM, etc., and the number of storage devices used can be determined according to actual needs.
  • the programmable logic device 13 which is, for example, DDR4, DDR3, DDR2, LPDDR2, SDRAM, etc., and the number of storage devices used can be determined according to actual needs.
  • the Ethernet interfaces 16a and 16b are electrically connected to the two SerDes channels configured by the programmable logic device 13 through the physical layer transceivers 15a and 15b, respectively.
  • each SerDes channel includes two pairs of differential signal lines, and one of the two pairs of differential signal lines is used for data transmission and the other pair of differential signal lines is used for data reception.
  • the physical layer transceivers 15a and 15b are, for example, 10Gbase-T or 5Gbase-T Ethernet physical layer transceivers, which can use commercially available chips such as AQR111C, AQR114C, BCM54892, BCM54992, and BCM54991.
  • the transmission rate of a single Ethernet interface 16a/16b can be 10Gbps/5Gbps/2.5Gbps/1Gbps.
  • the Ethernet interfaces 16a and 16b may be RJ45 integrated network transformers, or a separate design of network transformer and RJ45, or 2*1 integrated network transformers RJ45.
  • the embodiment shown in FIG. 4 is based on the embodiment shown in FIG. For example, two USB3.0 interfaces are used to expand the signal transmission mode.
  • the receiving card 30 of this embodiment includes: a circuit board 31 and a plug-in assembly 32 arranged on the circuit board 31, a programmable logic device 33, a storage device 34, and a physical layer transceiver group 35a And 35b, a plurality of, for example, two Ethernet interfaces 36a and 36b, a plurality of, for example, two USB3.0 interfaces 37a and 37b, and a DC power supply circuit 38.
  • the structure and function of the plug-in component 32, the programmable logic device 33, the storage device 34, the physical layer transceiver group 35a and 35b, and the Ethernet interface 36a and 36b are the same as those of the plug-in component 12, programmable logic shown in FIG.
  • the structures and functions of the device 13, the storage device 14, the physical layer transceiver groups 15a and 15b, and the Ethernet interfaces 16a and 16b are similar, so they are not repeated here.
  • USB3.0 interfaces 37a and 37b are respectively electrically connected to a plurality of SerDes channels configured by the programmable logic device 33, and the USB3.0 interfaces 37a and 37b are also electrically connected to the DC power supply circuit 38 for obtaining power signals for external transmission.
  • the USB3.0 interfaces 37a and 37b here are interfaces with multiple pairs of high-speed differential signal pins and power signal pins, so they can also be replaced with other interfaces with multiple pairs of high-speed differential signal pins and power signal pins. For example, Mini HDMI interface.
  • the display control card assembly using the wireless transmission daughter card 40 shown in FIG. 5 is derived.
  • the main purpose of the wireless transmission solution shown in Figure 5 is to solve the pain points of frequent plugging and unplugging of the industry network cable, which is easy to be broken and unstable, and the cost of early installation and later maintenance is high.
  • the design of front maintenance is becoming more and more popular; for the front maintenance program of LED display, wireless transmission undoubtedly provides a very high-quality solution. Convenient for LED display design and on-site installation and maintenance.
  • each USB3.0 interface 37a, 37b is connected to a wireless transmission subcard 40 through a USB3.0 cable.
  • the USB3.0 cable here is a cable that can transmit data signals and power signals at the same time.
  • the wireless transmission daughter card 40 includes: a circuit board and a DC-to-DC circuit 43 arranged on the circuit board, a wireless transmitting chip 45a and a wireless receiving chip 45b.
  • a pad group 41 is provided on the circuit board, and the pad group 41 is electrically connected to one end of the USB3.0 cable.
  • the DC-to-DC circuit 43 is electrically connected to the pad group 41, the wireless transmitting chip 45a and the wireless receiving chip 45b for obtaining a power signal from the pad group 41 and providing working voltage to the wireless transmitting chip 45a and the wireless receiving chip 45b.
  • the wireless transmitting chip 45a and the wireless receiving chip 45b are arranged at intervals and are electrically connected to the pad group 41 through a SerDes channel; the SerDes channel includes two pairs of differential signal lines, and one pair of the two pairs of differential signal lines is used for Data transmission and another pair of differential signal lines are used for data reception. Furthermore, the working frequencies of the wireless transmitting chip 45a and the wireless receiving chip 45b are located in the millimeter wave frequency band.
  • the millimeter wave frequency band here typically refers to a frequency range of 30 GHz to 300 GHz, and a corresponding wavelength of 1 mm to 10 mm.
  • the wireless transmitting chip 45a and wireless receiving chip 45b of this embodiment working in the millimeter wave frequency band are very suitable for the application of the display box in the LED display screen, because the LED display screen is typically formed by splicing multiple display boxes.
  • the wireless transmission sub-card 40 is installed in each display box, the first consideration is how to avoid the wireless signal crosstalk between the two wireless transmission sub-cards 40 in the same LED display screen that do not need to transmit and receive data.
  • the wireless transmitting chip 45a and the wireless receiving chip 45b in the wireless transmission daughter card 40 of this embodiment work in the millimeter wave frequency band, which can greatly reduce wireless signal crosstalk compared with wireless transmission modules such as WiFi modules and Bluetooth modules in the prior art. may. Furthermore, based on the performance of the current wireless chip and the availability of frequency bands, the working frequency of the wireless transmitting chip 45a and the wireless receiving chip 45b is preferably in the frequency range of 57GHZ-67GHZ or 71GHZ-87GHZ, for example 60GHZ or 80GHZ.
  • the receiving card 50 of this embodiment removes the Ethernet interface + physical layer transceiver of the receiving card 30 shown in Figure 4, and connects all the SerDes channels of the programmable logic device to interfaces such as USB3.0 (corresponding to the first Type interface).
  • This design can not only reduce the size of the receiving card, but also make the design of the LED display control system using this receiving card diversified.
  • the receiving card 50 includes: a circuit board 51, a plug-in assembly 52 provided on the circuit board 51, a programmable logic device 53, a storage device 54, and multiple, for example, four USB3.0 interfaces 57a And 57b and 59a and 59b, and the DC power supply circuit 58.
  • the structure and function of the plug-in component 52, the programmable logic device 53, and the storage device 54 are similar to those of the plug-in component 12, the programmable logic device 13, and the storage device 14 shown in FIG. Repeat.
  • USB3.0 ports 57a, 57b, 59a, and 59b are respectively electrically connected to the multiple SerDes channels configured by the programmable logic device 53, and the USB3.0 ports 57a, 57b, 59a, and 59b are also electrically connected to the DC power supply circuit 58 for use To get the power signal and send it out.
  • the USB3.0 interfaces 57a, 57b, 59a, 59b here are interfaces with multiple pairs of high-speed differential signal pins and power signal pins, so they can also be replaced with other multiple pairs of high-speed differential signal pins and power signal pins. Pin interface, such as Mini HDMI interface.
  • the transmission rate and signal transmission mode can be determined directly on the daughter card, because for each USB3.0 interface
  • the four USB3.0 ports 57a of the receiving card 50 are listed below with reference to Figures 8 to 11 , 57b, 59a, 59b multiple connection options.
  • USB3.0 interfaces 57a, 57b, 59a, 59b can be connected to the wireless transmission sub-card 40 via USB3.0 cables, respectively, to realize wireless signal transmission.
  • the four USB3.0 interfaces 57a, 57b, 59a, 59b can be connected to the wired network transmission subcard 60 through USB3.0 lines, respectively.
  • the wired network transmission daughter card 60 includes: a circuit board and a USB3.0 interface (corresponding to the second type interface) 61 provided on the circuit board, a DC-to-DC circuit 63, and a physical layer transceiver ⁇ 65 and Ethernet interface 67.
  • the USB3.0 interface 61 is connected to one end of the USB3.0 line, which is an interface with multiple pairs of high-speed differential signal pins and power signal pins.
  • the DC-to-DC circuit 63 is electrically connected to the USB3.0 interface 61 and the physical layer transceiver 65 for obtaining a power signal from the USB3.0 interface 61 and providing a working voltage to the physical layer transceiver 65.
  • the physical layer transceiver 65 is electrically connected to the USB3.0 interface 61 through the SerDes channel, and the SerDes channel here includes two pairs of differential signal lines, and a pair of differential signal lines in the two pairs of differential signal lines is used for data transmission and another A pair of differential signal lines are used for data reception.
  • the physical layer transceiver 65 here can be a 1GBase-T/2.5GBase-T/5GBase-T/10GBase-T type Ethernet physical layer transceiver.
  • the Ethernet interface 67 is electrically connected to the physical layer transceiver 65, which is, for example, an integrated network converter RJ45, or a separate network converter and RJ45 design.
  • USB3.0 interfaces 57a, 57b, 59a, 59b can be connected to two wireless transmission sub-cards 40 and two wired network transmission sub-cards 60, respectively.
  • the receiving card and display control card assembly of the embodiment of the present application can have one or more of the following beneficial effects: (i) For the transmission rate solution, it can effectively solve the problem of insufficient gigabit bandwidth, and is more suitable for small spacing. For applications, the bandwidth can be selected from 10G/5G/2.5G/1G or even other bandwidths, with higher flexibility and greater applicability; (ii) For signal transmission solutions, it solves the problem of frequent plugging and unplugging of traditional transmission methods.
  • LVDS differential signals are added, which can strengthen the transmission anti-interference ability, effectively suppress electromagnetic interference (EMI) and improve EMC.

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  • Physics & Mathematics (AREA)
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Abstract

本申请实施例涉及一种接收卡，例如包括：电路板和设置在所述电路板上的可编程逻辑器件、存储器件、接插组件、物理层收发器组及多个以太网接口。其中，所述存储器件和所述接插组件电连接所述可编程逻辑器件；所述多个以太网接口分别通过所述物理层收发器组电连接所述可编程逻辑器件配置的多个SerDes通道；每个所述SerDes通道包括两对差分信号线，以及所述两对差分信号线中的一对差分信号线用于数据发送且另一对差分信号线用于数据接收。将以太网接口连接至可编程逻辑器件的SerDes通道并对SerDes通道中的差分信号线数量及功能进行定义，SerDes通道为高速串行数据通道，藉此可以提升整个接收卡的传输速率。

Description

接收卡和显示控制卡组件 技术领域
本申请涉及显示技术领域，尤其涉及一种接收卡和一种显示控制卡组件。
背景技术
LED显示屏的优势除了亮度高、色域广优势以外，可以灵活拼接为大型显示屏的优势至关重要。LED显示屏是由一个一个的配置有接收卡的显示箱体拼接组成，显示箱体配置的接收卡之间通过网线连接，用以传递图像数据信号。LED显示屏行业发展已有多年之久，但就目前市场而言，产品普遍还停留在1Gbps的传输速率期间；随着LED显示屏向小间距显示屏方向发展，1Gbps的传输速率显然不够。
发明内容
为克服相关技术中存在的缺陷和不足，本申请的实施例提供一种接收卡以及一种显示控制卡组件。
一方面，本申请实施例提出的一种接收卡，包括：电路板和设置在所述电路板上的可编程逻辑器件、存储器件、接插组件、物理层收发器组及多个以太网接口。其中，所述存储器件和所述接插组件电连接所述可编程逻辑器件；所述多个以太网接口分别通过所述物理层收发器组电连接所述可编程逻辑器件配置的多个SerDes通道；每个所述SerDes通道包括两对差分信号线，以及所述两对差分信号线中的一对差分信号线用于数据发送且另一对差分信号线用于数据接收。
本实施例将以太网接口连接至可编程逻辑器件的SerDes通道并对SerDes通道中的差分信号线数量及功能进行定义，SerDes通道为高速串行数据通道，藉此可以提升整个接收卡的传输速率。
在本申请的一个实施例中，所述物理层收发器组包括两个5Gbase-T或10GBASE-T型以太网物理层收发器，所述多个以太网接口的数量为两个，且所述两个以太网接口分别通过所述两个5Gbase-T或10GBASE-T型以太网物理层收发器电连接所述可编程逻辑器件配置的两个所述SerDes通道。
在本申请的一个实施例中，所述接插组件包含显示数据单端信号引脚组、显示控制信号单端信号引脚组和显示数据差分信号引脚组；所述可编程逻辑器件电连接显示数据单端信号引脚组和显示数据差分信号引脚组，以用于以单端信号和LVDS差分信号二选一方式输出显示数据；以及所述可编程逻辑器件电连接所述显示控制信号单端信号引脚组，以用于以单端信号输出显示控制信号。
在本申请的一个实施例中，所述接收卡还包括：设置在所述电路板上的直流电源电路和多个第一类型接口，且所述第一类型接口不同于所述以太网接口；所述多个第一类型接口分别电连接所述可编程逻辑器件配置的另外多个SerDes通道，并且所述多个第一类型接口还电连接所述直流电源电路以用于获取电源信号向外传送。
在本申请的一个实施例中，所述多个第一类型接口为两个USB3.0接口，且每个所述USB3.0接口电连接所述可编程逻辑器件配置的一个SerDes通道。
另一方面，本申请实施例提供的另一种接收卡，包括：电路板和设置在所述电路板上的可编程逻辑器件、存储器件、插接组件、直流电源电路及多个第一类型接口；其中，所述存储器件和所述接插组件电连接所述可编程逻辑器件；所述多个第一类型接口分别电连接所述可编程逻辑器件配置的多个SerDes通道，且还电连接所述直流电源电路以用于获取电源信号向外传送；每个所述SerDes通道包括两对差分信号线，以及所述两对差分信号线中的一对差分信号线用于数据发送且另一对差分信号线用于数据接收。
本实施例将第一类型接口连接至可编程逻辑器件的SerDes通道并对SerDes通道中的差 分信号线数量及功能进行定义，SerDes通道为高速串行数据通道，藉此可以提升整个接收卡的传输速率；再者，第一类型接口还可以向外传送电源信号，因此可以简化接收卡与其他器件的连接。
在本申请的一个实施例中，所述多个第一类型接口为两个USB3.0接口，且每个所述USB3.0接口电连接所述可编程逻辑器件配置的一个所述SerDes通道。
在本申请的一个实施例中，所述多个第一类型接口为四个USB3.0接口，且每个所述USB3.0接口电连接所述可编程逻辑器件配置的一个所述SerDes通道。
在本申请的一个实施例中，所述接插组件包含显示数据单端信号引脚组、显示控制信号单端信号引脚组和显示数据差分信号引脚组；所述可编程逻辑器件电连接显示数据单端信号引脚组和显示数据差分信号引脚组，以用于以单端信号和LVDS差分信号二选一方式输出显示数据；以及所述可编程逻辑器件电连接所述显示控制信号单端信号引脚组，以用于以单端信号输出显示控制信号。
再一方面，本申请实施例提供的一种显示控制卡组件，包括：前述接收卡以及至少一个子卡。其中，每个所述子卡通过用于传输数据信号和电源信号的线缆连接所述接收卡的所述多个第一类型接口中的一个所述第一类型接口。
在本申请的一个实施例中，所述至少一个子卡包括无线传输子卡，且所述无线传输子卡包括：第二电路板和设置在所述第二电路板上的直流转直流电路、无线发送芯片和无线接收芯片；所述第二电路板上设有焊盘组，且所述焊盘组电连接所述线缆的一端；所述直流转直流电路电连接所述焊盘组、所述无线发送芯片和所述无线接收芯片，以用于从所述焊盘组获取电源信号并向所述无线发送芯片和所述无线接收芯片提供工作电压；所述无线发送芯片和所述无线接收芯片间隔设置并通过第二SerDes通道电连接所述焊盘组，所述第二SerDes通道包含两对第二差分信号线，以及所述两对第二差分信号线中的一对第二差分 信号线用于数据发送、且另一对第二差分信号线用于数据接收；以及所述无线发送芯片和所述无线接收芯片的工作频率位于毫米波频段。
在本申请的一个实施例中，所述至少一个子卡包括有线网络传输子卡，且所述有线网络传输子卡包括：第三电路板和设置在所述第三电路板上的第二类型接口、直流转直流电路、物理层收发器和以太网接口；所述第二类型接口与所述第一类型接口为相同类型接口且连接所述线缆的一端；所述直流转直流电路电连接所述第二类型接口和所述物理层收发器，以用于从所述第二类型接口获取电源信号并向所述物理层收发器提供工作电压；所述物理层收发器通过第三SerDes通道电连接所述第二类型接口，且所述以太网接口电连接所述物理层收发器；所述第三SerDes通道包含两对第三差分信号线，以及所述两对第三差分信号线中的一对第三差分信号线用于数据发送、且另一对第三差分信号线用于数据接收。
综上所述，本申请实施例上述技术方案可以具有如下一个或多个有益效果：将以太网接口和/或第一类型接口(比如USB3.0接口)连接至可编程逻辑器件的SerDes通道并对SerDes通道中的差分信号线数量及功能进行定义，SerDes通道为高速串行数据通道，藉此可以提升整个接收卡的传输速率。再者，第一类型接口还可以向外传送电源信号，因此可以简化接收卡与其他器件的连接。另外，基于接收卡的接口灵活性，可以实现显示控制卡组件的结构多元化。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的一种接收卡的结构示意图。
图2为图1所示接收卡的另一视角示意图。
图3为图1所示接收卡的接插组件的引脚功能示意图。
图4为本申请实施例提供的另一种接收卡的结构示意图。
图5为采用图4所示接收卡的一种显示控制卡组件的结构示意图。
图6为图5所示无线传输子卡的结构示意图。
图7为本申请实施例提供的再一种接收卡的结构示意图。
图8为采用图7所示接收卡的一种显示控制卡组件的结构示意图。
图9为采用图7所示接收卡的另一种显示控制卡组件的结构示意图。
图10为图9所示有线网络传输子卡的结构示意图。
图11为采用图7所示接收卡的再一种显示控制卡组件的结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
参见图1、图2和图3，本申请实施例提供的一种接收卡10，包括：电路板11和设置在电路板11上的接插组件12、可编程逻辑器件13、存储器件14、物理层收发器组15a及15b、和多个例如两个以太网接口16a及16b。
其中，接插组件12电连接可编程逻辑器件13，其例如是由两个具有相同引脚数的接插件12a、12b构成，此处的接插件12a、12b例如分别是120Pin高密接插件，但本申请实施例并不以此为限。再者，从图2可知，接插组件12位于电路板11的一侧(例如电路板11的底面侧)，且可编程逻辑器件13、存储器件14、物理层收发器组15a及15b、和以太网接口 16a及16b位于电路板11的另一侧(例如电路板11的顶面侧)；这种排布方式便于接收卡11与转接板(图未示)的插接固定。此外，从图3可知，接插组件12包含显示数据单端信号引脚组121、显示控制信号单端信号引脚组123和显示数据差分信号引脚组125，可编程逻辑器件13电连接显示数据单端信号引脚组121和显示数据差分信号引脚组125，以用于以单端信号和LVDS(Low Voltage Differential Signaling，低电压差分信号)差分信号二选一方式输出显示数据比如RGB数据；以及可编程逻辑器件13电连接显示控制信号单端信号引脚组，以用于以单端信号输出显示控制信号比如行译码信号、使能信号、锁存信号、时钟信号甚至行消隐信号。如此一来，接收卡11在供给LED模组显示数据时不仅可以使用RGB数据单端信号传输，也可以直接以LVDS差分信号传输。LVDS差分信号与传统的单端信号相比，其优点有：(1)抗干扰能力强，干扰噪声一般会等值、同时的被加载到两根信号线上，而其差值为0，即噪声对信号的逻辑意义不产生影响；(2)能有效抑制电磁干扰(EMI)，由于两根线靠得很近且信号幅值相等，这两根线与地线之间的耦合电磁场的幅值也相等，同时它们的信号极性相反，其电磁场将相互抵消，故对外界的电磁干扰也小。
可编程逻辑器件13例如采用FPGA(Field Programmable Gate Array，现场可编程门阵列)器件。
存储器件14电连接可编程逻辑器件13，其例如是DDR4、DDR3、DDR2、LPDDR2、SDRAM等，同时可以根据实际需求来判断使用存储器件的数量。
以太网接口16a及16b分别通过物理层收发器15a及15b电连接可编程逻辑器件13配置的两个SerDes通道。本实施例中，每个SerDes通道包括两对差分信号线，以及所述两对差分信号线中的一对差分信号线用于数据发送且另一对差分信号线用于数据接收。物理层收发器15a及15b例如是10Gbase-T或5Gbase-T型以太网物理层收发器，其可以采用市售的AQR111C、AQR114C、BCM54892、BCM54992、BCM54991等芯片。本实施例搭配SerDes 通道，使得单个以太网接口16a/16b的传输速率可以为10Gbps/5Gbps/2.5Gbps/1Gbps。再者，以太网接口16a、16b可以分别是集成网变的RJ45，或者是采用网变与RJ45分离式设计，又或者是2*1集成网变的RJ45。
考虑到图1所示实施例依旧是用插拔网线的方式来传输信号，由于网线频繁拔插相对易损坏，因此图4所示实施例在图1所示实施例的基础上，增加了多个例如两个USB3.0接口，用来扩展信号传输方式。
具体地，如图4所示，本实施例的接收卡30包括：电路板31和设置在电路板31上的接插组件32、可编程逻辑器件33、存储器件34、物理层收发器组35a及35b、多个例如两个以太网接口36a及36b、多个例如两个USB3.0接口37a及37b、和直流电源电路38。其中，接插组件32、可编程逻辑器件33、存储器件34、物理层收发器组35a及35b和以太网接口36a及36b的结构及功能与图1所示的接插组件12、可编程逻辑器件13、存储器件14、物理层收发器组15a及15b和以太网接口16a及16b的结构及功能类似，故在此不再赘述。
再者，USB3.0接口37a、37b分别电连接可编程逻辑器件33配置的多个SerDes通道，并且USB3.0接口37a、37b还电连接直流电源电路38以用于获取电源信号向外传送。此处的USB3.0接口37a、37b为具有多对高速差分信号引脚和电源信号引脚的接口，因此其还可以替换成其他具有多对高速差分信号引脚和电源信号引脚的接口，比如Mini HDMI接口。
承上述，针对接收卡30的两个USB3.0接口(例如Micro USB3.0接口或其他类型USB3.0接口)，衍生出图5所示采用无线传输子卡40的显示控制卡组件。图5所示无线传输解决方案的主要目的是解决行业网线频繁拔插易坏、不稳定，前期安装和后期维护成本较大的痛点问题。同时随着LED显示屏行业的发展，小间距LED显示屏的需求越来越多，前维护的设计越来越流行；针对LED显示屏前维护方案，无线传输无疑提供了一个非常优质的方案，方便LED显示屏设计和现场安装维护。
具体地，如图5所示，每个USB3.0接口37a、37b通过USB3.0线连接一个无线传输子卡40。此处的USB3.0线为一种能够同时传输数据信号和电源信号的线缆。再者，如图6所示，无线传输子卡40包括：电路板和设置在所述电路板上的直流转直流电路43、无线发送芯片45a和无线接收芯片45b。所述电路板上设有焊盘组41，且焊盘组41电连接USB3.0线的一端。直流转直流电路43电连接焊盘组41、无线发送芯片45a和无线接收芯片45b，以用于从焊盘组41获取电源信号并向无线发送芯片45a和无线接收芯片45b提供工作电压。无线发送芯片45a和无线接收芯片45b间隔设置并通过SerDes通道电连接焊盘组41；所述SerDes通道包含两对差分信号线，以及所述两对差分信号线中的一对差分信号线用于数据发送、且另一对差分信号线用于数据接收。再者，无线发送芯片45a和无线接收芯片45b的工作频率位于毫米波频段。此处的毫米波频段典型地是指频率范围为30GHz～300GHz，相应波长为1毫米～10毫米。本实施例这种工作在毫米波频段的无线发送芯片45a、无线接收芯片45b非常适合于LED显示屏中显示箱体的应用场合，因为LED显示屏典型地由多个显示箱体拼接而成，当将无线传输子卡40装设在各个显示箱体之后，首要考虑的问题是如何避免同一个LED显示屏中不需要进行数据收发的两个无线传输子卡40之间的无线信号串扰，而本实施例无线传输子卡40中的无线发送芯片45a、无线接收芯片45b工作在毫米波频段，相较于现有技术中的WiFi模块、蓝牙模块等无线传输模块而言可以大大降低无线信号串扰可能。再者，基于目前无线芯片的性能和频段的易获得性，本实施例优选为无线发送芯片45a、无线接收芯片45b的工作频率为频率范围57GHZ-67GHZ或71GHZ-87GHZ，例如为60GHZ或80GHZ。
参见图7，本实施例的接收卡50去掉了图4所示接收卡30的以太网接口+物理层收发器，将可编程逻辑器件的SerDes通道全部连接至USB3.0等接口(对应第一类型接口)。此设计不仅仅可以缩小接收卡的尺寸大小，更是可以让采用该种接收卡的LED显示屏控制系统 设计方案可以变得多元化。
具体地，如图7所示，接收卡50包括：电路板51和设置在电路板51上的接插组件52、可编程逻辑器件53、存储器件54、多个例如四个USB3.0接口57a及57b和59a及59b、以及直流电源电路58。其中，接插组件52、可编程逻辑器件53和存储器件54结构及功能与图1所示的接插组件12、可编程逻辑器件13和存储器件14的结构及功能类似，故在此不再赘述。
再者，USB3.0接口57a、57b、59a、59b分别电连接可编程逻辑器件53配置的多个SerDes通道，并且USB3.0接口57a、57b、59a、59b还电连接直流电源电路58以用于获取电源信号向外传送。此处的USB3.0接口57a、57b、59a、59b为具有多对高速差分信号引脚和电源信号引脚的接口，因此其还可以替换成其他具有多对高速差分信号引脚和电源信号引脚的接口，比如Mini HDMI接口。
另外，对于图7中设有四个USB3.0接口57a、57b、59a、59b的接收卡50，可以直接在子卡上进行传输速率和信号传输方式的确定，因为对于每个USB3.0接口而言，都可以有多种连接方案，可以用来接无线传输子卡，也可用来接有线网络传输子卡，以下结合图8至图11列举出接收卡50的四个USB3.0接口57a、57b、59a、59b的多种连接方案。
具体地，如图8所示，可以将四个USB3.0接口57a、57b、59a、59b分别通过USB3.0线与无线传输子卡40连接，实现无线信号传输。
或者，如图9所示，可以将四个USB3.0接口57a、57b、59a、59b分别通过USB3.0线与有线网络传输子卡60连接。至于有线网络传输子卡60，如图10所示，其包括：电路板和设置在所述电路板上的USB3.0接口(对应第二类型接口)61、直流转直流电路63、物理层收发器65和以太网接口67。USB3.0接口61连接USB3.0线的一端，其为一种具有多对高速差分信号引脚和电源信号引脚的接口。直流转直流电路63电连接USB3.0接口61和物理 层收发器65，以用于从USB3.0接口61获取电源信号并向物理层收发器65提供工作电压。物理层收发器65通过SerDes通道电连接USB3.0接口61，且此处的SerDes通道包含两对差分信号线，以及所述两对差分信号线中的一对差分信号线用于数据发送且另一对差分信号线用于数据接收。再者，此处的物理层收发器65可以选用1GBase-T/2.5GBase-T/5GBase-T/10GBase-T型以太网物理层收发器等。此外，以太网接口67电连接物理层收发器65，其例如说集成网变的RJ45，或者采用网变和RJ45分离式设计。
又或者，如图11所示，可以将四个USB3.0接口57a、57b、59a、59b分别与两个无线传输子卡40和两个有线网络传输子卡60连接。
以上仅列出采用接收卡50的三种显示控制卡组件的结构，但本申请实施例并不以此为限；因为接收卡50的灵活性，可以用于多种场景，因此可以随着场景的不同去更改子卡的方案设计。
综上所述，本申请实施例的接收卡和显示控制卡组件可以具有以下一个或多个有益效果：(i)对于传输速率解决方案，能够有效解决千兆带宽不够问题，更适用于小间距应用，带宽可以选择10G/5G/2.5G/1G甚至其他带宽，且灵活性更高、适用性更强；(ii)对于信号传输方式解决方案，解决了传统传输方式网线频繁拔插易坏这一痛点问题，可以根据应用场景的不同去选择不同的信号传输方式，大大提升了LED显示屏控制系统的多元化与实际有效应用性，极大的缩短了安装和维护的工作量；以及(iii)保留常规的RGB单端信号外增加了LVDS差分信号，可以加强传输抗干扰能力，能有效抑制电磁干扰(EMI)、提升EMC。
此外，可以理解的是，前述各个实施例仅为本申请的示例性说明，在技术特征不冲突、结构不矛盾、不违背本申请的发明目的前提下，各个实施例的技术方案可以任意组合、搭配使用。
最后应说明的是：以上实施例仅用以说明本申请的技术方案，而非对其限制；尽管 参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围。

Claims (12)

  1. 一种接收卡，其特征在于，包括：电路板和设置在所述电路板上的可编程逻辑器件、存储器件、接插组件、物理层收发器组及多个以太网接口；其中，
    所述存储器件和所述接插组件电连接所述可编程逻辑器件；
    所述多个以太网接口分别通过所述物理层收发器组电连接所述可编程逻辑器件配置的多个SerDes通道；
    每个所述SerDes通道包括两对差分信号线，以及所述两对差分信号线中的一对差分信号线用于数据发送且另一对差分信号线用于数据接收。
  2. 如权利要求1所述的接收卡，其特征在于，所述物理层收发器组包括两个5Gbase-T或10GBASE-T型以太网物理层收发器，所述多个以太网接口的数量为两个，且所述两个以太网接口分别通过所述两个5Gbase-T或10GBASE-T型以太网物理层收发器电连接所述可编程逻辑器件配置的两个所述SerDes通道。
  3. 如权利要求2所述的接收卡，其特征在于，所述接插组件包含显示数据单端信号引脚组、显示控制信号单端信号引脚组和显示数据差分信号引脚组；所述可编程逻辑器件电连接显示数据单端信号引脚组和显示数据差分信号引脚组，以用于以单端信号和LVDS差分信号二选一方式输出显示数据；以及所述可编程逻辑器件电连接所述显示控制信号单端信号引脚组，以用于以单端信号输出显示控制信号。
  4. 如权利要求1所述的接收卡，其特征在于，所述接收卡还包括：设置在所述电路板上的直流电源电路和多个第一类型接口，且所述第一类型接口不同于所述以太网接口；
    所述多个第一类型接口分别电连接所述可编程逻辑器件配置的另外多个SerDes通道，并且所述多个第一类型接口还电连接所述直流电源电路以用于获取电源信号向外传送。
  5. 如权利要求4所述的接收卡，其特征在于，所述多个第一类型接口为两个USB3.0 接口，且每个所述USB3.0接口电连接所述可编程逻辑器件配置的一个SerDes通道。
  6. 一种接收卡，其特征在于，包括：电路板和设置在所述电路板上的可编程逻辑器件、存储器件、插接组件、直流电源电路及多个第一类型接口；其中，
    所述存储器件和所述接插组件电连接所述可编程逻辑器件；
    所述多个第一类型接口分别电连接所述可编程逻辑器件配置的多个SerDes通道，且还电连接所述直流电源电路以用于获取电源信号向外传送；
    每个所述SerDes通道包括两对差分信号线，以及所述两对差分信号线中的一对差分信号线用于数据发送且另一对差分信号线用于数据接收。
  7. 如权利要求6所述的接收卡，其特征在于，所述多个第一类型接口为两个USB3.0接口，且每个所述USB3.0接口电连接所述可编程逻辑器件配置的一个所述SerDes通道。
  8. 如权利要求6所述的接收卡，其特征在于，所述多个第一类型接口为四个USB3.0接口，且每个所述USB3.0接口电连接所述可编程逻辑器件配置的一个所述SerDes通道。
  9. 如权利要求6所述的接收卡，其特征在于，所述接插组件包含显示数据单端信号引脚组、显示控制信号单端信号引脚组和显示数据差分信号引脚组；所述可编程逻辑器件电连接显示数据单端信号引脚组和显示数据差分信号引脚组，以用于以单端信号和LVDS差分信号二选一方式输出显示数据；以及所述可编程逻辑器件电连接所述显示控制信号单端信号引脚组，以用于以单端信号输出显示控制信号。
  10. 一种显示控制卡组件，其特征在于，包括：如权利要求6至9任意一项所述的接收卡，以及至少一个子卡；
    其中，每个所述子卡通过用于传输数据信号和电源信号的线缆连接所述接收卡的所述多个第一类型接口中的一个所述第一类型接口。
  11. 如权利要求10所述的显示控制卡组件，其特征在于，所述至少一个子卡包括无线 传输子卡，且所述无线传输子卡包括：第二电路板和设置在所述第二电路板上的直流转直流电路、无线发送芯片和无线接收芯片；所述第二电路板上设有焊盘组，且所述焊盘组电连接所述线缆的一端；所述直流转直流电路电连接所述焊盘组、所述无线发送芯片和所述无线接收芯片，以用于从所述焊盘组获取电源信号并向所述无线发送芯片和所述无线接收芯片提供工作电压；所述无线发送芯片和所述无线接收芯片间隔设置并通过第二SerDes通道电连接所述焊盘组，所述第二SerDes通道包含两对第二差分信号线，以及所述两对第二差分信号线中的一对第二差分信号线用于数据发送、且另一对第二差分信号线用于数据接收；以及所述无线发送芯片和所述无线接收芯片的工作频率位于毫米波频段。
  12. 如权利要求10或11所述的显示控制卡组件，其特征在于，所述至少一个子卡包括有线网络传输子卡，且所述有线网络传输子卡包括：第三电路板和设置在所述第三电路板上的第二类型接口、直流转直流电路、物理层收发器和以太网接口；所述第二类型接口与所述第一类型接口为相同类型接口且连接所述线缆的一端；所述直流转直流电路电连接所述第二类型接口和所述物理层收发器，以用于从所述第二类型接口获取电源信号并向所述物理层收发器提供工作电压；所述物理层收发器通过第三SerDes通道电连接所述第二类型接口，且所述以太网接口电连接所述物理层收发器；所述第三SerDes通道包含两对第三差分信号线，以及所述两对第三差分信号线中的一对第三差分信号线用于数据发送、且另一对第三差分信号线用于数据接收。
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