WO2021015618A2

WO2021015618A2 - Amplifier with continuous gain control

Info

Publication number: WO2021015618A2
Application number: PCT/NL2020/050481
Authority: WO
Inventors: Michiel Antonius Petrus Pertijs; Euchul KANG
Original assignee: Technische Universiteit Delft
Priority date: 2019-07-23
Filing date: 2020-07-22
Publication date: 2021-01-28
Also published as: WO2021015618A3; EP4005089A2; NL2023557B1

Abstract

A variable gain amplifier with an amplifier (A), a current-steering circuit (CSC), a feedback network (FBN), and a gain control circuit (GCC). The current-steering circuit (CSC) divides an output current (I_out) of the amplifier (A) into a plurality of control currents (I_i), wherein the output current (I_out) is divided using associated current-steering fractions (α_i), the current-steering fractions α_ibeing determined using a control input from the gain control circuit (GCC). The feedback network (FBN) comprises a network of components and is arranged to provide the feedback current (I_fb) as a weighted sum of the control currents (Ii), in accordance with I_fb = Σ^N _i ₌₁ β _i I _ι, wherein β_i are feedback factors, 0≤ β_i≤ 1, determined by the components in the feedback network (FBN). The gain control circuit (GCC) is arranged to control the associated current-steering fractions (α_i) in a continuous time-varying manner, wherein at any time Σ^N _α=1 α_i = 1.

Description

Amplifier with continuous gain control Field of the invention

The present invention relates to a variable gain amplifier in a first aspect, in a second aspect to an ultrasound imaging device, and in a third aspect to a method of operating a variable gain amplifier.

Background art

US patent publication US2004/0090269 discloses a variable gain amplifier using interpolation between discrete gain steps, exploiting the characteristics of a differential pair of transistors as smooth current steering device. A differential pair at the output of an amplifier directs a fraction of the output current back to the input, and a fraction towards the output. The current gain of this amplifier can be continuously controlled through the voltage applied to the differential pair.

US patent publication US2018/262169 discloses a time gain compensation circuit including an impedance network and a differential amplifier coupled to the impedance network. The impedance network provides a fixed impedance to the differential amplifier when a gain of the time gain compensation circuit is changed from a maximum value to a minimum value.

Japanese patent publication JP-H03-232310 discloses a variable gain amplifier having high linearity, using a ladder resistance network in a current feedback loop. The resistors in the ladder network are switched on or off in the feedback loop using discrete switches, under control of a digital control signal.

US patent publication US2018/3671 1 1 discloses an amplifier with built in time gain compensation for ultrasound applications. A feedback loop in an amplifier circuit uses a combination of resistors and capacitors forming a variable impedance feedback circuit, wherein inclusion of the individual resistors and capacitors is controlled by switching on or off NMOS transistors under control of a digital control signal.

The article by H. Y. Xie et al.‘A SiGe low noise variable gain amplifier with controllable feedback of a p-i-n diode’, Microwave Conference Procedings (CMJW), 20 April 201 1 , pages 1 -4, discloses a variable gain amplifier using a P-i-N diode in the amplifier feedback circuit.

Summary of the invention

The present invention seeks to provide a variable gain amplifier which is particularly suited for applications requiring a continuous and smooth gain control over a wide range, and requiring a time dependent control, e.g. for implementing a time-gain control (TGC) amplifier scheme.

According to the present invention, a variable gain amplifier is provided as defined in claim 1 . In a further aspect, an ultrasound imaging device is provided as defined in claim 12, and in an even further aspect, a method is provided as defined in claim 15.

The present invention embodiments allow to provide a variable gain amplifier, that is particularly suited for time-gain control (TGC) amplifier schemes. The present invention embodiments allow to provide continuous, smooth gain control, without introducing gain-switching artefacts (in contrast with prior-art TGC implementation schemes based on discrete gain steps). Furthermore, the present invention embodiments do not rely on the process, supply and temperature dependent properties of transistors, but defines the gain based on well-defined ratios of discrete components (resistors or capacitors). This in contrast with prior-art TGC implementation schemes that approximate an exponential gain by means of non-linear device characteristics. Additionally, the present invention embodiments do not require a preceding low-noise amplifier (LNA) in the signal path as it can provide low input referred noise in a power-efficient manner, in contrast with prior-art TGC implementation schemes that employ an attenuator at their input, which needs to be driven by a power-hungry high-dynamic-range LNA.

Short description of drawings

The present invention will be discussed in more detail below, with reference to the attached drawings, in which

Fig. 1 shows a circuit diagram of an exemplary embodiment of a variable gain amplifier according to the present invention;

Fig. 2 shows a timing diagram of current-steering fractions as applied in the embodiment of

Fig. 1 ;

Fig. 3 shows a circuit diagram of a further embodiment of the variable gain amplifier according to the present invention;

Fig. 4 shows an exemplary example of a timing diagram of control input parameters as used in the embodiment of Fig. 3;

Fig. 5 shows a circuit diagram of an exemplary embodiment of a gain-control circuit in accordance with the present invention;

Fig. 6 shows a circuit diagram of a further embodiment a variable gain amplifier according to the present invention;

Fig. 7 shows a circuit diagram of an even further embodiment a variable gain amplifier according to the present invention;

Fig. 8 shows a circuit diagram of yet a further embodiment a variable gain amplifier according to the present invention; and

Fig. 9 shows a schematic diagram of an ultrasound imaging device including a variable gain amplifier according to one of the present invention embodiments.

Description of embodiments

Many communication and sensing applications require variable-gain amplifiers (VGAs) to compress the dynamic range (DR) of an input signal of which the amplitude varies as a function of time. A specific example of interest is ultrasound imaging, in which a transducer is used to transmit an acoustic pulse into a medium and record the echoes resulting from backscattering of this pulse. Due to absorption and scattering, the acoustic signal is attenuated as it travels through the medium. Echo signals from scatterers close to the transducer arrive first and are attenuated less than subsequent echo signals originating from scatterers further away. This results in a signal received by the transducer of which the amplitude decreases exponentially with time (linearly in decibels). It is important to compensate for this, in order to maintain image uniformity and to reduce the required DR of the receiver circuitry. This can be realized by amplifying the received echo signals with a gain that increases exponentially with time. This is often referred to as time-gain compensation (TGC).

Amplifiers with discrete gain steps approximate the ideal exponentially-varying gain by a number of discrete gain steps that are sequentially applied. They are also referred to as programmable-gain amplifiers (PGAs). An important advantage of this approach is that the gain steps can be accurately defined by means of a digitally-programmable resistive feedback network, a digitally-programmable capacitive feedback network, or a digitally-programmable current-steering feedback network. Moreover, the gain steps can be divided among multiple amplifier stages, with course gain steps realized in the low-noise amplifier (LNA) at the input of the receive signal path, which enables the realization of highly power-efficient amplifiers. Switching from one discrete gain step to the next, however, is typically associated with a switching transient that can lead to artefacts in the ultrasound image at a depth that corresponds to the gain-switching moment. Such artefacts can be made negligible by making the gain steps small, but this requires a large number of gain steps to cover the gain range, leading to a complex circuit that requires substantial die area.

Amplifiers with continuous gain control are also referred to as variable-gain amplifiers (VGAs) and typically have a gain that can be set by an analogue control input, typically a control voltage. The gain tends to depend (approximately) exponentially on the control voltage, giving a linear-in-dB gain control. By ramping the control voltage linearly as a function of time, the gain can be swept across a desired range to realize TGC without the disadvantages associated with discrete gain steps.

According to the present invention embodiments, an example of which is shown in the circuit diagram of Fig. 1 , a variable gain amplifier 1 is provided comprising an amplifier A, a currentsteering circuit CSC, a feedback network FBN, and a gain control circuit GCC. The current-steering circuit CSC is connected to an output of the amplifier A, and to a plurality of inputs of the feedback network FBN. The feedback network FBN is connected to an input of the amplifier A which is connected to receive an input current (I IN) in operation, the feedback network (FBN) being arranged to provide a feedback current 1®. The current-steering circuit CSC is arranged to divide an output current lout of the amplifier A into a plurality of control currents l·, 1 < / < N, N being an integer larger than or equal to 2. The output current lout is divided using associated current-steering fractions a, the current-steering fractions a being determined using a control input from the gain control circuit GCC to have a value of 0 < a £ 1 . The feedback network FBN comprises a network of (passive and/or active) components and is arranged to provide the feedback current I® as a weighted sum of the control currents l·, in accordance with I_fb = S^bbi, wherein b, are feedback factors, 0 < b, < 1 , determined by the components in the feedback network FBN, e.g. by ratios of passive components in the FBN. The gain control circuit GCC is arranged for providing the control input (e.g. in the form of multiple control input signals) to the current-steering circuit CSC, the gain control circuit GCC being arranged to control the associated current-steering fractions a, in a continuous time-varying manner wherein at any time å„=_! <¾ = 1. This embodiment allows a precise control of the feedback current 1® by dividing the output current lout towards the feedback network FBN, e.g. by having two steering fractions a, to be non-zero, while the other steering fractions a, are substantially zero.

It is noted that amplifier A in the embodiments described herein is implemented as an error amplifier that receives the difference between the input current IIN and feedback current I® and provides gain so as to null this difference.

In a specific embodiment, the gain control circuit GCC is arranged to control the associated steering fractions in accordance with ak = g; ai= 1 -g; a, = 0 for i ¹ k, I, and y being a fraction parameter set in the control input.

In the embodiment shown in Fig. 1 , the FBN defines a number of N discrete gain steps, while the CSC enables smooth interpolation between those gain steps. Each gain step is associated with a current applied to the FBN, 1 £ i £ N. The FBN provides a weighted sum of these currents to the input of the amplifier in the form of a feedback current /¾:

where b, are the feedback factors, which are defined by ratios of passive components (resistors, capacitors, or direct connections), and as a result are attenuating: 0 < b_\ £ 1.

The CSC steers the loop amplifier’s output current lout to one or more of the FBN’s inputs, in such a way that the total output current lout is divided among the FBN’s inputs:

where a, is the fraction of lout that is steered to l·. The fractions a, can be changed by means of the control input (e.g. a control voltage) to the CSC.

The loop amplifier senses the voltage at its input and, ideally, provides an output current lout such that its input voltage is nulled. In Fig. 1 , the amplifier shown has two outputs, which provide the same current lout, so that this current can both flow into CSC and be delivered to a load (e.g. the next stage in the signal path). The loop amplifier’s input voltage can only be nulled if the feedback current 1® equals the input current L, and thus lout will satisfy

This shows that lout is an amplified version of the input current, with a gain G = 1//?_eff, where b^ί is the effective feedback factor due to the combination of the CSC and the FBN. The gain G depends on the fractions a, and can therefore be changed via the control input.

For the case in which lout is fully steered to only one of the inputs of the FBN, say to input I_k, i.e. O_k = 1 , a, = 0 for i ¹ k, the circuit simplifies to a conventional feedback amplifier in which the gain is defined by feedback factor b . G = 1//?_k. By changing the selected input of the FBN, the gain can then be changed, but as long as the current is fully steered to one input FBN at any point in time, this forms an amplifier with discrete gain steps, with the associated disadvantages mentioned earlier.

In accordance with the present invention embodiments, the CSC is arranged such that lout can be smoothly steered from one input of the FBN to another. Assume that the current is partially steered to input I_k and partially to input li, i.e. ak = g; ai = 1 -g; a, = 0 for i ¹ k, I, where 0 < y < 1 is set by the control input and defines the fraction of lout that is steered to I_k. Then, the gain becomes

1

^G Ubϋ + (1 - U)bi

allowing the gain to be changed to any value between 1//?_k and 1//?i by changing g. Thus, a smooth interpolation between the gain steps is realized.

Fig. 2 shows, as an example, how the fractions a, can be changed as a function of time to sweep the gain of the variable gain amplifier 1 smoothly from 1/bi to 1 //?N.

The exemplary embodiment of the variable gain amplifier 1 shown as a general block diagram in Fig. 1 is a current amplifier, with a current input and a current output. Other input and output configurations are possible, and intended to be within the scope of the present invention embodiments. By adding a resistor or a capacitor at the input of the amplifier A of Fig. 1 , an input voltage can be converted into a current, which is then amplified. Thus, the variable gain amplifier 1 becomes a transconductance amplifier. By adding a resistor or a capacitor at the output of the amplifier A in Fig. 1 , the output current lout can be converted into a voltage, making the variable gain amplifier 1 a transimpedance amplifier. By combining these methods, i.e. by adding a resistor or capacitor at the input and at the output, a voltage amplifier can be realized. Finally, while the implementations shown have single-ended inputs and outputs, it is also possible to obtain a differential input and/or output by an appropriate design of the amplifier A and the feedback network FBN.

In a further embodiment, the present invention relates to variable gain amplifier 1 in which the current-steering circuit CSC comprises a plurality oftransistors TI-TN, ofwhich source terminals are commonly connected to the output of the amplifier A, and the control input is provided as gate voltages V_g,i- V₉,N to each of the plurality of transistors TI-TN.

Fig. 3 shows a circuit diagram of a further embodiment wherein the CSC is implemented using source-coupled PMOS transistors TI-TN, in more generic words the plurality of transistors (TI- TN) comprise MOS transistors. The output current lout of the (loop) amplifier A in this example flows into the common-sources of the transistors TI-TN at the top. The path that the current takes towards the outputs /i to 7N depends on the voltages V_g,i to _&N applied to the gates of the PMOS transistors TI-TN, with a lower voltage causing more of the current to flow to the corresponding output. Thus, the fractions <¾ can be set by applying appropriate gate voltages V_g,i. Note that, while this example shows an implementation using PMOS transistors, a similar circuit can readily be constructed using NMOS transistors. Fig. 4 shows, again as an example, how the time-varying fractions <¾ shown in Fig. 2 can be realized with time-varying gate voltages applied to the circuit in Fig. 3. In the embodiment shown in Fig. 3 also an example implementation of a feedback network FBN is shown that realizes exponentially-spaced gain steps by means of a network consisting of capacitors Cj. Note that the capacitor values in this example can be chosen to obtain a desired set of gain steps, and that the ladder topology allows the realization of a wide gain range without requiring a large ratio between the smallest and largest capacitor Cj in the network. Thus, in a further embodiment, the feedback network FBN comprises a ladder network of capacitors Cj.

Note that in the implementation shown in Fig. 3, the DC biasing of the network is not well defined. This can be taken care of in a further embodiment, wherein the feedback network FBN further comprises a resistor in parallel to one or more of the capacitors in the ladder network of capacitors (Cj). E.g. by including resistors (not shown) in parallel to the capacitors Cj, with sufficiently high values to ensure that within the frequency range of interest, the transfer function of the network is determined by the capacitors Cj.

Given the exponentially spaced gain steps of the feedback network FBN and the smooth interpolation provided by the CSC, the embodiments of the present invention described herein can be used as a time-gain compensation amplifier with an approximately linear-in-dB gain control, e.g. in ultrasound imaging transducer circuits.

The present invention in a further aspect relates to an ultrasound imaging device 5, an exemplary embodiment of which is shown in the schematic diagram shown in Fig. 9. The ultrasound imaging device 5 comprises a transducer 6 to transmit an acoustic signal (e.g. a pulse type signal) into a medium and to receive echo signals, the transducer 6 being connected to a variable gain amplifier 1 according to any one of the embodiments described herein. More specifically, in a further embodiment, the ultrasound imaging device further comprises an imaging device control unit 8, the imaging device control unit 8 being connected to the variable gain amplifier 1 and arranged to implement a time-gain compensation (TGC) scheme using the control input of the variable gain amplifier 1. In an even further embodiment, the transducer 6 and the variable gain amplifier 1 are part of an in-probe receiver circuit 7. As the variable gain amplifier 1 according to any one of the embodiments described herein may be implemented as a single integrated circuit device, it can be easily miniaturized and included together with the transducer 6 in the probe of an ultrasound imaging apparatus 5. It is noted that Fig. 9 shows a simplified block diagram, in actual implementations further components would be present, such as analog-to-digital converters (ADC), beamforming circuitry, etc. Furthermore, in practical implementations a plurality of these in-probe receiver circuits 7 are present in a parallel operating manner to serve elements of a transducer array.

The time-gain compensation scheme (TGC) can be obtained using an even further aspect of the present invention, relating to a method of operating a variable gain amplifier 1 according to any one of the embodiments described herein, comprising receiving an input signal IIN at the input of the variable gain amplifier 1 , and controlling the control input of the variable gain amplifier 1 to implement a time-gain compensation TGC scheme for signal processing of the input signal I IN.

Fig. 5 shows an example implementation of the gain control circuit GCC that generates the gate voltages Vg,i from a single control voltage ^co_ntrol. This control voltage ^co_ntrol can optionally be shared by multiple (variable gain) amplifiers, for instance by an array of variable gain amplifiers 1 associated with an array of ultrasound transducer elements, the echo signals of which can be compressed by the same time-varying gain.

As shown in the exemplary embodiment of Fig. 5, the gain control circuit GCC comprises a plurality of stacked MOS (e.g. NMOS) differential pair connected transistors TDI-TDN-I , the gates of each differential pair connected transistors TDI being connected to a control input voltage Vcontroi and an associated reference voltage V_ren, respectively. A bias current source IB is connected to the plurality of stacked MOS differential pair connected transistors TDI-TDN-I . A plurality of diode- connected MOS (e.g. PMOS) transistors MPi is present, each connected to an associated one of the plurality of stacked MOS (e.g. NMOS) differential pair connected transistors TDI-TDN-I . The gate voltages V_{g, i} of the plurality of diode connected MOS (e.g. PMOS) transistors MPi are provided as control input to the current-steering circuit CSC.

In this embodiment, by means of a set of stacked NMOS differential pairs TDI-TDN-I , a bias current h is steered to one of a set of N diode-connected PMOS transistors MPi - MPN, the gate voltages of which are the required voltages V_g,i. Each NMOS differential pair TDI-TDN-I compares

steered to MPi. If Vreti < controi < Vref,2, / B is steered to MP2. Thus, as Vcontroi increases, h is gradually steered from MPi to MP2 etc. until it finally fully flows to MPN if Vcontroi > V_ref,N-i. If Vcontroi increases linearly with time, this leads to gate voltages V_g,i in accordance with e.g. the timing diagram shown Fig. 4.

The reference voltages V_reti can be generated, for instance, by passing an appropriate bias current through a string of resistors. To save power and chip area, the circuit of Fig. 5 can be shared by multiple amplifiers, e.g. multiple variable gain amplifiers 1 according to one of the present invention embodiment. Note that the circuit in Fig. 5 is just an example of how the voltages

can be generated. A similar complementary circuit with diode-connected NMOS transistors and PMOS differential pairs can also be used. Also, current mirrors can be employed to allow the circuit to operate with smaller voltage headroom.

The control voltage Vco_ntroi can be an externally-generated analog control signal, but it can also be generated on-chip, for instance by an digital-to-analog converter (DAC) to enable digital gain control, or by an integrator-type circuit that generates a voltage that ramps as a function of time.

An important challenge in realizing a variable gain amplifier 1 such as the embodiment shown in Fig. 1 is the realization of the loop amplifier A. As said, ideally, this amplifier A provides an output current lout such that its input voltage is nulled. This, however, would require infinite loop gain. Practical amplifiers provide finite loop gain, which should be sufficiently high across the frequency range of interest to ensure that the closed-loop transfer function is sufficiently close to the desired transfer function. For higher values of the desired closed-loop gain G =

which correspond to larger attenuation in the feedback network FBN, the loop gain is lower, and hence the error is larger. If the loop amplifier A has a fixed gain and bandwidth, the time varying nature of G comes with an undesired time-varying error and typically also a time-varying closed loop bandwidth.

In order to obtain a gain accuracy and bandwidth that are less dependent on the variable gain, the gain of the loop amplifier A is made dependent on the control input in a further embodiment, so as to obtain a more constant loop gain. This control can also be employed to ensure that the feedback loop is stable across the range of gain values. A possible way to implement this is to make the biasing of the transistors in the loop amplifier A dependent on the control input. A suitable control-dependent bias current for the loop amplifier A can be derived from a control voltage using a circuit similar to that shown in Fig. 5, in which current is steered based on the level of the control voltage relative to a set of reference voltages. In a further embodiment, the amplifier A has a finite loop gain, which finite loop gain is dependent on an amplifier gain control input.

An alternative implementation of an amplifier 1 with continuous gain control according to the present invention is shown in Fig. 6. Here, the feedback network FBN is implemented using a string of resistors Rj ratherthan a capacitive network, so that the feedback factors are set by resistor ratios. This embodiment has the feature that the feedback network FBN comprises a circuit of resistors Rj, e.g. a series circuit.

In another exemplary embodiment, shown in Fig. 7, the feedback network FBN consists of a direct feedback to the input and a connection to ground, realizing feedback factors /?i = 1 and bi = 0. The current-steering circuit CSC in this embodiment is a PMOS differential pair that steers a fraction g of /out to the input. This results in a transfer function /_{ou t} = 1/y I_m allowing the gain to be changed in a continuous manner by changing g by means of the control voltage. For instance, if g is swept from 1 to 0.1 , the gain increases from 1 to 10. Referring to the more generic embodiments described above, in this specific embodiment N=2, and the feedback network FBN comprises a direct feedback to the input of the amplifier A and a connection to ground.

In another exemplary embodiment, the CSC comprises a cascade of K several differential transistor pairs T_Daj, T_Dbj, each of which steers a fraction g\ towards the input. Fig. 8 shows this for K = 2. The fraction of /_out that is fed back to the input is thus the product of the fractions g_\, resulting in a transfer function

allowing the gain to be changed in a continuous manner by changing the control voltages Vg,i. For instance, if K = 2, and gi and gi are initially 1 , the gain can be swept from 1 to 100 by first sweeping gi from 1 to 0.1 , and then sweeping gi from 1 to 0.1 . This embodiment has the feature that the feedback network FBN and current-source circuit CSC are combined in a cascaded circuit of K differential transistor pairs T_Daj, T_Dbj, K being an integer larger than or equal to 2, and 1 <i<K. Each differential transistor pair T_Daj, T_Dbj provides a fraction y, of the output current lout as feedback current I® to the input of the amplifier A, as function of the control input. In a further embodiment, the first differential pair To_a,i, T_Db,i provides a fraction gi of lout. The further differential transistor pairs then provide a fraction y, of the output current of the previous differential transistor pairs T_Daj- 1 , T _Db,i-i . In a further embodiment, the control input comprises gate voltages of individual transistors in the cascaded circuit of K differential transistor pairs T_Da , T_Db to set the associated fractions g,.

The present invention has been described above with reference to a number of exemplary embodiments as shown in the drawings. Modifications and alternative implementations of some parts or elements are possible, and are included in the scope of protection as defined in the appended claims.

Claims

1 . A variable gain amplifier comprising

an amplifier (A), a current-steering circuit (CSC), a feedback network (FBN), and a gain control circuit (GCC),

the current-steering circuit (CSC) being connected to an output of the amplifier (A), and to a plurality of inputs of the feedback network (FBN),

the feedback network (FBN) being connected to an input of the amplifier (A) which is connected to receive an input current (IIN) in operation, the feedback network (FBN) being arranged to provide a feedback current (Im),

wherein the current-steering circuit (CSC) is arranged to divide an output current (lout) of the amplifier (A) into a plurality of control currents (I), 1 < / < N, N being an integer larger than or equal to 2, wherein the output current (lout) is divided using associated current-steering fractions (a), the current-steering fractions (a) being determined using a control input from the gain control circuit (GCC) to have a value of 0 < a, < 1 ,

wherein the feedback network (FBN) comprises a network of components and is arranged to provide the feedback current (Im) as a weighted sum of the control currents (I), in accordance with I_fb = å ₌₁ iIi, wherein b, are feedback factors, 0 < b· < 1 , determined by the components in the feedback network (FBN),

and the gain control circuit (GCC) is arranged for providing the control input to the current-steering circuit, the gain control circuit (GCC) being arranged to control the associated currentsteering fractions (a) in a continuous time-varying manner, wherein at any time å„=_! <¾ = 1.

2. The variable gain amplifier according to claim 1 , wherein the gain control circuit (GCC) is arranged to control the associated current-steering fractions (a) in accordance with ak = g; ai

= (1 -y); <3i = 0 for i ¹ k, I, and y being a fraction parameter set in the control input.

3. The variable gain amplifier according to claim 1 or 2, wherein the current-steering circuit (CSC) comprises a plurality of transistors (TI-TN), of which source terminals are commonly connected to the output of the amplifier (A), and the control input is provided as gate voltages

(V_g,i- Vg,N) to each of the plurality of transistors (TI-TN).

4. The variable gain amplifier according to claim 3, wherein the plurality of transistors (TI-TN) comprise MOS transistors.

5. The variable gain amplifier according to any one of claims 1 -4, wherein the feedback

network (FBN) comprises a ladder network of capacitors (Cj).

6. The variable gain amplifier according to claim 5, wherein the feedback network (FBN) further comprises a resistor in parallel to one or more of the capacitors in the ladder network of capacitors (Cj).

7. The variable gain amplifier according to any one of claims 1 -4, wherein the feedback

network (FBN) comprises a circuit of resistors (Rj).

8. The variable gain amplifier according to any one of claims 1 -4, wherein N=2, and the

feedback network (FBN) comprises a direct feedback to the input of the amplifier (A) and a connection to ground.

9. The variable gain amplifier according to any one of claims 1-4, wherein the feedback

network (FBN) and current-steering circuit (CSC) are combined in a cascaded circuit of K differential transistor pairs (T_Daj, T_Dbj), K being an integer larger than or equal to 2, each differential transistor pair (T_Daj, T_Dbj) providing a fraction (y) of the output current (lout) as feedback current (Im) to the input of the amplifier (A), as function of the control input.

10. The variable gain amplifier according to claim 9, wherein the control input comprises gate voltages of individual transistors in the cascaded circuit of K differential transistor pairs (TDa , TDb ) to set the associated fractions (g,).

11. The variable gain amplifier according to any one of claims 1-10, wherein the gain control circuit (GCC) comprises

a plurality of stacked MOS differential pair connected transistors (TDI-TDN-I) , the gates of each differential pair connected transistor (TD) being connected to a control input voltage (Vcontroi) and an associated reference voltage (V_ren) , respectively,

a bias current source (IB) connected to the plurality of stacked MOS differential pair connected transistors (TDI-TDN-I) , and

a plurality of diode-connected MOS transistors (MPi), each connected to an associated one of the plurality of stacked MOS differential pair connected transistors (TDI-TDN-I) ,

wherein the gate voltages (V_g, ,) of the plurality of diode connected MOS transistors (MPi) is

provided as control input to the current-steering circuit (CSC).

12. The variable gain amplifier according to any one of claims 1 -11 , wherein the amplifier (A) has a finite loop gain, which finite loop gain is dependent on an amplifier gain control input.

13. An ultrasound imaging device (5) comprising a transducer (6) to transmit an acoustic signal into a medium and to receive echo signals, the transducer (6) being connected to a variable gain amplifier (1) according to any one of claims 1-12.

14. The ultrasound imaging device according to claim 13, the transducer (6) further comprising an imaging device control unit (8), the imaging device control unit (8) being connected to the variable gain amplifier (1) and arranged to implement a time-gain compensation (TGC) scheme using the control input of the variable gain amplifier (1).

15. The ultrasound imaging device according to claim 13 or 14, wherein the transducer (6) and the variable gain amplifier (1) are part of an in-probe receiver circuit (7).

16. A method of operating a variable gain amplifier according to any one of claims 1-11 ,

comprising

receiving an input signal (IIN) at the input of the variable gain amplifier (1 ),

controlling the control input of the variable gain amplifier (1) to implement a time-gain

compensation (TGC) scheme for signal processing of the input signal (IIN).