WO2021008301A1

WO2021008301A1 - Method and apparatus for accessing hybrid cache in electronic device

Info

Publication number: WO2021008301A1
Application number: PCT/CN2020/097274
Authority: WO
Inventors: 白平昌
Original assignee: 华为技术有限公司
Priority date: 2019-07-17
Filing date: 2020-06-20
Publication date: 2021-01-21
Also published as: CN112242976A; CN112242976B

Abstract

Disclosed are a method and apparatus for accessing a hybrid cache in an electronic device, belonging to the technical field of computer storage. The method comprises: receiving a read instruction for data to be accessed; and when the logical address of said data is found in an index table, acquiring state information of said data from the index table, and then reading said data, wherein the state information is used for indicating whether data is stored in a volatile cache or a nonvolatile cache. That is, according to the present application, an index table is uniformly set for the hybrid cache, and the index table records the logical address of data stored in the hybrid cache and indicates whether data corresponding to each logical address is stored in a DRAM or a PCM, and in this way, when the data is read from the hybrid cache, whether the data is stored in the DRAM or the PCM of the hybrid cache, in which cache the data is stored can be determined merely by searching the index table once, thereby improving the efficiency of accessing the data in the hybrid cache.

Description

Method and device for accessing mixed cache in electronic equipment

Technical field

This application relates to the field of computer storage technology, and in particular to a method and device for accessing a hybrid cache in an electronic device.

Background technique

With the advent of the big data era, a hybrid cache based on dynamic random access memory (DRAM) and phase change memory (PCM) has gradually gained popularity. Among them, compared with DRAM, PCM has the advantages of non-volatile, low power consumption and high storage density. But compared to PCM, DRAM has certain advantages in write delay, so a hybrid cache based on DRAM and PCM can have the advantages of both at the same time. Since the hybrid cache includes two different types of storage media, it is urgent to study a method for accessing the hybrid cache.

In the related art, the index tables of the stored data are respectively set for DRAM and PCM. When the processor accesses certain data, it first determines whether the data is stored in the DRAM according to the DRAM index table. If the data is not stored in the DRAM, it is determined whether the data is stored in the PCM according to the index table of the PCM. If this data is stored in the PCM, the data is obtained from the PCM. Based on the above description, when data needs to be accessed in the hybrid cache, it may be necessary to query the index tables corresponding to DRAM and PCM respectively, thereby affecting the speed of accessing the hybrid cache.

Summary of the invention

The present application provides a method and device for accessing a hybrid cache in an electronic device, which can increase the speed of accessing the hybrid cache. The technical solution is as follows:

In the first aspect, a method for accessing a hybrid cache in an electronic device is provided. The method is applied to the electronic device. The hybrid cache includes a volatile cache and a non-volatile cache. The method includes: receiving a read instruction for the data to be accessed, the read instruction carries the logical address of the data to be accessed; looking up the logical address in an index table, and the index table stores state information corresponding to the logical address of the data stored in the hybrid cache , The status information is used to indicate whether the data stored in the hybrid cache is stored in the volatile cache or the non-volatile cache; when the logical address of the data to be accessed is found in the index table, the data to be accessed is obtained from the index table. Access data status information; read the data to be accessed from the non-volatile cache or volatile cache according to the status information of the data to be accessed.

When using a two-level hybrid cache, if DRAM and PCM set their respective index tables, the DRAM index table needs to be searched first, and when the read data is not in the DRAM index table, the PCM index table needs to be searched. In this way, if the read data is not in the DRAM, a process of looking up the PCM index table needs to be performed, which will increase the delay of data reading. Therefore, in the embodiment of the present application, an index can be uniformly set for the hybrid cache. The index table records the logical address of the data stored in the hybrid cache and indicates whether the data corresponding to each logical address is stored in DRAM or In PCM, when reading data in the hybrid cache, no matter whether the data is stored in the DRAM or PCM of the hybrid cache, it only needs to look up the index table once to determine which cache the data is stored in, thereby improving access The efficiency of mixing data in the cache.

Optionally, each logical address in the index table corresponds to a physical address that stores the data corresponding to each logical address; correspondingly, the method further includes: when obtaining the status information of the data to be accessed from the index table, also obtaining The physical address of the data to be accessed. Correspondingly, reading the data to be accessed from the non-volatile cache or the volatile cache according to the state information of the data to be accessed includes: from the non-volatile cache or the physical address of the data to be accessed according to the state information of the data to be accessed and the physical address of the data to be accessed. Read the data to be accessed in the volatile cache.

In the embodiment of the present application, each logical address in the index table corresponds to a physical address that stores the data corresponding to each logical address. In this way, when determining the status information of the data to be accessed, the physical address of the data to be accessed can also be obtained. Furthermore, the data to be accessed is directly read according to the status information and the physical address, which further improves the efficiency of accessing the data in the hybrid cache.

Optionally, the index table includes a primary index table and a plurality of secondary index tables, and the primary index in the primary index table is the value of the first p bits in the sorting from high to low in the logical address. The 2^p bit value combinations obtained by the combination, p is a positive integer, each bit value combination corresponds to a secondary index table pointer, the secondary index table pointer is used to indicate a secondary index table among multiple secondary index tables , The secondary index table is used to store the logical address and the physical address corresponding to each logical address. The stored logical address is the data logical address stored in the hybrid cache, and the first p bits of the stored logical address are the same as the first level The bit values in the bit value combinations corresponding to the pointers of the secondary index table in the index table are the same. Searching the logical address in the index table includes: searching the first-level index for the bit value combination corresponding to the first p bits of the logical address of the data to be accessed; according to the bit value combination corresponding to the second-level index table pointer, from multiple second-level Obtain a secondary index table from the index table; look up the logical address of the data to be accessed in the secondary index table.

In this embodiment of the application, in order to prevent the structure of the index table from being too large, the index table may include a primary index table and multiple secondary index tables, so that the secondary index table pointer can be configured in the values in the primary index table , In order to be able to quickly find the secondary index table, thereby improving the efficiency of finding the logical address of the data to be accessed.

Optionally, the primary index table of the index table also includes stored state information of the data corresponding to each logical address, specifically: the query result corresponding to each primary index also includes a state information set, and the state information set is used for The storage logical address meets the status information of the data of the corresponding primary index, and the logical address is stored in the secondary index table in order; the status information of the data to be accessed is determined from the status information of each data included in the index table, including: according to the data to be accessed The sorting of logical addresses in the acquired secondary index table determines the status information of the data to be accessed from the status information set included in the query result corresponding to the primary index. Optionally, the secondary index table of the index table further includes the stored state information of the data corresponding to each logical address. Specifically: the secondary index table is also used to store the state information of the data corresponding to each logical address; the secondary index table includes Determining the status information of the data to be accessed in the status information of each data includes: determining the status information of the data to be accessed in the obtained secondary index table.

In the embodiment of the present application, the status information of the data corresponding to each logical address stored in the index table can be set in the primary index table or the secondary index table, which improves the flexibility of the index table.

Optionally, the secondary index in the secondary index table is the bit value of q bits in the logical address except p bits, q is a positive integer, and each secondary index in the secondary index table The query result corresponding to the index includes a logical address set. Each logical address in the logical address set corresponds to a physical address, and the logical address included in the logical address set is the logical address in the hybrid cache and satisfies the corresponding primary index and corresponding secondary The logical address of the indexed data.

When the secondary index table is configured according to the above settings, the number of items included in the secondary index table can be prevented from being excessive, thereby improving the efficiency of searching for information in the secondary index table.

Optionally, after reading the data to be accessed, it further includes: obtaining a heat record sequence corresponding to the logical address of the data to be accessed from the heat record table according to the logical address of the data to be accessed, and the heat record table includes a plurality of heat record sequences Each heat record sequence corresponds to a logical address interval, the logical address of the data to be accessed falls within the logical address interval, and each heat record sequence is used to record the heat of the data corresponding to the logical address interval; update the obtained heat record sequence The recorded heat.

In the embodiment of the present application, it is necessary to configure a heat record for the data in the volatile cache of the hybrid cache, so as to subsequently determine which hot data in the volatile cache needs to be eliminated as warm data based on the heat record.

Optionally, each heat record sequence includes a plurality of bits, and each bit corresponds to an update period. Correspondingly, updating the heat recorded in the acquired heat record sequence includes: acquiring the update period corresponding to the current time, and updating the bit corresponding to the update period corresponding to the current time to indicate that the data corresponding to the logical address corresponding to the heat record sequence is Identifiers visited.

In the embodiment of the present application, an update period can be configured for the bits. In a certain update period, only the bits corresponding to the update period need to be updated, so as to quickly determine whether the data is the most recent according to the bits corresponding to each update period. The popularity of visits over a period of time.

Optionally, the method further includes: detecting the heat decay instruction; obtaining the bit corresponding to the next update cycle after the update cycle corresponding to the current time among the multiple bits of each heat recording sequence; The bit value on the bit position corresponding to the next update cycle is updated to indicate that the data corresponding to the logical address corresponding to the heat record sequence has not been accessed; the next update cycle in each heat record sequence is determined as the update corresponding to the current time cycle.

If some data is frequently accessed within a period of time, the bits in the heat record sequence corresponding to these data will be updated to indicate that the data corresponding to the logical address corresponding to the heat record sequence has been accessed. If these data continue to be accessed in the future, then the heat record sequence will not represent the records that these data have been accessed in the most recent period of time. Therefore, in the embodiment of the present application, it is also necessary to perform heat attenuation on the heat record sequence in the heat record table in the above-mentioned manner.

Optionally, a plurality of bits are periodically arranged in a specified order; the heat record table is equipped with a clock and pointers, the clock periodically counts according to the set time after the system is initialized, and the pointers point to the multiple bits when the system is initialized Each time the timing duration of the clock reaches the set duration, the trigger pointer switches to the next bit position according to the sequence; the bit position corresponding to the update period corresponding to the current time is the bit position pointed to by the current time pointer. Through the configuration of the pointer and the clock, the update period corresponding to each of the multiple bits can be quickly determined.

Optionally, detecting the heat decay instruction includes: triggering the heat decay instruction when the current time reaches the update time point of the heat record table, and the heat record table update time point is configured when the system is initialized; and/or, when the heat record table is updated When the proportion of the sequence in all the heat record sequences is greater than the reference ratio, the heat attenuation instruction is triggered. The high bit of the high heat record sequence refers to the heat of the identifier that the data corresponding to the logical address corresponding to the heat record sequence has been accessed. In the recording sequence, the high-order bits refer to the bits in the multiple bits whose update period is within the reference time period before the current time. That is, heat attenuation can be performed in the above two scenarios, which improves the flexibility of heat attenuation.

Optionally, the method further includes: determining the popularity value of the data stored in the volatile cache according to the heat rate record table; if the popularity value of the data is less than the popularity threshold, eliminating the data to the non-volatile cache. Since a heat record sequence in the heat record table can correspond to a logical address interval, the method of eliminating data provided by the embodiment of this application can take advantage of the spatial locality of the heat data and process a batch of data at the same time, which improves Eliminate the efficiency of hot data.

Optionally, after determining the popularity value of the data stored in the volatile cache according to the popularity record table, it further includes: if the popularity value is less than the popularity threshold, determining the data corresponding to the logical address adjacent to the logical address of the data Heat value; determine the average heat value of the data and the data corresponding to the logical address adjacent to the logical address of the data; if the average heat value is greater than or equal to the heat threshold, keep the data in the volatile cache.

In order to improve the occurrence of errors due to accidental elimination of data, if the heat value of a certain data is less than the heat threshold, the data is not eagerly eliminated to the non-volatile cache, but the logical address is adjacent to the logical address of the data. The heat value of the data is used to comprehensively determine whether the data needs to be eliminated to the non-volatile cache, which improves the flexibility of eliminating hot data.

Optionally, after the average popularity value is determined, the method further includes: if the average popularity value is less than the popularity threshold, evict the data to the non-volatile cache.

If the average heat value is less than the heat threshold, it indicates that most of the data corresponding to the logical address adjacent to the logical address of the data has not been accessed frequently recently. At this time, the data can be eliminated to the non-volatile cache to improve The flexibility of eliminating hot data.

Optionally, before determining the popularity value of the data stored in the volatile cache according to the heat record table, it further includes: when it is detected that the remaining storage capacity of the volatile cache is lower than the idle capacity threshold, and/or when it is detected When the hot data instruction is eliminated, the step of determining the heat value of the data stored in the volatile cache according to the heat record table is executed. That is, hot data elimination can be performed in the above two scenarios, which improves the flexibility of eliminating hot data.

Optionally, each bit of the multiple bits is configured with a time weight, and the time weight of each bit is used to indicate how far the update time of the bit value on the corresponding bit is from the current time, among the multiple bits The time weight of the bit to be updated at the current time is the largest; determining the heat value of the data stored in the volatile cache according to the heat record table, including: obtaining the time weight of multiple bits included in each heat record sequence in the heat record table ; According to the time weights of the multiple bits included in each thermal record sequence, the bit values on the multiple bits included in each thermal record sequence are weighted and summed, and the sum obtained is used as the corresponding to each thermal record sequence The popularity value of the data corresponding to the logical address interval. This way of determining the popularity value can enable the determined popularity value to indicate that the data has been accessed within the most recent period of time at the current time. Specifically, the larger the popularity value is, it indicates that the data has been accessed more frequently recently, and the smaller the popularity value is, it indicates that the data has been accessed less frequently.

Optionally, if the popularity value is greater than the popularity threshold, then retaining the data of the logical address corresponding to the first popularity record sequence before the volatile cache, and also includes: if the current time reaches the popularity threshold update time point, from the heat record table Randomly select m heat record sequences, m is a positive integer greater than or equal to 1, and the heat threshold update time point is configured when the system is initialized; according to the heat value and volatility of each heat record sequence in the m heat record sequences The expected storage data ratio in the cache determines the popularity threshold. The expected storage data ratio refers to the ratio between the size of the data expected to be stored in the volatile cache and the size of the data expected to be stored in the hybrid cache.

In order to make the hotness threshold reflect the current data access situation in the hybrid cache, the processor can dynamically adjust the hotness threshold periodically, so that the hot data will be eliminated according to the adjusted hotness threshold, so that the volatile cache after the hot data is eliminated The visit hit rate is high.

The method further includes: determining an access hit rate of the volatile cache, where the access hit rate is used to indicate the proportion of the accessed data as data in the volatile cache; and determining m according to the access hit rate of the volatile cache. Among them, the number of randomly selected heat record sequences is also determined according to the current data access situation in the hybrid cache, so that the hot data will be eliminated according to the adjusted heat threshold, so that the volatile cache after the hot data is eliminated The visit hit rate is high.

Optionally, after determining the access hit rate of the volatile cache, the method further includes: determining the hotness threshold update time point according to the access hit rate of the volatile cache. In addition, the period of periodically dynamically adjusting the hotness threshold can also be determined according to the current data access situation in the hybrid cache, so that the hot data will be eliminated according to the adjusted hotness threshold, so that the access hits of the volatile cache after the hot data is eliminated The rate is higher.

In a second aspect, a device for accessing a hybrid cache in an electronic device is provided, and the device has the function of implementing the behavior of the method for accessing the hybrid cache in an electronic device in the first aspect. The device includes at least one module, and the at least one module is used to implement the method for accessing a hybrid cache in an electronic device provided in the first aspect.

In a third aspect, an apparatus for accessing a hybrid cache in an electronic device is provided. The structure of the device includes a processor and a memory, and the memory is used to store and support the device to execute the hybrid cache in the access electronic device provided in the first aspect. The program of the caching method, and storing the data involved in the method for accessing the hybrid cache in the electronic device provided in the first aspect. The processor is configured to execute the program stored in the memory. The operating device of the storage device may further include a communication bus, and the communication bus is used to establish a connection between the processor and the memory.

In a fourth aspect, a computer-readable storage medium is provided, and instructions are stored in the computer-readable storage medium. When the instructions are run on a computer, the computer executes the method for accessing a hybrid cache in an electronic device in the first aspect. .

In a fifth aspect, a computer program product containing instructions is provided, which when the computer program product runs on a computer, causes the computer to execute the method for accessing data in the hybrid cache as described in the first aspect.

The technical effects obtained by the above-mentioned second, third, fourth and fifth aspects are similar to those obtained by the corresponding technical means in the first aspect, and will not be repeated here.

Description of the drawings

FIG. 1 is a schematic structural diagram of an electronic device provided by an embodiment of the present application;

Fig. 2 is a schematic diagram of a process for a processor to access data according to an embodiment of the present application;

FIG. 3 is a flowchart of a method for accessing a hybrid cache in an electronic device according to an embodiment of the present application;

FIG. 4 is a schematic diagram of an index table provided by an embodiment of the present application;

FIG. 5 is a flowchart of a method for recording heat provided by an embodiment of the present application;

Fig. 6 is a schematic diagram of a heat record table provided by an embodiment of the present application;

FIG. 7 is a flowchart of a heat attenuation method provided by an embodiment of the present application;

FIG. 8 is a flowchart of a hot data elimination method provided by an embodiment of the present application;

FIG. 9 is a schematic diagram of an apparatus for accessing a hybrid cache in an electronic device according to an embodiment of the present application;

FIG. 10 is a schematic diagram of another apparatus for accessing a hybrid cache in an electronic device according to an embodiment of the present application;

FIG. 11 is a schematic diagram of another apparatus for accessing a hybrid cache in an electronic device according to an embodiment of the present application;

FIG. 12 is a schematic diagram of another apparatus for accessing a hybrid cache in an electronic device according to an embodiment of the present application.

Detailed ways

In order to make the objectives, technical solutions, and advantages of the present application clearer, the following will further describe the embodiments of the present application in detail with reference to the accompanying drawings.

FIG. 1 is a schematic structural diagram of an electronic device provided by an embodiment of the present application. As shown in FIG. 1, the electronic device includes at least one processor 101, a bus 102, a hybrid cache 104, an external memory 105, and at least one communication interface 106.

The processor 101 may be a general-purpose central processing unit (CPU) or one or more integrated circuits for controlling the execution of the program of the present application. Each processor can be a single-CPU (single-CPU) processor or a multi-core (multi-CPU) processor. The processor here may refer to one or more devices, circuits, and/or processing cores for processing data (for example, computer program instructions).

The bus 102 is used to connect the processor 101, the memory 103, the hybrid cache 104 and the external memory 105 to transfer information. In addition to the data bus, the bus 102 may also include a power bus and a control bus. However, for clear description, various buses are marked as the bus 102 in the figure.

As the memory of the electronic device, the hybrid cache 104 includes a volatile cache 103 and a non-volatile cache 107, and the volatile cache 103 can be divided into two areas. These two areas are called write data cache 1031 and Read data buffer 1032. The write data cache 1031 is used to provide a cache for the processor 101 to perform write data operations. The data in the write data buffer 1031 is flushed down to the external memory 105 according to a certain algorithm. The embodiment of the present application does not limit the specific implementation manner of downloading the data in the write data cache 1031 to the external memory 105.

The read data cache 1032 and the non-volatile cache 107 are used to provide two levels of cache for the processor 101 to perform read data operations.

The aforementioned volatile cache 103 may be random access memory (RAM), DRAM, or the like. The non-volatile cache 107 may be a new type of non-volatile storage device such as PCM, ferroelectric memory, or magnetic memory.

In addition, the external memory 105 can be a read-only memory (read-only memory, ROM) or other types of static storage devices that can store static information and instructions, or it can be an electrically erasable programmable read-only memory (electrically erasable programmable read-only memory). only memory, EEPROM), compact disc (read-only Memory, CD-ROM) or other optical disc storage, optical disc storage (including compact discs, laser discs, optical discs, digital universal discs, Blu-ray discs, etc.), magnetic disk storage media Or other magnetic storage devices, or any other medium that can be used to carry or store desired program codes in the form of instructions or data structures and that can be accessed by a computer, but is not limited thereto.

In addition, the read data cache 1031 is also used to store program codes for executing the solution of the present application, and the processor 101 controls the execution. One or more software modules can be included in the program code.

The communication interface 106 uses any device such as a transceiver to communicate with other devices or communication networks, such as Ethernet, wireless access network (RAN), wireless local area networks (WLAN), etc.

The aforementioned computer equipment may be a general-purpose computer equipment or a special-purpose computer equipment. In a specific implementation, the computer device may be a desktop computer, a portable computer, a network server, a PDA (Personal Digital Assistant, PDA), a mobile phone, a tablet computer, a wireless terminal device, a communication device, or an embedded device. The embodiments of this application do not limit the type of computer equipment.

Based on the above shown in FIG. 1, the computer device includes three types of storage media with different functions: a write data cache 1031, a read data cache 1032, a nonvolatile cache 107, and an external memory 105. When the processor accesses data, it can access these three types of storage media in a certain order. Fig. 2 is a schematic diagram of a process for a processor to access data according to an embodiment of the present application. As shown in Figure 2, when the processor accesses data, it first accesses the data from the write data cache 1031. If the data does not exist in the write data cache 1031, the data is accessed from the read data cache 1032 and the nonvolatile cache 107. If the data does not exist in the read data buffer 1032 and the nonvolatile buffer 107, the data is accessed from the external storage 105.

The read data cache 1032 in FIG. 2 is used to store the index table and hot data of the two-level cache of the read data cache 1032 and the non-volatile cache 107. The index table includes the index of the data stored in the read data cache 1032 and the index of the data stored in the non-volatile cache 107.

The non-volatile cache 107 is used to store the warm data eliminated from the read data cache 1032. The embodiment of the present application provides a data popularity recognition algorithm and a data elimination algorithm. The data popularity recognition algorithm is used to identify the popularity of data stored in the read data cache 1032. The data elimination algorithm is used to eliminate the data in the read data cache 1032 to the non-volatile cache 107 according to the heat of the identified data. Subsequent embodiments will explain this in detail and will not be described here.

In addition, as shown in FIG. 2, the non-volatile cache 107 can also eliminate the stored data according to a certain strategy, and store the eliminated cold data in the external storage 105. Regarding the explanation of eliminating the data in the non-volatile cache 107 to the external memory 105, reference may be made to the related technology of the existing cache elimination, which is not described in detail in the embodiment of this application.

In the embodiment of the present application, the data is divided into hot data, warm data, and cold data according to the frequency of access. The access frequency is greater than or equal to the first preset value is hot data, the access frequency is less than the first preset value and greater than the second preset value is warm data, and the access frequency is less than or equal to the second preset value is cold data.

Next, the method for accessing the hybrid cache in the electronic device provided by the embodiment of the present application will be explained. It should be noted that the hybrid cache accessed in the embodiment of the present application specifically refers to the two-level cache of the read data cache 1032 and the non-volatile cache 107 in FIG. 1 and FIG. 2. Among them, the accessed hybrid cache is volatile The sexual cache specifically refers to the read data cache 1032 in FIG. 1 and FIG. 2, and will not be explained one by one in the following.

FIG. 3 is a flowchart of a method for accessing a hybrid cache in an electronic device according to an embodiment of the present application. Used in the processor of the electronic device shown in FIG. 1. As shown in Figure 3, the method includes the following steps:

Step 301: Receive a read instruction for the data to be accessed, where the read instruction carries the logical address of the data to be accessed.

Based on the process of processing access data shown in FIG. 2, it can be known that when the processor receives a read instruction, it first determines whether the data to be accessed is stored in the write data cache. If the data to be accessed is stored in the write data cache, the data to be accessed is directly read. If the data to be accessed does not exist in the write data cache, it is determined whether the data to be accessed is stored in the two-level hybrid cache of the read data cache and the nonvolatile cache. The method for accessing the hybrid cache in the electronic device provided by the embodiment of the present application can be applied in this scenario.

For hybrid cache, if DRAM and PCM set their own index tables, the index table of each cache in the hybrid cache is used to indicate the mapping relationship between the logical address and physical address of the data stored in the cache, then the data is read At this time, the index table of DRAM needs to be searched first. When the read data is not in the index table of DRAM, the index table of PCM needs to be searched.

In this way, if the read data is not in the DRAM, a process of looking up the PCM index table needs to be performed, which will increase the delay of data reading. Therefore, in the embodiment of the present application, an index table can be uniformly set for the hybrid cache. The index table records the logical address of the data stored in the hybrid cache and indicates whether the data corresponding to each logical address is stored in DRAM or In PCM, when reading data in the hybrid cache, no matter whether the data is stored in the DRAM or PCM of the hybrid cache, it only needs to look up the index table once to determine which cache the data is stored in, thereby improving access The efficiency of mixing data in the cache.

For the convenience of subsequent description, the index table provided in the embodiment of the present application is explained here first.

Fig. 4 is a schematic diagram of an index table provided by an embodiment of the present application. The index table records the logical address of the data stored in the hybrid cache, the physical address corresponding to each logical address, and the status information of the data corresponding to each logical address. The status information is used to indicate that the data corresponding to the logical address is stored in In DRAM, it is still stored in PCM. As shown in FIG. 4, the index table may include a primary index table 401 (entry table) and multiple secondary index tables 402 (node tables). For ease of description, the indexes in the primary index table are called primary indexes, and the indexes in the secondary index table are called secondary indexes.

The first-level index may be 2^p bit value combinations obtained by combining bit values on p bits in the logical address. p is a positive integer. The p bits may be the first p bits in the order from high to low.

Since the bit values on p bits can be combined to obtain 2^p different bit value combinations, the index table in FIG. 4 is used to record the logical address of the data in the mixed buffer, the physical address corresponding to the logical address, and The status information of the data corresponding to each logical address. Although not all data in the logical addresses are stored in the hybrid cache, in order to avoid subsequent changes in the data in the hybrid cache, a certain item of information needs to be frequently added or deleted in the first-level index table. Therefore, as shown in FIG. 4, the primary index table may include 2^p items of information. Each item of information includes a primary index and the query result corresponding to the primary index. The query result corresponding to each primary index in the primary index table includes a secondary index table pointer and a state information set. That is, each bit value combination corresponds to a secondary index table pointer and a state information set. In this way, when the data in the hybrid cache changes subsequently, only the query results corresponding to each primary index need to be updated, without changing the structure of the entire primary index table.

For any primary index in the primary index table, the state information set in the query result corresponding to the primary index includes the state of the data indicated by the logical address determined in the secondary index indicated by the pointer of the secondary index table information. Since not all the data in the logical address are stored in the hybrid cache, for the state information set corresponding to the first-level index, the state information set only includes the first p bits of the logical address in the hybrid cache and the first-level index State information of data with the same bit value in the corresponding bit value combination. For example, if the number of data with the same bit value in the first p bits of the logical address in the mixed buffer and the bit value combination corresponding to the level 1 index is 1, then the number of state information in the state information set Is one. If the number of data with the same bit value in the first p bits of the logical address in the mixed buffer and the bit value combination corresponding to the level 1 index is more than one, then the number of state information in the state information set is more One. If there is no data with the same bit value in the bit value combination corresponding to the first p bits of the logical address in the mixed buffer, the number of state information in the state information set is zero.

For any primary index in the primary index table, the secondary index table pointer in the query result corresponding to the primary index is used to indicate a secondary index table among multiple secondary index tables, that is, Each item of information in the primary index table in FIG. 4 corresponds to a secondary index table. The secondary index table is used to record the logical address and the physical address corresponding to each logical address. The recorded logical address is the data logical address in the hybrid cache whose logical address meets the corresponding primary index. The logical address meets the corresponding primary index means : The bit value on the p bits before the logical address is the same as the bit value in the combination of the p bits indicated by the corresponding first-level index. That is, the stored logical address in the secondary index table is the data logical address stored in the hybrid cache, and the first p bits of the stored logical address are the same as the secondary index table pointer in the primary index table The bit values in the corresponding bit value combinations are the same. Wherein, the implementation manner of recording the logical address in the secondary index table may be: recording the value of bits other than p bits in the logical address, or recording the bit values of the logical address on all bits.

For example, the logical address includes 32 bits, and the upper 10 bits in the logical address can be used as the first-level index of the first-level index table. At this time, the first-level index table shown in FIG. 4 includes 2^10 items of information. Each item of information corresponds to a secondary index table. It is assumed that the first-level index included in the first item of information in the first-level index table is 00000000, that is, the bit values of the upper 10 bits are all 0. At this time, the state information set in the query result corresponding to the primary index of 0000000000 includes the state information of all data whose bit values on the upper 10 bits of the logical address in the hybrid cache are all 0. The secondary index table indicated by the secondary index table pointer in the query result corresponding to the primary index of 0000000000 is used to record the logical addresses and logical addresses of all data whose bit values on the upper 10 bits of the logical address in the hybrid cache are all 0. The physical address corresponding to each logical address. Among them, for the secondary index table, since the secondary index table is the secondary index table corresponding to the primary index of 00000000, it indicates that the bit value of the first p bits of the logical address recorded in the secondary index table is 0000000000. Therefore, the logical address of each data in the hybrid buffer recorded in the secondary index table may only record the bit value of the logical address on the remaining 22 bits. Of course, the logical address of each data in the hybrid buffer recorded in the secondary index table may also record the bit value of the logical address in all 32 bits, which is not specifically limited.

For another example, for any one level index, it is assumed that the state information set in the query result corresponding to the level one index is the state information of each data in the 100 data of data 1, data 2, data 3 to data 100. Then, the secondary index table indicated by the secondary index table pointer in the query result corresponding to the primary index is used to store the logical address of each data in the 100 data.

In addition, the sorting of the logical addresses of the multiple data stored in the secondary index table corresponds to the sorting of the status information of the multiple data in the status information set. For example, the order of the status information of each data in the status information set may be consistent with the order of the logical addresses of the data in the secondary index table. The consistent sorting means that in the sorting result of the state information and the sorting result of the logical address, the state information and the logical address at the same position correspond to the same data. For example, the state information of the above 100 data is sorted according to the state information of data 1, the state information of data 2, the state information of data 3,..., the state information of data 100. The logical addresses of the 100 data in the secondary index table are also arranged in this way: the logical address of data 1, the logical address of data 2, the logical address of data 3,..., the logical address of data 100. In this way, it can be ensured that in the sorting result of the state information and the sorting result of the logical address, the state information and the logical address at the same position correspond to the same data.

Among them, the sorting of each state information in the state information set and the sorting of each logical address in the secondary index table are correspondingly set, so that the position of the logical address of a certain data in the secondary index table can be directly obtained from the state information. The status information of the corresponding location in the collection is used as the status information of this data, thereby improving the efficiency of acquiring status information.

In addition, in order to facilitate the management of the addresses in the secondary index table, the secondary indexes in the secondary index table may be bit values on q bits in the logical address. The q bits may be other bits in the logical address except the p bits of the first level index. For example, the first q bits in the logical address can be sorted from low to high. At this time, since the bit values on the q bits can be combined to obtain 2^q different combined bit values, the same reason as the first-level index table, in order to avoid subsequent changes in the data in the mixed buffer, resulting in the second-level index The items in the table need to be deleted or added continuously. Therefore, for any one level index in the level level index table, the secondary index table indicated by the secondary index table pointer corresponding to the level level index includes 2^q Item information, each item of information includes a secondary index and the query result corresponding to the secondary index. For any secondary index in the secondary index table, the query result corresponding to the secondary index is a logical address set, each logical address in the logical address set corresponds to a physical address, and the logical address included in the logical address set It is the logical address of the data in the hybrid cache that satisfies both the corresponding primary index and the corresponding secondary index. That is, the logical address included in the logical address set not only has the same bit value on the q bits as the bit value indicated by the secondary index, but also the bits on the p bits and the bit value indicated by the secondary index. The bit values indicated by the corresponding primary indexes are the same. In addition, because not all the data in the logical addresses are stored in the hybrid cache, the number of logical addresses in the logical address set can be any integer, and the logical address set corresponding to each secondary index in the secondary index table Can be different.

For example, the bits in the lower 10 bits of the logical address can be used as the secondary index of the secondary index table. At this time, suppose that the primary index included in the first item of the primary index table is 0000000000, and the primary index is The corresponding secondary index table includes 2^10 items of information, and each item of information includes a secondary index and a query result corresponding to the secondary index. Assume that the secondary index included in the first item of information in the secondary index table is 00000000. At this time, the logical address set indicated by the query result corresponding to the secondary index includes the logical address and each logical address of the data in the hybrid cache that simultaneously satisfy the data whose bit values on the lower 10 bits and upper 10 bits are 0. The corresponding physical address.

That is, in the index table shown in FIG. 4, the primary index table includes 2^p items of information, and each item of information corresponds to a secondary index table, and the secondary index table includes 2^q items of information. Each piece of information includes a logical address set. Assume that each logical address set includes k logical addresses and k physical addresses corresponding to the k logical addresses one-to-one. Therefore, for the secondary index table indicated by any item of information in the primary index table, the secondary index table includes (2^q)×k logical addresses and the physical address corresponding to each logical address. In addition, the state information set in one item of information in the primary index table corresponding to the secondary index table includes (2^q)×k state information. Where k is a positive integer, the above k is only an example of the number of logical addresses included in the logical address set, and does not constitute a limitation on the number of logical addresses included in the logical address set

When the system is initialized, the index table shown in FIG. 4 may be configured first. At this time, the state information set of the primary index table in the index table and the logical address set of the secondary index table may be null at this time. When data is added or deleted later in the hybrid cache, only the state information set in the index table and the specific elements in the logical address set need to be updated, and there is no need to change the structure of the index table.

As shown in Figure 4, the index table is directly mapped according to the logical address of the data, the physical address corresponding to the logical address, and the state information collection. There is no need to construct the index table through complex hash calculations, which improves the efficiency of building the index table. . In addition, since both the primary index table and the secondary index table in the index table use some bits in the logical address as indexes, the storage positions of adjacent logical addresses in the index table can be made adjacent. Hot data usually has spatial locality, that is, data in a logical address interval is usually hot data. Therefore, the index table provided in the embodiment of the present application can also make full use of the spatial locality of hot data to facilitate subsequent basis The index table processes the hot data in batches, further improving the flexibility of processing hot data.

In addition, in the embodiment of the present application, the index table may be configured as the primary index table and the secondary index table shown in FIG. 4. In other implementations, you can also configure more levels of index tables for the index table. For example, you can configure a primary index table, a secondary index table, and a tertiary index table in the index table. The configuration method is the same as that shown in Figure 4 above. The configuration method is basically the same. Alternatively, only the first-level index table can be set, which will not be explained here.

In addition, in the primary index table shown in FIG. 4, each status information may use 1 bit to indicate whether the corresponding data is stored in a volatile cache or a nonvolatile cache. For example, when the value of this bit is 1, it indicates that the corresponding data is stored in the volatile buffer. When the value of this bit is 0, it indicates that the corresponding data is stored in the non-volatile buffer.

In the index table shown in Figure 4, the status information is configured in the primary index table. For specific applications, the status information can also be configured in the secondary index table. At this time, in the index table shown in FIG. 4, the primary index table includes 2^p items of information, and each item of information includes a primary index and a query result corresponding to the primary index, and the query result corresponding to the primary index includes A pointer to the secondary index table. The pointer of the secondary index table corresponding to each primary index corresponds to a secondary index table. The secondary index table includes 2^q items of information. Each item of information includes a logical address set, and each logical address set includes logical Address, physical address corresponding to each logical address, and status information of data corresponding to each logical address.

That is, in the embodiment of the present application, the status information of the data corresponding to each logical address stored in the index table can be set in the primary index table as shown in FIG. 4, and of course, can also be set in the secondary index table. There is no specific limitation here.

In addition, in order to further improve the efficiency of searching data in the index table, the index table shown in FIG. 4 may be stored in a key-value manner. Storing an index table in a key-value manner means that for a primary index table or a secondary index table, the indexes in the table are used as keys, and the query results corresponding to each index are stored as values. Because the data of the key-value structure can be directly located in the index table when querying, the corresponding data can be found without traversing the entire index table. Therefore, storing the index table by key value can improve the efficiency of subsequent data search .

Step 302: Look up the logical address in the index table.

Based on the index table shown in FIG. 4, the implementation of step 302 can be: look up the bit value combination corresponding to the first p bits of the logical address of the data to be accessed in the primary index; according to the bit value combination corresponding to the secondary The index table pointer obtains a secondary index table from multiple secondary index tables; searches the logical address of the data to be accessed in the secondary index table.

Specifically, the bit value on p bits in the logical address of the data to be accessed can be determined, the bit value on p bits in the logical address of the data to be accessed is used as the first-level index, and the first-level index table is looked up. The query result corresponding to the primary index. The query result includes a pointer to a secondary index table. According to the secondary index table pointer, a secondary index table is obtained from the multiple secondary index tables shown in FIG. 4. Determine the bit value of q bits in the logical address of the data to be accessed, and use the bit value of the q bits in the logical address of the data to be accessed as the secondary index. The query result corresponding to the secondary index is searched from the secondary index table obtained above, and the query result is a logical address set. Then the logical address set is traversed, and if the logical address of the data to be accessed is traversed in the logical address set, it is determined that the logical address of the data to be accessed is stored in the index table.

Step 303: When the logical address of the data to be accessed is found in the index table, the status information of the data to be accessed is obtained from the index table.

Based on step 302, it can be known that the primary index table or secondary index table of the index table also includes stored state information of data corresponding to each logical address. Therefore, when the logical address of the data to be accessed is found in the secondary index table through step 302, the status information of the data to be accessed can be determined from the status information of each data included in the index table.

In a possible implementation, if it is an index table, the primary index table also includes stored status information of the data corresponding to each logical address, as shown in Figure 4, the query result corresponding to each primary index also includes A state information set, the state information set is used to store the state information of the data whose logical address meets the corresponding primary index, and the secondary index table stores the logical address sequence arrangement. At this time, the method for determining the status information of the data to be accessed from the status information of the data included in the index table may be: according to the sorting of the logical address of the data to be accessed in the acquired secondary index table, corresponding from the primary index The status information of the data to be accessed is determined from the status information set included in the query result.

For example, the order of the status information of each data in the status information set in the primary index table may be consistent with the order of the logical addresses of each data in the secondary index table. The explanation of ordering consistency has been explained in the index table shown in Figure 4 above. At this time, if the secondary index table found according to the primary index includes 50 items of information, the query result corresponding to the secondary index included in each item of information in the secondary index table is a logical address set, and each logical address The set includes 8 logical addresses, which are arranged in order. Suppose that the secondary index determined according to the logical address of the data to be accessed is the secondary index included in the 26th item of the 50 items of information, and the logical address of the data to be accessed is in the logical address set corresponding to the secondary index If the order is the fourth, the 204th (that is, (26-1)*8+4) state information in the state information set can be used as the state information of the data to be accessed.

Of course, the sorting of each state information in the state information set in the first-level index table can also be exactly the opposite of the logical address sorting in the values corresponding to the keys in the second-level index table. In this case, the sorting can also be done accordingly. Obtain the status information of the data to be accessed from the status information collection, which will not be elaborated here.

In another possible implementation manner, if it is an index table, the secondary index table also includes stored state information of data corresponding to each logical address. That is, the secondary index table is also used to store the status information of the data corresponding to each logical address. At this time, an implementation manner of determining the state information of the data to be accessed from the state information of each data included in the index table may be: determining the state information of the data to be accessed in the obtained secondary index table.

In addition, based on the content shown in FIG. 4, the physical address corresponding to each logical address is also stored in the secondary index table. Therefore, when the logical address of the data to be accessed is found in the secondary index table through step 302 , You can directly obtain the physical address of the data to be accessed.

Step 304: Read the data to be accessed from the non-volatile cache or the volatile cache according to the state information of the data to be accessed.

Based on step 303, it can be known that when the status information of the data to be accessed is obtained from the index table, the physical address of the data to be accessed is also obtained. Therefore, the implementation of step 304 may be: reading the data to be accessed from the non-volatile cache or the volatile cache according to the state information of the data to be accessed and the physical address of the data to be accessed.

Specifically, after determining the status information of the data to be accessed according to step 303, if the storage location indicated by the status information of the data to be accessed is a volatile cache, access from the volatile cache according to the physical address of the data to be accessed Data to be accessed. If the storage location indicated by the status information of the data to be accessed is a non-volatile cache, the data to be accessed is accessed from the non-volatile cache according to the physical address of the data to be accessed. In addition, after the data to be accessed is accessed through the non-volatile cache, the data to be accessed is copied from the non-volatile cache to the volatile cache, so as to facilitate subsequent direct access to the data to be accessed through the volatile cache.

Step 305: When the logical address of the data to be accessed is not found in the index table, read the data to be accessed from the external memory.

In the process of traversing the logical address set in step 302, since the index table is an index table configured for the hybrid cache, if the data to be accessed is stored in the hybrid cache, the logical address set can be traversed to the index table to be accessed. The logical address of the data. Correspondingly, if the data to be accessed is not stored in the hybrid cache, the logical address of the data to be accessed cannot be traversed in the logical address set. In this case, the processor determines that the data to be accessed is stored in the external memory, and can then read the data to be accessed from the external memory. After the data to be accessed is accessed through the external memory, the data to be accessed is copied from the external memory to the volatile cache, so that the data to be accessed can be accessed directly through the volatile cache in the future.

The hybrid cache provided by the embodiments of the present application includes two different types of cache media, and the volatile cache is used to store hot data, and the non-volatile cache is used to store warm data eliminated from the hot data. Based on this scenario, a heat record needs to be configured for the data in the volatile cache of the hybrid cache, so as to determine which data in the volatile cache needs to be eliminated as warm data based on the heat record. Among them, the heat record is also the data access frequency record.

Therefore, the embodiment of the present application also provides a heat record table. As shown in FIG. 6, the heat record table includes a plurality of heat record sequences, and each heat record sequence uses a CNT mark. Each heat record sequence corresponds to a logical address interval (not shown). The logical address interval can include one logical address or multiple adjacent logical addresses. The logical addresses in the logical address interval are in the volatile cache. The logical address of the stored hot data. Since the data in the volatile cache changes dynamically, in the embodiment of the present application, if new or deleted data in the volatile cache is detected, the logical address of the added or deleted data is determined, and In the heat record table shown in Figure 6, the heat record sequence corresponding to the logical address of the added or deleted data is updated to ensure that the heat record table is used to indicate the current time of all data stored in the volatile cache Visit heat. For the convenience of description, FIG. 6 only shows the thermal recording sequence, and does not show the logical address space corresponding to each thermal recording sequence.

As shown in Figure 6, each heat record sequence includes a plurality of bits, and each time the data of the logical address in the logical address interval corresponding to the heat record sequence is accessed, the bit of one bit above the plurality of bits is updated Value to realize that the thermal record sequence can indicate the access status of the data in the logical address interval corresponding to the logical address in the most recent period of time. The detailed update method will be described in the following embodiments, and will not be elaborated here.

Therefore, in step 303, after accessing the data to be accessed, the heat record table needs to be updated through the following steps. FIG. 5 is a flowchart of a thermal recording method provided by an embodiment of the present application, which is applied to the processor of the electronic device shown in FIG. 1. As shown in Figure 5, the method includes the following steps:

Step 501: According to the logical address of the data to be accessed, a heat record sequence corresponding to the logical address of the data to be accessed is obtained from the heat record table.

Since each heat record sequence in the heat record table corresponds to a logical address interval, the heat record sequence corresponding to the logical address of the data to be accessed can be directly obtained from the heat record table according to the logical address of the data to be accessed.

Step 502: Update the heat recorded in the acquired heat record sequence.

In the embodiment of the present application, an update period can be configured for each bit. In this way, in a certain update period, only the bits corresponding to the update period need to be updated, so that the access heat of the data in the recent period can be quickly determined according to the bits corresponding to each update period.

At this time, the implementation of step 502 may be: obtaining the update period corresponding to the current time, and updating the bit corresponding to the update period corresponding to the current time to an identifier indicating that the data corresponding to the logical address corresponding to the heat record sequence has been accessed. The identifier indicating that the data corresponding to the logical address corresponding to the thermal record sequence has been accessed may be the first bit value. For example, the value of the first bit may be 1, which is used to indicate that the data to be accessed is currently accessed.

In the embodiment of the present application, in order to indicate the access status of the data corresponding to the logical address in the corresponding logical address interval in the recent period of time through the heat record sequence, a clock and pointer may be configured for the heat record table. After the computer device is initialized, the clock periodically counts according to the set duration. The multiple bits included in this heat record sequence are periodically arranged in a specified order, and the pointer points to one of the multiple bits during initialization. Bit. Each time the timing of the clock reaches one cycle, the pointer points to the next bit according to the order of multiple bits. At this time, the bit corresponding to the update period corresponding to the current time in step 502 is the bit pointed to by the pointer at the current time. Wherein, the bit corresponding to the update period corresponding to the current time may also be referred to as the bit to be updated at the current time. Through this configuration, the bit value of the bit that is located before the bit to be updated at the current time in the sorting, and the bit closer to the bit to be updated at the current time is used to indicate the time closer to the current time When the data in the segment is accessed, the bit value on the bit farther from the bit to be updated at the current time is used to indicate the data access in the time segment farther from the current time.

As shown in FIG. 6, each heat recording sequence is marked as CNT, and each CNT includes 8 bits. These 8 bits are marked as bit A, bit B, bit C, bit D, bit E, bit F, bit G, and bit H, respectively. Assuming that the configured clock has a timing duration of 1 hour, these 8 bits are in accordance with A, B, C, D, E, F, G, H, A, B, C, D, E, F, G, H,... The sequence of A, B, C, D, E, F, G, and H is arranged periodically. When the system is initialized, the pointer points to bit A. When the timing of the clock reaches 1 hour, the pointer switches from bit A to bit B, and the clock restarts timing. When the timing of the clock reaches 1 hour again, the pointer switches from bit B to bit C, and the clock restarts timing. By analogy, suppose that when the timing of a clock reaches 1 hour, the pointer switches from bit G to bit H, and the clock restarts timing. Then next time the timing of the clock reaches 1 hour, the pointer switches from bit H to bit A, and the clock restarts timing. The clock and hands repeat the above process.

As shown in Figure 6, the bit pointed to by the current time of the pointer is bit A, then it is determined that bit A is the bit corresponding to the update period corresponding to the current time, and the bit value on bit A is updated to 1 to indicate The data to be accessed has been accessed at the current time.

In addition, for the thermal recording sequence in Figure 6, in order to facilitate recording the distance between the update time of the bit value on each bit and the current time, the same time weight as the number of multiple bits is pre-configured, and the time weight can be Indicates the distance to the current time, where the greater the time weight, the closer to the current time, and the smaller the time weight, the farther away from the current time. Each time the pointer switches to point to a bit, it is determined that multiple bits are arranged in a closed ring based on the specified order, and the next bit is located next to the bit pointed to by the pointer, and the next bit is the starting point. The multiple bits are sorted, and multiple pre-configured time weights are allocated to the multiple bits after sorting, and the time weight of each bit after sorting is sequentially reduced. In this way, whenever the timing of the clock reaches and the pointer switches to the bit position, the time weight on each bit position is updated, so that the bit position pointed to by the pointer has the largest time weight at any time, and the pointer will point to the next time The time weight of the bit position is the smallest.

For example, 8 time weights are pre-configured, which are labeled L0, L1, L2, L3, H0, H1, H2, and H3. These 8 time weights increase sequentially. The 8 bits in Figure 6 are marked as A, B, C, D, E, F, G, and H respectively. And these 8 bits are arranged in a closed ring in the order of A, B, C, D, E, F, G, and H. If the current time pointer points to bit C, then each time weight is allocated to each bit according to the allocation method in Table 1 below.

Table 1

For another example, if the current time pointer points to bit D, then each time weight is allocated to each bit according to the allocation method in Table 2 below.

Table 2

For another example, as shown in FIG. 6, the current time pointer points to bit A, and each time weight is allocated to each bit according to the allocation method in Table 3 below.

table 3

In the heat recording sequence shown in Figure 6, the pointer points to one of the bits after the 8 bits are periodically arranged in the specified order. Therefore, during the time when the pointer points to a certain bit, the pointer on the bit The bit value may have been updated in the last cycle. At this time, the hot record sequence corresponding to the data will not be able to characterize the access situation of the data in the recent period of time. Therefore, in the embodiment of the present application, it is also necessary to perform heat attenuation on the heat record sequence in the heat record table.

Fig. 7 is a flowchart of a heat attenuation method provided by an embodiment of the present application, which is applied to the processor of the electronic device shown in Fig. 1. As shown in Figure 7, the method includes the following steps:

Step 701: Detect the heat attenuation command.

The processor can detect the heat decay command in the following two scenarios.

The first scenario: the computer equipment is configured with the update time point of the heat record table when the system is initialized. Therefore, when the current time reaches the point in time when the heat record table is updated, the computer device will automatically trigger the heat attenuation instruction. For example, when the computer equipment system is initialized, it can be configured to update the heat record table every 1 day. Assuming that the computer equipment system is initialized at 0:00, then the heat record table is updated at 0:00 every day.

The second scenario: When the proportion of the high heat recording sequence in all the heat recording sequences is greater than the reference ratio, at this time, the heat attenuation command can be triggered. The high heat recording sequence refers to a heat recording sequence in which the high order bits are all identifiers indicating that the data corresponding to the logical address corresponding to the heat recording sequence has been accessed. Among them, the high-order bits refer to the bits within the reference period of the update period before the current time among the multiple bits, that is, the high-order bits refer to the bits updated in the most recent period before the current time. Since each bit can be determined according to the time weight to update the bit value on the bit value of the time and the current time, therefore, the high bit can refer to the multiple bits of the heat record sequence with time weight from high to low n Bit position, n is a positive integer greater than or equal to 1.

Assuming that the time weight on each bit of the current time is as shown in Table 2, the high bit can be bit D, bit B, bit D, and so on. If the high-order bit is bit D, then the high-heat recording sequence is a thermal recording sequence with bit D being 1, and if the reference ratio is 90%, the proportion of the high-heat recording sequence in all thermal recording sequences is greater than 90% , The heat decay instruction is triggered.

The above two scenarios can be used alone or in combination, which is not specifically limited in the embodiment of the present application.

Step 702: Obtain the bit corresponding to the next update period after the update period corresponding to the current time among the multiple bits of each heat record sequence.

As shown in Table 2, as long as the bit pointed to by the current time pointer is determined, the time weight of each bit of multiple bits can be determined. At this time, the bit with the smallest time weight is the bit corresponding to the next update cycle. Bit. As shown in Figure 6, before the heat decays, the bit corresponding to the next update period is bit H.

Step 703: Update the bit corresponding to the next update cycle in each heat record sequence to an identifier indicating that the data corresponding to the logical address corresponding to the heat record sequence has not been accessed.

In step 702, the bit value on the time weight L0 in all the popularity record sequences can be updated to the second bit value. In this embodiment, the second bit value is zero. For the convenience of subsequent description, step 703 is referred to as a reset operation. As shown in Fig. 6, the bit value on the bit H in all the heat recording sequences can be reset to 0.

Step 704: Determine the bit position corresponding to the next update period in each heat record sequence as the bit position corresponding to the update period corresponding to the current time.

In step 703, the pointer can be directly pointed to the bit corresponding to the next update period to determine the bit corresponding to the next update period in each heat record sequence as the bit corresponding to the update period corresponding to the current time. Since the computer device reassigns the time weight to each bit every time the pointer switches to the bit, in step 703, the bit corresponding to the next update period in each heat record sequence is determined as After the bits corresponding to the update period corresponding to the current time, the time weight of each bit is equivalent to a sequential shift. For the convenience of subsequent description, step 704 is referred to as a weight transfer operation.

For example, suppose that before step 703 is performed, the time weight on each bit position is as shown in Table 1, then after step 703 is performed, the time weight on each bit position is updated to the situation shown in Table 2.

Table 4

For another example, as shown in FIG. 6, before the heat decay, the time weight on each bit position is as shown in Table 3 above, and after the heat decay, the time weight on each bit position is as shown in Table 4 below.

In addition, in this embodiment of the present application, the bits corresponding to the same time weight in different thermal recording sequences are stored in a continuous address space. As shown in FIG. 6, the bits of all the heat recording sequences corresponding to the time weight L0 are stored in a continuous address space, and the bits of all the heat recording sequences corresponding to the time weight L1 are stored in a continuous address space. Therefore, when the processor executes step 703, since the bits to be updated next time in all the heat record sequences are stored in a continuous address space, at this time, only the bits of the bits in the continuous address space are needed. The value can be reset to 0 uniformly. When the processor executes step 704, it is sufficient to re-allocate time weights for each segment of continuous address space, which is equivalent to only performing a reset operation and a weight transfer operation, and there is no need to perform the

above steps

703 and 703 for each heat record sequence. In step 704, the efficiency of performing heat attenuation is improved.

In addition, since it is necessary to eliminate the hot data in the volatile cache according to the heat record sequence in the heat record table, in the embodiment of the present application, the heat record sequence in the heat record table is only for the volatile cache. The hot data in the configuration. Since the data in the volatile cache changes dynamically, in the embodiment of the present application, if new data in the volatile cache is detected, the logical address of the newly added data is determined, and shown in FIG. 6 Reset the heat record sequence corresponding to the logical address of the new data in the heat record table of the new data. For example, reset the bit value of the bit pointed to by the current time of the pointer in all bits to 1, and the other bits The bit value is reset to 0. Or if volatile cache delete data is detected, the logical address of the newly added data is determined, and the heat record sequence corresponding to the logical address of the deleted data is reset in the heat record table shown in Figure 6, for example , Reset all bit values to 0. Through the above maintenance of the heat record table, each heat record sequence included in the heat record table is always maintained as a heat record sequence for the data in the volatile cache.

Through the embodiments shown in FIGS. 5 and 7, the data in the volatile cache of the hybrid cache can be used to record the recent access of the data through the heat recording sequence. Therefore, the present application can record the data according to the heat recording sequence Eliminate the volatile data to achieve the elimination of hot data into warm data.

FIG. 8 is a flowchart of a hot data elimination method provided by an embodiment of the present application, which is applied to the processor of the electronic device shown in FIG. 1. The hot data elimination method shown in FIG. 8 is also the hot spot identification elimination algorithm in FIG. 2. As shown in Figure 8, the method includes the following steps:

Step 801: Determine the popularity value of the data stored in the volatile cache according to the popularity record table.

In the embodiment of the present invention, the method for calculating the popularity value of the data stored in the volatile cache is: determining the logical address interval corresponding to each popularity record sequence according to the bit values on the multiple bits included in each popularity record sequence The popularity value of the corresponding data.

Based on the embodiments shown in Fig. 5 and Fig. 7, it can be known that at any time, according to the bit pointed to by the current time pointer, the time weight of each bit in the heat recording sequence can be determined. Therefore, the method of determining the popularity value of the data corresponding to the logical address interval corresponding to each thermal recording sequence may be: according to the time weight of the multiple bits included in each thermal recording sequence, the multiple thermal recording sequences include The bit values on each bit position are weighted and summed, and the obtained sum value can be used as the data popularity value corresponding to the logical address interval corresponding to each popularity record sequence. This way of determining the popularity value can enable the determined popularity value to indicate that the data has been accessed within the most recent period of time at the current time. Specifically, the larger the popularity value is, it indicates that the data has been accessed more frequently recently, and the smaller the popularity value is, it indicates that the data has been accessed less frequently.

For example, the time weight of each bit included in the heat recording sequence is the time weight shown in Table 2 above. At this time, for any thermal record sequence, the thermal value of the data corresponding to the logical address interval corresponding to the thermal record sequence can be: bit value on bit A×H0+bit value on bit B×H1+on bit C Bit value of bit × H2 + bit value on bit D × H3 + bit value on bit E × L0 + bit value on bit F × L1 + bit value on bit G × L2 + bit value on bit H × L3 .

In addition, in the embodiment of the present application, the hot data elimination method provided in the embodiment of FIG. 8 can be executed in the following two scenarios.

The first scenario is to detect that the remaining storage capacity of the volatile cache is lower than the threshold. In the first scenario, the processor can eliminate hot data in time based on the remaining storage capacity of the volatile cache, so as to avoid the situation that the volatile cache is too full.

The second scenario is the detection of the elimination of hot data instructions. The hot data elimination instruction can be triggered by the background manager. In the second scenario, the processor can eliminate the hot data according to the user's needs, which improves the flexibility of hot data elimination.

Step 802: If the popularity value of the data is less than the popularity threshold, then the data is eliminated to the non-volatile cache.

Correspondingly, if the popularity value of the data is greater than or equal to the popularity threshold, it is kept in the volatile cache. If the popularity value of the data is greater than or equal to the popularity threshold, it indicates that the data has been accessed more frequently in the most recent period of time. At this time, there is no need to eliminate the data in the non-volatile cache, that is, keep the data in Volatile cache.

If the popularity value of the data is less than the popularity threshold, it indicates that the data has been accessed less frequently in the recent period of time. At this time, in a possible implementation manner, the data can be directly eliminated into the non-volatile cache. In another possible implementation manner, the data can also be eliminated through the following steps 803 to 806, which improves the flexibility of eliminating hot data. That is, step 802 and step 803 to step 806 in FIG. 8 are two parallel implementations.

Step 803: If the popularity value of the data is less than the popularity threshold, determine the popularity value of the data corresponding to the logical address adjacent to the logical address of the data.

In the embodiment of the present application, in order to improve the occurrence of errors in the eliminated data due to accidental reasons, if the heat value of the data is less than the heat threshold, the data is not eagerly eliminated to the non-volatile cache, but combined with the logical address adjacent to it. The heat value of the data is used to comprehensively determine whether the data needs to be eliminated to the non-volatile cache, which improves the flexibility of eliminating hot data.

Therefore, if the popularity value of the data is less than the popularity threshold, the popularity value of the data corresponding to the logical address adjacent to the logical address of the data is determined to determine whether hot data elimination is required through the following steps 804 to 806. Wherein, to determine the popularity value of the data corresponding to the logical address adjacent to the logical address of the data, the popularity value of the data corresponding to the adjacent logical address can also be determined according to the data popularity record sequence corresponding to the adjacent logical address. No longer.

Step 804: Determine the average popularity value of the data and the data corresponding to the logical address adjacent to the logical address of the data.

Step 805: If the average popularity value is greater than or equal to the popularity threshold, keep the data in the volatile cache.

If the average heat value is greater than or equal to the heat threshold, it indicates that most of the data on the logical address adjacent to the logical address of the data is the data that has been frequently accessed recently. According to the spatial locality of the hot data, the data is very likely Will be frequently visited recently. At this time, if the data is directly eliminated to the non-volatile cache, it is easy to access the data immediately after elimination, resulting in unnecessary elimination. Therefore, in the embodiment of the present application, the data can continue to be kept in the volatile cache. It is equivalent to giving the data a second chance.

Step 806: If the average popularity value is less than the popularity threshold, the data is eliminated to the non-volatile cache.

If the average heat value is less than the heat threshold, it indicates that most of the data on the logical address adjacent to the logical address of the data has not been accessed frequently recently. At this time, the data can be eliminated into the non-volatile cache.

The heat threshold in the process of eliminating hot data can be configured by the background manager. At this time, after the heat threshold is configured, the data can be eliminated subsequently according to the fixed heat threshold. In addition, in order to enable the heat threshold to reflect the current data access situation in the hybrid cache, the processor may dynamically adjust the heat threshold periodically, so as to subsequently eliminate hot data according to the adjusted heat threshold.

In a possible implementation, the processor periodically dynamically adjusts the heat threshold value specifically as follows: if the current time reaches the heat threshold update time point, randomly select m heat record sequences from the heat record table, and m is greater than or equal to 1. A positive integer. According to the heat value of each heat record sequence in the m heat record sequences and the proportion of expected stored data in the volatile cache, the heat threshold is determined. The expected storage data ratio refers to the ratio between the size of the data expected to be stored in the volatile cache and the size of the data expected to be stored in the hybrid cache.

For example, when the storage capacity in the hybrid cache is 1 terabyte (TB), and the DRAM space used as the hot data cache is only 100 gigabytes (gigabyte, GB), the expected storage in the volatile cache If the data ratio is 10%, a heat threshold can be determined based on the heat value of each heat record sequence in the 10% and m heat record sequences, so that only those heat record sequences with a heat value greater than 90% of other heat values correspond to The data can be left in DRAM.

Among them, the number of randomly selected thermal record sequences is also determined according to the current data access situation in the hybrid cache. In a possible implementation manner, before adjusting the popularity threshold each time, the access hit rate of the volatile cache can be determined, and the access hit rate is used to indicate the proportion of the accessed data as the data in the volatile cache; The access hit rate of the lossless cache, determine m. For example, the higher the access hit rate of the volatile cache is, it indicates that the hotness threshold before adjustment is more accurate, and m can be smaller at this time. If the access hit rate of the volatile cache is low, it indicates that the heat threshold before the adjustment is not very accurate, and m can be larger at this time, so that the heat threshold after the adjustment can be accurate. Among them, the accuracy of the heat threshold means that after data is eliminated according to the heat threshold, the data accessed by the processor each time is basically in the volatile cache.

In addition, the period of regularly dynamically adjusting the popularity threshold can also be determined according to the current data access situation in the hybrid cache. In a possible implementation manner, the hotness threshold update time point can be determined according to the access hit rate of the volatile cache. For example, when the access hit rate of the volatile cache is high, it indicates that the heat threshold before adjustment is relatively accurate. At this time, the cycle of the heat threshold update time point is set longer, that is, it is not necessary to frequently update the heat threshold. When the access hit rate of the volatile cache is low, it indicates that the heat threshold before adjustment is not very accurate. At this time, the cycle of the heat threshold update time point is set shorter, that is, the heat threshold needs to be updated frequently to make the adjustment The heat threshold is more accurate.

Referring to FIG. 9, an embodiment of the present application provides an apparatus for accessing a hybrid cache in an electronic device. As shown in FIG. 9, the apparatus 900 includes:

The receiving module 901 is configured to perform step 301 in the embodiment of FIG. 3;

The search module 902 is configured to execute step 302 in the embodiment of FIG. 3;

The first obtaining module 903 is configured to perform step 303 in the embodiment of FIG. 3;

The reading module 904 is configured to execute step 304 in the embodiment of FIG. 3.

Optionally, each logical address in the index table corresponds to a physical address that stores data corresponding to each logical address;

The first obtaining module is also used to obtain the physical address of the data to be accessed when obtaining the status information of the data to be accessed from the index table; the reading module is specifically used to: according to the status information of the data to be accessed and the physical address of the data to be accessed The address reads the data to be accessed from the non-volatile cache or the volatile cache.

Optionally, the index table includes a primary index table and a plurality of secondary index tables, and the primary index in the primary index table is the value of the first p bits in the sorting from high to low in the logical address. The 2^p bit value combinations obtained by the combination, p is a positive integer, each bit value combination corresponds to a secondary index table pointer, the secondary index table pointer is used to indicate a secondary index table among multiple secondary index tables , The secondary index table is used to store the logical address and the physical address corresponding to each logical address. The stored logical address is the data logical address stored in the hybrid cache, and the first p bits of the stored logical address are the same as the first level The bit values in the bit value combinations corresponding to the pointers of the secondary index table in the index table are the same;

The search module is specifically used to: search for the bit value combination corresponding to the first p bits of the logical address of the data to be accessed in the primary index; according to the secondary index table pointer corresponding to the bit value combination, from multiple secondary index tables Obtain a secondary index table in the secondary index table; find the logical address of the data to be accessed in the secondary index table.

Optionally, the primary index table of the index table also includes stored state information of the data corresponding to each logical address, specifically: the query result corresponding to each primary index also includes a state information set, and the state information set is used for The storage logical address meets the status information of the data of the corresponding primary index, and the logical address is stored in the secondary index table in order; the first acquisition module is specifically used for: according to the logical address of the data to be accessed Sorting, determining the state information of the data to be accessed from the state information set included in the query result corresponding to the primary index.

Optionally, the secondary index table of the index table further includes the stored state information of the data corresponding to each logical address. Specifically: the secondary index table is also used to store the state information of the data corresponding to each logical address; the first acquisition module , Specifically used for: determining the status information of the data to be accessed in the obtained secondary index table.

Optionally, the secondary index in the secondary index table is the bit value of q bits in the logical address except p bits, q is a positive integer, and each secondary index in the secondary index table The query structure corresponding to the index includes a logical address set, each logical address in the logical address set corresponds to a physical address, and the logical address included in the logical address set is the logical address in the hybrid cache and satisfies the corresponding primary index and corresponding secondary The logical address of the indexed data.

Optionally, as shown in FIG. 10, the device 900 further includes:

The second obtaining module 905 is configured to execute step 501 in the embodiment of FIG. 5;

The first update module 906 is configured to execute step 502 in the embodiment of FIG. 5.

Optionally, each heat record sequence includes a plurality of bits, and each bit corresponds to an update period; the first update module is specifically configured to: obtain the update period corresponding to the current time, and associate the update period corresponding to the current time with The bit is updated to indicate that the data corresponding to the logical address corresponding to the heat record sequence has been accessed.

Optionally, as shown in FIG. 11, the device 900 further includes:

The detection module 907 is configured to execute step 701 in the embodiment of FIG. 7;

The third acquiring module 908 is configured to execute step 702 in the embodiment of FIG. 7;

The second update module 909 is configured to execute step 703 in the embodiment of FIG. 7;

The third update module 910 is configured to perform step 704 in the embodiment of FIG. 7.

Optionally, multiple bits are periodically arranged in a specified order;

The heat record table is equipped with a clock and a pointer. The clock periodically counts according to the set duration after the system is initialized. The pointer points to one of the multiple bits when the system is initialized, and each time the timing of the clock reaches the set duration When, the trigger pointer switches to the next bit position according to the sequence;

The bit corresponding to the update period corresponding to the current time is the bit pointed to by the current time pointer.

Optionally, the detection module 907 is specifically configured to:

When the current time reaches the update time point of the heat record table, the heat attenuation command is triggered, and the heat record table update time point is configured during system initialization; and/or,

When the proportion of the high heat record sequence in all the heat record sequences is greater than the reference ratio, the heat attenuation command is triggered. The high heat record sequence means that the bit value on the high bit is corresponding to the logical address corresponding to the heat record sequence The heat record sequence of the identifier whose data has been accessed, the high-order bit refers to the bit in the reference period of the update period before the current time among the multiple bits.

Optionally, as shown in FIG. 12, the device 900 further includes:

The first determining module 911 is configured to execute step 801 in the embodiment of FIG. 8;

The elimination module 912 is configured to perform step 802 in the embodiment of FIG. 8.

Optionally, the first determining module 911 is further configured to perform step 803 and step 804 in the embodiment of FIG. 8;

The device also includes a reservation module for executing step 805 in the embodiment of FIG. 8.

Optionally, the elimination module 912 is also used to perform step 806 in the embodiment of FIG. 8.

Optionally, the first determining module is also used for:

When it is detected that the remaining storage capacity of the volatile cache is lower than the idle capacity threshold, and/or when a hot data elimination instruction is detected, the process of determining the heat value of the data stored in the volatile cache according to the heat record table is executed step.

Optionally, each bit of the multiple bits is configured with a time weight, and the time weight of each bit is used to indicate how far the update time of the bit value on the corresponding bit is from the current time, among the multiple bits The time weight of the bit to be updated at the current time is the largest;

The first determining module is specifically used for:

Acquire the time weights of multiple bits included in each heat record sequence in the heat record table;

According to the time weight of the multiple bits included in each thermal record sequence, the bit values on the multiple bits included in each thermal record sequence are weighted and summed, and the obtained sum value is used as the corresponding to each thermal record sequence The popularity value of the data corresponding to the logical address interval.

Optionally, the device further includes:

The selection module is used to randomly select m heat record sequences from the heat record table if the current time reaches the heat threshold update time point, where m is a positive integer greater than or equal to 1, and the heat threshold update time point is configured during system initialization ；

The second determining module is used to determine the heat threshold value according to the heat value of each heat record sequence in the m heat record sequences and the expected stored data ratio in the volatile cache. The expected stored data ratio refers to the expected stored data in the volatile cache The ratio between the size of the data expected to be stored and the size of the data expected to be stored in the hybrid cache.

Optionally, the device further includes:

The third determining module is used to determine the access hit rate of the volatile cache, and the access hit rate is used to indicate the proportion of the accessed data as the data in the volatile cache;

The fourth determining module is used to determine m according to the access hit rate of the volatile cache.

Optionally, the device further includes:

The fifth determining module is used to determine the update time point of the popularity threshold according to the access hit rate of the volatile cache.

When the cache adopts a two-level hybrid cache, in the embodiment of the present application, an index table can be set for the hybrid cache. The index table records the logical address of the data stored in the hybrid cache and the physical address corresponding to the logical address, and indicates Whether the data corresponding to each logical address is stored in DRAM or PCM, when reading data in the hybrid cache, no matter if the data is stored in the DRAM or PCM of the hybrid cache, you only need to look up the index table once. This improves the efficiency of accessing data in the hybrid cache.

It should be noted that when the device for accessing data in the hybrid cache provided in the above embodiment accesses the data in the hybrid cache, only the division of the above-mentioned functional modules is used as an example for illustration. In actual applications, the above-mentioned functions can be changed according to needs. The allocation is completed by different functional modules, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. In addition, the device for accessing data in the hybrid cache provided by the foregoing embodiment and the embodiment of the method for accessing data in the hybrid cache belong to the same concept. For the specific implementation process, please refer to the method embodiment, which will not be repeated here.

In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented by software, it can be implemented in the form of a computer program product in whole or in part. The computer program product includes one or more computer instructions. When the computer instructions are loaded and executed on the computer, the processes or functions described in the embodiments of the present application are generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from a website, computer, server, or data center. Transmission to another website, computer, server, or data center via wired (for example: coaxial cable, optical fiber, Digital Subscriber Line (DSL)) or wireless (for example: infrared, wireless, microwave, etc.). The computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server or a data center integrated with one or more available media. The usable medium can be a magnetic medium (for example: floppy disk, hard disk, tape), optical medium (for example: Digital Versatile Disc (DVD)), or semiconductor medium (for example: Solid State Disk (SSD) )Wait.

Those of ordinary skill in the art can understand that all or part of the steps in the foregoing embodiments can be implemented by hardware, or by a program instructing relevant hardware to be completed. The program can be stored in a computer-readable storage medium. The storage medium mentioned can be a read-only memory, a magnetic disk or an optical disk, etc.

The above-mentioned examples provided for this application are not intended to limit this application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of this application shall be included in the protection scope of this application. Inside.

Claims

A method for accessing a hybrid cache in an electronic device, characterized in that the method is applied to an electronic device, the hybrid cache includes a volatile cache and a non-volatile cache, and the method includes:

Receiving a read instruction for the data to be accessed, where the read instruction carries the logical address of the data to be accessed;

The logical address is searched in an index table, and the state information corresponding to the logical address of the data stored in the hybrid cache is stored in the index table, and the state information is used to indicate whether the data stored in the hybrid cache is stored In the volatile cache or the non-volatile cache;

When the logical address of the to-be-accessed data is found in the index table, acquiring the state information of the to-be-accessed data from the index table;

The data to be accessed is read from the non-volatile cache or the volatile cache according to the state information of the data to be accessed.
The method according to claim 1, wherein each logical address in the index table corresponds to a physical address that stores data corresponding to each logical address;

The method also includes:

When acquiring the status information of the data to be accessed from the index table, also acquiring the physical address of the data to be accessed;

The reading the data to be accessed from the non-volatile cache or the volatile cache according to the state information of the data to be accessed includes:

The data to be accessed is read from the non-volatile cache or the volatile cache according to the state information of the data to be accessed and the physical address of the data to be accessed.
The method according to claim 2, wherein the index table includes a primary index table and a plurality of secondary index tables, and the primary index in the primary index table is a logical address from high to low 2^p bit value combinations obtained by combining the bit values on the first p bits in the sorting, where p is a positive integer, and each bit value combination corresponds to a secondary index table pointer, the secondary index table The pointer is used to indicate a secondary index table among multiple secondary index tables, the secondary index table is used to store a logical address and a physical address corresponding to each logical address, and the stored logical address is stored in the hybrid cache And the first p bits of the stored logical address are the same as the bit value in the bit value combination corresponding to the pointer of the secondary index table in the primary index table;

The searching the logical address in the index table includes:

Searching the first-level index for the bit value combination corresponding to the first p bits of the logical address of the data to be accessed;

Obtaining a secondary index table from the plurality of secondary index tables according to the secondary index table pointer corresponding to the bit value combination;

Look up the logical address of the data to be accessed in the secondary index table.
The method according to any one of claims 1 to 3, characterized in that, after the reading of the data to be accessed, the method further comprises:

According to the logical address of the data to be accessed, a heat record sequence corresponding to the logical address of the data to be accessed is obtained from a heat record table. The heat record table includes a plurality of heat record sequences, and each heat record sequence corresponds to a segment A logical address interval, where the logical address of the data to be accessed falls within the logical address interval, and each heat record sequence is used to record the heat of the data corresponding to the logical address interval;

Update the heat recorded in the acquired heat record sequence.
The method according to claim 4, wherein each heat record sequence includes a plurality of bits, and each bit corresponds to an update period;

The update of the heat recorded in the acquired heat record sequence includes:

The update period corresponding to the current time is acquired, and the bit corresponding to the update period corresponding to the current time is updated to an identifier indicating that the data corresponding to the logical address corresponding to the heat record sequence has been accessed.
The method according to claim 4, wherein the method further comprises:

Check the heat attenuation command;

Acquiring the bit corresponding to the next update period after the update period corresponding to the current time among the multiple bits in each heat record sequence;

Updating the bit corresponding to the next update period in each heat record sequence to an identifier indicating that the data corresponding to the logical address corresponding to the heat record sequence has not been accessed;

The bit corresponding to the next update period in each popularity record sequence is determined as the bit corresponding to the update period corresponding to the current time.
The method according to claim 5 or 6, wherein the multiple bits are arranged periodically in a specified order;

The heat record table is configured with a clock and a pointer. The clock periodically counts according to a set time after the system is initialized. The pointer points to one of the multiple bits when the system is initialized. When the timing duration of the clock reaches the set duration, trigger the pointer to switch to the next bit position according to the sequence;

The bit corresponding to the update period corresponding to the current time is the bit pointed to by the pointer at the current time.
The method according to claim 4, wherein the method further comprises:

Determining the heat value of the data stored in the volatile cache according to the heat record table;

If the popularity value of the data is less than the popularity threshold, the data is eliminated to the non-volatile cache.
A device for accessing a hybrid cache in an electronic device, wherein the hybrid cache includes a volatile cache and a non-volatile cache, and the device includes:

A receiving module, configured to receive a read instruction for the data to be accessed, and the read instruction carries the logical address of the data to be accessed;

The search module is configured to search for the logical address in an index table. The index table stores state information corresponding to the logical address of the data stored in the hybrid cache, and the state information is used to indicate Whether the stored data is stored in the volatile cache or the non-volatile cache;

The first obtaining module is configured to obtain the status information of the data to be accessed from the index table when the logical address of the data to be accessed is found in the index table;

The reading module is configured to read the data to be accessed from the non-volatile cache or the volatile cache according to the state information of the data to be accessed.
9. The device according to claim 9, wherein each logical address in the index table corresponds to a physical address that stores data corresponding to each logical address;

The first obtaining module is also used to obtain the physical address of the data to be accessed when obtaining the state information of the data to be accessed from the index table;

The reading module is specifically configured to read the to-be-accessed data from the non-volatile cache or the volatile cache according to the status information of the to-be-accessed data and the physical address of the to-be-accessed data data.
The device according to claim 10, wherein the index table includes a primary index table and a plurality of secondary index tables, and the primary indexes in the primary index table are from high to low in the logical address 2^p bit value combinations obtained by combining the bit values on the first p bits in the sorting, where p is a positive integer, and each bit value combination corresponds to a secondary index table pointer, the secondary index table The pointer is used to indicate a secondary index table among multiple secondary index tables, the secondary index table is used to store a logical address and a physical address corresponding to each logical address, and the stored logical address is stored in the hybrid cache And the first p bits of the stored logical address are the same as the bit value in the bit value combination corresponding to the pointer of the secondary index table in the primary index table;

The search module is specifically used for:

Searching the first-level index for the bit value combination corresponding to the first p bits of the logical address of the data to be accessed;

Obtaining a secondary index table from the plurality of secondary index tables according to the secondary index table pointer corresponding to the bit value combination;

Look up the logical address of the data to be accessed in the secondary index table.
The device according to any one of claims 9 to 11, wherein the device further comprises:

The second acquiring module is configured to acquire a heat record sequence corresponding to the logical address of the data to be accessed from a heat record table according to the logical address of the data to be accessed, the heat record table including a plurality of heat record sequences, Each heat record sequence corresponds to a logical address interval, the logical address of the data to be accessed falls within the logical address interval, and each heat record sequence is used to record the heat of the data corresponding to the corresponding logical address interval;

The first update module is used to update the heat recorded in the acquired heat record sequence.
The device of claim 12, wherein each heat record sequence includes a plurality of bits, and each bit corresponds to an update period;

The first update module is specifically configured to: obtain the update period corresponding to the current time, and update the bit corresponding to the update period corresponding to the current time to an identifier indicating that the data corresponding to the logical address corresponding to the heat record sequence has been accessed .
The device of claim 12, wherein the device further comprises:

Detection module, used to detect heat attenuation instructions;

The third acquiring module is used to acquire the bit corresponding to the next update period after the update period corresponding to the current time among the multiple bits of each heat record sequence;

The second update module is configured to update the bit corresponding to the next update period in each heat record sequence to an identifier indicating that the data corresponding to the logical address corresponding to the heat record sequence has not been accessed;

The third update module is configured to determine the bit corresponding to the next update period in each heat record sequence as the bit corresponding to the update period corresponding to the current time.
The device according to claim 13 or 14, wherein the multiple bits are periodically arranged in a specified order;

The heat record table is configured with a clock and a pointer. The clock periodically counts according to a set time after the system is initialized. The pointer points to one of the multiple bits when the system is initialized. When the timing duration of the clock reaches the set duration, trigger the pointer to switch to the next bit position according to the sequence;

The bit corresponding to the update period corresponding to the current time is the bit pointed to by the pointer at the current time.
The device of claim 12, wherein the device further comprises:

The first determining module is configured to determine the popularity value of the data stored in the volatile cache according to the popularity record table;

The elimination module is used to eliminate the data to the non-volatile cache if the popularity value of the data is less than the popularity threshold.