WO2021001645A1 - A semiconductor device and methods for production thereof - Google Patents

A semiconductor device and methods for production thereof Download PDF

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Publication number
WO2021001645A1
WO2021001645A1 PCT/GB2020/051566 GB2020051566W WO2021001645A1 WO 2021001645 A1 WO2021001645 A1 WO 2021001645A1 GB 2020051566 W GB2020051566 W GB 2020051566W WO 2021001645 A1 WO2021001645 A1 WO 2021001645A1
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Prior art keywords
layer
region
dopant
jfet
implantation
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PCT/GB2020/051566
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French (fr)
Inventor
Neophytos LOPHITIS
Anastasios ARVANITOPOULOS
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Coventry University
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Publication of WO2021001645A1 publication Critical patent/WO2021001645A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1608—Silicon carbide

Definitions

  • the present invention relates to semiconductor devices such as transistors and sensors, and methods for producing the same. Aspects of the invention relate to a method for producing a semiconductor device, to a semiconductor device, and to a use of a semiconductor device produced in accordance with the invention.
  • the cubic polytype (3C-) of Silicon Carbide (SiC) is an emerging semiconductor technology for power devices.
  • the featured isotropic material properties along with the Wide Band Gap (WBG) characteristics make it a desirable choice for power Metal Oxide Semiconductor (MOS) devices, for example Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), Insulated Gate Bipolar Transistors (IGBTs) and MOS sensors.
  • MOSFETs Metal Oxide Semiconductor Field Effect Transistors
  • IGBTs Insulated Gate Bipolar Transistors
  • MOS sensors MOS sensors.
  • MOSFETs Metal Oxide Semiconductor Field Effect Transistors
  • IGBTs Insulated Gate Bipolar Transistors
  • MOS sensors for example, such characteristics should theoretically provide at least two times wider energy bandgap, an order of magnitude higher critical electric field and largely improved thermal conductivity when compared to silicon.
  • 3C-SiC can be heteroepitaxially grown on silicon substrates using chemical vapour deposition (CVD). This enables for large 3C-SiC-on-Si crystals that match the diameters of commercially available Si wafers. In consequence, devices of reduced cost can be obtained.
  • CVD chemical vapour deposition
  • 3C-SiC is particularly promising for MOS devices mainly because the majority of the observed Si0 2 /SiC interface traps are energetically located in the conduction band (Ec), essentially improving the effective channel mobility.
  • a method for producing a semiconductor device comprising: epitaxially forming a first layer of a first conductivity type on a substrate or on a previously epitaxially formed layer; epitaxially forming a second layer primarily of a second conductivity type on the first layer; and forming a region within the second layer having an opposite conductivity type to the second layer.
  • the region of opposite conductivity type may act as the Junction Field Effect Transistor (JFET) region in a MOS device, for example.
  • JFET Junction Field Effect Transistor
  • the method may comprise sequentially epitaxially forming two or more layers having alternating conductivity types. For example, the method may extend to epitaxially forming a third layer of the first conductivity type on the second layer. The method may continue likewise with sub-layers of alternate conductivity types being formed on a preceding layer.
  • the method may comprise doping (e.g. via implantation of dopants) a portion of the second layer to form the region within the second layer having the opposite conductivity type to the second layer.
  • the method may comprise selectively epitaxially forming the region within the second layer having the opposite conductivity type to the second layer.
  • a method for producing a semiconductor device comprising: epitaxially forming a first layer of n- type conductivity on a substrate or on a previously epitaxially formed layer; epitaxially forming a body layer of p-type conductivity on the first layer; and doping at least a portion of the body layer with a dopant to form a JFET region of n-type conductivity within the body layer.
  • forming the body layer via epitaxy and partially doping the body layer to form the JFET region of n-type conductivity removes the need to implant p-type dopants (such as Aluminium) to form the various regions of the semiconductor device.
  • p-type dopants such as Aluminium
  • the substrate comprises a 3C-SiC-on-Si device where only a negligible level of activation of A1 dopants within the device can occur when annealing at temperatures below the melting point of silicon.
  • the first layer comprises a drift layer.
  • the method may comprise homo-epitaxially forming the layers, and/or may comprise hetero-epitaxially forming the layers.
  • the dopant comprises an n-type dopant.
  • doping at least a portion of the body layer comprises implantation of the dopant to (over-) compensate the p-type conductivity of the body layer, thereby forming the region of n- type conductivity in the JFET region.
  • the method may comprise implanting the dopant at two or more implant energies. Implantation at different energy levels may result in different concentrations of dopant at different depths within the body layer. Accordingly, implanting the dopant at two or more energy levels may provide a substantially constant doping concentration at different depths of the JFET region.
  • implanting at different implant energies enables control over the doping concentration profile throughout the JFET region, for example to provide a JFET region having a substantially constant or variable doping concentration profile throughout the JFET - for example, at different depths within the body layer.
  • the method comprises sequentially epitaxially forming two or more sub-layers of the body layer. In such embodiments each of the two or more sub layers may comprise the same doping concentration.
  • the two or more sub-layers may comprise different doping concentrations.
  • the method may comprise epitaxially forming a first sub-layer of p-type conductivity on the drift layer, the first sub-layer having a first doping concentration; and epitaxially forming a second sub layer of p-type conductivity on the first sub-layer, the second sub-layer having a second doping concentration, and wherein the second doping concentration is greater than the first doping concentration.
  • the method may extend to epitaxially forming a third sub layer of p-type conductivity on the second sub-layer, the third sub-layer having a third doping concentration, and wherein the third doping concentration is greater than the second doping concentration.
  • a more effective compensation of the p-type dopants in the body layer through doping with n-type dopants can be achieved.
  • this enables a smoother doping profile in the JFET region with dopant concentrations (and hence conductivity levels) being comparable to the drift layer. This has a direct impact on the blocking capabilities of the semiconductor device and reduces the E-field in this region.
  • the method comprises preventing implantation of a portion of the body layer.
  • the formed JFET region may comprise an anti-region of p- type conductivity.
  • the method comprises preventing implantation of a portion of the body layer such that the formed JFET region comprises an anti-region of p-type conductivity substantially central within the JFET region.
  • the method may comprise implanting the body layer with the dopant such that the formed JFET region comprises regions of n-type conductivity either side of the central anti-region of p-type conductivity.
  • the anti-region of p-type conductivity may provide a higher blocking voltage for the device.
  • the method comprises implanting the dopant in two or more implantation stages to form JFET portions, each JFET portion being associated with each implantation stage.
  • the method may comprise implanting the dopant in a first implantation stage to form a first JFET portion having a first width, and implanting the dopant in a second implantation stage to form a second JFET portion having a second width different to the first width.
  • the JFET region may, at least in part, be reduced in width thereby reducing the distance between opposing portions of the body layer either side of the JFET region. This results in an improved forward breakdown performance of the power device. Retaining a wider JFET region of high over-compensated first conductivity doping, preferably at or proximal to a surface of the device provides a reduced on- resistance of the final device.
  • the method may comprise implanting the dopant at a first energy level/set during a first stage of implantation, and implanting the dopant at a second energy level/set during a second stage of implantation.
  • the method comprises applying a mask to the body layer during implantation to target specific locations of the body layer for implantation with the dopant.
  • the method may comprise applying a first mask during a first stage of implantation, and applying a second mask during the second stage of implantation.
  • different areas or regions of the body layer may be targeted during implantation. This may be desirable, for example, where the width of the JFET region is required to vary at different locations or depths of the JFET region.
  • the method comprises etching the surface of the body layer.
  • the method may comprise etching the surface of the semiconductor device or selectively etching the JFET region to a given depth, which may in some embodiments be approximately 0.5pm, although other depths are envisaged and the invention is not limited in this sense as will be appreciated.
  • the method may comprise etching the surface of the body layer after implantation of the body layer with the dopant.
  • etching may account for known issues with implantation in that at or very close to the surface of a substrate it is difficult to achieve the desired dopant concentration through implantation. By etching, this area at or proximal to the surface can be removed.
  • the method comprises implanting the body layer with an n-type dopant at regions either side of the JFET region to form highly doped source regions within the body layer.
  • doping in this manner ensure good ohmic contacts for the semiconductor device at the source regions.
  • the method may additionally comprise forming a gate oxide on the body layer, spanning the width of the JFET region.
  • the method may additionally comprise depositing a polysilicon on the gate oxide to form a gate contact of the semiconductor device.
  • the method may comprise a metallization process.
  • the substrate may comprise silicon.
  • the drift layer and/or the body layer may comprise silicon carbide.
  • the drift layer and/or the body layer comprises 3C-silicon carbide (3C-SiC).
  • the dopant comprises nitrogen. In other embodiments phosphorus, arsenic or antimony may be used as a dopant. In embodiments where a p-type dopant may be used, the dopant may comprise aluminium, boron, gallium, indium or titanium, for example.
  • a semiconductor device formed by the method according to an aspect of the invention.
  • the semiconductor device comprises a transistor.
  • the semiconductor device comprises a Metal Oxide Semiconductor Field-Effect Transistor (MOSFET).
  • MOSFET Metal Oxide Semiconductor Field-Effect Transistor
  • a semiconductor device comprising: a substrate; two body regions of p-type conductivity; two source regions of n-type conductivity; a JFET of n-type conductivity located substantially central between the two body regions; and an anti-region of p-type conductivity within the JFET and spatially separated from the body regions.
  • the substrate comprises silicon
  • the source regions, body regions, JFET region and/or anti-region comprises silicon carbide.
  • the source regions comprise 3C-silicon carbide.
  • the source regions, body regions, JFET region and/or anti-region comprises 3C-SiC doped with p-type or n-type dopants.
  • the JFET region comprises 3C-SiC doped with nitrogen.
  • the semiconductor device may comprise a transistor.
  • the semiconductor device comprises a MOSFET.
  • the semiconductor device comprises any device which includes a Metal Oxide Semiconductor region, which can include IGBTs, MOS controlled thyristors, MOS capacitors and MOS Sensors, for example.
  • Figure 1A is a series of images illustrating a prior art method for forming a semiconductor device
  • Figure IB is a graph illustrating energy levels of dopants used in the prior art method shown in Figure 1 ;
  • Figure 2 is a series of images illustrating an embodiment of a method of the invention for forming a semiconductor device
  • Figure 3 is a series of images illustrating an extension of the method shown in
  • Figure 4 is a series of images illustrating an extension of the method shown in
  • Figure 5 is a series of images illustrating an extension of the method shown in
  • Figure 6 is a series of images illustrating an extension of the method shown in
  • Figure 7 is a graph illustrating energy levels of dopants used in methods according to the invention
  • Figure 8 is a graph showing modelled output characteristics of semiconductor devices formed according to the methods shown in Figures 3-6 when compared with the prior art method of Figure 1 ;
  • Figure 9 is a graph showing modelled transfer characteristics of semiconductor devices formed according to the methods shown in Figures 3-6 when compared with the prior art method of Figure 1 ;
  • Figure 10 is a graph showing modelled output characteristics at different gate voltages for semiconductor devices formed according to the methods shown in Figures 3-6 when compared with the prior art method of Figure 1.
  • embodiments of the invention relate to methods for forming semiconductor devices 100, 200, 300, 400 described herein comprise epitaxially forming a drift layer 104, 204, 304, 404 of n-type conductivity on a substrate 102, 202, 302, 402; epitaxially forming a body layer 112, 212, 312, 412 of p-type conductivity on the drift layer 104, 204, 304, 404; and doping a portion of the body layer 112, 212, 312, 412 with a dopant to form a JFET region 120, 220, 320, 420 comprising a region of n-type conductivity within the body layer 112, 212, 312, 412.
  • FIG. 1A A conventional method for forming a semiconductor device in the form of a 3C-SiC- on-Si MOSFET 10 is shown in Figure 1A.
  • a 3C-SiC drift layer 14 is epitaxially formed on a silicon (Si) substrate 12.
  • the substrate is of the order of a few hundred microns and has an n-type conductivity, and a dopant concentration of the order of lxlO 19 cm 3 .
  • the drift layer 14 is of n-type conductivity and has a dopant concentration of the order of 10 15 cm 3 .
  • the drift layer 14 has a dopant concentration of 5xl0 15 cm 3 .
  • the drift layer 14 is of the order of lOpm thick.
  • step (b) an implantation process is performed using Aluminium (Al) implants as dopants to dope the drift layer 14 to form body regions 16a, 16b of p-type conductivity and a dopant concentration in the region of lxlO 18 cm 3 .
  • Al Aluminium
  • the A1 dopants are implanted at various energies to form the required doping profile in the body regions 16a, 16b.
  • various energy levels of A1 implants are used ranging from 50keV to 400keV, resulting in an overall dopant concentration which gradually reduces with depth in the drift layer 14.
  • the body regions 16a, 16b are further implanted with nitrogen (N) implants to form source regions 18a, 18b therein.
  • the desired doping concentration in the source regions 18a, 18b is of the order of 2xl0 19 cm 3 .
  • the formation of the body regions 16a, 16b results in a defined JFET region 20 positioned centrally between the two body regions 16a, 16b.
  • the JFET region 20 is of n-type conductivity.
  • step (c) the surface of the 3C-SiC is etched, optionally to about 0.5pm.
  • This etching step is to ensure that the body regions 16a, 16b are sufficiently doped to overcome a known problem with a dopant implantation process in that for depths very close to the surface, the desired doping concentration is hard to achieve. For instance, a significantly lower level of dopant concentration is observed at very shallow depths (approx. 0 -> 0.1pm) when compared with concentrations observed at depths greater than O. lpm.
  • Etching after implantation ensures a desired doping concentration at and just below the surface.
  • an oxide cap may be used during the implantation process. This cap can then be removed post implantation having the same effect at etching the surface.
  • step (d) a gate oxide 22 is formed over the JFET 20, and a poly-silicon layer 24 is deposited on the gate oxide 22 to form a gate contact.
  • step (e) comprises a metallisation process 26.
  • Figure 2 illustrates an embodiment of a method in accordance with an aspect of the invention, the method being used to form a semiconductor device in the form of a 3C- SiC-on-Si MOSFET 100.
  • a 3C-SiC drift layer 104 is epitaxially formed on a silicon (Si) substrate 102.
  • the drift layer 104 is of n-type conductivity and has a dopant concentration of the order of 10 15 cm 3 .
  • the drift layer 104 has a dopant concentration of 5xl0 15 cm 3 .
  • the drift layer 104 is of the order of lOpm thick.
  • Steps (b) - (d) comprise epitaxially forming a 3C-SiC body layer 112 of p-type conductivity.
  • the body layer 112 has a linearly varying dopant concentration, as will be described herein.
  • a first film layer 106 is epitaxially formed on the drift layer 104.
  • the first film layer 106 has a thickness in the region of 0.2pm and has a dopant concentration of the order of 10 16 cm 3 , preferably 5xl0 16 cm 3 .
  • a second film layer 108 is epitaxially formed on the first film layer 106.
  • the second film layer 108 has a thickness in the region of 0.3pm and has a dopant concentration of the order of 10 17 cm 3 , preferably 7xl0 17 cm 3 .
  • a third film layer 110 is epitaxially formed on the second film layer 108.
  • the third film layer 110 has a thickness in the region of 0.3pm and has a dopant concentration of the order of 10 18 cm 3 , and preferably a peak concentration of lxlO 18
  • Whist the embodiment of Figure 2 comprises forming the body layer 112 from a series of film layers 106, 108, 110 with varying dopant concentrations
  • the body layer 112 may be formed as a single layer, for example having a constant dopant concentration across its depth.
  • having a varying level of dopant concentration with depth in the body layer 112 may at least partially mitigate difficulties in accurately overcompensating for the p-type dopants in the body layer 112 with n-type implants (see Figures 3-6) which may otherwise adversely affect the blocking capabilities of the final device 100.
  • Figure 3 illustrates an embodiment of a method for forming a semiconductor device in the form of a 3C-SiC-on-Si MOSFET device 100, which includes an implanted n- type/JFET region.
  • the method comprises implanting a region of the body layer 112 with dopants (preferably nitrogen) of n-type conductivity to form a JFET region 120 within the body layer 112.
  • the JFET 120 is formed within the body layer 112 and results in body regions 116a, 116b of the body layer 112 positioned either side of the JFET region 120.
  • Implanting the n-type dopants overcompensates for the p-type dopants of the body layer 112 resulting in a JFET region 120 having n-type conductivity within the p-type body layer 112.
  • the N dopants are implanted at various energies to form the required doping profile in the channel 120.
  • various energy levels of N implants are used ranging from 60keV to 375keV, resulting in an overall dopant concentration which is roughly constant with depth.
  • the body regions 116a, 116b are each doped with nitrogen (N) implants to form source regions 118a, 118b therein.
  • the desired doping concentration in the source regions 118a, 118b is of the order of 2xl0 19 cm 3 .
  • step (g) the surface of the 3C-SiC is etched, optionally to about 0.5pm. As with the etching step described with reference to Figure 1, this is to ensure that the JFET region 120 is sufficiently doped throughout.
  • step (h) a gate oxide 122 is formed over the JFET 120, and in step (i) a poly-silicon layer 124 is deposited on the gate oxide 122 to form a gate contact.
  • step (i) also comprises a metallisation process 126.
  • Table 1 below provides a direct comparison of simulated characteristic values for the MOSFET 100 formed in accordance with the method illustrated in Figures 2 and 3, and the conventional method illustrated in Figure 1.
  • MOSFET 100 provides a comparable Gate threshold voltage, and a significantly reduced on-resistance for the Gate and Drain voltages provided above.
  • the breakdown voltage achieved by MOSFET 100 is significantly less than that obtained with a MOSFET formed via a conventional method.
  • the method comprises implanting a region of a body layer 212 with dopants of n-type conductivity (preferably nitrogen) and at a first energy level/range to form a first JFET portion 220a of a JFET region within the body layer 212.
  • the dopants are implanted at a series of energy levels up to approximately 225keV to form the first JFET portion 220a.
  • a mask is used to target specific locations of the body layer 212 for further implantation with n-type dopants.
  • the body layer 212 is further implanted with n-type dopants at a second energy level/range, greater than the first energy level/range using the mask to form a second JFET portion 220b in the body layer 212.
  • the JFET portions 220a, 220b form a JFET region within the body layer 212 resulting in body regions 216a, 216b of the body layer 212 positioned either side of the JFET region.
  • implanting the n-type dopants overcompensates for the p-type dopants of the body layer 212 resulting in a JFET region having n-type conductivity within the p-type body layer 212.
  • the JFET region comprises a second JFET portion 220b which is smaller in width than the first channel portion 220a and effectively brings opposing portions of the body regions 216a, 216b closer together.
  • the N dopants are implanted at various energies to form the required doping profile in the channel.
  • various energy levels of N implants are used ranging from 60keV to 375keV, resulting in an overall dopant concentration which is roughly constant with depth.
  • energy levels up to approximately 225keV are used to form the first channel portion 220a
  • energy levels above 225keV and up to approximately 375keV are used to form the second channel portion 220b due to the increased energy requirement to implant at greater depths within the body layer 212.
  • the body regions 216a, 216b are each doped with nitrogen (N) implants to form source regions 218a, 218b therein.
  • the desired doping concentration in the source regions 218a, 218b is of the order of 2xl0 19 cm 3 .
  • step (h) the surface of the 3C-SiC is etched, optionally to about 0.5pm. As with the etching step described with reference to Figure 1, this is to ensure that the JFET region is sufficiently doped throughout.
  • step (i) a gate oxide 222 is formed over the JFET, and in step (j) a poly-silicon layer 224 is deposited on the gate oxide 222 to form a gate contact.
  • step (j) also comprises a metallisation process 226.
  • Having the wider first JFET portion 220a preserves a low resistance JFET region proximal to the gate contact (where the channel is formed) with the aim of maintaining a low on-resistance in the final MOSFET device 200.
  • Table 2 below provides a direct comparison of simulated characteristic values for the MOSFET 200 formed in accordance with the method illustrated in Figures 2 and 4, and the conventional method illustrated in Figure 1.
  • Table 2 Comparison of simulated characteristic values for a MOSFET 200 with extended p-body edges.
  • MOSFET 200 provides a comparable Gate threshold voltage, and a significantly reduced on-resistance for the Gate and Drain voltages provided above when compared with a MOSFET formed through conventional techniques (but a small increase on the on-resistance of MOSFET 100).
  • the breakdown voltage achieved by MOSFET 200 is a significant improvement on that predicted for MOSFET 100, and is predicted to be much closer to that obtained with a MOSFET formed via a conventional method.
  • a further method for forming a semiconductor device in the form of a 3C-SiC-on-Si MOSFET device 300 is proposed which includes a“buried” p-type anti-region within the n-type channel. This is illustrated in Figure 5, where like reference numerals have been used to represent similar components.
  • the method comprises implanting a region of a body layer 312 with dopants of n-type conductivity (preferably nitrogen) and at a first energy level/range to form a first JFET portion 320a of a JFET region within the body layer 312.
  • the dopants are implanted at a series of energy levels up to approximately 225keV to form the first JFET portion 320a.
  • a mask is used to target specific locations of the body layer 312 for further implantation with n-type dopants.
  • the body layer 312 is further implanted with n-type dopants at a second energy level/range, greater than the first energy level/range using the mask to form second and third JFET portions 320b, 320c in the body layer 312.
  • the mask used prevents implantation of a region substantially central within the formed JFET region resulting in an anti-region 320d of p-type conductivity positioned between second and third JFET portions 320b, 320c of the JFET region.
  • the JFET portions 320a, 320b and 320c define a JFET region within the body layer 312 between body regions 316a, 316b and anti-region 320d of the body layer 312.
  • implanting the n-type dopants overcompensates for the p-type dopants of the body layer 312 resulting in a JFET region, at least for JFET portions 320a, 320b, 320c, having n-type conductivity within the p-type body layer 312.
  • the N dopants are implanted at various energies to form the required doping profile in the JFET region.
  • various energy levels of N implants are used ranging from 60keV to 375keV, resulting in an overall dopant concentration which is roughly constant with depth.
  • energy levels up to approximately 225keV are used to form the first JFET portion 320a
  • energy levels above 225keV and up to approximately 375keV are used to form the second and third JFET portions 320b, 320c due to the increased energy requirement to implant at greater depths within the body layer 312.
  • the body regions 316a, 316b are each doped with nitrogen (N) implants to form source regions 318a, 318b therein.
  • the desired doping concentration in the source regions 318a, 318b is of the order of 2xl0 19 cm 3 .
  • step (h) the surface of the 3C-SiC is etched, optionally to about 0.5pm. As with the etching step described with reference to Figure 1, this is to ensure that the JFET region is sufficiently doped throughout.
  • step (i) a gate oxide 322 is formed over the channel, and in step (j) a poly-silicon layer 324 is deposited on the gate oxide 322 to form a gate contact.
  • Step (j) also comprises a metallisation process 326.
  • the JFET region Having the p-type anti-region 320d within the JFET region balances the charge of the region and it lowers the overall electric field. As a consequence, the blocking voltage of the device can reach high values. At the same time, because the JFET region is higher doped than the typical values, the on-resistance drops dramatically. Without the presence of the anti-region the JFET cannot have high doping concentration value because this compromises the blocking voltage ability.
  • Table 3 provides a direct comparison of simulated characteristic values for the MOSFET 300 formed in accordance with the method illustrated in Figures 2 and 5, and the conventional method illustrated in Figure 1.
  • MOSFET 300 provides a comparable Gate threshold voltage, and a significantly reduced on-resistance for the Gate and Drain voltages provided above when compared with a MOSFET formed through conventional techniques (but a small increase on the on-resistance of MOSFET 100).
  • the breakdown voltage achieved by MOSFET 300 is a significant improvement on that predicted for MOSFET 100, and is predicted to be much closer to that obtained with a MOSFET formed via a conventional method.
  • a further method for forming a semiconductor device in the form of a 3C-SiC-on-Si MOSFET device 400 which includes a pillar shaped p-type anti-region within the n-type JFET region.
  • the method comprises implanting a region of a body layer 412 with dopants of n-type conductivity (preferably nitrogen) at various energy levels to form a JFET region within the body layer 412.
  • the dopants are implanted at a series of energy levels up to approximately 375keV.
  • a mask is used to target specific locations of the body layer 412 for implantation with n-type dopants. Specifically, the mask prevents implantation of a region substantially central within the formed JFET region resulting in a pillar shaped anti region 420c of p-type conductivity positioned between first and second JFET portions 420a, 420b of n-type conductivity.
  • the JFET portions 420a, 420b define a JFET region within the body layer 412 between body regions 416a, 416b and anti-region 420c of the body layer 412.
  • implanting the n-type dopants overcompensates for the p-type dopants of the body layer 412 resulting in a JFET region, at least for JFET portions 420a, 420b having n-type conductivity within the p- type body layer 412.
  • the N dopants are implanted at various energies to form the required doping profile in the JFET region.
  • various energy levels of N implants are used ranging from 60keV to 375keV, resulting in an overall dopant concentration which is roughly constant with depth.
  • the body regions 416a, 416b are each doped with nitrogen (N) implants to form source regions 418a, 418b therein.
  • the desired doping concentration in the source regions 418a, 418b is of the order of 2xl0 19 cm 3 .
  • step (g) the surface of the 3C-SiC is etched, optionally to about 0.5pm. As with the etching step described with reference to Figure 1, this is to ensure that the JFET region is sufficiently doped throughout.
  • step (h) a gate oxide 422 is formed over the JFET, and in step (i) a poly-silicon layer 424 is deposited on the gate oxide 422 to form a gate contact.
  • step (i) also comprises a metallisation process 426.
  • Table 4 provides a direct comparison of simulated characteristic values for the MOSFET 300 formed in accordance with the method illustrated in Figures 2 and 6, and the conventional method illustrated in Figure 1.
  • Table 4 Comparison of simulated characteristic values for a MOSFET 400 with a pillar shaped p-type anti-region within the channel.
  • MOSFET 400 provides a comparable Gate threshold voltage, and a significantly reduced on-resistance for the Gate and Drain voltages provided above when compared with a MOSFET formed through conventional techniques (but a small increase on the on-resistance of MOSFET 100).
  • the breakdown voltage achieved by MOSFET 300 is a significant improvement on that predicted for MOSFET 100, and is predicted to be much closer to that obtained with a MOSFET formed via a conventional method.
  • Figure 8 is a graph 600 showing modelled output characteristics of semiconductor devices (MOSFETS 100, 200, 300, 400) formed according to the methods shown in Figures 3-6 when compared with the prior art method of Figure 1. Specifically, graph 600 plots Drain Current ID against Drain Voltage VD for each of the MOSFETs described herein. As shown, the modelled output characteristics for each of MOSFETS 200, 300, 400 are comparable to the output characteristics for a MOSFET 10 formed via conventional methods.
  • Figure 9 is a graph 700 showing modelled transfer characteristics of semiconductor devices (MOSFETS 100, 200, 300, 400) formed according to the methods shown in Figures 3-6 when compared with the prior art method of Figure 1. Specifically, graph 700 plots Drain Current I D against Gate Voltage V G for each of the MOSFETs described herein.
  • MOSFETs e.g. MOSFETS 100, 200, 300, 400
  • MOSFET 10 MOSFET 10
  • a highly doped channel/JFET region results in a reduction in the blocking ability. Accordingly, methods of the invention provide means to address this issue, e.g. by reducing the separation between body regions of the device. Reducing the separation between body regions 118, 218, 318, 418 enables a better distribution of the electrostatic potential in the channel/JFET region and the drift layer. This is demonstrated in particular by the configurations of MOSFETs 200, 300, 400. As a result, such MOSFETs have been identified as having at least a comparable breakdown voltage to those formed via conventional methods (e.g. MOSFET 10).

Abstract

A method for producing a semiconductor device, which includes epitaxially forming a first layer of n-type conductivity on a substrate or on a previously epitaxially formed layer; epitaxially forming a body layer of p-type conductivity on the first layer; and doping a portion of the body layer with a dopant to form a JFET region comprising a region of n-type conductivity within the body layer.

Description

A Semiconductor Device and Methods for Production thereof
Technical Field of the Invention
The present invention relates to semiconductor devices such as transistors and sensors, and methods for producing the same. Aspects of the invention relate to a method for producing a semiconductor device, to a semiconductor device, and to a use of a semiconductor device produced in accordance with the invention.
Background to the Invention
The cubic polytype (3C-) of Silicon Carbide (SiC) is an emerging semiconductor technology for power devices. The featured isotropic material properties along with the Wide Band Gap (WBG) characteristics make it a desirable choice for power Metal Oxide Semiconductor (MOS) devices, for example Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), Insulated Gate Bipolar Transistors (IGBTs) and MOS sensors. For example, such characteristics should theoretically provide at least two times wider energy bandgap, an order of magnitude higher critical electric field and largely improved thermal conductivity when compared to silicon.
Further, 3C-SiC can be heteroepitaxially grown on silicon substrates using chemical vapour deposition (CVD). This enables for large 3C-SiC-on-Si crystals that match the diameters of commercially available Si wafers. In consequence, devices of reduced cost can be obtained.
3C-SiC is particularly promising for MOS devices mainly because the majority of the observed Si02/SiC interface traps are energetically located in the conduction band (Ec), essentially improving the effective channel mobility.
However, to date, material related limitations have meant that semiconductor devices formed from 3C-SiC are unsuitable for commercial implementation. For example, using conventional techniques an almost negligible activation of the p-type dopants is observed after ion implantation. This is primarily due to the fact that the formed device must be annealed at relatively low temperatures.
For example, and as is described in detail below, it is conventional to perform p-type (acceptor type) doping using Aluminium (Al). However, its activation has been proved difficult to achieve. One cause of this issue for the specific case of 3C-SiC-on-Si comes from the fact that the annealing temperature needs to be kept relatively low, for example lower than the melting point of the Si substrate. This value of approximately 1350°C is lower than the required activation temperatures of Al, which can be as high as 1700°C for a nearly perfect activation (>95%). Similar issues exist with other acceptor impurities. In consequence, p-type regions in 3C-SiC by ion implantation is difficult to achieve.
It is therefore desirable to provide a method for forming a semiconductor device which overcomes the limitations of conventional methods, particularly where the semiconductor device is formed from 3C-SiC-on-Si.
It is an aim of an embodiment or embodiments of the invention to overcome or at least partially mitigate one or more problems associated with the prior art.
Summary of the Invention
According to an aspect of the invention there is provided a method for producing a semiconductor device, the method comprising: epitaxially forming a first layer of a first conductivity type on a substrate or on a previously epitaxially formed layer; epitaxially forming a second layer primarily of a second conductivity type on the first layer; and forming a region within the second layer having an opposite conductivity type to the second layer.
In embodiments, the region of opposite conductivity type may act as the Junction Field Effect Transistor (JFET) region in a MOS device, for example.
In embodiments, the method may comprise sequentially epitaxially forming two or more layers having alternating conductivity types. For example, the method may extend to epitaxially forming a third layer of the first conductivity type on the second layer. The method may continue likewise with sub-layers of alternate conductivity types being formed on a preceding layer.
In embodiments the method may comprise doping (e.g. via implantation of dopants) a portion of the second layer to form the region within the second layer having the opposite conductivity type to the second layer. Alternatively, the method may comprise selectively epitaxially forming the region within the second layer having the opposite conductivity type to the second layer.
According to a further aspect of the invention there is provided a method for producing a semiconductor device, the method comprising: epitaxially forming a first layer of n- type conductivity on a substrate or on a previously epitaxially formed layer; epitaxially forming a body layer of p-type conductivity on the first layer; and doping at least a portion of the body layer with a dopant to form a JFET region of n-type conductivity within the body layer.
Advantageously, forming the body layer via epitaxy and partially doping the body layer to form the JFET region of n-type conductivity removes the need to implant p-type dopants (such as Aluminium) to form the various regions of the semiconductor device. As is described herein, this is particularly beneficial where the substrate comprises a 3C-SiC-on-Si device where only a negligible level of activation of A1 dopants within the device can occur when annealing at temperatures below the melting point of silicon.
In embodiments, the first layer comprises a drift layer.
In embodiments, the method may comprise homo-epitaxially forming the layers, and/or may comprise hetero-epitaxially forming the layers.
In embodiments, the dopant comprises an n-type dopant. In some embodiments, doping at least a portion of the body layer comprises implantation of the dopant to (over-) compensate the p-type conductivity of the body layer, thereby forming the region of n- type conductivity in the JFET region.
The method may comprise implanting the dopant at two or more implant energies. Implantation at different energy levels may result in different concentrations of dopant at different depths within the body layer. Accordingly, implanting the dopant at two or more energy levels may provide a substantially constant doping concentration at different depths of the JFET region.
Advantageously, implanting at different implant energies enables control over the doping concentration profile throughout the JFET region, for example to provide a JFET region having a substantially constant or variable doping concentration profile throughout the JFET - for example, at different depths within the body layer. In some embodiments the method comprises sequentially epitaxially forming two or more sub-layers of the body layer. In such embodiments each of the two or more sub layers may comprise the same doping concentration.
Alternatively, the two or more sub-layers may comprise different doping concentrations. For example, in some embodiments the method may comprise epitaxially forming a first sub-layer of p-type conductivity on the drift layer, the first sub-layer having a first doping concentration; and epitaxially forming a second sub layer of p-type conductivity on the first sub-layer, the second sub-layer having a second doping concentration, and wherein the second doping concentration is greater than the first doping concentration. The method may extend to epitaxially forming a third sub layer of p-type conductivity on the second sub-layer, the third sub-layer having a third doping concentration, and wherein the third doping concentration is greater than the second doping concentration.
Advantageously, a more effective compensation of the p-type dopants in the body layer through doping with n-type dopants can be achieved. In turn, this enables a smoother doping profile in the JFET region with dopant concentrations (and hence conductivity levels) being comparable to the drift layer. This has a direct impact on the blocking capabilities of the semiconductor device and reduces the E-field in this region.
In some embodiments the method comprises preventing implantation of a portion of the body layer. In this way, the formed JFET region may comprise an anti-region of p- type conductivity. In embodiments, the method comprises preventing implantation of a portion of the body layer such that the formed JFET region comprises an anti-region of p-type conductivity substantially central within the JFET region. The method may comprise implanting the body layer with the dopant such that the formed JFET region comprises regions of n-type conductivity either side of the central anti-region of p-type conductivity. The anti-region of p-type conductivity may provide a higher blocking voltage for the device.
In some embodiments the method comprises implanting the dopant in two or more implantation stages to form JFET portions, each JFET portion being associated with each implantation stage. The method may comprise implanting the dopant in a first implantation stage to form a first JFET portion having a first width, and implanting the dopant in a second implantation stage to form a second JFET portion having a second width different to the first width.
Advantageously, the JFET region may, at least in part, be reduced in width thereby reducing the distance between opposing portions of the body layer either side of the JFET region. This results in an improved forward breakdown performance of the power device. Retaining a wider JFET region of high over-compensated first conductivity doping, preferably at or proximal to a surface of the device provides a reduced on- resistance of the final device.
The method may comprise implanting the dopant at a first energy level/set during a first stage of implantation, and implanting the dopant at a second energy level/set during a second stage of implantation.
In embodiments the method comprises applying a mask to the body layer during implantation to target specific locations of the body layer for implantation with the dopant. In such embodiments the method may comprise applying a first mask during a first stage of implantation, and applying a second mask during the second stage of implantation. Advantageously, different areas or regions of the body layer may be targeted during implantation. This may be desirable, for example, where the width of the JFET region is required to vary at different locations or depths of the JFET region.
In embodiments, the method comprises etching the surface of the body layer. For example, in some embodiments the method may comprise etching the surface of the semiconductor device or selectively etching the JFET region to a given depth, which may in some embodiments be approximately 0.5pm, although other depths are envisaged and the invention is not limited in this sense as will be appreciated. The method may comprise etching the surface of the body layer after implantation of the body layer with the dopant. Advantageously, etching may account for known issues with implantation in that at or very close to the surface of a substrate it is difficult to achieve the desired dopant concentration through implantation. By etching, this area at or proximal to the surface can be removed.
In embodiments, the method comprises implanting the body layer with an n-type dopant at regions either side of the JFET region to form highly doped source regions within the body layer. Advantageously, doping in this manner ensure good ohmic contacts for the semiconductor device at the source regions.
The method may additionally comprise forming a gate oxide on the body layer, spanning the width of the JFET region.
The method may additionally comprise depositing a polysilicon on the gate oxide to form a gate contact of the semiconductor device.
The method may comprise a metallization process.
The substrate may comprise silicon.
The drift layer and/or the body layer may comprise silicon carbide. In embodiments, the drift layer and/or the body layer comprises 3C-silicon carbide (3C-SiC).
In embodiments, the dopant comprises nitrogen. In other embodiments phosphorus, arsenic or antimony may be used as a dopant. In embodiments where a p-type dopant may be used, the dopant may comprise aluminium, boron, gallium, indium or titanium, for example.
According to an aspect of the invention there is provided a semiconductor device formed by the method according to an aspect of the invention.
Optionally, the semiconductor device comprises a transistor. In some embodiments the semiconductor device comprises a Metal Oxide Semiconductor Field-Effect Transistor (MOSFET).
According to an aspect of the invention there is provided a semiconductor device, comprising: a substrate; two body regions of p-type conductivity; two source regions of n-type conductivity; a JFET of n-type conductivity located substantially central between the two body regions; and an anti-region of p-type conductivity within the JFET and spatially separated from the body regions.
In embodiments, the substrate comprises silicon.
In embodiments, the source regions, body regions, JFET region and/or anti-region comprises silicon carbide. Optionally, the source regions comprise 3C-silicon carbide. Optionally, the source regions, body regions, JFET region and/or anti-region comprises 3C-SiC doped with p-type or n-type dopants. Optionally, the JFET region comprises 3C-SiC doped with nitrogen.
The semiconductor device may comprise a transistor. In embodiments, the semiconductor device comprises a MOSFET. In embodiments, the semiconductor device comprises any device which includes a Metal Oxide Semiconductor region, which can include IGBTs, MOS controlled thyristors, MOS capacitors and MOS Sensors, for example.
Detailed Description of the Invention
In order that the invention may be more clearly understood one or more embodiments thereof will now be described, by way of example only, with reference to the accompanying drawings, of which:
Figure 1A is a series of images illustrating a prior art method for forming a semiconductor device;
Figure IB is a graph illustrating energy levels of dopants used in the prior art method shown in Figure 1 ;
Figure 2 is a series of images illustrating an embodiment of a method of the invention for forming a semiconductor device;
Figure 3 is a series of images illustrating an extension of the method shown in
Figure 2;
Figure 4 is a series of images illustrating an extension of the method shown in
Figure 2;
Figure 5 is a series of images illustrating an extension of the method shown in
Figure 2;
Figure 6 is a series of images illustrating an extension of the method shown in
Figure 2;
Figure 7 is a graph illustrating energy levels of dopants used in methods according to the invention; Figure 8 is a graph showing modelled output characteristics of semiconductor devices formed according to the methods shown in Figures 3-6 when compared with the prior art method of Figure 1 ;
Figure 9 is a graph showing modelled transfer characteristics of semiconductor devices formed according to the methods shown in Figures 3-6 when compared with the prior art method of Figure 1 ; and
Figure 10 is a graph showing modelled output characteristics at different gate voltages for semiconductor devices formed according to the methods shown in Figures 3-6 when compared with the prior art method of Figure 1.
In general, embodiments of the invention relate to methods for forming semiconductor devices 100, 200, 300, 400 described herein comprise epitaxially forming a drift layer 104, 204, 304, 404 of n-type conductivity on a substrate 102, 202, 302, 402; epitaxially forming a body layer 112, 212, 312, 412 of p-type conductivity on the drift layer 104, 204, 304, 404; and doping a portion of the body layer 112, 212, 312, 412 with a dopant to form a JFET region 120, 220, 320, 420 comprising a region of n-type conductivity within the body layer 112, 212, 312, 412. As is detailed below, this differs from prior art methods wherein body layers are conventionally formed through doping the drift layer rather than formation through epitaxy. A conventional method for forming a semiconductor device in the form of a 3C-SiC- on-Si MOSFET 10 is shown in Figure 1A.
In step (a), a 3C-SiC drift layer 14 is epitaxially formed on a silicon (Si) substrate 12. The substrate is of the order of a few hundred microns and has an n-type conductivity, and a dopant concentration of the order of lxlO19 cm 3. The drift layer 14 is of n-type conductivity and has a dopant concentration of the order of 1015 cm 3. Preferably, the drift layer 14 has a dopant concentration of 5xl015 cm 3. The drift layer 14 is of the order of lOpm thick.
In step (b), an implantation process is performed using Aluminium (Al) implants as dopants to dope the drift layer 14 to form body regions 16a, 16b of p-type conductivity and a dopant concentration in the region of lxlO18 cm 3. As is shown in Figure IB, the A1 dopants are implanted at various energies to form the required doping profile in the body regions 16a, 16b. Specifically, various energy levels of A1 implants are used ranging from 50keV to 400keV, resulting in an overall dopant concentration which gradually reduces with depth in the drift layer 14.
Turning back to Figure 1A, the body regions 16a, 16b are further implanted with nitrogen (N) implants to form source regions 18a, 18b therein. The desired doping concentration in the source regions 18a, 18b is of the order of 2xl019 cm 3. The formation of the body regions 16a, 16b results in a defined JFET region 20 positioned centrally between the two body regions 16a, 16b. The JFET region 20 is of n-type conductivity.
In step (c), the surface of the 3C-SiC is etched, optionally to about 0.5pm. This etching step is to ensure that the body regions 16a, 16b are sufficiently doped to overcome a known problem with a dopant implantation process in that for depths very close to the surface, the desired doping concentration is hard to achieve. For instance, a significantly lower level of dopant concentration is observed at very shallow depths (approx. 0 -> 0.1pm) when compared with concentrations observed at depths greater than O. lpm. Etching after implantation ensures a desired doping concentration at and just below the surface. Alternatively, an oxide cap may be used during the implantation process. This cap can then be removed post implantation having the same effect at etching the surface.
In step (d), a gate oxide 22 is formed over the JFET 20, and a poly-silicon layer 24 is deposited on the gate oxide 22 to form a gate contact. Step (e) comprises a metallisation process 26.
Figure 2 illustrates an embodiment of a method in accordance with an aspect of the invention, the method being used to form a semiconductor device in the form of a 3C- SiC-on-Si MOSFET 100.
In step (a), a 3C-SiC drift layer 104 is epitaxially formed on a silicon (Si) substrate 102. The drift layer 104 is of n-type conductivity and has a dopant concentration of the order of 1015 cm 3. Preferably, the drift layer 104 has a dopant concentration of 5xl015 cm 3. The drift layer 104 is of the order of lOpm thick. Steps (b) - (d) comprise epitaxially forming a 3C-SiC body layer 112 of p-type conductivity. The body layer 112 has a linearly varying dopant concentration, as will be described herein.
In step (b), a first film layer 106 is epitaxially formed on the drift layer 104. The first film layer 106 has a thickness in the region of 0.2pm and has a dopant concentration of the order of 1016 cm 3, preferably 5xl016 cm 3.
In step (c), a second film layer 108 is epitaxially formed on the first film layer 106. The second film layer 108 has a thickness in the region of 0.3pm and has a dopant concentration of the order of 1017 cm 3, preferably 7xl017 cm 3.
Finally, in step (d), a third film layer 110 is epitaxially formed on the second film layer 108. The third film layer 110 has a thickness in the region of 0.3pm and has a dopant concentration of the order of 1018 cm 3, and preferably a peak concentration of lxlO18
-3
cm .
Whist the embodiment of Figure 2 comprises forming the body layer 112 from a series of film layers 106, 108, 110 with varying dopant concentrations, it will be appreciated that the body layer 112 may be formed as a single layer, for example having a constant dopant concentration across its depth. However, it has been found that having a varying level of dopant concentration with depth in the body layer 112 may at least partially mitigate difficulties in accurately overcompensating for the p-type dopants in the body layer 112 with n-type implants (see Figures 3-6) which may otherwise adversely affect the blocking capabilities of the final device 100.
The design formed through steps (a) - (d) illustrated in Figure 2 is subsequently used in different embodiments of the invention to form MOSFET devices 100, 200, 300, 400 shown in Figures 3-6.
Figure 3 illustrates an embodiment of a method for forming a semiconductor device in the form of a 3C-SiC-on-Si MOSFET device 100, which includes an implanted n- type/JFET region.
In step (e), and starting from step (d) of Figure 2, the method comprises implanting a region of the body layer 112 with dopants (preferably nitrogen) of n-type conductivity to form a JFET region 120 within the body layer 112. The JFET 120 is formed within the body layer 112 and results in body regions 116a, 116b of the body layer 112 positioned either side of the JFET region 120. Implanting the n-type dopants overcompensates for the p-type dopants of the body layer 112 resulting in a JFET region 120 having n-type conductivity within the p-type body layer 112.
As is shown in Figure 7, the N dopants are implanted at various energies to form the required doping profile in the channel 120. Specifically, various energy levels of N implants are used ranging from 60keV to 375keV, resulting in an overall dopant concentration which is roughly constant with depth.
Turning back to Figure 3, in step (f), the body regions 116a, 116b are each doped with nitrogen (N) implants to form source regions 118a, 118b therein. The desired doping concentration in the source regions 118a, 118b is of the order of 2xl019 cm 3.
In step (g), the surface of the 3C-SiC is etched, optionally to about 0.5pm. As with the etching step described with reference to Figure 1, this is to ensure that the JFET region 120 is sufficiently doped throughout.
In step (h), a gate oxide 122 is formed over the JFET 120, and in step (i) a poly-silicon layer 124 is deposited on the gate oxide 122 to form a gate contact. Step (i) also comprises a metallisation process 126.
Table 1 below provides a direct comparison of simulated characteristic values for the MOSFET 100 formed in accordance with the method illustrated in Figures 2 and 3, and the conventional method illustrated in Figure 1. The on-resistance is provided for Gate Voltage (VG) = 15V, and Drain Voltage (VD) = 0.5V.
Figure imgf000013_0001
Figure imgf000014_0001
implanted n-type channel/JFET region.
As shown, MOSFET 100 provides a comparable Gate threshold voltage, and a significantly reduced on-resistance for the Gate and Drain voltages provided above. However, the breakdown voltage achieved by MOSFET 100 is significantly less than that obtained with a MOSFET formed via a conventional method.
To improve the breakdown performance, a further method for forming a semiconductor device in the form of a 3C-SiC-on-Si MOSFET device 200 is proposed which includes extended p-body deep edges. This is illustrated in Figure 4, where like reference numerals have been used to represent similar components.
In step (e), and starting from step (d) of Figure 2, the method comprises implanting a region of a body layer 212 with dopants of n-type conductivity (preferably nitrogen) and at a first energy level/range to form a first JFET portion 220a of a JFET region within the body layer 212. Preferably, the dopants are implanted at a series of energy levels up to approximately 225keV to form the first JFET portion 220a. In step (f), a mask is used to target specific locations of the body layer 212 for further implantation with n-type dopants. Specifically, the body layer 212 is further implanted with n-type dopants at a second energy level/range, greater than the first energy level/range using the mask to form a second JFET portion 220b in the body layer 212.
The JFET portions 220a, 220b form a JFET region within the body layer 212 resulting in body regions 216a, 216b of the body layer 212 positioned either side of the JFET region. As with the embodiment shown in Figure 3, implanting the n-type dopants overcompensates for the p-type dopants of the body layer 212 resulting in a JFET region having n-type conductivity within the p-type body layer 212. In contrast to the MOSFET 100 shown in Figure 3, the JFET region comprises a second JFET portion 220b which is smaller in width than the first channel portion 220a and effectively brings opposing portions of the body regions 216a, 216b closer together.
As is shown in Figure 7, the N dopants are implanted at various energies to form the required doping profile in the channel. Specifically, various energy levels of N implants are used ranging from 60keV to 375keV, resulting in an overall dopant concentration which is roughly constant with depth. As discussed above, energy levels up to approximately 225keV are used to form the first channel portion 220a, whereas energy levels above 225keV and up to approximately 375keV are used to form the second channel portion 220b due to the increased energy requirement to implant at greater depths within the body layer 212.
Turning back to Figure 4, in step (g), the body regions 216a, 216b are each doped with nitrogen (N) implants to form source regions 218a, 218b therein. The desired doping concentration in the source regions 218a, 218b is of the order of 2xl019 cm 3.
In step (h), the surface of the 3C-SiC is etched, optionally to about 0.5pm. As with the etching step described with reference to Figure 1, this is to ensure that the JFET region is sufficiently doped throughout.
In step (i), a gate oxide 222 is formed over the JFET, and in step (j) a poly-silicon layer 224 is deposited on the gate oxide 222 to form a gate contact. Step (j) also comprises a metallisation process 226.
Having the wider first JFET portion 220a preserves a low resistance JFET region proximal to the gate contact (where the channel is formed) with the aim of maintaining a low on-resistance in the final MOSFET device 200.
Table 2 below provides a direct comparison of simulated characteristic values for the MOSFET 200 formed in accordance with the method illustrated in Figures 2 and 4, and the conventional method illustrated in Figure 1. The on-resistance is provided for Gate Voltage (VG) = 15V, and Drain Voltage (VD) = 0.5V.
Figure imgf000016_0001
Table 2 - Comparison of simulated characteristic values for a MOSFET 200 with extended p-body edges.
As shown, MOSFET 200 provides a comparable Gate threshold voltage, and a significantly reduced on-resistance for the Gate and Drain voltages provided above when compared with a MOSFET formed through conventional techniques (but a small increase on the on-resistance of MOSFET 100). The breakdown voltage achieved by MOSFET 200 is a significant improvement on that predicted for MOSFET 100, and is predicted to be much closer to that obtained with a MOSFET formed via a conventional method.
A further method for forming a semiconductor device in the form of a 3C-SiC-on-Si MOSFET device 300 is proposed which includes a“buried” p-type anti-region within the n-type channel. This is illustrated in Figure 5, where like reference numerals have been used to represent similar components.
In step (e), and starting from step (d) of Figure 2, the method comprises implanting a region of a body layer 312 with dopants of n-type conductivity (preferably nitrogen) and at a first energy level/range to form a first JFET portion 320a of a JFET region within the body layer 312. Preferably, the dopants are implanted at a series of energy levels up to approximately 225keV to form the first JFET portion 320a.
In step (f), a mask is used to target specific locations of the body layer 312 for further implantation with n-type dopants. Specifically, the body layer 312 is further implanted with n-type dopants at a second energy level/range, greater than the first energy level/range using the mask to form second and third JFET portions 320b, 320c in the body layer 312. The mask used prevents implantation of a region substantially central within the formed JFET region resulting in an anti-region 320d of p-type conductivity positioned between second and third JFET portions 320b, 320c of the JFET region.
The JFET portions 320a, 320b and 320c define a JFET region within the body layer 312 between body regions 316a, 316b and anti-region 320d of the body layer 312. As with the embodiments shown in Figures 3 and 4, implanting the n-type dopants overcompensates for the p-type dopants of the body layer 312 resulting in a JFET region, at least for JFET portions 320a, 320b, 320c, having n-type conductivity within the p-type body layer 312.
As is shown in Figure 7, the N dopants are implanted at various energies to form the required doping profile in the JFET region. Specifically, various energy levels of N implants are used ranging from 60keV to 375keV, resulting in an overall dopant concentration which is roughly constant with depth. As discussed above, energy levels up to approximately 225keV are used to form the first JFET portion 320a, whereas energy levels above 225keV and up to approximately 375keV are used to form the second and third JFET portions 320b, 320c due to the increased energy requirement to implant at greater depths within the body layer 312.
Turning back to Figure 5, in step (g), the body regions 316a, 316b are each doped with nitrogen (N) implants to form source regions 318a, 318b therein. The desired doping concentration in the source regions 318a, 318b is of the order of 2xl019 cm 3.
In step (h), the surface of the 3C-SiC is etched, optionally to about 0.5pm. As with the etching step described with reference to Figure 1, this is to ensure that the JFET region is sufficiently doped throughout.
In step (i), a gate oxide 322 is formed over the channel, and in step (j) a poly-silicon layer 324 is deposited on the gate oxide 322 to form a gate contact. Step (j) also comprises a metallisation process 326.
Having the p-type anti-region 320d within the JFET region balances the charge of the region and it lowers the overall electric field. As a consequence, the blocking voltage of the device can reach high values. At the same time, because the JFET region is higher doped than the typical values, the on-resistance drops dramatically. Without the presence of the anti-region the JFET cannot have high doping concentration value because this compromises the blocking voltage ability.
Table 3 below provides a direct comparison of simulated characteristic values for the MOSFET 300 formed in accordance with the method illustrated in Figures 2 and 5, and the conventional method illustrated in Figure 1. The on-resistance is provided for Gate Voltage (VG) = 15V, and Drain Voltage (VD) = 0.5V.
Figure imgf000018_0001
Table 3 - Comparison of simulated characteristic values for a MOSFET 300 with a
“buried” p-type anti-region within the channel.
As shown, MOSFET 300 provides a comparable Gate threshold voltage, and a significantly reduced on-resistance for the Gate and Drain voltages provided above when compared with a MOSFET formed through conventional techniques (but a small increase on the on-resistance of MOSFET 100). The breakdown voltage achieved by MOSFET 300 is a significant improvement on that predicted for MOSFET 100, and is predicted to be much closer to that obtained with a MOSFET formed via a conventional method.
A further method for forming a semiconductor device in the form of a 3C-SiC-on-Si MOSFET device 400 is proposed which includes a pillar shaped p-type anti-region within the n-type JFET region. This is illustrated in Figure 6, where like reference numerals have been used to represent similar components. In step (e), and starting from step (d) of Figure 2, the method comprises implanting a region of a body layer 412 with dopants of n-type conductivity (preferably nitrogen) at various energy levels to form a JFET region within the body layer 412. Preferably, the dopants are implanted at a series of energy levels up to approximately 375keV. During step (e), a mask is used to target specific locations of the body layer 412 for implantation with n-type dopants. Specifically, the mask prevents implantation of a region substantially central within the formed JFET region resulting in a pillar shaped anti region 420c of p-type conductivity positioned between first and second JFET portions 420a, 420b of n-type conductivity.
The JFET portions 420a, 420b define a JFET region within the body layer 412 between body regions 416a, 416b and anti-region 420c of the body layer 412. As with the embodiments shown in Figures 3, 4 and 5, implanting the n-type dopants overcompensates for the p-type dopants of the body layer 412 resulting in a JFET region, at least for JFET portions 420a, 420b having n-type conductivity within the p- type body layer 412.
As is shown in Figure 7, the N dopants are implanted at various energies to form the required doping profile in the JFET region. Specifically, various energy levels of N implants are used ranging from 60keV to 375keV, resulting in an overall dopant concentration which is roughly constant with depth.
Turning back to Figure 6, in step (f), the body regions 416a, 416b are each doped with nitrogen (N) implants to form source regions 418a, 418b therein. The desired doping concentration in the source regions 418a, 418b is of the order of 2xl019 cm 3.
In step (g), the surface of the 3C-SiC is etched, optionally to about 0.5pm. As with the etching step described with reference to Figure 1, this is to ensure that the JFET region is sufficiently doped throughout.
In step (h), a gate oxide 422 is formed over the JFET, and in step (i) a poly-silicon layer 424 is deposited on the gate oxide 422 to form a gate contact. Step (i) also comprises a metallisation process 426.
Table 4 below provides a direct comparison of simulated characteristic values for the MOSFET 300 formed in accordance with the method illustrated in Figures 2 and 6, and the conventional method illustrated in Figure 1. The on-resistance is provided for Gate Voltage (VG) = 15V, and Drain Voltage (VD) = 0.5V.
Figure imgf000020_0001
Table 4 - Comparison of simulated characteristic values for a MOSFET 400 with a pillar shaped p-type anti-region within the channel.
As shown, MOSFET 400 provides a comparable Gate threshold voltage, and a significantly reduced on-resistance for the Gate and Drain voltages provided above when compared with a MOSFET formed through conventional techniques (but a small increase on the on-resistance of MOSFET 100). The breakdown voltage achieved by MOSFET 300 is a significant improvement on that predicted for MOSFET 100, and is predicted to be much closer to that obtained with a MOSFET formed via a conventional method.
Figure 8 is a graph 600 showing modelled output characteristics of semiconductor devices (MOSFETS 100, 200, 300, 400) formed according to the methods shown in Figures 3-6 when compared with the prior art method of Figure 1. Specifically, graph 600 plots Drain Current ID against Drain Voltage VD for each of the MOSFETs described herein. As shown, the modelled output characteristics for each of MOSFETS 200, 300, 400 are comparable to the output characteristics for a MOSFET 10 formed via conventional methods.
Figure 9 is a graph 700 showing modelled transfer characteristics of semiconductor devices (MOSFETS 100, 200, 300, 400) formed according to the methods shown in Figures 3-6 when compared with the prior art method of Figure 1. Specifically, graph 700 plots Drain Current ID against Gate Voltage VG for each of the MOSFETs described herein.
Figure 10 is a graph 800 showing modelled output characteristics at different gate voltages (shown in different colours on graph 800; blue - VG=8V, red - VG=10V, orange - VG=15V) for semiconductor devices (MOSFETS 100, 200, 300, 400) formed according to the methods shown in Figures 3-6 when compared with the prior art method of Figure 1.
It has been shown that with a conventional design method (e.g. that shown in Figure 1), the channel/JFET region is one of the major contributors to the total MOSFET resistance. Methods of the present invention provide MOSFETs (e.g. MOSFETS 100, 200, 300, 400) having a lower on-resistance compared to conventional MOSFETs (e.g. MOSFET 10). This is attributed to fact that MOSFETs formed using methods of the present invention comprise a higher doping concentration in the channel/ JFET region.
However, as a consequence, a highly doped channel/JFET region results in a reduction in the blocking ability. Accordingly, methods of the invention provide means to address this issue, e.g. by reducing the separation between body regions of the device. Reducing the separation between body regions 118, 218, 318, 418 enables a better distribution of the electrostatic potential in the channel/JFET region and the drift layer. This is demonstrated in particular by the configurations of MOSFETs 200, 300, 400. As a result, such MOSFETs have been identified as having at least a comparable breakdown voltage to those formed via conventional methods (e.g. MOSFET 10).
The one or more embodiments are described above by way of example only. Many variations are possible without departing from the scope of protection afforded by the appended claims.

Claims

1. A method for producing a semiconductor device, the method comprising: epitaxially forming a first layer of n-type conductivity on a substrate or on a previously epitaxially formed layer; epitaxially forming a body layer of p-type conductivity on the first layer; and doping a portion of the body layer with a dopant to form a JFET region comprising a region of n-type conductivity within the body layer.
2. A method as claimed in claim 1, wherein the dopant comprises an n-type dopant, and doping at least a portion of the body layer comprises implantation of the dopant to over-compensate the p-type conductivity of the body layer to form the region of n-type conductivity in the formed JFET region.
3. A method as claimed in claim 2, comprising implanting the dopant at two or more implant energies in order to form a JFET region having a substantially constant doping concentration throughout the JFET region.
4. A method as claimed in any preceding claim, wherein epitaxially forming the body layer comprises sequentially epitaxially forming two or more sub-layers.
5. A method as claimed in claim 4, wherein the two or more sub-layers comprise different doping concentrations.
6. A method as claimed in claim 5, comprising: epitaxially forming a first sub-layer of p-type conductivity on the first layer, the first sub-layer having a first doping concentration; and epitaxially forming a second sub-layer of p-type conductivity on the first sub-layer, the second sub-layer having a second doping concentration, and wherein the second doping concentration is greater than the first doping concentration.
7. A method as claimed in claim 6, comprising epitaxially forming a third sub layer of p-type conductivity on the second sub-layer, the third sub-layer having a third doping concentration, and wherein the third doping concentration is greater than the second doping concentration.
8. A method as claimed in any preceding claim, comprising preventing implantation of a portion of the body layer such that the formed JFET region comprises an anti-region of p-type conductivity therein.
9. A method as claimed in claim 8, comprising preventing implantation of a portion of the body layer such that the formed JFET region comprises an anti region of p-type conductivity substantially central within the JFET region.
10. A method as claimed in claim 9, wherein the method comprises implanting the body layer with the dopant such that the formed JFET region comprises regions of n-type conductivity either side of the central anti-region of p-type conductivity.
11. A method as claimed in any preceding claim, comprising implanting the dopant in two or more implantation stages to form JFET portions, each JFET portion being associated with each implantation stage.
12. A method as claimed in claim 11, comprising implanting the dopant in a first implantation stage to form a first JFET portion having a first width, and implanting the dopant in a second implantation stage to form a second JFET portion having a second width different to the first width.
13. A method as claimed in claim 11 or claim 12, comprising implanting the dopant at a first energy level/set during a first stage of implantation, and implanting the dopant at a second energy level/set during a second stage of implantation.
14. A method as claimed in any preceding claim, comprising applying a mask to the body layer during implantation to target specific locations of the body layer for implantation with the dopant.
15. A method according to claim 14 when dependent on any of claims 11 to 13, comprising applying a first mask during a first stage of implantation, and applying a second mask during the second stage of implantation.
16. A method as claimed in any preceding claim, wherein the first layer and/or body layer comprises 3C-silicon carbide.
17. A method as claimed in any preceding claim, wherein the dopant comprises nitrogen.
18. A semiconductor device formed by the method of any of claims 1 to 17.
19. A semiconductor device of claim 18, comprising a Metal Oxide Semiconductor Field-Effect Transistor, MOSFET.
20. A semiconductor device, comprising: a substrate; a drift layer; multiple body regions of p-type conductivity; two source regions of n-type conductivity; a JFET region of n-type conductivity located substantially central between the two body regions; and an anti-region of p-type conductivity within the JFET region and spatially separated from the body regions.
21. A semiconductor device of claim 20, wherein the source regions and JFET region comprise 3C-SiC doped with n-type dopants.
22. A semiconductor device of claim 20 or 21, wherein the substrate comprises silicon.
23. A method for producing a semiconductor device, the method comprising:
epitaxially forming a first layer of a first conductivity type on a substrate or on a previously epitaxially formed layer;
epitaxially forming a second layer of a second conductivity type on the first layer; and doping at least a portion of the second layer with a dopant having the first conductivity type, thereby forming a region within the second layer having an opposite conductivity type to the second layer.
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