WO2020261278A1

WO2020261278A1 - Digital readout enabling 2d and 3d analysis for silicon photo multiplier

Info

Publication number: WO2020261278A1
Application number: PCT/IL2020/050714
Authority: WO
Inventors: Aharon Roni EL-BAHAR
Original assignee: 5D Sensing Ltd.
Priority date: 2019-06-25
Filing date: 2020-06-25
Publication date: 2020-12-30

Abstract

A digital readout architecture for a silicon photomultiplier comprises a plurality of single photon avalanche diodes (SPADs). Each of the SPADs is electrically connected to a digital logic gate configured to transform analog outputs generated during SPAD firing events into digital output pulses. Each SPAD is also electrically connected to a digital electronic circuit connected to a respective one of the digital logic gates and configured to count digital output pulses outputted by respective SPADs. At least one processing circuitry is adapted to identify temporally correlated output pulses from at least two different SPADs, and, in response to the identification of the temporally correlated output pulses, output an indication of a verified SPAD firing event. A programmable digital bus is configured to change one or more conditions for outputting an indication of a verified firing event by the at least one processing circuitry.

Description

DIGITAL READOUT ENABLING 2D AND 3D ANALYSIS FOR

SILICON PHOTO MULTIPLIER

RELATED APPLICATIONS

This Application claims priority to U.S. Provisional Patent Application No. 62/866,135, filed June 25, 2019, entitled Multi Output Readout Technique Enabling 2d and 3d Readout Concurrently of CMOS Based Sensors, and U.S. Provisional Patent Application No. 62/866,173, filed June 25, 2019, entitled Novel Digital Controlled Readout Technique for Single Photon Avalanche Diode Array and Silicon Photo Multiplier, the contents of which are incorporated by reference as if fully set forth herein.

BACKGROUND

The present invention, in some embodiments, relates to a digital readout architecture for a silicon photomultiplier, and more specifically, but not exclusively, to a network of single photon avalanche diodes (SPADs) each having a digital output, and connected to processing circuitry for 2D intensity imaging and 3D depth mapping. The invention further relates, in some embodiments, to a digital readout architecture for a silicon photomultiplier with a network of SPADs each having a digital output, and including a programmable digital bus configured to change conditions for outputting an indication of a verified firing event.

A SPAD is a semiconductor diode that is reverse biased well above its breakdown voltage. Due to this reverse bias, absorption of radiation results in an avalanche effect and complete breakdown of the reverse bias potential. Even a single photon can cause this avalanche effect, and accordingly a SPAD may be used for single photon detection. This capability for single photon detection is also known as absorption in Geiger mode. A SPAD may be used for high-sensitivity applications, such as ultra- sensitive cameras for night vision or space, and/or high-speed applications, such as distance sensing using time-of-flight measurements.

A schematic block diagram of prior art SPAD 10 is shown in FIG. 1A. SPAD 10 includes a diode D1 that is biased in reverse bias from VDD supply using a quenching resistor Rl. A typical value for the VDD supply voltage is 25 Volts. At a p-n junction in diode Dl, a single charge carrier injected into the depletion layer triggers a self-sustaining avalanche. During the avalanche, the current across diode Dl rises swiftly, and, correspondingly, the voltage across diode Dl drops. The avalanche effect almost completely discharges the reverse bias charge from SPAD 10.

The flow of current continues until the avalanche is quenched, due to the charging of the SPAD with quenching resistor Rl. The resistance of resistor Rl is set to be large enough so as not to result in instant breakdown. In addition, the resistance of R1 determines the recharge time, so the resistance must be small enough to permit recharging between firing events. Capacitor Cl is used for AC coupling of the SPAD device to an analog output readout.

FIG. IB shows a typical curve showing analog values for internal voltage of a SPAD measured across capacitor Cl, during a firing and quenching sequence. At the flat region of the curve, before absorption of the photon by the SPAD, the SPAD is at a constant voltage equivalent to drain voltage VDD. At time Tl, the SPAD absorbs a photon, and the voltage drops to near zero. The voltage then gradually increases as the quenching resistor charges the SPAD, until the voltage is restored to VDD. A typical time for a single SPAD discharge is 0.5 nanoseconds, and a typical charging time is around 10 nanoseconds. The exact charging time is determined by the resistance in quenching resistor Rl.

A SPAD may detect arrival of a single photon in a sub nanosecond time scale. The SPAD may thus be used to detect events, such as absorptions of photons, occurring on this time scale. A SPAD may also be used to count events, for example, if a counter is added to the SPAD output. The output of the SPAD may also be measured as a photon count per second. This measurement is an expression of light intensity.

SPADs may be combined in an array known as a Silicon Photo Multiplier (SiPM). SiPMs are used to verify that a firing of a SPAD resulted from a phenomenon that is being measured. Because of the high sensitivity of SPADs, SPADs often fire in response to “noise,” i.e., disturbances in the background that are unrelated to the phenomenon being measured. In order to neutralize the effect of this noise on the intensity measurement, the output of individual SPADs is combined and averaged.

FIG. 2A shows a representative SiPM 20 including four SPADs arranged in a 2x2 array, demarcated as SPAD 11, SPAD 12, SPAD 13, and SPAD 14. The SPADs 11-14 include, respectively, a diode Dl l-14, a capacitor Cl 1-14, and a quenching resistor Rl l-14 connected to VDD. Output voltage of SPADs 11-14 is connected in parallel into a single SiPM output voltage. The SiPM output voltage is measurable across aggregated capacitor C15. In an analog SiPM such as that of FIG. 2A, the number of SPADs connected to the averaging capacitor is fixed and hard wired.

FIG. 2B depicts a process of averaging the output voltage of the SPADS in SiPM 20. A reference voltage and analog comparator are used to detect deviations of the SiPM voltage from the reference voltage. The difference in the SiPM analog voltage measured across the aggregated capacitor C15, over time, reflects the count of SPADs that were activated at the same time. As depicted in FIG. 2B, at time Ti l, a single SPAD in the SiPM had fired, and the voltage dropped to level VI 1. At time T 12, two SPADS had fired, and the voltage dropped further to V12. At time T13, three SPADs had fired, and the voltage dropped further to V13, and at time T14, four SPADs had fired, and the voltage drops to V14. The simultaneous firing of more than one SPAD at the same time indicates that the firing is a result of a verified event, rather than noise sensed by each SPAD individually. A threshold value for a number of simultaneous SPAD firings may be set in order to determine a verified firing event. A sensitivity of the SiPM may be controlled by modifying the reference voltage.

SUMMARY

Due to the manner in which they are averaged, analog SiPMs have limitations in their resolution. The resolution of analog SiPMs is necessarily fixed in accordance with the number of SPADs that are incorporated in each SiPM. For example, when a SiPM includes 100 SPADs, and averaging determines that a verified firing event has occurred, the location of the light source can be defined only as within the entire SiPM, and it cannot be pinpointed further. In addition, the averaging is fixed regardless of the amount of noise that is present in the location of each individual SPAD. Some of the SPADs in the array may experience relatively little noise. In such scenarios, theoretically, it is not necessary to average the output of those SPADs with as many other SPADs, or at all, because each firing event is much more likely to be a verified firing event. However, the fixed configuration of analog SiPMs requires that outputs of all the SPADs in the SiPM must always be averaged in the exact same way. These constraints result in a loss of resolution.

The present disclosure addresses these and other limitations of analog SiPMs by disclosing embodiments of a novel circuit design topology. The topology includes a digital readout architecture comprising an analog-to-digital converter for the readouts of each SPAD in the array, and processing circuitry configured to analyze the digital readouts. The outputted digital pulse may be outputted as a single SPAD readout, for uses such as a 2D photon counter for night vision applications. The digital pulse may also be merged and averaged with digital outputs of other SPADs as part of a SiPM. Digital output pulses of any number of SPADs, and any combination of SPADs, may be averaged digitally. This digital averaging replaces the analog averaging that is used to determine whether a verified firing event has occurred. 2D intensity images and 3D depth maps for each SPAD may be generated and compared with each other in order to identify SPADs in the SiPM that experience more or less noise. The topology may also include a digital control bus that is programmable to determine which SPADs should be combined into a given SiPM, and under what circumstances the SiPM should output a verified firing event. According to a first aspect, a digital readout architecture for a silicon photomultiplier is disclosed. The architecture comprises a plurality of single photon avalanche diodes (SPADs). Each of the SPADs is electrically connected to a digital logic gate comprising an inverter configured to transform a plurality of analog outputs generated during a plurality of SPAD firing events of the respective SPAD into a plurality of digital output pulses. Each of the SPADs is also electrically connected to a digital electronic circuit connected to a respective one of the digital logic gates and configured to count digital output pulses outputted by respective SPADs. At least one processing circuitry is electrically connected to the plurality of SPADs and is adapted to: identify temporally correlated output pulses from at least two different SPADs, and, in response to the identification of the temporally correlated output pulses, output an indication of a verified SPAD firing event.

Advantageously, because the outputs of each SPAD are expressed as digital signals, the outputs of each SPAD may be averaged with a different number of other SPADs, or with a different grouping of other SPADs. In addition, the digital readout architecture enables concurrent collection, for each SPAD, of 2D intensity data, represented by the digital output pulses counted by the digital electronic circuits, and 3D depth data, represented by the temporally correlated output pulses identified by the processing circuitry. The 2D intensity data may be used to identify which SPADs in the SiPM array experience a higher degree of noise. Consequently, this information about noise may be used to determine an optimal degree of averaging for the outputs of each SPAD.

In another implementation according to the first aspect, the digital logic gate comprises a filter comprising a network of at least one resistor and at least one capacitor. The filter adjusts the output voltage of each SPAD during the firing cycle so that it exceeds a gate threshold of the digital logic gate. This adjusting thereby adjusts a pulse shape of the digital output pulse, to make the digital logic gate work more effectively.

In another implementation according to the first aspect, the architecture further comprises processing circuitry configured to conduct time-of-flight analysis for each temporally correlated digital output pulse received by the at least one processing circuitry, and thereby convert the temporally correlated digital output pulses into a 3D depth map. Advantageously, the 3D depth map may be used in LIDAR applications to identify distance, depth, and contours of target objects.

In another implementation according to the first aspect, each digital electronic circuit comprises a photon counter for measuring 2D light intensity received by each respective digital electronic circuit, and the architecture further comprises processing circuitry for converting output of the photon counters into a 2D intensity image, and for overlaying the 2D intensity image and the 3D depth map. Advantageously, the overlaying of the 2D intensity images with the 3D depth map enables identification of which portions of the 3D depth map were measured with SPADs having more or less environmental noise.

In another implementation according to the first aspect, the at least one processing circuitry comprises a plurality of processing circuitries, wherein each respective processing circuitry is configured to correlate digital outputs of one or more discrete combinations of SPADs with time values output by at least one digital clock. Optionally, at least one SPAD is configured to output a digital pulse to two or more processing circuitries of the at least one processing circuitry. Advantageously, unlike in an analog SiPM in which the component SPADs of the SiPM are fixed, the digital output of each SPAD is adaptable to be averaged with any combination of surrounding SPADs. As a result, the resolution of the array of SPADs is greatly improved.

In another implementation according to the first aspect, processing circuitry is configured to average outputs of respective SPADs when said outputs are temporally correlated with each other. This averaging is used for a similar purpose as analog averaging, in that the averaging of the outputs is used to identify a probable location of the source of energy.

Optionally, the processing circuitry that is configured to average the outputs of respective SPADs is further configured to compare the outputs of the digital counters and the indications of verified firing events, and to average outputs of respective SPADs only when a SPAD outputs a predetermined minimum number of digital pulses that are not identified of verified firing events and are therefore determined to be noise. Advantageously, the output of SPADs that do not register noise is not averaged, allowing higher resolution measurement of the output of those SPADs.

Optionally, the processing circuitry is configured to determine a degree of averaging required for the output of each respective SPAD in order to obtain a desired resolution, based on the amount of noise present at that respective SPAD, and to average the output of each respective SPAD with a different number of outputs of other SPADS, according to the determined degree. An optimal averaging level may be determined for the 3D digital output, based on the local 2D information for each SPAD which is at the same location and almost the same time as the 3D measurement. It is therefore possible to average each SPAD in a different manner, and thereby tailor the averaging to the noise level at each respective SPAD, thereby improving the resolution and signal-to-noise ratio of the SPAD array.

Optionally, the digital readout architecture further comprises a memory for storing history data of digital output pulses output by each SPAD. Processing circuitry is configured to predict a degree of averaging required for the output of each respective SPAD in order to obtain a desired resolution, based on the amount of noise detected in the history data for that respective SPAD. Advantageously, the prediction of the required degree of averaging may be used to prepare an initial high resolution output, without requiring further processing of the 2D and 3D output pulses. The prediction enabled by the history data may also improve the calculation for the degree of averaging required.

In another implementation according to the first aspect, the digital readout architecture further comprises a programmable digital bus configure to change one or more conditions for outputting an indication of a verified firing event by the at least one processing circuitry. Advantageously, the programmable digital bus further increases the adaptability of the digital readout architecture, by changing the conditions under which a firing event is determined to be verified or under which an indication of a verified firing event is output.

Optionally, the digital control bus is programmable to change a number of digital output pulses required to be temporally correlated with each other in order to output the indication of a verified firing event. For example, the number of digital output pulses may be a minimum of two, or a maximum of all of the digital output pulses connected to the at least one processing circuitry. The number of temporally correlated digital output pulses may thus be tailored to a desired degree of accuracy or resolution.

Optionally, the digital control bus is programmable to change which of the plurality of digital input pulses are input to the at least one processing circuitry. The digital control bus may thus change the SPAD inputs for a given SiPM.

Optionally, the digital control bus is programmable to instruct the at least one processing circuitry to correlate respective digital pulses with time values output by multiple clocks. Advantageously, the different clocks may advance at different rates, and thus provide alternative benchmarks for determining whether digital output pulses are temporally correlated.

Optionally, the digital control bus is programmable to instruct the at least one processing circuitry to output a series of indications of verified firing events having different resolutions, wherein each resolution is based on averaging the output of each respective SPAD with a different number of outputs of other SPADs. The number of neighboring SPADs used in each averaging, and the selection of each SPAD used in the averaging, may be determined based on 2D intensity data collected for individual SPADs. Advantageously, each SPAD may thus serve as a basis for multiple outputs having different resolutions.

According to a second aspect, a digital readout architecture for a silicon photomultiplier is disclosed. The architecture comprises a plurality of single photon avalanche diodes (SPADs), each electrically connected to a digital logic gate comprising an inverter configured to transform a plurality of analog outputs generated during a plurality of SPAD firing events of the respective SPAD into a plurality of digital output pulses. At least one processing circuitry is electrically connected to the plurality of SPADs and adapted to: identify temporally correlated output pulses from at least two different SPADs, and, in response to the identification of the temporally correlated output pulses, output an indication of a verified firing event. A programmable digital bus is configured to change one or more conditions for outputting an indication of a verified firing event by the at least one processing circuitry.

Advantageously, because the outputs of each SPAD are expressed as digital signals, the outputs of each SPAD may be averaged with a different number of other SPADs, or with a different grouping of other SPADs. The programmable digital bus further increases the adaptability of the digital readout architecture, by changing the conditions under which a firing event is determined to be verified or under which an indication of a verified firing event is output.

In another implementation according to the second aspect, the digital logic gate comprises a filter comprising a network of at least one resistor and at least one capacitor. The filter adjusts the output voltage of each SPAD during the firing cycle so that it exceeds a gate threshold of the digital logic gate. This adjusting thereby adjusts a pulse shape of the digital output pulse, to make the digital logic gate work more effectively.

In another implementation according to the second aspect, processing circuitry is configured to conduct time-of-flight analysis for each temporally correlated digital output pulse received by the at least one digital logic block, and thereby convert the temporally correlated digital output pulses into a 3D depth map. Advantageously, the 3D depth map may be used in LIDAR applications to identify distance, depth, and contours of target objects.

In another implementation according to the second aspect, the at least one processing circuitry comprises a plurality of processing circuitries. Each respective processing circuitry is configured to correlate digital outputs of one or more discrete combinations of SPADs with time values output by at least one digital clock. Optionally, at least one SPAD is configured to output a digital pulse to two or more processing circuitries of the at least one processing circuitry. Advantageously, unlike in an analog SiPM in which the component SPADs of the SiPM are fixed, the digital output of each SPAD is adaptable to be averaged with any combination of surrounding SPADs. As a result, the resolution of the array of SPADs is greatly improved.

In another implementation according to the second aspect, processing circuitry is configured to average outputs of respective SPADs when said outputs are temporally correlated with each other. This averaging is used for a similar purpose as analog averaging, in that the averaging of the outputs is used to identify a probable location of the source of energy.

In another implementation according to the second aspect, the digital readout architecture further comprises a memory for storing history data, and further comprises processing circuitry configured to predict a degree of averaging required for the output of each respective SPAD in order to obtain a desired resolution, based on an amount of noise detected in the history data for that respective SPAD. Advantageously, the prediction of the required degree of averaging may be used to prepare an initial high resolution output, without requiring further processing of the output pulses. The prediction enabled by the history data may also improve the calculation for the degree of averaging required.

In another implementation according to the second aspect, the digital control bus is programmable to change a number of digital output pulses required to be temporally correlated with each other in order to output the indication of a verified firing event. For example, the number of digital output pulses may be a minimum of two, or a maximum of all of the digital output pulses connected to the at least one processing circuitry. The number of temporally correlated digital output pulses may thus be tailored to a desired degree of accuracy or resolution.

In another implementation according to the second aspect, the digital control bus is programmable to change which of the plurality of digital input pulses are input to the at least one processing circuitry. The digital control bus may thus change the SPAD inputs for a given SiPM.

In another implementation according to the second aspect, the digital control bus is programmable to instruct the at least one processing circuitry to correlate respective digital pulses with time values output by multiple clocks. Advantageously, the different clocks may advance at different rates, and thus provide alternative benchmarks for determining whether digital output pulses are temporally correlated.

In another implementation according to the second aspect, the digital control bus is programmable to instruct the at least one processing circuitry to output a series of indications of verified firing events having different resolutions, wherein each resolution is based on averaging the output of each respective SPAD with a different number of outputs of other SPADs. The number of SPADs used in each averaging, and the selection of each SPAD used in the averaging, may be determined based on 2D intensity data collected for individual SPADs. Advantageously, each SPAD may thus serve as a basis for multiple outputs having different resolutions.

According to a third aspect, a method of generating a digital readout for a silicon photomultiplier is disclosed. The silicon photomultiplier comprises a plurality of single photon avalanche diodes (SPADs), each electrically connected to a digital logic gate comprising an inverter and a digital counter connected to a respective one of the digital logic gates. At least one processing circuitry is electrically connected to the plurality of SPADs. The method comprises: triggering a plurality of firing events in a plurality of the SPADS; for each firing event in a respective SPAD, transforming, with a respective digital logic gate, an analog output of a respective SPAD into a digital output pulse; counting the digital output pulses outputted by each respective SPAD with a respective digital counter; identifying, with the at least one processing circuitry, temporally correlated output pulses from at least two different SPADs; and, in response to the identification of the temporally correlated output pulses, outputting, with the at least one processing circuitry, an indication of a verified SPAD firing event.

Advantageously, because the outputs of each SPAD are expressed as digital signals, the outputs of each SPAD may be averaged with a different number of other SPADs, or with a different grouping of other SPADs. In addition, the method enables concurrent collection, for each SPAD, of 2D intensity data, represented by the digital output pulses counted by the digital electronic circuits, and 3D depth data, represented by the temporally correlated output pulses identified by the processing circuitry. The 2D intensity data may be used to identify which SPADs in the SiPM array experience a higher degree of noise. Consequently, this information about noise may be used to determine an optimal degree of averaging for the outputs of each SPAD.

According to a fourth aspect, a method of generating a digital readout for a silicon photomultiplier is disclosed. The silicon photomultiplier comprises a plurality of single photon avalanche diodes (SPADs), each electrically connected to a digital logic gate comprising an inverter, at least one processing circuitry electrically connected to the plurality of SPADs, and a programmable digital bus. The method comprises: programming the digital control bus to change one or more conditions for outputting an indication of a verified firing event by the at least one processing circuitry; triggering a plurality of firing events in a plurality of the SPADs; for each firing event, transforming, with a respective digital logic gate, an analog output of a respective SPAD into a digital output pulse; identifying, with the at least one processing circuitry, temporally correlated output pulses from at least two different SPADs; and in response to the identification of the temporally correlated output pulses, outputting, with the at least one processing circuitry, an indication of a verified SPAD firing event.

Advantageously, because the outputs of each SPAD are expressed as digital signals, the outputs of each SPAD may be averaged with a different number of other SPADs, or with a different grouping of other SPADs. The programming of the digital control bus further increases the adaptability of the digital readout architecture, by changing the conditions under which a firing event is determined to be verified or under which an indication of a verified firing event is output.

According to a fifth aspect, a method of generating an array of silicon photomultipliers from an array of single photon avalanche diodes (SPADs) is disclosed. Each SPAD comprises a digital logic gate for converting an analog output into a digital output. The method comprises transforming an analog output of each SPAD into a digital output; and combining a plurality of digital outputs of respective SPADs in a plurality of unique combinations to thereby form a plurality of silicon photomultipliers. The number of silicon photomultipliers is equal to or larger than the number of SPADs. Advantageously, the method produces a SPAD array having“super resolution,” with a substantially larger density of silicon photomultipliers for a given array of SPADs compared to what would be available using combinations of analog outputs.

Other systems, methods, features, and advantages of the present disclosure will be or become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional systems, methods, features, and advantages be included within this description, be within the scope of the present disclosure, and be protected by the accompanying claims.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

Some embodiments of the invention are herein described, by way of example only, with reference to the accompanying drawings. With specific reference now to the drawings in detail, it is stressed that the particulars shown are by way of example and for purposes of illustrative discussion of embodiments of the invention. In this regard, the description taken with the drawings makes apparent to those skilled in the art how embodiments of the invention may be practiced.

In the drawings:

FIG. 1A is a block diagram of a prior art single photon avalanche diode (SPAD);

FIG. IB depicts an analog output of internal voltage of the SPAD of FIG. 1A before, during, and after a firing event;

FIG. 2A depicts a prior art silicon photomultiplier including an array of four SPADs of FIG. 1A;

FIG. 2B depicts analog output of voltage across an averaging capacitor combining each of the outputs of the SPADs of the silicon photomultiplier of FIG. 2A;

FIG. 3A depicts block diagrams of an array of four SPADs each having a digital logic gate for converting analog output into digital output, according to embodiments of the invention;

FIG. 3B depicts an analog output of internal voltage of a SPAD of FIG. 3A before, during, and after a firing event, according to embodiments of the invention;

FIG. 3C depicts a digital output of internal voltage of a SPAD of FIG. 3A before, during, and after a firing event, according to embodiments of the invention;

FIG. 4 depicts a digital readout architecture including the array of four SPADs of FIG. 3 A; digital counters configured to count digital output pulses outputted by respective SPADs; and processing circuitry adapted to identify temporally correlated output pulses from each of the SPADs in the array, according to embodiments of the invention;

FIG. 5A depicts a block diagram of a single SPAD having a digital logic gate for converting analog output into digital output, according to embodiments of the invention;

FIG. 5B schematically depicts a digital logic having processing circuitry for receiving digital inputs from a plurality of SPADs of FIG. 5A and for outputting different digital logic outputs, according to embodiments of the invention;

FIG. 6 schematically depicts a operation of a digital logic gate in the digital logic of FIG. 5B, according to embodiments of the invention;

FIG. 7 schematically depicts a programmable digital control bus for controlling an output function of the processing circuitry of FIGS. 4, 5B, or 6, according to embodiments of the invention;

FIG. 8A depicts four prior art silicon photomultipliers, each comprised of a 2x2 array of SPADs with analog outputs;

FIG. 8B depicts sixteen silicon photomultipliers, each comprised of a 2x2 array of SPADs, whose outputs are combined in a digital fashion, according to embodiments of the invention; and

FIG. 9 depicts digital outputs for four different SPADs in the silicon photomultiplier of FIG. 4 used for generation of both 2D intensity data, and for digital averaging to obtain 3D time of flight data for a silicon photomultiplier comprised of the same SPADs, according to embodiments of the invention.

DETAILED DESCRIPTION

Before explaining at least one embodiment of the invention in detail, it is to be understood that the invention is not necessarily limited in its application to the details of construction and the arrangement of the components and/or methods set forth in the following description and/or illustrated in the drawings and/or the Examples. The invention is capable of other embodiments or of being practiced or carried out in various ways. Elements of the present disclosure include processing circuitry. The processing circuitry may include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present invention. The computer readable storage medium may be a tangible device that may retain and store instructions for use by an instruction execution device. The computer readable storage medium may be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing.

Computer readable program instructions described herein can be downloaded to respective computing/processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and/or a wireless network.

The computer readable program instructions may execute entirely on the processing circuitry, partly on the processing circuitry, as a stand-alone software package, partly on the processing circuitry and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the processing circuitry through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) may execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present invention.

As used in the present disclosure, the term“firing event” refers to any episode in which a SPAD discharges, regardless of the cause. The term“verified firing event” refers to an episode in which a SPAD discharges due to absorption of one or more photons from a source whose output is being measured, such as reflections from a target object that is being analyzed using LIDAR. The term“noise” refers to discharge of a SPAD due to environmental or internal conditions unrelated to the target whose output is being measured.

Referring to FIG. 3A, SPAD array 100 comprises four SPADs 121, 122, 123, and 124. SPADs 121-124 each include a diode D121-124, an analog voltage output across capacitors 021- 124, and a quenching resistor R121-124 connected to VDD. Diodes D121-124, capacitors 021- 124, and quenching resistors R121-124 operate substantially the same as those in prior art SPADs. Each SPAD121-124 is AC coupled to a digital readout domain 111-114 using a respective capacitor C 121, C122, C123, or C124. The digital readout domain 111-114 includes a digital logic gate which, in the illustrated embodiment, includes a respective inverter INV121, 122, 123, or 124. In alternative embodiments, the digital logic gate may include other digital logic functions, such as NAND or NOR. The digital logic gate is configured to output either a low or high state depending on whether the voltage across the capacitor 021-124 is above or below a threshold value.

In the digital readout domain 111-114, each SPAD 121-124 is pulled up to VCC using a respective resistor, R125, R126, R127, or R128. The networks of resistors R125-128 with corresponding capacitors 021-124 function as a filter. The filters keep the input level of the voltage at the digital readout domain 111-114 high, to ensure that the voltage does not drop below the threshold value due to random fluctuations.

The depiction of four SPADs in a 2x2 array is merely for illustrative purposes, and a different number of SPADs may be used. For example, the SPADs may be in a 16x16 array or in a 100 x 100 array.

FIGS. 3B and 3C illustrate differences between analog and digital outputs of SPADs, according to embodiments of the invention, using SPAD 121 as an example. FIG. 3B depicts the analog output of SPAD 121. The analog output appears as a curve substantially identical to the curve depicted in FIG. IB for prior art SPADs. At time T121, the SPAD fires and discharges its voltage to near zero. The quenching resistor then gradually charges the SPAD, thereby raising the voltage back to VDD.

FIG. 3C depicts the digital output of SPAD 121. Due to the inverter INV121, acting in combination with the R125-C121 filter, the output rises when the voltage decreases, and vice versa. Specifically, at T 122, when the SPAD discharges, the digital output rises from a“low” value to a“high” value. T122 may be the same as T121, or a very short time after T121. The readout is maintained at“high” during the charging of SPAD 121, until, at T123, the voltage increases to past the threshold of the digital logic gate, at which point the digital readout reverts back to“low.” As a result, a square wave is formed, with the digital readout changing from“low” to“high” immediately after each firing event, and reverting back to“low” after the SPAD is charged.

FIG. 4 depicts a digital readout architecture 110 for analyzing and combining outputs of SPADs 121, 122, 123, and 124. Digital readout architecture 110 includes the array of SPADs 121- 124, with each SPAD being AC coupled to a digital readout domain, as described above in connection with FIG. 3A. The digital readout architecture 100 also includes blocks for analyzing the digital output pulses of each SPAD, as will be described herein. Each digital output pulse of a SPAD 121-124 is electrically connected to a respective digital counter block 185, 187, 186, or 188. Digital counter blocks 185-188 are also referred to herein as digital electronic circuits. Each digital electronic circuitl85-188 also receives input from a clock with a reset function. Processing circuitry in each digital electronic circuit is configured to correlate the digital output pulses with a clock value, and to count firing events experienced at each SPAD. Each digital counter 185-188 outputs the digital output pulses and clock values to a respective digital logical output bus 145, 146, 147, 148.

When the SPAD firing is used as clock input, the digital counter 185-188 serves as a photon counter. In photon counter mode, the digital counter 185-188 counts the number of photons absorbed between two reset cycles. This count of photons is an expression of the 2D light intensity received by each respective SPAD. As used in this disclosure, 2D intensity refers to a quantity of photons that are absorbed by any particular SPAD during a measurement period, without any corresponding information as to when the photons were absorbed. For example, SPAD 121 may absorb 10 photons in a given measurement period, SPAD 122 may absorb 20 photons, SPAD 123 may absorb 30 photons, and SPAD 124 may absorb 40 photons. These values may be counted by the digital electronic circuits, and may be plotted onto a 2D intensity image.

In parallel to the digital counters 185-188, digital logic block 130 receives digital output pulses from each of the SPADs 121-124. Digital logic block 130 also receives clock values input from one or more input clocks 160. Digital logic block 130 contains processing circuitry for correlating at least some of the digital output pulses from the SPADs 121-124 with clock values from the at least one input clock 160. Specifically, the processing circuitry is adapted to identify temporally correlated output pulses from a plurality of SPADs in digital readout architecture 110. This temporal correlation serves a similar function to the aggregating capacitor in an analog SPAD, to distinguish between verified firing events and noise. For example, the digital logic block 130 may include code instructions for identifying a verified firing event only when at least two SPADs fire at the same time, or when all of the SPADs in the array fire at the same time.

A clock cycle for input clock 160 may be significantly faster than a clock cycle than each of the digital counters, and may be, for example, faster than 1 nanosecond.

Digital logic output bus 142 receives time-correlated output pulse data from digital logic block 130. The processing circuitry for identifying the verified firing event may alternatively be included in digital logic output bus 142. In response to the identification of the temporally correlated output pulses, digital logic output bus 142 outputs an indication of a verified SPAD firing event. Digital logic output bus 142 may also include processing circuitry configured to conduct a time-of-flight analysis for each temporally correlated digital output pulse. For example, in LIDAR applications, a laser is transmitted onto an object of interest from a laser source adjacent to the digital readout architecture 110. The laser is reflected off of the object of interest, and is reflected back to the SPADs. The time-of-flight analysis is used to determine a distance of the object in reference to the array of SPADs. By correlating firing events at each SPAD in the array with the time of firing, it is possible to construct a 3D depth map of the object of interest.

Digital control bus 150 is electrically connected to digital logic 130, and supplies commands for controlling the output functions of the digital logic 130. Digital control bus 150 may be used to adapt the digital readout architecture 100 to generate various SiPM functions, as will be discussed further herein in connection with FIGS. 5A-7. In LIDAR applications, digital control bus 150 may also include a clock for synchronizing the digital pulses with the laser pulse.

FIGS. 5 A and 5B depict alternative schematic embodiments for a digital logic 230 of digital readout architecture 110, according to embodiments of the invention. FIG. 5A depicts a single SPAD 231 having a digital readout domain identical to the SPADs described in reference to FIG. 3 A. Digital logic 230 is electrically connected to digital output pulses of eight SPADs 231- 238. Digital logic 230 may also be connected to one or more clock inputs 260, as described above. Digital logic 230 includes processing circuitry for outputting three digital logic outputs 241-243. Digital logic outputs 241-243 may also be referred to herein as silicon photomultiplier functions. The use of three digital logic outputs is merely exemplary, and any number of digital logic outputs may be outputted.

Digital logic outputs 241-243 may be single bits, or may be vectors, i.e., strings of bits. The digital logic output buses 142 and 145-148 of FIG. 4 are depicted as arrows, indicating that they are vectors. Each of digital logic outputs 241-243 may be output on a bus, which may also include representation of a counter number.

Digital logic outputs 241-243 may differ from each other in one or more of the following ways.

First, the digital logic outputs may differ in the conditions required for outputting an indication of a verified firing event. For example, the processing circuitry may be set to require a different number of digital output pulses to be temporally correlated with each other in order to have the digital logic 230 output an indication of a verified firing event. In one example, digital logic output 241 outputs an indication of a verified firing event when at least two SPADs fire simultaneously, digital logic output 242 outputs an indication of a verified firing event when at least three SPADs fire simultaneously, and digital logic 243 outputs an indication of a verified firing event when all eight SPADs fire simultaneously.

Alternatively, the digital logic outputs 241-243 may differ based on which of the plurality of digital input pulses are input to the digital logic for comparison and averaging. For example, logic output 241 may include time correlated values for SPADs 231, 232, 233, and 234; logic output 242 may include time correlated values for SPADs 235, 236, 237, and 238; and logic output 243 may include time correlated values for all the SPADs in the array. The digital logic 230 may thus output a silicon photomultiplier function for any combination of SPADs in the array, and with any threshold for outputting an indication of a verified firing event. Furthermore, the digital output pulse of any given SPAD may be included in more than one silicon photomultiplier function.

Alternatively, the digital logic outputs may differ based on the use of different clock values for correlating with the respective digital pulses. The different clock values may be used for different timing synchronizations. For example, output logic 241 may be based on correlating the SPAD digital outputs with a clock having a clock cycle of 1 nanosecond; logic 242 may be based on correlating with a clock cycle of 2 nanoseconds, and logic 243 may be based on correlating with a clock cycle of 3 nanoseconds. The different clock cycles may be used to generate SiPM outputs with different degrees of resolution for filtering out noise, depending on the requirements of the analysis.

Alternatively, the digital logic outputs 241-243 may differ based on the degree of averaging implemented on the digital outputs of SPADs. For example, digital logic 241 may average all of the digital SPAD outputs 231-238 together, so that each individual SPAD is averaged with seven other SPADs. Digital logic 242 and 243 may average outputs of certain SPADs with fewer than seven other SPADs, or may even output the data of certain SPADs without any averaging. The degree of averaging applied to each SPAD output may be based on the amount of noise generated at each SPAD, as measured by the 2D intensity data generated at that SPAD. For example, a SPAD that registers a high degree of noise may have its output averaged with a larger number of surrounding SPADs, in order to eliminate the effect of the noise. A SPAD that registers a relatively small amount of noise may have its output averaged with fewer other SPADs, in order to increase the resolution of the data collected from that SPAD.

This flexibility in combining the outputs of the SPADs is made possible through the use of digital output pulses, rather than analog outputs, for averaging in the silicon photomultiplier functions.

FIG. 6 illustrates one example of a digital logic that may be implemented in a silicon photomultiplier function, according to embodiments of the present disclosure. In the embodiment of FIG. 6, the digital outputs of SPADs 331-338 and at least one clock 360 are input into digital logic 330. Digital logic 330 in this example is an AND logic gate. The digital logic output 341 indicates a“high” value only when all the SPADs 331-338, whose outputs are each connected to the digital logic output 341, fire at the same time. Other digital logic implementations including alternative digital logic commands may also be implemented, each in a manner known to those of skill in the art.

FIG. 7 schematically depicts a programmable digital control bus for controlling an output function of the processing circuitry or digital logic, according to embodiments of the invention. The system of FIG. 7 includes digital logic 430 receiving four SPAD digital inputs 431-434 and at least one clock input, and outputting two digital logic outputs 442. Digital control bus 450 is programmable to change to one or more conditions for outputting an indication of a verified firing event by the digital logic 430. For example, the digital control bus 450 may be used to input instructions regarding which SPADs should or should not be averaged, based on the degree of noise registered by each SPAD, as discussed above. Digital control bus 450 may likewise be programmed to implement any of the other SiPM functions discussed above.

The processing circuitries 130, 230, 330, 430 may include memories for recording history data of digital output pulses output by each SPAD. The history data may include, for example, the degree of noise measured at each SPAD as indicated by a comparison of its 2D intensity image with the number of verified firing events recorded at that SPAD, as will be discussed further below in connection with FIG. 9. The history data may be used to predict a degree of averaging required for the output of each respective SPAD in order to obtain a desired resolution, and a user may program the processing circuitries, via the digital control bus, according to the predictions by the history data.

Figures 8A and 8B illustrate differences between SiPM combinations available with analog SiPMs, and SiPM combinations available with a digitally controlled SiPM, according to embodiments of the present disclosure.

FIG. 8A depicts exemplary prior art SiPM arrays 500, 501, 510, and 511 of SPADs with analog outputs. In the illustrated embodiment, each array is comprised of a 2x2 array of four SPADs, having reference numerals from 402 to 433. When the outputs of each SPAD are combined into a SiPM, each 2x2 array forms a single pixel. The composition of SPADs in each SiPM is fixed, and correspondingly the resolution of each SiPM is fixed based on the number of SPADs in the pixel: Consequently, a verified firing event may be located to a particular pixel, namely a particular 2x2 array, but not to a particular SPAD within the array. In other words, in the event that the SiPM outputs a voltage drop consistent with a verified firing event, it is only possible to determine that at least one or more of the SPADs in the SiPM fired, but not to identify which of the SPADs fired. The location of the firing event could be anywhere on the SPAD array.

FIG. 8B depicts an array of SPADs arranged with the digital readout architecture of FIG. 4. In the embodiment of FIG. 8B, 25 SPADs are arranged in a 5x5 array, designated with reference numerals from 400 to 444. Different discrete combinations of SPADs are digitally combined by the processing circuitry into sixteen different SiPMs, designated with reference numerals from 600 to 633. Each of the sixteen SiPMs is made up of a 2x2 array of SPADs within the 5x5 array. For example, SiPM 600 is comprised of SPADs 400, 401, 410, and 411; SiPM 601 is comprised of SPADs 401, 402, 411, and 412; SiPM 602 is comprised of SPADs 402, 403, 412, and 413; SiPM 603 is comprised of SPADs 403, 404, 413, and 414, etc. Each SPAD may be combined with other SPADs in more than one SiPM. For example, SPAD 421 is part of SiPMs 610, 611, 620, and 621.

Although, in the illustrated embodiment, each SiPM has four SPADs, the number of SPADs in each SiPM may vary from a minimum of one, to a maximum of all of the SPADs in the array. If just a single SPAD is used to average the corresponding SiPM, the resolution of the SiPM is the same as that of one of the SPADs. Use of a single SPAD is also known as single-SPAD stepping.

The ability to combine the SPADs into different discrete SiPM groups results from the conversion of the SPAD outputs into digital outputs, and the processing circuitry that is used to combine of the digital outputs of the SPADs. As discussed above in connection with FIGS. 4-7, processing circuitry 130, 230, 330, 430 is programmable to form SiPMs that draw from various combinations of SPADs in the array. Digital control bus 150, 450 may program the processing circuitry to change the outputs of which SPADs are combined in a SiPM function, as discussed above.

The illustrated embodiment of FIG. 8B illustrates only 16 SiPMs formed from the array of 25 SPADs. Each of the SiPMs is formed of a 2x2 array of adjacent SPADs. In alternative embodiments, it is possible to form additional“edge” combinations of SiPMs, in which the SiPMs include SPADs that are on corners or edges of the array. Whereas in a typical array, each SPAD is surrounded by eight other SPADs, a SPAD on the comer is surrounded by only five other SPADs, and a SPAD on the edge is surrounded by only six other SPADs. Careful manipulation of the edge SiPM functions is necessary to generate SiPM functions with proper resolution on the corners and edges. For example, SPADs 400 and 410, which are on the edge of the array, may be averaged with each other and two other values representing the region outside the array. These two other values may be always given a value of zero or one. In addition or in the alternative, existing neighbors of SPADs 400 and 410 may be included in the averaging for the edge SiPMs. With careful manipulation of the edge SiPM functions, it is possible to produce a number of SiPMs that is larger than the number of SPADs in the array. In such embodiments, it is possible to achieve “super-resolution” within the SPAD array, a result that is not feasible with analog SiPMs.

FIG. 9 depicts a schematic process for comparing 2D and 3D digital outputs of SPADs, and for determining a degree of noise present at each SPAD, according to embodiments of the present disclosure. As shown in the uppermost graph, a laser is projected onto an object of interest at time Ti l, and is reflected back toward a SPAD array. The SPAD array is comprised of four SPADs, each of which is separately electrically connected to a digital counter for measuring 2D image intensity, and which are all connected to a digital logic block for comparing and averaging outputs in a SiPM function, in the manner described above.

Due to noise, certain of the SPADs of the SPAD array of FIG. 9 fire at different times. The SPADs also fire at the same time as a result of verified firing events. Each firing event is represented on an output graph as a peak, also referred to as a count. In the illustrated example, SPAD #1 Digital Output has counts at times T22, T23, T24, and T25; SPAD #2 Digital Output has counts at T32, T33, T34, T35, and T36; SPAD #3 Digital Output has counts at times T42 and T44; and SPAD #4 Digital Output has a count only at T51. The counts of the SPAD pulses represent the intensity of the background light present at each SPAD. These counts may be mapped into a 2D intensity image.

The four SPADs are combined in a single SiPM function. In the illustrated embodiment, the SiPM function is configured to output an indication of a verified firing event only when at least three of the four SPADs fire simultaneously. Accordingly, the SiPM function outputs a peak at T64, which has the same clock value as T24, T34, and T44. The digital logic for the SiPM function ignores the nonsynchronous firing events at T22, T23, T32, T33, T42, and T51; these peaks are determined to be noise. The time difference AT between the laser pulse Ti l and the SiPM pulse T64 represents the time taken for the laser to hit the target object and return to the array of SPADs. This time is referred to as 3D depth or Time of Flight data, and may be mapped into a 3D depth map.

Accordingly, each SPAD in the array has two readouts of its digital output pulses. One readout shows a 2D signal from counting SPAD firing events in a given time. This counting may be comparatively“slow,” on the order of one microsecond, according to the clock cycle in each digital counter. The second readout shows 3D time of flight information, based on the faster clock input to the processing circuitry of the digital logic. The two readouts show the exact same field of view, and virtually the same time stamps, and may accordingly be overlaid. The overlaying of the 2D intensity image and the 3D depth map may be used to identify which of the SPADs in the array require averaging, and, if averaging is required, a degree of averaging required in order to obtain a desired resolution. For example, the processing circuitry may be configured to average outputs of respective SPADs only when those SPADs output a predetermined number of digital pulses that are determined to be noise. Taking the example of FIG. 9, SPAD #3 Digital Output records two counts, of which one is noise, whereas SPAD #2 Digital Output records five counts, of which four are noise. The processing circuitry may be programmed not to average the output of SPAD #3 at all, due to the low noise. Alternatively, the processing circuitry may be programmed to average the output of SPAD #3 with a small number of other SPAD outputs, but to average the output of SPAD #2 with a large number of other SPAD outputs, in order to compensate for the higher noise at SPAD #2.

In addition, as discussed above, history data for the 2D intensity images and 3D times of flight may be stored in a memory. The processing circuitry may utilize this history data to predict a degree of averaging required for the output of each respective SPAD, in future measuring events, in order to obtain a desired resolution.

It is expected that during the life of a patent maturing from this application many photon counters and many digital logic gates will be developed that are suitable for the functions described herein, and the scope of the terms photon counters and digital logic gate is intended to include all such new technologies a priori.

The digital readout architectures and methods described in the present disclosure are not limited in their application to digital outputs of SPADs, and may be applied to digital outputs of any photon detector that is currently known or that may become known. In particular, the digital readout architectures and functions described herein may be applied to outputs of a photon detector as disclosed in the International Patent Application co-filed on herewith date, by inventor Aharon El-Bahar, Attorney Docket Number 83029, entitled Single Photon Detector Based on Thyristor Working Principle, which claims priority to U.S. Provisional Patent Application No. 62/866,188, filed June 25, 2019, entitled“LOW OPERATION VOLTAGE CONFIGURABLE SINGLE PHOTON DETECTOR DEVICE IN CMOS TECHNOLOGY”, the contents of which are incorporated by reference as if fully set forth herein.

As used herein the term“about” refers to ± 10 %.

The terms "comprises", "comprising", "includes", "including", “having” and their conjugates mean "including but not limited to". This term encompasses the terms "consisting of" and "consisting essentially of". The phrase "consisting essentially of" means that the composition or method may include additional ingredients and/or steps, but only if the additional ingredients and/or steps do not materially alter the basic and novel characteristics of the claimed composition or method.

As used herein, the singular form "a", "an" and "the" include plural references unless the context clearly dictates otherwise. For example, the term "a compound" or "at least one compound" may include a plurality of compounds, including mixtures thereof.

The word“exemplary” is used herein to mean“serving as an example, instance or illustration”. Any embodiment described as“exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments and/or to exclude the incorporation of features from other embodiments.

The word“optionally” is used herein to mean“is provided in some embodiments and not provided in other embodiments”. Any particular embodiment of the invention may include a plurality of“optional” features unless such features conflict.

Throughout this application, various embodiments of this invention may be presented in a range format. It should be understood that the description in range format is merely for convenience and brevity and should not be construed as an inflexible limitation on the scope of the invention. Accordingly, the description of a range should be considered to have specifically disclosed all the possible subranges as well as individual numerical values within that range. For example, description of a range such as from 1 to 6 should be considered to have specifically disclosed subranges such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6 etc., as well as individual numbers within that range, for example, 1, 2, 3, 4, 5, and 6. This applies regardless of the breadth of the range.

Whenever a numerical range is indicated herein, it is meant to include any cited numeral (fractional or integral) within the indicated range. The phrases“ranging/ranges between” a first indicate number and a second indicate number and“ranging/ranges from” a first indicate number “to” a second indicate number are used herein interchangeably and are meant to include the first and second indicated numbers and all the fractional and integral numerals therebetween.

It is appreciated that certain features of the invention, which are, for clarity, described in the context of separate embodiments, may also be provided in combination in a single embodiment. Conversely, various features of the invention, which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable subcombination or as suitable in any other described embodiment of the invention. Certain features described in the context of various embodiments are not to be considered essential features of those embodiments, unless the embodiment is inoperative without those elements. All publications, patents and patent applications mentioned in this specification are herein incorporated in their entirety by reference into the specification, to the same extent as if each individual publication, patent or patent application was specifically and individually indicated to be incorporated herein by reference. In addition, citation or identification of any reference in this application shall not be construed as an admission that such reference is available as prior art to the present invention. To the extent that section headings are used, they should not be construed as necessarily limiting.

In addition, any priority document(s) of this application is/are hereby incorporated herein by reference in its/their entirety.

Claims

WHAT IS CLAIMED IS:

1. A digital readout architecture for a silicon photomultiplier, comprising:

a plurality of single photon avalanche diodes (SPADs), each electrically connected to: a digital logic gate comprising an inverter configured to transform a plurality of analog outputs generated during a plurality of SPAD firing events of the respective SPAD into a plurality of digital output pulses, and

a digital electronic circuit connected to a respective one of the digital logic gates and configured to count digital output pulses outputted by respective SPADs;

and at least one processing circuitry electrically connected to the plurality of SPADs and adapted to:

identify temporally correlated output pulses from at least two different SPADs; and in response to the identification of the temporally correlated output pulses, output an indication of a verified SPAD firing event.

2. The digital readout architecture of claim 1, wherein the digital logic gate comprises a filter comprising a network of at least one resistor and at least one capacitor.

3. The digital readout architecture of claim 1, further comprising processing circuitry configured to conduct time-of-flight analysis for each temporally correlated digital output pulse received by the at least one processing circuitry, and thereby convert the temporally correlated digital output pulses into a 3D depth map.

4. The digital readout architecture of claim 3, wherein each digital electronic circuit comprises a photon counter for measuring 2D light intensity received by each respective digital electronic circuit, and the architecture further comprises processing circuitry for converting output of the photon counters into a 2D intensity image, and for overlaying the 2D intensity image and the 3D depth map.

5. The digital readout architecture of claim 1, wherein the at least one processing circuitry comprises a plurality of processing circuitries, wherein each respective processing circuitry is configured to correlate digital outputs of one or more discrete combinations of SPADs with time values output by at least one digital clock.

6. The digital readout architecture of claim 5, wherein at least one SPAD is configured to output a digital pulse to two or more processing circuitries of the at least one processing circuitry.

7. The digital readout architecture of claim 1, further comprising processing circuitry configured to average outputs of respective SPADs when said outputs are temporally correlated with each other.

8. The digital readout architecture of claim 7, wherein said processing circuitry that is configured to average the outputs of respective SPADs is further configured to compare the outputs of the digital counters and the indications of verified firing events, and to average outputs of respective SPADs only when a SPAD outputs a predetermined minimum number of digital pulses that are not identified as verified firing events and are therefore determined to be noise.

9. The digital readout architecture of claim 8, wherein the processing circuitry is configured to determine a degree of averaging required for the output of each respective SPAD in order to obtain a desired resolution, based on the amount of noise present at that respective SPAD, and to average the output of each respective SPAD with a different number of outputs of other SPADs, according to the determined degree.

10. The digital readout architecture of claim 8, further comprising a memory for storing history data of digital output pulses output by each SPAD, and further comprising processing circuitry configured to predict a degree of averaging required for the output of each respective SPAD in order to obtain a desired resolution, based on the amount of noise detected in the history data for that respective SPAD.

11. The digital readout architecture of claim 1, further comprising a programmable digital control bus configured to change one or more conditions for outputting an indication of a verified firing event by the at least one processing circuitry.

12. The digital readout architecture of claim 11, wherein the digital control bus is programmable to change a number of digital output pulses required to be temporally correlated with each other in order to output the indication of a verified firing event.

13. The digital readout architecture of claim 11, wherein the digital control bus is programmable to change which of the plurality of digital input pulses are input to the at least one processing circuitry.

14. The digital readout architecture of claim 11, wherein the digital control bus is programmable to instruct the at least one processing circuitry to correlate respective digital pulses with time values output by multiple clocks.

15. The digital readout architecture of claim 11, wherein the digital control bus is programmable to instruct the at least one processing circuitry to output a series of indications of verified firing events having different resolutions, wherein each resolution is based on averaging the output of each respective SPAD with a different number of outputs of other SPADS.

16. A digital readout architecture for a silicon photomultiplier, comprising:

a plurality of single photon avalanche diodes (SPADs), each electrically connected to a digital logic gate comprising an inverter configured to transform a plurality of analog outputs generated during a plurality of SPAD firing events of the respective SPAD into a plurality of digital output pulses,

at least one processing circuitry electrically connected to the plurality of SPADs and adapted to:

identify temporally correlated output pulses from at least two different SPADs; and in response to the identification of the temporally correlated output pulses, output an indication of a verified SPAD firing event;

and a programmable digital control bus configured to change one or more conditions for outputting an indication of a verified firing event by the at least one processing circuitry.

17. The digital readout architecture of claim 16, wherein the digital logic gate comprises a filter comprising a network of at least one resistor and at least one capacitor, (digital logic gate).

18. The digital readout architecture of claim 16, further comprising processing circuitry configured to conduct time-of-flight analysis for each temporally correlated digital output pulse received by the at least one digital logic block, and thereby convert the temporally correlated digital output pulses into a 3D depth map.

19. The digital readout architecture of claim 16, wherein the at least one processing circuitry comprises a plurality of processing circuitries, wherein each respective processing circuitry is configured to correlate digital outputs of one or more discrete combinations of SPADs with time values output by at least one digital clock.

20. The digital readout architecture of claim 19, wherein at least one SPAD is configured to output a digital pulse to two or more processing circuitries of the at least one processing circuitry.

21. The digital readout architecture of claim 16, further comprising processing circuitry that is configured to average outputs of respective SPADs when said outputs are temporally correlated with each other.

22. The digital readout architecture of claim 16, further comprising a memory for storing history data, and further comprising processing circuitry configured to predict a degree of averaging required for the output of each respective SPAD in order to obtain a desired resolution, based on an amount of noise detected in the history data for that respective SPAD.

23. The digital readout architecture of claim 16, wherein the digital control bus is programmable to change a number of digital output pulses required to be temporally correlated with each other in order to output the indication of a verified firing event.

24. The digital readout architecture of claim 16, wherein the digital control bus is programmable to change which of the plurality of digital input pulses are input to the at least one processing circuitry.

25. The digital readout architecture of claim 16, wherein the digital control bus is programmable to instruct the at least one processing circuitry to correlate respective digital pulses with time values output by multiple clocks.

26. The digital readout architecture of claim 16, wherein the digital control bus is programmable to instruct the at least one processing circuitry to output a series of indications of verified firing events having different resolutions, wherein each resolution is based on averaging the output of each respective SPAD with a different number of outputs of other SPADs.

27. A method of generating a digital readout for a silicon photomultiplier, wherein the silicon photomultiplier comprises a plurality of single photon avalanche diodes (SPADs), each electrically connected to a digital logic gate comprising an inverter and a digital counter connected to a respective one of the digital logic gates; and at least one processing circuitry electrically connected to the plurality of SPADs; wherein the method comprises:

triggering a plurality of firing events in a plurality of the SPADs;

for each firing event in a respective SPAD, transforming, with a respective digital logic gate, an analog output of a respective SPAD into a digital output pulse;

counting the digital output pulses outputted by each respective SPAD with a respective digital counter;

identifying, with the at least one processing circuitry, temporally correlated output pulses from at least two different SPADs; and

in response to the identification of the temporally correlated output pulses, outputting, with the at least one processing circuitry, an indication of a verified SPAD firing event.

28. A method of generating a digital readout for a silicon photomultiplier, wherein the silicon photomultiplier comprises a plurality of single photon avalanche diodes (SPADs), each electrically connected to a digital logic gate comprising an inverter; at least one processing circuitry electrically connected to the plurality of SPADs; and a programmable digital control bus, wherein the method comprises:

programming the digital control bus to change one or more conditions for outputting an indication of a verified firing event by the at least one processing circuitry;

triggering a plurality of firing events in a plurality of the SPADs;

for each firing event, transforming, with a respective digital logic gate, an analog output of a respective SPAD into a digital output pulse;

29. A method of generating an array of silicon photomultipliers from an array of single photon avalanche diodes (SPADs), wherein each SPAD comprises a digital logic gate for converting an analog output into a digital output, and the method comprises:

transforming an analog output of each SPAD into a digital output; and combining a plurality of digital outputs of respective SPADs in a plurality of unique combinations to thereby form a plurality of silicon photomultipliers;

wherein the number of silicon photomultipliers is equal to or larger than the number of

SPADs.